A method of forming a mask layer on a semiconductor fin structure

Abstract

A method of forming a mask layer (190) on a semiconductor fin structure (100) is disclosed. The method includes forming a first set of spacers and a second set of spacers (131, 132, 133, 134) disposed at side surfaces of the first set of spacers, providing a first filler material (140) between the second set of spacers, etching a top portion of the first filler material to form recesses (150) between the second set of spacers, providing a second filler material (160) in the recesses, and causing the second filler material to form a set of dummy mask lines. Further, the method includes recessing a top portion (170) of at least the first set of spacers, providing a mask layer material (180) between the dummy mask lines, and removing the dummy mask lines and the first filler material.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor processing, and more particularly, to a method for forming a mask layer on a semiconductor fin structure, wherein the mask layer is capable of forming a gate structure for a transistor device formed in the fin structure. Background Art

[0002] Semiconductor devices such as field effect transistors (FETs) typically have a source, a channel, and a drain, and a gate structure that controls the flow of current through the channel, with current flowing from the source to the drain. Transistor devices can have various different structures. For example, a transistor can be a flat type with a source, a channel, and a drain formed in the substrate material itself, or a type in which the channel extends outward from the substrate. The channel can be an upright plate of thin material, commonly referred to as a fin, and a cross-gate structure is provided on the fin to control the flow of current along the fin in the direction of the main surface of the substrate.

[0003] As device dimensions continue to decrease in the semiconductor industry, forming individual components and features becomes more difficult. In the field of photolithography, a technique called self-aligned double patterning (SADP) is used to form linewidth patterns that exceed the optical limits of conventional photolithography due to scaling. SADP employs a technique called pitch splitting, in which the pattern is divided into two or more parts that can be processed in a conventional manner and combined into the final sub-resolution pitch pattern.

[0004] SADP methods are known for providing fin transistor gate structures with reduced critical dimensions. However, there remains a need for an improved process that can meet the ever-increasing demands for gate pitch scaling, footprint reduction, and process reliability. Summary of the Invention

[0005] The present invention provides a method for forming a mask layer on a semiconductor fin structure. Other and / or alternative purposes may be understood from the following description.

[0006] According to one aspect of the present inventive concept, there is provided a method for forming a mask layer on a semiconductor fin structure, the method comprising:

[0007] forming a mandrel on the fin structure;

[0008] providing a first spacer material on the mandrel, thereby forming a first set of spacers, the first set of spacers including first spacers at a first side surface of the mandrel and second spacers at a second side surface of the mandrel;

[0009] Remove the mandrel;

[0010] providing a second spacer material on the first and second spacers, thereby forming a second set of spacers disposed at side surfaces of the first set of spacers;

[0011] providing a first filler material between the second set of spacers;

[0012] etching a top portion of the first filler material to form recesses between the second set of spacers;

[0013] providing a second filler material in the recess, the second filler material forming a set of dummy mask lines;

[0014] recessing a top portion of at least a first set of spacers;

[0015] providing a mask layer material between the dummy mask lines; and

[0016] The dummy mask lines and the first filler material are removed.

[0017] In modern device manufacturing, advanced gate patterning can include multiple patterning processes, such as self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP) for defining gate critical dimensions (CD). The present invention concept uses a different approach, wherein similar gate CDs can be provided without resorting to multiple patterning processes. The difference is that the mandrels can be formed in a direct patterning process, and the gate CD is defined by a first set and a second set of spacers positioned by the mandrels. The fact that the same gate CD can be provided without using multiple patterning processes makes further scaling possible.

[0018] Furthermore, the inventive concepts allow for the mask layer to be provided after the first and second sets of spacers have been formed. This is advantageous for multiple patterning techniques where the same hard mask is often used for both the multiple patterning process and the final gate mask layer, since in those cases there is a risk of damage or over-etching of the hard mask, particularly during spacer recessing. By instead forming the final mask layer after processing the first and second sets of spacers, the mask layer can be designed without regard to processing requirements associated with forming the spacers. Differently, the mask layer can be designed with respect to requirements associated with subsequent processing of the gate structure, such as replacement dummy gate processing. In particular, the mask layer can be adapted to have improved etch resistance and / or to be an improved chemical mechanical polishing (CMP) stop layer.

[0019] The fin structure may be a fin-shaped semiconductor structure extending along and protruding from a substrate. Even though this aspect refers to "(one) semiconductor fin structure", it should be understood that the present invention is also applicable to multiple semiconductor fin structures, for example, a first fin structure and a second fin structure. The first fin structure may extend along a first fin track (i.e., along a first geometric straight line of the substrate). The second fin structure may extend along a second fin track (i.e., along a second geometric straight line of the substrate). The first fin structure and the second fin structure may extend parallel to each other.

[0020] One or more transistor devices may be formed in the fin structure. The transistor device may be, for example, a field effect transistor (FET), also known as a finFET, having a source region and a drain region formed in the fin and a horizontal channel therebetween.

[0021] A "mandrel" as used herein refers to a core or feature that can serve as a support for subsequent growth or deposition of a first spacer material. The mandrel can be formed in a single patterning step using the same mask, or in a multiple patterning process using multiple sub-masks. Patterning can be performed on a mandrel material layer formed on the fin structure. The mandrel material layer can be disposed directly on the fin structure or on an intermediate layer. In some embodiments, the mandrel can be oriented across the fin structure, for example, substantially orthogonal, thereby allowing the final gate structure to be formed across the fin structure.

[0022] The first set of spacers can be formed by depositing a first spacer material on the mandrel, preferably as a conformal layer, and etching the deposited first spacer material so that the first spacer material remains on at least a portion of the side surface of the mandrel, thereby forming the first set of spacers. For example, the etching can be anisotropic so that the first spacer material remains on the side surface of the mandrel.

[0023] The second set of spacers can be formed in a similar manner, for example, by depositing a second spacer material over the first set of spacers (after removing the mandrels). The second spacer material can be deposited as a conformal layer and etched so that the second spacer material remains on at least a portion of the side surfaces of the first set of spacers.

[0024] The first spacer material and the second spacer material may be selectively etched relative to one another, whereby, for example, the first spacer material may be etched away while the second spacer material remains.

[0025] The term "mask layer" may be understood as a layer that is able to counteract etching in the areas covered by the layer. The areas exposed by the etch mask may be etched accordingly, whereas the areas covered by the etch mask need not be significantly affected. Alternatively or in addition, a mask layer may be understood as a pattern or structure that allows features to be defined in a subsequent processing step in which material is added, for example by growth or deposition. The areas exposed by the mask layer may be provided with the added material, whereas the covered areas may be protected from the added material. In the context of the present application, a mask layer formed according to the inventive concept may define a plurality of linear gates, wherein, for example, dummy gates or metal gates may be provided.

[0026] A material can be selectively etched relative to another material. Selectively etching material "A" relative to material "B" means that features of material A adjacent to features of material B can be removed while retaining features of material B. Selectively etching or removing feature "A" relative to feature "B" means that feature A located adjacent to feature B can be removed while retaining feature B. This can be achieved by covering feature B to be retained with an etch mask. This can be achieved by exposing feature A and feature B to an etching process in which feature A is etched at a greater rate than feature B. Thus, the portion of feature A exposed to the etching process can be removed while the portion of feature B exposed to the etching process can be retained after the etching process. In particular, the retention of feature B can be complete (in the sense that feature B is not significantly affected during the etching process) or at least partial (in the sense that feature B is retained to at least the extent that it can perform its intended function during subsequent processing steps). The etch rate ratio of the materials of feature B can advantageously be 2:1 or higher, but is preferably 10:1 or higher, or even more preferably 40:1 or higher.

[0027] The term "on" herein refers to a relative position when viewed normal to a major surface of a substrate. The term "on" therefore does not refer to the absolute orientation of layers or features, but rather their relative order. Thus, a "side" or "lateral surface" can refer to a surface or portion of a surface that faces in a direction along a major surface of a substrate. In other words, the normal direction of the term "lateral surface" can be orthogonal to the normal direction from the major surface of the substrate.

[0028] According to one embodiment, the mandrel can be formed from a carbon-based material, such as spin-on carbon (SoC), photoresist, bottom anti-reflective coating (BARC), or advanced patterning film (APF). These types of materials can be advantageous over, for example, silicon-based materials because they are generally more suitable for high aspect ratio patterning and can often be etched while maintaining a relatively straight profile for the resulting mandrel. SoC can be particularly advantageous because it allows planarization, where the fin topography can be polished and planarized by, for example, CMP. On the other hand, APF can withstand higher temperatures than SoC, BARC, and photoresist.

[0029] According to one embodiment, the first spacer material can be provided by an atomic layer deposition (ALD) process. The first spacer material can be, for example, amorphous silicon (a-Si). ALD can be advantageous over, for example, chemical vapor deposition (CVD) because ALD allows for relatively conformal deposition of the material and relatively easy layer deposition control. CVD has been shown to produce more voids and irregularities in the deposited material.

[0030] According to one embodiment, the step of providing the first spacer material may be followed by an etch-back process to remove the first spacer material that has been deposited on the fin structure. This may be performed in an etching process that removes the first spacer material disposed between and on top of the first set of spacers while leaving at least some of the first spacer material on side surfaces of the first and second spacers.

[0031] According to one embodiment, the second spacer material may comprise a material that is etch selective relative to the first spacer material. For example, the second spacer material may be a dielectric material such as silicon nitride, a low-k dielectric such as SiCO or SiOCN. The second spacer material may be provided after the mandrels have been stripped or removed, such that the second set of spacers is formed at the side surfaces of the first set of spacers. In a subsequent step, the second spacer material may be etched back to remove the second spacer material from the fin structure, leaving the second spacer material as a spacer on the first set of spacers.

[0032] At this stage of the process, a set of mask lines or gaps can be provided, wherein the thickness of the mask lines can be determined by the thickness of the first set of spacers and the thickness of the second set of spacers deposited on the sides of the first set of spacers. The width of the gap can be determined by the width and critical dimensions of the final gate line provided by the mask layer, which can be obtained by the present invention.

[0033] According to one embodiment, a first filler material may be disposed between the second set of spacers, which may be a carbon-based material similar to those discussed above in connection with the mandrel material.

[0034] The first filler material can be etched back to allow recesses to form between the second set of spacers. These recesses can then be filled with a second filler material, such as silicon dioxide, to form a set of dummy mask lines. Preferably, the top portion of the first filler material is removed; the size of the top portion determines the height of the dummy mask lines and the thickness of the final mask layer.

[0035] According to one embodiment, not only the first set of spacers can be recessed, but also the tops of the second set of spacers can be recessed, and then a mask layer material can be provided between the dummy mask lines. Thus, the mask layer not only protects the first set of spacers underneath, but also protects the second set of spacers disposed on the side surfaces of the first set of spacers. For example, the mask layer can be SiO2, Si3N4, SiCO or SiOCN, a metal or metal oxide such as titanium nitride, titanium dioxide or hafnium dioxide.

[0036] The present concepts can be used in replacement dummy gate processing, where a dummy structure, such as oxide or nitride, can replace a metal gate during a high temperature step. After completing these steps (which can include, for example, a source / drain implant activation anneal), the dummy structure can be etched away, a gate dielectric can be grown or deposited, and the final metal gate can be deposited in the gate track defined between the spacers of the second set of spacers. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The above and other objects, features and advantages of the present invention can be better understood through the following description and non-limiting detailed description with reference to the accompanying drawings. Unless otherwise specified, the same reference numerals are used to represent the same elements in the accompanying drawings.

[0038] 1 a , b ; 2 a , 2 b ; . . . 7 a , b and 8 a - d , 9 a - d and 10 a - d schematically illustrate a method of forming a mask layer on a semiconductor fin structure according to one or more embodiments of the inventive concept.

[0039] In the drawings, the sizes of layers, features or other structures may be exaggerated or not drawn to scale for illustrative purposes. Accordingly, the drawings are provided to illustrate the general elements of the embodiments.

[0040] In the drawings, like numbers are used for like elements unless otherwise specified. DETAILED DESCRIPTION

[0041] A method for forming a mask layer will now be described with reference to the drawings, wherein “a” generally shows a cross section across a fin structure and “b” generally shows a cross section along the fin structure.

[0042] A cross section taken across a plurality of fin structures 100 is disclosed in Figure 1a. Figure 1b is a cross section taken along one fin structure 100. In the following, features of the inventive concept will be discussed with reference to Figures 1a and 1b.

[0043] Each fin structure 100 may be disposed on a substrate 102 having a main surface extending along a plane aligned with the length of the fin structure 100. For example, the fin structure 100 may be formed by patterning and / or epitaxial growth of the substrate 102. For example, the substrate 102 and the fin structure 100 may be formed of silicon. As shown in FIG. 1 a , an isolation layer 104 (e.g., a shallow trench isolation) may be disposed on the substrate 102 such that only an upper portion of the fin structure 100 protrudes above a top surface of the isolation layer 104.

[0044] The mandrels 110 can be disposed on the fin structure 100. The mandrels can be formed as cores or elongated features extending across the fin structure 100 in a lateral direction (not shown in this figure) that is consistent with the orientation of the final device gate trace. The mandrels 110 can be formed by spin-on deposited carbon-based materials, such as Applied Materials' Advanced Patterning Film (APF) or Spin-On Carbon (SoC). One or more mandrels 110 can be provided; the number depends on the desired mask pattern to be formed. In the example shown in the present FIG. 1 b , three mandrels are shown. The mandrels 110 can be formed in a direct patterning process, or in a multiple patterning process (e.g., the SADP and SAQP examples described above), in which a single patterning step can be used. FIG. 1 a and 1 b show an example of using a hard mask layer 112 to define the mandrels 110. The hard mask layer 112 can be formed, for example, from amorphous silicon a-Si.

[0045] In the present illustrative example, four fin structures 100 are shown, with the upper 50 nm of the fin structures 100 protruding from the isolation portion 104 on the substrate. The protruding portion may also be referred to as the active area of ​​the fin structure 100, where the resulting transistor device may be formed. In some examples, the width of each fin is 5-10 nm and they are arranged adjacent to each other in a parallel manner with a spacing of, for example, 21-30 nm.

[0046] Turning to the mandrels 110, the present example discloses arranging three mandrels 110 to allow for the formation of a mask layer defining four gate tracks—two across the fin structure 100, and one on each fin structure 100 (as viewed along the length of the fin structure 100). This configuration is merely an example of a configuration that can be achieved with the present inventive concept, allowing for a target gate line CD of 16 nm, given a spacer width of 6 nm, a gap / trench width of 14 nm, and a total gate pitch of 42 nm.

[0047] FIG2a shows a cross-section of the structure of FIG1a and FIG1b taken across the fin structure 100 at a location between two adjacent mandrels after providing a first spacer material 120. The first spacer material 120 can be deposited as a conformal layer 120 covering the entire mandrel 110. In one example, the first spacer material can be amorphous silicon deposited by ALD. It should be understood that the first spacer material can be disposed directly on the mandrel material or indirectly by providing an intermediate layer therebetween.

[0048] The deposition method for providing the first spacer material 120 can result in conformal deposition of the material not only on the mandrels 110, but also on the fin structure 100. Therefore, the step of providing the first spacer material 120 can be followed by an etch-back process to remove the first spacer material from the fin structure 100. The results are shown in Figures 3a and 3b, after etching the first spacer material 120 by, for example, anisotropic etching to define a first set of spacers, the first set of spacers including first spacers 121 on the first side surface and second spacers 122 on the second side surface of each of the three mandrels 110 shown in this example.

[0049] In the present example, the spacing between the mandrels 110 can be selected along with the thickness of the first spacer material 120 forming the first set of spacers to define a gap between the spacers of adjacent mandrels 110. Preferably, the width of the gap is selected to correspond to the width of the mandrels 110 so that the first set of spacers are arranged in an equidistant configuration.

[0050] 4a and 4b show the first set of spacers 121, 122 after removal of the mandrel 110. The mandrel 110 may be removed, for example, by plasma stripping. As described above, the thickness and spacing of the mandrel 110 may be selected so that the first set of spacers 121, 122 are arranged at a constant spacing.

[0051] In Figures 5a and 5b, a second spacer material 130 is disposed on the first set of spacers 121, 122. The second spacer material 130 can be disposed directly on the first set of spacers 121, 122, or indirectly by disposing an intermediate layer therebetween. In the case where the second spacer material 130 is formed as a conformal layer covering all surfaces of the first set of spacers 121, 122, an etch-back process can be performed after the layer formation to define the second set of spacers. The etch-back process can include, for example, an anisotropic etching process similar to that discussed above for defining the first set of spacers 121, 122.

[0052] 5a and 5b, where the side surfaces of the first and second spacers 121, 122 are provided with corresponding spacers forming a second set of spacers 131, 132, 133, 134. The second set of spacers 131, 132, 133, 134 may be formed of a dielectric material, such as silicon nitride, or a low-k dielectric such as SiCO.

[0053] In a subsequent step, the gaps between the second set of spacers 131, 132, 133, 134 can be filled with a first filler material 140. The first filler material 140, which can include a carbon-based material similar to those discussed above with respect to the mandrel material, is etched back to form recesses 150 between the second set of spacers 131, 132, 133, 134. As shown in Figures 6a and 6b, the recesses 150 can be disposed on the topmost portions of the second set of spacers 131, 132, 133, 134. Due to the geometry of the second set of spacers 131, 132, 133, 134, the recesses 150 extending therebetween can be considered trenches extending along the spacers. As will be shown later, the depth of the recesses 150 can determine the thickness of the final mask structure.

[0054] In Figures 7a and 7b, a second filler material 160 (e.g., silicon dioxide) is disposed in the recess 150. The second filler material can be deposited on top of the structure shown in Figures 7a and 7b and polished by CMP to expose the top surfaces of the first and second sets of fins. The second filler material 160 disposed in the recess 150 can form dummy mask lines that can later be used to define mask lines for the final mask layer.

[0055] 8a-d, 9a-d and 10a-d show the steps of forming a final mask layer on the semiconductor fin structure 100. Two alternative examples will be provided: a first flow in Figures "a" and "b" and an alternative flow in Figures "c" and "d".

[0056] After providing the second filler material 160 to form the dummy mask lines, at least the top portions 170 of the first set of spacers 121, 122 can be recessed to form trenches extending along the spacers. In Figures 8a and 8b, the material of the first set of spacers 121, 122 is selectively etched relative to the second set of spacers 131, 132, 133, 134 to maintain the top portions of the second set of spacers 131, 132, 133, 134. In the case where the spacer material is amorphous silicon and the second spacer material is silicon nitride, the amorphous silicon can be selectively etched relative to the adjacent silicon nitride.

[0057] In Figures 8c and 8d, the second spacer material is also etched so that the recess includes the top portions 170 of the first set of spacers 121, 122 and the second set of spacers 131, 132, 133, 134. Preferably, this is done in a single etch process capable of etching both materials (e.g., amorphous silicon and silicon nitride). Alternatively, two different etch processes may be used.

[0058] Figures 9a to 9d show the structure after providing a mask layer material 180 between the dummy mask lines. For example, the mask layer material 180 can be silicon nitride and can be provided in a recess fill process, preferably followed by CMP that stops on the material of the dummy mask lines. Figures 9a and 9b show the mask layer material covering the underlying first set of spacers 121, 122, while Figures 9c and 9d show an alternative process in which the mask layer material 180 also covers the underlying second set of spacers 131, 132, 133, 134.

[0059] Figures 10a to 10d show the mask layer 190 after removing the dummy mask lines and the first filler material 140. In Figures 10a and 10b, the mask layer 190 is formed from the mask layer material 180 and the second set of spacers 131, 132, 133, 134, where the mask layer material 180 covers the underlying first set of spacers 121, 122. In Figures 10c and 10d, the mask layer 190 is formed from the mask layer material 180 covering the first set of spacers 121, 122 and the second set of spacers 131, 132, 133, 134.

[0060] By removing the first filler material defined in the gaps between the second set of spacers, the mask layer 190 can be prepared for a subsequent replacement gate process to contact the exposed fin structure in the gaps. This can include forming a dummy structure, such as an oxide or nitride, in place of the metal gate during a high-temperature step. After completing these steps (which can include, for example, a source / drain implant activation anneal), the dummy structure can be etched away, a gate dielectric can be grown or deposited, and the final metal gate can be deposited in the gate track defined between the spacers of the second set of spacers.

[0061] In the above, the inventive concept has been mainly described with reference to a limited number of embodiments. However, as will be readily appreciated by those skilled in the art, other embodiments than the above described embodiments may also fall within the scope of the invention as defined in the appended claims.

Claims

1. A method for forming a mask layer (190) on a semiconductor fin structure (100), the method comprising the following steps: forming a mandrel (110) on the fin structure; providing a first spacer material (120) on the mandrel thereby forming a first set of spacers comprising first spacers (121) at a first side surface of the mandrel and second spacers (122) at a second side surface of the mandrel, Remove the mandrel; providing a second spacer material (130) on the first and second spacers, thereby forming a second set of spacers (131, 132, 133, 134) disposed at side surfaces of the first set of spacers; providing a first filler material (140) between the second set of spacers; etching a top portion of the first filler material to form recesses (150) between the second set of spacers; providing a second filler material (160) in the recess, the second filler material forming a set of dummy mask lines; Recessing at least a top portion (170) of a first set of spacers; providing a mask layer material (180) between the dummy mask lines; as well as removing the dummy mask lines and the first filler material, After providing the first spacer material, an etch-back process is performed to remove the first spacer material from the fin structure.

2. The method according to claim 1, wherein The mandrel is formed from a spin-on carbon material.

3. The method according to claim 1, wherein The first spacer material is provided by an atomic layer deposition (ALD) process.

4. The method according to claim 3, wherein: The first spacer material includes amorphous silicon.

5. The method according to claim 1, wherein The second spacer material includes a dielectric material.

6. The method according to claim 5, wherein: The second spacer material includes silicon nitride.

7. The method according to claim 5 or 6, wherein: An etch-back process is performed after providing the second spacer material to remove the second spacer material from the fin structure.

8. The method of claim 1, wherein: The first filler material includes a spin-on carbon material.

9. The method of claim 1, further comprising: The top portions of the second set of spacers are recessed, and then a mask layer material is provided between the dummy mask lines.

10. The method of claim 1, wherein: The second filler material includes silica.

11. The method of claim 1, wherein: The mask layer includes silicon dioxide or hafnium dioxide.

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