High voltage, high drive, high power supply rejection ratio LDO

Abstract

A high-voltage, high-drive, high-power supply rejection ratio LDO belongs to the field of LDO technology. The present invention is aimed at the problems of high noise and poor circuit stability in the prior art for improving the power supply rejection ratio of the LDO circuit with off-chip capacitors. It includes a common-source and common-gate resistive source degradation circuit and a dynamic compensation circuit. The common-source and common-gate resistive source degradation circuit uses an NMOS differential pair tube input to obtain a low-voltage difference fixed primary output voltage; the dynamic compensation circuit uses dynamic zero point compensation and dynamic biasing to the primary output voltage to obtain the final output voltage. The present invention can significantly reduce the output voltage noise and ensure the stability of the operating point.

Description

Technical Field

[0001] The invention relates to a high-voltage, high-drive, high-power supply rejection ratio LDO, and belongs to the technical field of LDO. Background Art

[0002] LDO (Low Dropout Linear Regulator) is a very critical part of integrated circuits. It is the core component of advanced systems such as data converters, precision amplifiers, and VCOs (voltage-controlled oscillators). These advanced systems all require high power supply rejection ratio, low noise, and high current power supply. The noisy power supply output by DCDC cannot meet the use requirements of the advanced systems due to its large ripple. High-performance LDO can avoid the above drawbacks and greatly reduce the probability of the performance of the advanced system being affected by noise. Therefore, the high power supply rejection ratio and low noise design of LDO are crucial.

[0003] LDO with off-chip capacitors is mainly dominated by 1 / f noise in the low frequency band, which is much higher than the thermal noise of the device in the low frequency band. Resistors are passive components that mainly contribute to thermal noise. Transforming ordinary MOS tube current sources into resistive source degeneration current sources can significantly reduce the low-frequency noise of current output. Therefore, resistive source degeneration structures are widely used in low-noise LDOs to reduce noise.

[0004] The worst point of the power supply rejection ratio of the LDO with off-chip capacitors is at the loop unity gain bandwidth. Using PMOSFET power tubes can achieve low voltage difference and good reliability, but its PSR (primary side feedback) is worse than that of NMOSFET, and a high power supply rejection ratio needs to be achieved by improving the internal circuit structure.

[0005] The modification of the LDO circuit in the prior art often causes the working point of the LDO to change to a great extent under the premise of process, voltage and temperature (PVT) changes, thereby affecting the performance of the LDO circuit and its normal working state. Summary of the invention

[0006] In view of the problems of large noise and poor circuit stability in the prior art of modifying an LDO circuit with an off-chip capacitor to improve the power supply rejection ratio, the present invention provides a high-voltage, large-drive, high power supply rejection ratio LDO.

[0007] A high-voltage, high-drive, high-power supply rejection ratio LDO of the present invention comprises a common-source and common-gate resistive source degradation circuit and a dynamic compensation circuit.

[0008] The common-source and common-gate resistive source degeneration circuit adopts NMOS differential pair tube input to obtain a low voltage difference fixed primary output voltage;

[0009] The dynamic compensation circuit uses dynamic zero point compensation and dynamic biasing to the first-level output voltage to obtain a final output voltage.

[0010] According to the high-voltage, high-drive, high-PSRR LDO of the present invention, the common-source and common-gate resistive source degradation circuit includes MOS tube Mn0, MOS tube Mn1, MOS tube Mn2, MOS tube Mn3, MOS tube Mp0, MOS tube Mp1, resistor R0, resistor R2, resistor R3 and a current source.

[0011] The source electrodes of the MOS transistor Mn0 and the MOS transistor Mn1 are connected to one end of a current source, and the other end of the current source is grounded;

[0012] The gate of the MOS tube Mn0 is connected to the primary output voltage connection terminal VREF, and the resistor R0 is connected between the drain and the low-voltage power supply; the resistor R1 is connected between the drain of the MOS tube Mn1 and the low-voltage power supply;

[0013] The drain of the MOS tube Mn0 is connected to the source of the MOS tube Mp0, the drain of the MOS tube Mp0 is connected to the drain of the MOS tube Mn2, the resistor R2 is connected between the source of the MOS tube Mn2 and the grounding point; the drain of the MOS tube Mn2 is connected to the gate;

[0014] The gate of MOS tube Mp0 is connected to the gate of MOS tube Mp1, the source of MOS tube Mp1 is connected to the drain of MOS tube Mn1, the drain of MOS tube Mp1 is connected to the drain of MOS tube Mn3, the gate of MOS tube Mn3 is connected to the gate of MOS tube Mn2, and the source of MOS tube Mn3 is connected to the ground point with resistor R3;

[0015] The drain of the MOS tube Mn3 serves as a primary output voltage connection terminal VREF.

[0016] According to the high-voltage, high-drive, high-power supply rejection ratio LDO of the present invention, the common-source and common-gate resistive source degeneration circuit (100) further comprises a MOS tube Mn5 and a capacitor C0,

[0017] The drain of the MOS transistor Mn3 is connected to the gate of the MOS transistor Mn5 , the source of the MOS transistor Mn5 is grounded, and a capacitor C0 is connected between the drain and the gate.

[0018] According to the high-voltage, high-drive, high-power supply rejection ratio LDO of the present invention, the dynamic compensation circuit (200) comprises a MOS transistor Mn4, a MOS transistor Mn6, a MOS transistor Mp2, a MOS transistor Mp3, a MOS transistor PMOSFET, a resistor R4, a resistor R5 and a capacitor C1,

[0019] The gate of the MOS tube Mn5 is connected to the gate of the MOS tube Mn4, the source of the MOS tube Mn4 is grounded, the drain is connected to the source of the MOS tube Mn6, the gate of the MOS tube Mn6 is connected to a fixed bias voltage, the drain of the MOS tube Mn6 is connected to one end of the resistor R4, and the other end of the resistor R4 is connected to a high-voltage power supply; the drain of the MOS tube Mn6 is connected to the gate of the MOS tube Mp2, the gate of the MOS tube Mp2 is connected to the drain, the source of the MOS tube Mp2 is connected to one end of the resistor R5, the other end of the resistor R5 is connected to the high-voltage power supply, and the capacitor C1 is connected between the other end of the resistor R5 and the drain of the MOS tube Mn4; the gate of the MOS tube Mp2 is connected to the gate of the MOS tube Mp3, the gate of the MOS tube Mp3 is connected to the drain, and the source of the MOS tube Mp3 is connected to the high-voltage power supply; the gate of the MOS tube Mp3 is connected to the gate of the MOS tube PMOSFET, the source of the MOS tube PMOSFET is connected to the high-voltage power supply, and the drain serves as an intermediate voltage output terminal.

[0020] According to the high-voltage, high-drive, high-power supply rejection ratio LDO of the present invention, the dynamic compensation circuit (200) further includes an off-chip resistor R EXT 0. External resistance R EXT 1 and the external capacitor C L ,

[0021] The off-chip resistor R is connected in series between the drain of the MOS tube PMOSFET and the ground point. EXT 1 and the off-chip resistor R EXT 0, external capacitance C L With the external resistor R EXT 1 and the off-chip resistor R EXT 0 parallel connection;

[0022] External resistor R EXT 1 and the off-chip resistor R EXT 0 is used as a connection terminal VFB, and the connection terminal VFB is connected to the gate of the MOS tube Mn1.

[0023] Beneficial effects of the present invention: the input voltage range of the present invention can be 2.6V-40V; the output drive current can be as high as 200mA; the off-chip capacitance is as low as 1uF; the power supply rejection ratio at 1MHz frequency is as high as 50dB; the minimum voltage difference of the circuit is 250mV; and the fixed output voltage has low noise, which is only 10.5uVrms at room temperature. The circuit of the present invention adopts NMOS differential pair input and resistive source degenerate common source and common gate structure. The loop compensation of the circuit adopts dynamic zero point compensation and dynamic bias circuit to achieve low no-load static power consumption and heavy-load loop stability. At the same time, a feedforward zero point can be added at the high frequency point 1MHz to improve PSR.

[0024] The circuit of the present invention can significantly reduce the noise of the LDO fixed output voltage, and at the same time adopts matching and dynamic compensation methods to ensure the stability of the operating point under the conditions of process, voltage, temperature and full load. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a circuit schematic diagram of the high voltage, large drive and high power supply rejection ratio LDO of the present invention;

[0026] Figure 2 It is the reference low noise principle diagram of the present invention. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0029] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0030] Specific implementation method 1. Combination Figure 1 As shown, the present invention provides a high voltage, high drive, high power supply rejection ratio LDO, including a common source and common gate resistive source degradation circuit 100 and a dynamic compensation circuit 200,

[0031] The common-source and common-gate resistive source degeneration circuit 100 uses NMOS differential pair input to obtain a low-voltage difference fixed primary output voltage;

[0032] The dynamic compensation circuit 200 uses dynamic zero point compensation and dynamic biasing to the primary output voltage to obtain a final output voltage.

[0033] Further, combined with Figure 1 As shown, the common-source and common-gate resistive source degradation circuit (100) comprises a MOS transistor Mn0, a MOS transistor Mn1, a MOS transistor Mn2, a MOS transistor Mn3, a MOS transistor Mp0, a MOS transistor Mp1, a resistor R0, a resistor R2, a resistor R3 and a current source.

[0034] The source electrodes of the MOS transistor Mn0 and the MOS transistor Mn1 are connected to one end of a current source, and the other end of the current source is grounded;

[0035] The gate of the MOS tube Mn0 is connected to the primary output voltage connection terminal VREF, and the resistor R0 is connected between the drain and the low-voltage power supply; the resistor R1 is connected between the drain of the MOS tube Mn1 and the low-voltage power supply;

[0036] The drain of the MOS tube Mn0 is connected to the source of the MOS tube Mp0, the drain of the MOS tube Mp0 is connected to the drain of the MOS tube Mn2, the resistor R2 is connected between the source of the MOS tube Mn2 and the grounding point; the drain of the MOS tube Mn2 is connected to the gate;

[0037] The gate of MOS tube Mp0 is connected to the gate of MOS tube Mp1, the source of MOS tube Mp1 is connected to the drain of MOS tube Mn1, the drain of MOS tube Mp1 is connected to the drain of MOS tube Mn3, the gate of MOS tube Mn3 is connected to the gate of MOS tube Mn2, and the source of MOS tube Mn3 is connected to the ground point with resistor R3;

[0038] The drain of the MOS tube Mn3 serves as a primary output voltage connection terminal VREF.

[0039] Going a step further, combined Figure 1 As shown, the common-source and common-gate resistive source degradation circuit 100 further includes a MOS tube Mn5 and a capacitor C0.

[0040] The drain of the MOS transistor Mn3 is connected to the gate of the MOS transistor Mn5 , the source of the MOS transistor Mn5 is grounded, and a capacitor C0 is connected between the drain and the gate.

[0041] Going a step further, combined Figure 1 As shown, the dynamic compensation circuit 200 includes a MOS transistor Mn4, a MOS transistor Mn6, a MOS transistor Mp2, a MOS transistor Mp3, a MOS transistor PMOSFET, a resistor R4, a resistor R5 and a capacitor C1.

[0042] The gate of the MOS tube Mn5 is connected to the gate of the MOS tube Mn4, the source of the MOS tube Mn4 is grounded, the drain is connected to the source of the MOS tube Mn6, the gate of the MOS tube Mn6 is connected to a fixed bias voltage, the drain of the MOS tube Mn6 is connected to one end of the resistor R4, and the other end of the resistor R4 is connected to a high-voltage power supply; the drain of the MOS tube Mn6 is connected to the gate of the MOS tube Mp2, the gate of the MOS tube Mp2 is connected to the drain, the source of the MOS tube Mp2 is connected to one end of the resistor R5, the other end of the resistor R5 is connected to the high-voltage power supply, and the capacitor C1 is connected between the other end of the resistor R5 and the drain of the MOS tube Mn4; the gate of the MOS tube Mp2 is connected to the gate of the MOS tube Mp3, the gate of the MOS tube Mp3 is connected to the drain, and the source of the MOS tube Mp3 is connected to the high-voltage power supply; the gate of the MOS tube Mp3 is connected to the gate of the MOS tube PMOSFET, the source of the MOS tube PMOSFET is connected to the high-voltage power supply, and the drain serves as an intermediate voltage output terminal.

[0043] The circuit of this embodiment adopts diode following and dynamic compensation to achieve wide-band high PSR characteristics. The MOS transistor Mn5, MOS transistor Mn4 and capacitor C0 realize matching and dynamic compensation in the circuit.

[0044] Going a step further, combined Figure 1 As shown, the dynamic compensation circuit 200 further includes an off-chip resistor R EXT 0. External resistance R EXT 1 and the external capacitor C L ,

[0045] The off-chip resistor R is connected in series between the drain of the MOS tube PMOSFET and the ground point. EXT 1 and the off-chip resistor R EXT 0, external capacitance C L With the external resistor R EXT 1 and the off-chip resistor R EXT 0 parallel connection;

[0046] External resistor R EXT 1 and the off-chip resistor R EXT 0 is used as a connection terminal VFB, and the connection terminal VFB is connected to the gate of the MOS tube Mn1.

[0047] The off-chip resistor R EXT 1 is a variable resistor.

[0048] The LDO circuit of the present invention adopts a dynamic output resistance method to increase the secondary pole as the load increases in order to achieve large drive and ensure loop stability. The corresponding components include MOS tube Mp2, MOS tube Mp3, resistor R4 and resistor R5.

[0049] Combine the following Figure 2 , the process of realizing the low noise reference voltage circuit of the present invention is described:

[0050] In the LDO of the present invention, the circuit for realizing noise shaping includes: MOS tube Mn0, MOS tube Mn1, MOS tube Mp0, MOS tube Mp1, capacitor C0 and bias current source. This circuit adopts MOS tube asymmetric mirror bias circuit, MOS tube Mn0 is a proportional tube, MOS tube Mn1 is an inverse proportional tube, MOS tube Mp0 is a proportional tube, and MOS tube Mp1 is an inverse proportional tube; it can be judged that, Figure 2 The voltage between VREF_NOISE and VREF is equivalent to high impedance, and thus forms a noise shaping circuit with the capacitor C0.

[0051] The LDO of the present invention uses a resistive source degenerate common source and common gate structure, dynamic compensation and high frequency compensation, has a high PSR in a wide frequency band, improves the PSR by adding a feedforward zero at a high frequency, and uses a large RC method inside the circuit to filter out reference noise, so that the LDO fixed output voltage noise is greatly reduced; at the same time, it has low power consumption and low noise characteristics, and ensures a stable operating point under no-load and full-load conditions, as well as under process, voltage and temperature fluctuations.

[0052] Although the present invention is described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the present invention. It should therefore be understood that many modifications may be made to the exemplary embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that the various dependent claims and features described herein may be combined in a manner different from that described in the original claims. It should also be understood that the features described in conjunction with a single embodiment may be used in other described embodiments.

Claims

1. A high voltage, high drive, high power supply rejection ratio LDO, characterized in that: It comprises a common-source and common-gate resistive source degradation circuit (100) and a dynamic compensation circuit (200), The common-source and common-gate resistive source degeneration circuit (100) adopts NMOS differential pair tube input to obtain a low voltage difference fixed primary output voltage; The dynamic compensation circuit (200) uses dynamic zero point compensation and dynamic biasing methods on the primary output voltage to obtain a final output voltage; The common-source and common-gate resistive source degradation circuit (100) comprises a MOS transistor Mn0, a MOS transistor Mn1, a MOS transistor Mn2, a MOS transistor Mn3, a MOS transistor Mp0, a MOS transistor Mp1, a resistor R0, a resistor R1, a resistor R2, a resistor R3 and a current source. The source electrodes of the MOS transistor Mn0 and the MOS transistor Mn1 are connected to one end of a current source, and the other end of the current source is grounded; The gate of the MOS tube Mn0 is connected to VREF, and the resistor R0 is connected between the drain and the low-voltage power supply; the resistor R1 is connected between the drain of the MOS tube Mn1 and the low-voltage power supply; The drain of the MOS tube Mn0 is connected to the source of the MOS tube Mp0, the drain of the MOS tube Mp0 is connected to the drain of the MOS tube Mn2, the resistor R2 is connected between the source of the MOS tube Mn2 and the grounding point; the drain of the MOS tube Mn2 is connected to the gate; The gate of MOS tube Mp0 is connected to the gate of MOS tube Mp1, the source of MOS tube Mp1 is connected to the drain of MOS tube Mn1, the drain of MOS tube Mp1 is connected to the drain of MOS tube Mn3, the gate of MOS tube Mn3 is connected to the gate of MOS tube Mn2, and the source of MOS tube Mn3 is connected to the ground point with resistor R3; The drain of the MOS tube Mn3 outputs the primary output voltage; The common-source and common-gate resistive source degeneration circuit (100) further comprises a MOS tube Mn5 and a capacitor C0. The drain of the MOS tube Mn3 is connected to the gate of the MOS tube Mn5, the source of the MOS tube Mn5 is grounded, and a capacitor C0 is connected between the drain and the gate; The dynamic compensation circuit (200) comprises a MOS transistor Mn4, a MOS transistor Mn6, a MOS transistor Mp2, a MOS transistor Mp3, a MOS transistor PMOSFET, a resistor R4, a resistor R5 and a capacitor C1. The gate of the MOS tube Mn5 is connected to the gate of the MOS tube Mn4, the source of the MOS tube Mn4 is grounded, the drain is connected to the source of the MOS tube Mn6, the gate of the MOS tube Mn6 is connected to a fixed bias voltage, the drain of the MOS tube Mn6 is connected to one end of the resistor R4, and the other end of the resistor R4 is connected to a high-voltage power supply; the drain of the MOS tube Mn6 is connected to the gate of the MOS tube Mp2, the gate of the MOS tube Mp2 is connected to the drain, the source of the MOS tube Mp2 is connected to one end of the resistor R5, the other end of the resistor R5 is connected to the high-voltage power supply, and the capacitor C1 is connected between the other end of the resistor R5 and the drain of the MOS tube Mn4; the gate of the MOS tube Mp2 is connected to the gate of the MOS tube Mp3, the gate of the MOS tube Mp3 is connected to the drain, and the source of the MOS tube Mp3 is connected to the high-voltage power supply; the gate of the MOS tube Mp3 is connected to the gate of the MOS tube PMOSFET, the source of the MOS tube PMOSFET is connected to the high-voltage power supply, and the drain serves as the final output voltage output terminal.

2. The high voltage, high drive, high power supply rejection ratio LDO according to claim 1, characterized in that: The dynamic compensation circuit (200) further includes an off-chip resistor R EXT 0. External resistance R EXT 1 and the external capacitor C L , The off-chip resistor R is connected in series between the drain of the MOS tube PMOSFET and the ground point. EXT 1 and the off-chip resistor R EXT 0, external capacitance C L With the external resistor R EXT 1 and the off-chip resistor R EXT 0 parallel connection; External resistor R EXT 1 and the off-chip resistor R EXT 0 is used as a connection terminal VFB, and the connection terminal VFB is connected to the gate of the MOS tube Mn1.

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