A chip with a composite layer and its application in biological detection

Abstract

The present invention provides a chip with a composite layer and its application in biological detection. The chip comprises at least a first base layer and a second base layer disposed one above the other. The first base layer is provided with at least one first blind via leading to the second base layer. The chip is also provided with at least one metalized via extending through the second base layer. Electrodes are disposed below the first blind vias. The chip is provided with contacts, and the electrodes and contacts are connected via circuits. The present invention combines plastic and metal to develop a chip with a composite layer. Through the rational layout of the chip's base layer, circuit layer, and internal circuitry, the chip achieves its basic functions. The chip is simple to manufacture and inexpensive.

Description

Technical Field

[0001] The present invention belongs to the technical field of chips, and in particular relates to a chip with a composite layer and application thereof in biological detection. Background Art

[0002] With the rapid development of electronics and information technology, my country has entered the Information Age. Chips, as micro-integrated circuits, are widely used in a variety of electronic products and systems, including computers, mobile phones, home appliances, automobiles, high-speed rail, power grids, medical equipment, robotics, and industrial control. They are the core cornerstone of high-end manufacturing. Chips are composed of a substrate and circuits. The substrate is made of single-crystal silicon wafers. Components such as metal-oxide semiconductor field-effect transistors (MOSFETs) and bipolar junction transistors (BJTs) are manufactured using techniques such as photolithography, doping, and chemical mechanical polishing (CMP). Thin film and CMP techniques are then used to create the circuits, completing chip production.

[0003] At present, the mainstream chip substrate is single crystal silicon. In electronic components and chips made of silicon crystal, the carrier energy can reach 0.1m 2 / Vs high mobility and fast transmission. However, the current silicon crystal production process is extremely expensive, often unaffordable for the consumer electronics industry, which has huge demand for these products, and hinders the widespread use of these chips. Therefore, researchers are committed to finding and developing other low-cost alternatives. Plastic, as an inexpensive and highly malleable material, has attracted the attention of scientists. Currently, the main research direction is to physically and chemically modify insulating plastic materials to make them conductive. For example, Austrian scientists have successfully created a solar cell using plastics such as polystyrene, achieving an efficiency of 3%. In 2011, scientists at the Belgian Microelectronics Research Center developed a prototype plastic chip. Philips in the Netherlands has launched a thin, flexible plastic computer display made of plastic-based semiconductors. Japanese scientists have developed a flexible conductive plastic containing hundreds of organic computer chips, and have used this conductive plastic to create new flat-panel displays and electronic tags. Although research on plastic-based semiconductors or conductive plastics has achieved some results, large-scale, low-cost application is still a long way off.

[0004] Currently, plastic and metal are commonly used as chip packaging materials, which are suitable for most chip applications. If ordinary plastic materials can be applied to the chip substrate, it will greatly reduce the production cost of the chip. However, there is a problem.

[0005] Patent CN201710699800.0 discloses an online automatic monitoring system for contaminated areas based on wireless remote control. The system's conductivity sensor includes an insulating plastic substrate with a wavy upper surface, coated with insulating porcelain. Metal clips are provided at each end of the insulating plastic substrate, tightly fitting the insulating porcelain. Protective sleeves surround the metal clips. The conductivity sensor also includes a driver chip connected to the two metal clips, which are connected to the motherboard. This invention connects electrodes to the metal clips to enable the operation of the entire monitoring system.

[0006] In addition, chips have important application value in the biological field, especially in genetic testing. Chips can replace traditional laser lenses, fluorescent dyes, etc. to become new sequencers. Faced with massive amounts of genetic testing and analysis data, the application of multifunctional chips is the future development direction. At present, the new generation of gene sequencing technology uses nanometer-sized pores as sensors. When nucleic acid molecules pass through the nanopores, the ion current passing through each nanopore is detected. According to the current characteristics of different bases when passing through the pores, the gene sequence of each genomic fragment is determined by tracking the changes in current. For example, patent CN201810019657.0 discloses a disposable nanopore biosensor, including a substrate, an electrode layer and a top cover stacked in sequence. The top cover is provided with micropores with a diameter of 5-200μm. The micropores are used to inject nanopores and phospholipid films. The substrate and the top cover are both plastic layers. The electrodes are a pair of silver electrodes arranged on the surface of the substrate. The micropores are opened in an insulating cover. The insulating cover covers the surface of a silver electrode. The micropores are arranged on the top of the silver electrode so that the silver electrode is exposed only through the micropores.

[0007] Patent CN200880126160.3 discloses a method for forming a layer of aqueous solution separating two volumes. In the formed device, the upper part is a device containing a chamber, and the lower part includes a body of non-conductive material with at least one groove leading to the chamber. A biolayer lipid membrane (BLM) is formed between the chamber and the groove. The device has a pair of electrodes, the upper electrode is located in the chamber and leads out of the chamber, and the lower electrode is located at the bottom of the groove and leads out of the non-conductive material body.

[0008] As chips are increasingly used in nanopore genetic testing, their structure must adapt to the requirements of massive genetic testing, achieving a more rational structure, easier operation, and more diverse functions. This invention combines plastic and metal materials to develop a chip with a composite layer. Through the rational layout of the composite layer, the chip achieves its basic function for nanopore genetic testing. Summary of the Invention

[0009] To achieve the above-mentioned objectives, the present invention provides a chip having a composite layer, the chip comprising at least a first base layer and a second base layer arranged one above the other, the first base layer being provided with at least one first blind hole leading to the second base layer, the chip also being provided with at least one metallized via passing through the second base layer, an electrode being provided below the first blind hole, the chip being provided with contacts, and the electrodes and contacts being connected via circuits.

[0010] A first electrode is further provided on the upper and lower surfaces of the first base layer or above the first base layer. The chip is further provided with a first contact. The first electrode and the first contact are connected via a circuit.

[0011] Preferably, an inner layer circuit is provided in the second base layer, and more preferably, an inner layer circuit extending outward is provided on the inner wall of the metallized via, and the inner layer circuit extends and is embedded in the interior of the first base layer and the second base layer to form an interconnected circuit; the interconnected circuit can extend to and connect other circuit components inside the chip, thereby realizing the interconnection of multiple components, which is conducive to the chip to realize multiple functional applications.

[0012] Preferably, at least one third base layer is disposed between the first base layer and the second base layer. More preferably, 1 to 5 third base layers are disposed between the first base layer and the second base layer. For example, 1, 2, 3, 4, or 5 third base layers are disposed between the first base layer and the second base layer.

[0013] In one form of the chip described in the present invention, the first base layer is further provided with at least one second blind via leading to the second base layer, and a first electrode is provided below the second blind via. The chip is provided with at least two metallized vias extending through the second base layer, and the outer walls of the metallized vias are provided with inner-layer circuits. The first electrode is connected to the first metallized via via a metal circuit, and the electrode is connected to the second metallized via via a metal circuit. A first contact is provided on the inner-layer circuit of the first metallized via or on the metal circuit extending from the lower surface of the second base layer; and a contact is provided on the inner-layer circuit of the second metallized via or on the metal circuit extending from the lower surface of the second base layer.

[0014] In one embodiment of the present invention, a second blind via is provided on the first base layer, leading to the second base layer. A first electrode is provided below the second blind via. The first electrode is connected to the first metallized via via an extended metal circuit. The first contact is provided on the extended metal circuit on the lower surface of the second base layer. The first and second metallized vias penetrate the second base layer but not the first base layer. The first and second metallized vias are provided with inner circuits in the second base layer, and the inner circuits extend around the walls of the first and second metallized vias. The contact is located on the extended metal circuit on the lower surface of the second base layer through the second metallized via. The electrode is provided at the bottom of the first blind via and connected to the second metallized via via the extended metal circuit, thereby indirectly connecting the inner circuit and the ring-shaped metal circuit on the lower surface of the second base layer, and further connecting the contact.

[0015] When in use, the first contact and the contact are connected to a power source, so that a voltage can be formed between the first electrode and the electrode, and the conductive medium is connected above the first blind hole and the second blind hole.

[0016] In another form of the chip described in the present invention, the first electrode is arranged on the upper surface of the first base layer. Preferably, the first electrode is arranged at the upper edge of the first metallized via. More preferably, the first electrode is arranged near the upper end of the first metallized via.

[0017] The electrode is arranged on the lower surface of the bottom of the first base layer and passes through the bottom of the first blind hole. More preferably, the electrode is arranged between the first base layer and the second base layer. More preferably, the electrode covers the entire bottom surface of the first blind hole. Particularly preferably, the electrode extends to the second metallized via.

[0018] The first blind hole is located in the first base layer, an electrode is provided at the bottom of the first blind hole, and the first blind hole, the first electrode and the electrode constitute a hole electrode.

[0019] The first contact is located on an extended metal line of the first metalized via on the upper surface of the first base layer or the lower surface of the second base layer, and the contact is located on an extended metal line of the second metalized via on the upper surface of the first base layer or the lower surface of the second base layer. The first electrode can be connected to the first contact through a ring-shaped metal line and an inner layer line on the upper surface of the first base layer or the lower surface of the second base layer via the first metalized via, and the electrode can be connected to the contact through a ring-shaped metal line and an inner layer line on the upper surface of the first base layer or the lower surface of the second base layer via the second metalized via.

[0020] More preferably, the metal circuit and the inner layer circuit are copper foil.

[0021] The first base layer and the second base layer are made of plastic.

[0022] Preferably, the material of the first base layer is plastic, preferably, the material of the first base layer is a polyimide resin board, FR-4 board, FR-1 board or CEM-1 / 3 board, more preferably, the FR-4 board is a glass fiber board or epoxy resin board with FR-4 grade. In a specific embodiment of the present invention, the material of the first base layer is a polyimide resin board.

[0023] The thickness of the first base layer is 0.05-0.5 mm, preferably, the thickness of the first base layer is 0.08-0.2 mm. In a specific embodiment of the present invention, the thickness of the first base layer is 0.1 mm.

[0024] The first and second blind holes are provided on the upper surface of the first base layer. Preferably, the first and second blind holes are circular holes. Preferably, the diameter of the first blind hole is 0.05-0.2 mm, more preferably, the diameter of the first blind hole is 0.1-0.15 mm. The first blind hole can be formed by laser drilling. Preferably, the diameter of the second blind hole is 0.5-2 mm, more preferably, the diameter of the second blind hole is 1-1.5 mm. The second blind hole can be formed by laser drilling.

[0025] The second base layer is made of plastic. Preferably, the second base layer is made of a polyimide resin board, an FR-4 board, an FR-1 board, or a CEM-1 / 3 board. More preferably, the second base layer is made of an FR-4 board. More preferably, the FR-4 board is a glass fiber board or an epoxy resin board having an FR-4 grade. In one embodiment of the present invention, the second base layer is made of an FR-4 epoxy resin board.

[0026] The materials of the first and second base layers are insulated, ensuring that the current signal of the chip can only be conducted by the metal circuits and inner-layer circuits, making it easy to design metal circuits and inner-layer circuits with different structures according to actual needs; the materials of the first and second base layers are corrosion-resistant, and while ensuring a certain strength, they also have strong impact resistance, making the chip widely applicable; the materials of the first and second base layers are highly plastic, making it easy to manufacture chips using PCB processing technology.

[0027] In a specific embodiment of the present invention, the chip includes a first base layer and a second base layer.

[0028] In another specific embodiment of the present invention, the chip includes a first base layer, a second base layer, and a third base layer between the first base layer and the second base layer.

[0029] The present invention also provides the use of the chip in biological detection, preferably, the use of the chip in nucleic acid sequencing, and more preferably, the use of the chip in nanopore nucleic acid sequencing.

[0030] The inner layer circuit of the chip can be connected to the required detection and analysis equipment. The hole electrode, first contact and contact of the chip are connected to the current, and the current is then conducted to the required detection and analysis equipment through the inner layer circuit. Therefore, the chip realizes the control function of the detection and analysis equipment.

[0031] The present invention also provides the use of the chip as a biomonitoring chip, preferably as a nucleic acid sequencing chip, and more preferably as a nanopore sequencing chip. Compared to silicon-based chips, the chip can realize circuit layout across multiple substrates, and is low-cost and simple to manufacture. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a chip structure diagram of the present invention.

[0033] Figure 2 This is an optional chip structure diagram of the present invention.

[0034] Figure 3 It is a structural diagram of the chip of the present invention applied to a nanopore gene sequencing device.

[0035] Figure 4 This is a structural diagram of the chip of the present invention applied to an optional nanopore gene sequencing device.

[0036] Figure 5 It is a structural diagram of the chip surface of the present invention.

[0037] Figure 6 This is an optional chip structure diagram of the present invention.

[0038] In the accompanying drawings, 1-first base layer, 2-second base layer, 3-first blind hole, 4-metal line, 401-first electrode, 402-electrode, 5-first metallized via, 501-second metallized via, 6-inner layer line, 7-first contact, 8-contact, 9-third base layer, 10-electrolyte chamber, 11-phospholipid layer membrane, 12-second blind hole. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention.

[0040] The present invention provides a chip with a composite layer, the chip including at least a first base layer 1 and a second base layer 2 arranged one above the other, the first base layer 1 being provided with at least one first blind hole 3 leading to the second base layer 2, the chip also being provided with at least one metallized via passing through the second base layer 2, an electrode 402 being provided under the first blind hole 3, the chip being provided with a contact 8, and the electrode 402 being connected to the contact 8 through a line.

[0041] All metal circuits in the following embodiments are copper foils.

[0042] Example 1

[0043] The chip structure of this embodiment is as follows Figure 1 As shown, the first base layer 1 is located on the upper part of the chip, the first base layer 1 is a polyimide resin board, and the thickness of the first base layer 1 is 0.1mm; a hole electrode is provided on the first base layer 1, and a first blind hole 3 is provided on the upper surface of the first base layer 1. The first blind hole 3 is a circular hole with a hole diameter of 0.1mm. The first blind hole 3 is formed by laser drilling technology. A metal circuit 4 is provided at the bottom of the first blind hole 3. The first blind hole 3 and the metal circuit 4 constitute a hole electrode; a first electrode 401 is provided near the upper end of the first metallized via 5, and an electrode 402 is provided between the first base layer 1 and the second base layer 2, and covers the entire bottom surface of the first blind hole 3. The electrode 402 extends to the second metallized via 501; the second base layer 2 is located below the first base layer 1 and is close to the first base layer 1. The second base layer 2 is an FR-4 epoxy resin board; the first metallized via The via 5 and the second metallized via 501 pass through the first base layer 1 and the second base layer 2. The inner layer circuit 6 is provided on the hole wall of the first metallized via 5 and the second metallized via 501. Multiple metal circuits of the inner layer circuit 6 extend into the first base layer 1 and the second base layer 2. The metal circuit 4 of the hole electrode is connected to the inner layer circuit 6 of the second metallized via 501; the first contact 7 is arranged on the metal circuit at the top or bottom of the first metallized via 5, and the contact 8 is arranged on the metal circuit at the top or bottom of the second metallized via 501. The first electrode 401 is connected to the first contact 7 through the metal circuit of the first metallized via 5 and the inner layer circuit 6, and the electrode 402 is connected to the contact 8 through the metal circuit of the second metallized via 501 and the inner layer circuit 6 to achieve interconnection, thereby realizing the circuit arrangement of the first base layer 1 and the second base layer 2.

[0044] Example 2

[0045] The chip structure of this embodiment is as follows Figure 2As shown, the first base layer 1 is located on the upper part of the chip, the first base layer 1 is a polyimide resin board, and the thickness of the first base layer 1 is 0.1 mm; a hole electrode is provided on the first base layer 1, and a first blind hole 3 is provided on the upper surface of the first base layer 1. The first blind hole 3 is a circular hole with a hole diameter of 0.1 mm. The first blind hole 3 is formed by laser drilling technology. A metal circuit 4 is provided at the bottom of the first blind hole 3. The first blind hole 3 and the metal circuit 4 constitute a hole electrode; a first electrode 401 is provided near the upper end of the first metallized via 5, and an electrode 402 is provided between the first base layer 1 and the third base layer 9, and covers the entire bottom surface of the first blind hole 3. The electrode 402 extends to the second metallized via 501; the third base layer 9 is located below the first base layer 1 and is in close contact with the first base layer 1, the second base layer 2 is located below the third base layer 9 and is in close contact with the third base layer 9, and the second base layer 2 and the third base layer 9 are both FR-4 epoxy resin boards. material; the first metallized via 5 and the second metallized via 501 pass through the first base layer 1, the third base layer 9 and the second base layer 2, and the inner layer circuit 6 is provided on the hole wall of the first metallized via 5 and the second metallized via 501. Multiple metal circuits of the inner layer circuit 6 extend into the first base layer 1, the third base layer 9 and the second base layer 2, and the metal circuit 4 of the hole electrode is connected to the inner layer circuit 6 of the second metallized via 501; the first contact 7 is arranged on the metal circuit at the top or bottom of the first metallized via 5, and the contact 8 is arranged on the metal circuit at the top or bottom of the second metallized via 501. The first electrode 401 is connected to the first contact 7 through the metal circuit of the first metallized via 5 and the inner layer circuit 6, and the electrode 402 is connected to the contact 8 through the metal circuit of the second metallized via 501 and the inner layer circuit 6 to achieve interconnection, thereby realizing the circuit arrangement of the first base layer 1, the third base layer 9 and the second base layer 2.

[0046] Example 3

[0047] The structure of the chip used in the nanopore gene sequencing device is as follows Figure 3As shown, the first substrate 1 is located on the top of the chip. This substrate is a polyimide resin sheet with a thickness of 0.1 mm. An electrolyte chamber 10 is located on the top of the chip to accommodate an electrolyte containing a DNA test sample. A via electrode is provided on the first substrate 1. A first blind hole 3 is provided on the top surface of the first substrate 1. This first blind hole 3 is a circular hole with a diameter of 0.1 mm and is formed using laser drilling. A metal trace 4 is provided at the bottom of the first blind hole 3. The first blind hole 3 and the metal trace 4 together form the via electrode. A first electrode 401 is located near the top of the first metalized via 5. An electrode 402 is located between the first substrate 1 and the second substrate 2, covering the entire bottom surface of the first blind hole 3. The electrode 402 extends to the second metalized via 501. A second substrate 2 is located below the first substrate 1 and is in close contact with the first substrate 1. This second substrate 2 is made of FR-4 epoxy resin. The first metallized via 5 and the second metallized via 501 extend through the first and second substrates 1 and 2 and are located outside the electrolyte chamber 10. Inner-layer circuits 6 are provided on the walls of the first and second metallized vias 5 and 501. Multiple metal lines of the inner-layer circuits 6 extend into the first and second substrates 1 and 2. The metal line 4 of the via electrode is connected to the inner-layer circuit 6 of the second metallized via 501. A first contact 7 is provided on the metal line at the top or bottom of the first metallized via 5, and a contact 8 is provided on the metal line at the top or bottom of the second metallized via 501. The first electrode 401 is connected to the first contact 7 via the metal line of the first metallized via 5 and the inner-layer circuit 6, and the electrode 402 is connected to the contact 8 via the metal line of the second metallized via 501 and the inner-layer circuit 6, thereby interconnecting and forming the circuit arrangement of the first and second substrates 1 and 2.

[0048] A phospholipid bilayer membrane 11 is provided between the electrolyte chamber 10 and the first blind hole 3, forming two chambers. A protein having a nanopore structure is embedded in the phospholipid bilayer membrane 11. When the first contacts 7 and 8 are powered on, that is, when the first electrodes 401 and 402 are powered on, the DNA test sample in the electrolyte chamber 10 moves under the action of the current and enters the first blind hole 3 through the nanopore of the protein. The current changes as different bases on the DNA pass through the nanopore are recorded to analyze the DNA sequence.

[0049] Example 4

[0050] The chip is used in an optional nanopore gene sequencing device structure such as Figure 4As shown, the first substrate 1 is located on the top of the chip. It is a polyimide resin sheet with a thickness of 0.1 mm. An electrolyte chamber 10 is located on the top of the chip to hold the electrolyte containing the DNA test sample. A via electrode is provided on the first substrate 1. A first blind hole 3 is provided on the top surface of the first substrate 1. This first blind hole 3 is a circular hole with a diameter of 0.1 mm and is formed using laser drilling. A metal trace 4 is provided at the bottom of the first blind hole 3. The first blind hole 3 and the metal trace 4 together form the via electrode. A first electrode 401 is located above the electrolyte chamber 10 and extends externally for connection to a power source. An electrode 402 is located between the first substrate 1 and the second substrate 2, covering the entire bottom surface of the first blind hole 3. The electrode 402 extends to the second metalized via 501. The second substrate 2 is located below and in close contact with the first substrate 1. The second substrate 2 is made of FR-4 epoxy resin. The second metallized via 501 extends through the first and second substrates 1 and 2 and is located outside the electrolyte chamber 10. An inner layer circuit 6 is provided on the wall of the second metallized via 501. Multiple metal traces of the inner layer circuit 6 extend into the first and second substrates 1 and 2. The metal trace 4 of the via electrode is connected to the inner layer circuit 6 of the second metallized via 501. A first contact 7 is provided on the first electrode 401, and a contact 8 is provided on the metal trace at the top or bottom of the second metallized via 501. The electrode 402 is connected to the contact 8 via the metal trace of the second metallized via 501 and the inner layer circuit 6, thereby achieving interconnection and forming the circuit arrangement of the first and second substrates 1 and 2.

[0051] A phospholipid bilayer membrane 11 is provided between the electrolyte chamber 10 and the first blind hole 3, forming two chambers. A protein having a nanopore structure is embedded in the phospholipid bilayer membrane 11. When the first contacts 7 and 8 are powered on, that is, when the first electrodes 401 and 402 are powered on, the DNA test sample in the electrolyte chamber 10 moves under the action of the current and enters the first blind hole 3 through the nanopore of the protein. The current changes as different bases on the DNA pass through the nanopore are recorded to analyze the DNA sequence.

[0052] Example 5

[0053] The surface structure of the chip is as follows Figure 5 As shown, the first contact 7 is located on the extended metal circuit of the first metallized via 5 on the upper surface of the first base layer 1, the first electrode 401 is connected to the first contact 7 through the ring metal circuit on the upper surface of the first base layer 1 through the metallized via 5, and the electrode 402 is located at the bottom of the first blind hole 3, and the electrode 402 is connected to the contact 8 through the inner wall of the second metallized via 501 and the ring metal circuit on the upper surface of the first base layer 1.

[0054] Example 6

[0055] The chip structure of this embodiment is as follows Figure 6 As shown, a second blind via 12 leading to the second base layer 2 is provided on the first base layer 1. A first electrode 401 is disposed below the second blind via 12. The first electrode 401 communicates with the first metallized via 5 via an extended metal trace 4. A first contact 7 is provided on the extended metal trace of the first metallized via 5 on the lower surface of the second base layer 2. The first and second metallized vias 501 penetrate the second base layer 2 but not the first base layer 1. The first and second metallized vias 501 are provided with inner-layer traces 6 in the second base layer 2, extending around the walls of the first and second metallized vias 501. A contact 8 is located on the extended metal trace of the second metallized via 501 on the lower surface of the second base layer 2. An electrode 402 is provided at the bottom of the first blind via 3 and connected to the second metallized via 501 via the extended metal trace 4. This indirectly connects the inner-layer trace 6 to the annular metal trace on the lower surface of the second base layer 2, and thus to the contact 8.

[0056] When in use, the first contact 7 and the contact 8 are connected to a power source, so that a voltage is generated between the first electrode 401 and the electrode 402 , and the conductive medium is connected above the first blind hole 3 and the second blind hole 12 .

Claims

1. A chip having a composite layer, characterized in that: The chip includes at least a first base layer and a second base layer arranged one above the other. The first base layer is provided with at least one first blind hole leading to the second base layer. The chip is also provided with at least two metallized vias passing through the second base layer, wherein the inner layer circuit of the first metallized via or the first metallized via is provided with a first contact on the extended metal circuit on the lower surface of the second base layer, the inner layer circuit of the second metallized via or the second metallized via is provided with a contact on the extended metal circuit on the lower surface of the second base layer, the outer wall of the metallized via is provided with an inner layer circuit, an electrode is provided under the first blind hole, and at least one second blind hole leading to the second base layer is further provided on the first base layer. A first electrode is provided under the second blind hole, the first electrode is connected to the first contact through the ring-shaped metal circuit and the inner layer circuit on the upper surface of the first base layer or the lower surface of the second base layer through the first metallized via, and the electrode is connected to the contact through the ring-shaped metal circuit and the inner layer circuit on the upper surface of the first base layer or the lower surface of the second base layer through the second metallized via. The materials of the first and second base layers are insulated.

2. The chip according to claim 1, characterized in that The aperture of the first blind hole is 0.1-0.15 mm, and the aperture of the second blind hole is 1-1.5 mm.

3. A chip having a composite layer, characterized in that: The chip includes at least a first base layer and a second base layer arranged one above the other, at least one first blind hole leading to the second base layer is provided on the first base layer, at least one metallized via penetrating the first base layer and the second base layer is also provided on the chip, an electrode is provided under the first blind hole, the chip is provided with a contact and a first contact, the first contact is located at an extended metal circuit on the upper surface of the first base layer or the lower surface of the second base layer through the first metallized via, a first electrode is also provided on the upper surface of the first base layer or above the first base layer, the first electrode is arranged at the upper end edge of the first metallized via, the first electrode is connected to the first contact through the annular metal circuit and the inner layer circuit on the upper surface of the first base layer or the lower surface of the second base layer through the first metallized via, the electrode is connected to the contact through the annular metal circuit and the inner layer circuit on the upper surface of the first base layer or the lower surface of the second base layer through the second metallized via, and the materials of the first base layer and the second base layer are insulated.

4. The chip according to claim 3, characterized in that The contact is located on an extended metal line of the second metallized via on the upper surface of the first base layer or the lower surface of the second base layer.

5. The chip according to any one of claims 1 to 4, characterized in that: The second base layer is provided with an inner layer circuit.

6. The chip according to any one of claims 1 to 4, characterized in that: At least one third base layer is further provided between the first base layer and the second base layer.

7. The chip according to any one of claims 1 to 4, characterized in that: The first base layer and the second base layer are made of plastic.

8. The chip according to any one of claims 1 to 4, characterized in that: The materials of the first base layer and the second base layer are polyimide resin board, FR-4 board, FR-1 board or CEM-1 / 3 board.

9. The chip according to any one of claims 3-4, characterized in that: The aperture of the first blind hole is 0.1-0.15 mm.

10. Use of the chip according to any one of claims 1 to 9 in biological detection.

11. The use according to claim 10, characterized in that The application is the application of the chip in nucleic acid sequencing.

12. The use according to claim 10, characterized in that The application is the application of the chip in nanopore nucleic acid sequencing.

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