Through Silicon Via Manufacturing

Abstract

The present invention is entitled "Through Silicon Via Fabrication". One or more embodiments relate to establishing electrical connections through a silicon wafer with low resistance and high density while maintaining processability for further manufacturing. Such connections through the silicon wafer achieve a low resistance connection from the top side of the silicon wafer to the bottom side of the silicon wafer.

Description

Technical Field

[0001] The present disclosure relates to the formation of through silicon vias in silicon wafers. Background Art

[0002] Some existing technologies for establishing connections from the top side of a silicon wafer to the bottom side of a silicon wafer include doped silicon pillars (Silex) formed by isolation, doped polysilicon pillars, metal pillars, and hollow metal rings within isolation rings. Silicon as a conductor has electrical limitations and significant resistance (on the order of ohms) at low temperatures, whereas metals (such as copper) can have resistance levels measured in milliohms. Solid metal pillars offer the lowest resistance per unit volume, but they may have the highest contrast in terms of thermal expansion mismatch between the metal and the silicon wafer or substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figures 1A to 1M A method for fabricating a through silicon via is shown.

[0004] Figure 2 The pattern of through silicon vias and the structure of through silicon vias are shown.

[0005] Figure 3A and Figure 3B is a flow chart illustrating a method for fabricating a through silicon via. DETAILED DESCRIPTION

[0006] In the following description, reference is made to the accompanying drawings, which form a part of the detailed description, and in which specific embodiments that can be implemented are shown by way of illustration. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it should be understood that other embodiments may be utilized and structural changes, electrical changes, and optical changes may be made without departing from the scope of the invention. Therefore, the following description of exemplary embodiments is not restrictive, and the scope of the invention is defined by the appended claims.

[0007] One or more embodiments are directed to establishing electrical connections through a silicon wafer with low resistance and high density while maintaining processability for further manufacturing. This is generally intended as a start of a method step to achieve a low resistance connection from the top side of a silicon wafer to the bottom side of a silicon wafer.

[0008] One or more embodiments provide a moderator of a glass plug combined with a copper ring, which produces a more acceptable solution in terms of heat compared to existing manufacturing processes. By starting from a larger hole, a through silicon via (TSV) can be etched to a greater depth and more easily lined. The lined hole can then be filled with a vapor-grown glass with a lower coefficient of expansion. The combined structure can then be chemically mechanically polished (CMP), which produces a very flat silicon wafer having a metal-lined electrical via through the patterning of the silicon wafer. Then, moderate to low temperature devices can be manufactured on the top and back of the wafer to interconnect through TSV. If necessary, higher temperature devices can be manufactured before TSV is formed. This allows the possibility of having a hermetically sealed part or a bump-bonded part, rather than a wire-bonded connection. Both the top and bottom surfaces of the silicon wafer can be utilized, or the wafers can be stacked as needed.

[0009] The following description and accompanying drawings disclose a method for making through-silicon vias. Although the disclosed method starts with a smaller hole, the method makes the through-silicon vias or holes smaller, and the smaller holes allowed by better deep reactive ion etching (DRIE) tools can be lined and then filled to close the holes. In addition, when combined with chemical mechanical polishing (CMP), the result is a flat wafer that is more compatible with continuous manufacturing processes. Conductive liner metals have been made previously, but the holes resulting from these existing methods are open, and open holes severely limit lithography and manufacturing capabilities. In addition, other methods involve using chemical vapor deposition (CVD) tungsten, copper-plated pillars (Micross; www.micross.com), doped silicon (Silex) and other conductors to make through-silicon vias, but the embodiments disclosed herein not only provide high conductivity of copper, but also provide some stress repair through the ring configuration.

[0010] In one embodiment, after the silicon wafer is manufactured, it is placed in conjunction with a laser that travels along the surface of the silicon wafer. Therefore, there cannot be any wire bonds or other obstructions on the surface of the wafer, or at least only minimal obstructions. Specifically, the laser enters from the side of the wafer, and any wire bonds or other obstructions adhering from the wafer will then interfere with the laser. To prevent such interference, one embodiment has electrical connections at the top surface of the wafer, but these electrical connections are brought down to a lower level in the wafer so that when the wafer is wire bonded, these wire bonds will not be within the field of view of the top surface of the wafer and will not be within the path of any such laser beam.

[0011] Another way to solve the problem of obstacles on the surface of silicon wafers is to use highly doped silicon or polysilicon pillars that penetrate through the wafer. Such wafers have a moderate resistance, and this high resistance is not feasible for many devices. In addition, some cases require cryogenic temperatures, and silicon is not as conductive as metal at low temperatures. In another existing system, tungsten vias are formed, but the problem with tungsten vias is that the wafer must be very thin. Similarly, if copper is used in the holes or vias, the wafer must be about 100 microns thick, which makes the manufacture of the device extremely difficult.

[0012] Therefore, in one embodiment, the wafer used is thicker (e.g., about 300 microns thick). And instead of completely filling the hole or via with copper, the hole is first made slightly larger so that the wafer can be thicker and then lined with copper. When the wafer approaches about 300 microns thick, the copper expands, and when the temperature changes greatly with low temperature applications, the silicon wafer will be more likely to break. Therefore, in one embodiment, copper is electroplated on the wafer so that the copper lines the hole, but the copper does not completely fill the hole. When the hole is lined with copper, the elliptical hole works well because the challenge of putting copper in the hole is to find a way to deposit copper all the way through the wafer, and most deposition techniques deposit copper on a flat surface, but when copper is deposited on the sidewalls of the wafer, especially on the sidewalls that are relatively deep (i.e., about 300 microns), their performance is very poor. For circular holes, the hole must be relatively large, such as about 60-70 microns. Filling such a large hole is actually not feasible. However, when the hole is elliptical, copper is well deposited in the hole by electroplating, and specifically when a seed layer is used before electroplating. More specifically, in the case of an elliptical hole with a size of about 20×70 microns, the seed layer can be sputtered deposited by a 300-micron wafer by sputtering depositing on the top of the wafer and then turning the wafer over and sputtering depositing the bottom side of the wafer. About 2-3 microns are sputtered deposited on the surface of the wafer. Although it is not yet certain how much copper there is in the hole, copper does plate to about 2-3 microns on the wafer surface. In one embodiment, the ellipse is about 20 microns × a length between 50 and 70 microns. That is, in one embodiment, the ellipse is basically a 20-micron circle cut in half and extended into an ellipse with two straight edges. In the case of an ellipse, the wafer can be sputtered deposited, which results in a continuous coating of the seed layer in the hole, and copper can then be electroplated into the hole. By appropriate chemical processes, a copper layer of about 3 microns is formed in the hole. This will close the hole considerably, but it will not completely close the hole.

[0013] It should be noted that sputtering deposition occurs mainly on the surface of the silicon wafer. However, an important part of the sputtering deposition occurs in the through hole, but it is very thin, only about one thousand or two thousand angstroms. The sputtering deposition in the through hole only needs to be thick enough to make it conductive and make the copper plating solution electroplated onto it. The ellipse of the through hole helps here because along the length of the ellipse, the sputtering atoms have more freedom to contact the side of the through hole. In contrast, in the case of a circular through hole of about 20 microns, the sputtering will not penetrate very deeply into the through hole, specifically, the sputtering only penetrates about 1 / 3 or 1 / 4 of the path down into the circular through hole. It is beneficial for the inside of the through hole to be completely coated. If some areas of the through hole are not electroplated, that is, if the seed layer is not properly placed in place and the through hole is not electroplated, the resistance of the through hole connection will be considerable. Moreover, after the seed layer is deposited, the wafer is placed in the electroplating solution to fully electroplate copper to produce low resistance, but not too much so that the hole is blocked. Once again, this is about 3 microns of copper. In short, sputtering deposits some copper in the vias but mostly on the surface of the wafer, and electroplating deposits copper mostly within the vias.

[0014] After copper has been deposited by electroplating, thereby producing an elliptical hole lined with copper through the wafer, an adhesion layer of titanium tungsten is sputter-deposited on the copper. The adhesion layer is mainly located on the top and bottom surfaces, but some also penetrate into the holes. After this, tetraethyl orthosilicate (TEOS) is used to deposit about 5-8 microns of silicon dioxide. The TEOS on the top and bottom of the wafer covers the wafer, but it is not enough to block the hole. The wafer is then placed in a plasma etcher, and almost all of the deposited TEOS is etched back. Etching is directional here, so that silicon dioxide is removed from the top surface and some silicon dioxide is also removed near the top of the hole. The reason for doing this instead of depositing it all at once (TEOS) is that when it is deposited in the hole, the result is a so-called bread loaf top. In the case of a bread loaf top, silicon dioxide will tend to pinch off at the top, which will prevent silicon dioxide from filling the hole because it is closed on the top, but there is still a hole or key hole. This is usually below the surface and should be avoided. When a subsequent etch is performed and the silicon dioxide is removed from the top, this removes the bread loaf. From this point on, deposition occurs again and fills the holes deeper in the wafer. This may only need to be done once or twice. That is, there is one deposition, one etch back, another deposition, another etch back, and then a final deposition.

[0015] After two cycles on the top of the wafer and two cycles on the bottom of the wafer, the wafer has oval copper-lined through-holes with silicon cores (a few microns of silicon dioxide). Mechanical polishing is then performed on the top surface of the wafer so that the silicon dioxide is polished away. That is, the flat part of the silicon dioxide is polished down to the copper. The same polishing is then performed on the bottom of the wafer, and the copper surface is exposed. Subsequent chemical mechanical polishing is performed with a slurry designed for copper, and the copper is then removed from the top and bottom of the wafer. The result is a through-silicon via (TSV) that exposes a copper ring.

[0016] Figures 1A to 1M An embodiment of fabricating these through silicon vias in a silicon wafer is shown. Figure 1A , a top mask 102 of silicon dioxide is deposited on the silicon wafer 101. A photoresist may also be deposited on the top mask 102. As described above, the silicon wafer 101 is typically about 300 microns thick. It should be noted at this point that when features of the silicon wafer are described herein as being of approximate width or thickness, in one embodiment, this means that the feature is within about 10-15% of the stated value. The top mask of silicon dioxide is about 1-4 microns thick. Figure 1A Further shown is the deposition of a bottom mask 103 on the silicon wafer 101. The bottom mask 103 is an aluminum layer and is typically about 1-2 microns thick. The use of aluminum as the bottom mask 103 instead of a mask such as silicon dioxide is that when subsequently etching down to the bottom mask, a small undercut on the bottom of the silicon wafer is avoided (which would occur if the bottom mask was silicon dioxide instead of aluminum).

[0017] refer to Figure 1B and Figure 1C , the through silicon via pattern 104 is photopatterned and etched into the top mask 102. Then, using the through silicon via photopatterning, the through silicon via 105 is etched through the silicon wafer 101 to the bottom mask 103. In one embodiment, etching the through silicon via 105 through the silicon wafer to the bottom mask 103 is a deep reactive ion etch (DRIE). In another embodiment, the through silicon via 105 is a rounded rectangle or oval with a size of about 20 microns to 50 microns or 20 microns to 70 microns. As described above, these oval through holes can be formed by cut circles that extend through inserted straight parallel walls.

[0018] Reference now Figure 1D , the top mask 102 and the bottom mask 103 are removed from the silicon wafer 101, and a second thermal silicon dioxide layer 106 is grown on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon vias 105. In one embodiment, the second thermal silicon dioxide layer is about 1.5 microns thick.

[0019] refer to Figure 1E , the second thermal silicon dioxide layer 106 is etched away from the silicon wafer 101. In one embodiment, the etching of the second thermal silicon dioxide layer 106 involves wet etching. The wet etching widens the through silicon via 105 to about 21 microns. The wet etching further smoothes any scallops formed on the silicon wafer by deep reactive ion etching. Removing such scallops can be beneficial because such scallops may cause difficulty in coating the through silicon via 105 with the seed layer when performing subsequent seed layers and electroplating. To address this, the second silicon dioxide layer 106 is grown to a thickness of about microns, and then etched away the second silicon oxide layer. Compared with the flatter parts in silicon, the etching makes the sharper points in silicon more oxidized, and this makes the silicon surface smooth.

[0020] refer to Figure 1F , so that the third thermal silicon oxide layer 107 grows on the top of the silicon wafer, the bottom of the silicon wafer and the through silicon via. The third silicon oxide layer 107 forms a passivation layer and is ultimately used as an isolation layer and stop layer in the through silicon via 105 (for subsequent chemical mechanical polishing (CMP) so that the polishing does not reach the silicon wafer all the way and does not cause leakage between adjacent through silicon vias). In one embodiment, the third thermal silicon dioxide layer 107 is about 1.5 microns thick. The growth of the third thermal silicon dioxide layer 107 narrows the through silicon via to about 19.5 microns. The third silicon dioxide layer 107 produces a chemical mechanical polishing (CMP) stop layer.

[0021] refer to Figure 1G , an adhesion layer 108 is sputter deposited on top of the silicon wafer. The sputter deposition deposits about 2500 angstroms of titanium. Figure 1H , the silicon wafer is turned over and about 2500 angstroms of titanium are sputter deposited on the bottom of the silicon wafer, thereby forming an adhesion layer 109. These sputter deposits also penetrate into the through silicon vias to some extent, and this narrows the through silicon vias to about 19.4 microns.

[0022] refer to Fig. 1I , in a manner equivalent to a sputtered adhesion layer but with copper, to make the electroplated seed layer (not in Fig. 1I ) is deposited on the top of the silicon wafer, the bottom of the silicon wafer and the through-silicon via. The seed layer deposited in the through-silicon via 105 is a very small percentage of the thickness on the surface. However, this is beneficial for subsequent electroplating. After the seed layer is electroplated, the copper layer 110 is electroplated in the through-silicon via. The electroplating of the copper layer in the through-silicon via causes the copper layer to penetrate into the through-silicon via to a depth of about 3 microns and narrow the through-silicon via to about 13.4 microns. After electroplating, the second adhesion layer ( Fig. 1IThe second adhesion layer on the top of the silicon wafer and the bottom of the silicon wafer is a titanium tungsten layer with a thickness of about 2000 angstroms. The above are some examples. The challenge here is that the conductive layer that the through hole passes completely through needs to be copper-like so that it can be electroplated. Copper simply cannot be electroplated onto that much material.

[0023] refer to Figure 1J , causing a fourth silicon dioxide layer 111 to be deposited on the top of the silicon wafer, the bottom of the silicon wafer, and on the through silicon vias. The deposition of the fourth silicon dioxide layer on the top of the silicon wafer and on the bottom of the silicon wafer involves plasma enhanced chemical vapor deposition using tetraethyl orthosilicate (TEOS) chemistry. This chemical vapor deposition narrows the through silicon vias to about 3.4 microns and results in a fourth silicon dioxide layer of about 5 microns thick.

[0024] Still refer to Figure 1J , etching the fourth silicon dioxide layer 111 to remove a portion of the fourth silicon dioxide layer. Etching the fourth silicon dioxide layer to remove a portion of the fourth silicon dioxide layer includes directional dry etching. The directional dry etching removes about 4.5 microns of the fourth silicon dioxide layer on the outwardly facing surfaces of the top and bottom of the wafer, and causes the through silicon via 105 to be about 12.4 microns near the top of the silicon wafer, and the through silicon via is about 4 microns near the midpoint of the through silicon via and near the bottom of the silicon wafer. Then the fifth silicon dioxide layer ( Figure 1J The fifth silicon dioxide layer is deposited on the top of the silicon wafer, the bottom of the silicon wafer and the through silicon via. The deposition of the fifth silicon dioxide layer on the top of the silicon wafer and the bottom of the silicon wafer involves plasma enhanced chemical vapor deposition using tetraethyl orthosilicate (TEOS) chemistry. The plasma enhanced chemical vapor deposition narrows the through silicon via to about 2.4 microns at the top of the silicon wafer and closes the through silicon via at the top of the silicon wafer, the midpoint of the silicon wafer and the bottom of the silicon wafer. The fifth silicon dioxide layer is about 5 microns thick.

[0025] The fifth silicon dioxide layer is then etched to remove a portion of the fifth silicon dioxide layer. Etching the fifth silicon dioxide layer to remove a portion of the fifth silicon dioxide layer involves directional dry etching. The directional dry etching removes about 4.5 microns of the fifth silicon dioxide layer on the outwardly facing surfaces of the top and bottom of the wafer, and results in a through silicon via having a thickness of about 12.4 microns at the top of the silicon wafer, and further results in the through silicon via being closed within the silicon wafer and at the bottom of the silicon wafer.

[0026] refer to Figure 1K, causing a sixth silicon dioxide layer 112 to be deposited on the top of the silicon wafer and on the bottom of the silicon wafer. The deposition of the sixth silicon dioxide layer on the top of the silicon wafer and on the bottom of the silicon wafer involves plasma enhanced chemical vapor deposition using tetraethyl orthosilicate (TEOS) chemistry. The plasma enhanced chemical vapor deposition closes the through silicon vias at the top of the silicon wafer, the midpoint of the silicon wafer, and the bottom of the silicon wafer, and further results in a sixth silicon dioxide layer 112 that is about 5 microns thick.

[0027] refer to Figure 1L , the sixth silicon dioxide layer 112 is chemically mechanically polished (CMP) on the top and bottom of the silicon wafer until the copper layer 110. Then, referring to Figure 1M , the copper layer 110 , the first adhesion layer and the second adhesion layer are chemically mechanically polished until the silicon dioxide layer 107 .

[0028] Figure 2 Shown is a pattern of a through silicon via 105. The through silicon via 105 includes a 1 micron thermal silicon dioxide layer 105A, a titanium and copper seed layer 105B, about 4-5 microns of electroplated copper 105C, a 0.1 micron titanium layer 105D, and a TEOS filled middle portion 105E.

[0029] Figure 3A and Figure 3B is a block diagram illustrating the operation and features of a system and method 300 for fabricating through silicon vias (TSVs) in a silicon wafer. Figure 3A and Figure 3B includes a number of boxes 305-370. Although in Figure 3A and Figure 3B In the example of the embodiment of the present invention, the blocks are arranged substantially sequentially, but other examples can rearrange the blocks, omit one or more blocks, and / or use multiple processors or a single processor organized as two or more virtual machines or sub-processors to execute two or more blocks in parallel. In addition, other examples can implement these blocks as one or more specific interconnected hardware or integrated circuit modules, wherein related control and data signals are transmitted between and through the modules. Therefore, any process flow is applicable to software, firmware, hardware and hybrid implementations.

[0030] Reference now Figure 3A and Figure 3B , at 305, a top mask 102 is deposited onto the silicon wafer 101. The top mask is a first silicon dioxide layer. As shown at 306, the silicon wafer is about 300 microns thick, and as shown at 307, the top mask is about 1-4 microns thick. At 310, a bottom mask 103 is deposited onto the bottom of the silicon wafer 101. As indicated at 311, in one embodiment, the bottom mask is an aluminum layer, and the aluminum layer is about 1-2 microns thick.

[0031] At 315, through silicon vias are photopatterned (104) onto the top mask 102, and then through silicon vias 105 are etched into the top mask. As indicated at 316, in one embodiment, the through silicon vias comprise rounded rectangles or ovals having a size of about 20 microns to about 50 microns or about 20 microns to about 70 microns. Figure 2 ,

[0032] At 320, using the TSV pattern, TSVs 105 are etched through the silicon wafer 101 to the bottom mask 103. As indicated at 321, in one embodiment, etching the TSVs through the silicon wafer to the bottom mask is a deep reactive ion etch (DRIE), resulting in TSVs that are approximately 20 microns wide.

[0033] At 325, the top mask 102 and the bottom mask 103 are removed from the silicon wafer 101. And at 326, a second thermal silicon dioxide layer 106 is grown on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon vias 105. As indicated at 327, in one embodiment, the second thermal silicon dioxide layer is about 1.5 microns thick. At 328, the second thermal silicon dioxide layer is etched away from the silicon wafer. As shown at 329, in one embodiment, the etching of the second thermal silicon dioxide layer includes a wet etch that widens the through silicon vias to about 21 microns and that smoothes any scallops formed on the silicon wafer.

[0034] At 330, a third thermal silicon oxide layer 107 is grown on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon via. The third silicon dioxide layer forms a passivation layer. In one embodiment, as indicated at 331, the third thermal silicon dioxide layer is about 1.5 microns thick, the growth of the third thermal silicon dioxide layer narrows the through silicon via to about 19.5 microns, and the third silicon dioxide layer serves as a chemical mechanical polishing (CMP) stop layer.

[0035] At 335, an adhesion layer 108 is sputter deposited on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon via. At 336, the sputter deposition of the adhesion layer on the top of the silicon wafer and the bottom of the silicon wafer includes sputter deposition of about 2500 angstroms of titanium tungsten, followed by about 3 microns of copper seed layer on the top of the silicon wafer and the bottom of the silicon wafer. This sputter deposition results in narrowing the through silicon via to about 19.4 microns. Thereafter, at 338, an electroplated seed layer is deposited on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon via.

[0036] At 340, the copper layer 110 is electroplated in the through silicon via 105. As indicated at 341, the electroplating of the copper layer in the through silicon via causes the copper layer to penetrate into the through silicon via to a depth of about 3 microns and narrows the through silicon via to about 13.4 microns.

[0037] At 345, a second adhesion layer is deposited on the top of the silicon wafer and the bottom of the silicon wafer. As indicated at 346, in one embodiment, the second adhesion layer on the top of the silicon wafer and the bottom of the silicon wafer includes a titanium nitride layer having a thickness of about 1000 angstroms. The second adhesion layer may be deposited by atomic layer deposition (ALD).

[0038] At 350, a fourth silicon dioxide layer 111 is deposited on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon vias. In one embodiment, depositing the fourth silicon dioxide layer on the top of the silicon wafer and on the bottom of the silicon wafer involves plasma enhanced chemical vapor deposition using tetraethyl orthosilicate (TEOS) chemistry as indicated at 351. This results in narrowing the through silicon vias to about 3.4 microns and results in the fourth silicon dioxide layer being about 5 microns thick.

[0039] At 352, the fourth silicon dioxide layer is etched to remove a portion of the fourth silicon dioxide layer. In one embodiment, the etching of the fourth silicon dioxide layer to remove a portion of the fourth silicon dioxide layer involves a directional dry etch, as indicated at 353. The directional dry etch removes approximately 4.5 microns of the fourth silicon dioxide layer and results in a through silicon via of approximately 12.4 microns near the top of the silicon wafer and a through silicon via of approximately 4 microns near the midpoint of the through silicon via and near the bottom of the silicon wafer.

[0040] At 355, a fifth silicon dioxide layer is deposited on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon vias. In one embodiment, the deposition of the fifth silicon dioxide layer on the top of the silicon wafer and the bottom of the silicon wafer involves plasma enhanced chemical vapor deposition using tetraethyl orthosilicate (TEOS) chemistry as indicated at 356. This results in narrowing the through silicon vias to about 2.4 microns at the top of the silicon wafer, closing the through silicon vias at the top of the silicon wafer, the midpoint of the silicon wafer, and near the bottom of the silicon wafer, and results in the fifth silicon dioxide layer being about 5 microns thick.

[0041] At 357, the fifth silicon dioxide layer is etched to remove a portion of the fifth silicon dioxide layer. At 358, one embodiment etches the fifth silicon dioxide layer using a directional dry etch to remove a portion of the fifth silicon dioxide layer. The directional dry etch removes about 4.5 microns of the fifth silicon dioxide layer and results in a through silicon via having a thickness of about 12.4 microns at the top of the silicon wafer and closed through silicon vias within the silicon wafer and at the bottom of the silicon wafer.

[0042] At 360, a sixth silicon dioxide layer 112 is deposited on the top of the silicon wafer and on the bottom of the silicon wafer. At 361, in one embodiment, the deposition of the sixth silicon dioxide layer on the top of the silicon wafer and on the bottom of the silicon wafer involves plasma enhanced chemical vapor deposition using tetraethyl orthosilicate (TEOS) chemistry. This chemical vapor deposition closes through silicon vias at the top of the silicon wafer, near the midpoint of the silicon wafer, and near the bottom of the silicon wafer, and results in the sixth silicon dioxide layer being about 5 microns thick.

[0043] At 365, the sixth silicon dioxide layer is chemically mechanically polished (CMP) on the top of the silicon wafer and the bottom of the silicon wafer to the copper layer, and at 366, the copper layer, the first adhesion layer, and the second adhesion layer are chemically mechanically polished to the third silicon dioxide layer. This essentially completes the method of making through silicon vias in a silicon wafer. Then, as indicated at 370, a device is coupled to the through silicon via at the top layer of the silicon wafer and / or a device is coupled to the through silicon via at the bottom layer of the silicon wafer.

[0044] It should be understood that there are other variations and modified embodiments of the present invention and its various aspects, such as may be apparent to those of ordinary skill in the art, and the present invention is not limited to the specific embodiments described herein. The above features and embodiments may be combined with each other in different combinations. Therefore, it is contemplated that any and all modifications, variations, combinations or equivalents falling within the scope of the present invention are covered.

[0045] The Abstract is provided to comply with 37 CFR §1.72(b) and will allow the reader to quickly ascertain the nature and gist of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

[0046] In the above description of the embodiments, various features are grouped together in a single embodiment for the purpose of simplifying the disclosure. This method of the disclosure should not be understood to reflect that the claimed embodiments have more features than those expressly stated in each claim. On the contrary, as reflected in the following claims, the inventive subject matter lies in less than all the features of a single disclosed embodiment. Therefore, the following claims are hereby incorporated into the description of the embodiments, with each claim standing on its own as a separate exemplary embodiment.

Claims

1. A method comprising: depositing a top mask onto the silicon wafer, the top mask comprising a first silicon dioxide layer; depositing a bottom mask onto a bottom of the silicon wafer; photopatterning a through silicon via pattern and etching through silicon vias into the top mask; etching the through-silicon via through the silicon wafer to the bottom mask using the through-silicon via pattern; removing the top mask and the bottom mask from the silicon wafer; growing a second thermal silicon dioxide layer on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon vias; etching away the second thermal silicon dioxide layer from the silicon wafer; growing a third thermal silicon dioxide layer on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon vias, thereby forming a passivation layer; sputter depositing a first adhesion layer on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon vias; Depositing an electroplating seed layer on the top of the silicon wafer, the bottom of the silicon wafer, and the through-silicon vias; electroplating a copper layer in the through silicon via; depositing a second adhesion layer on the top of the silicon wafer and on the bottom of the silicon wafer; depositing a fourth silicon dioxide layer on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon vias; etching the fourth silicon dioxide layer to remove a portion of the fourth silicon dioxide layer; depositing a fifth silicon dioxide layer on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon vias; etching the fifth silicon dioxide layer to remove a portion of the fifth silicon dioxide layer; depositing a sixth silicon dioxide layer on the top of the silicon wafer and the bottom of the silicon wafer; chemically mechanically polishing the sixth silicon dioxide layer on the top of the silicon wafer and the bottom of the silicon wafer down to the copper layer; as well as The copper layer, the first adhesion layer, and the second adhesion layer are chemically mechanically polished down to the third thermal silicon dioxide layer.

2. The method according to claim 1, wherein: The top mask is 1-4 microns thick; and The bottom mask includes an aluminum layer, and wherein the aluminum layer is 1-2 microns thick.

3. The method according to claim 1, wherein: The second thermal silicon dioxide layer is about 1.5 microns thick; and The etching of the second thermal silicon dioxide layer includes wet etching, wherein the wet etching widens the through silicon via to about 21 microns, and wherein the wet etching smoothes the scallops on the silicon wafer.

4. The method of claim 1 , wherein the third thermal silicon dioxide layer is approximately 1.5 microns thick, and wherein growing the third thermal silicon dioxide layer narrows the through silicon via to approximately 19.5 microns, and wherein the third thermal silicon dioxide layer comprises a chemical mechanical polishing stop layer.

5. The method of claim 1 , wherein said sputter depositing said first adhesion layer on said top portion of said silicon wafer and said bottom portion of said silicon wafer comprises sputter depositing about 2500 angstroms of titanium followed by about 3 microns of a copper seed layer on said top portion of said silicon wafer and said bottom portion of said silicon wafer, thereby narrowing said through silicon via to about 19.4 microns. 6 . The method of claim 1 , wherein the electroplating of the copper layer in the TSV causes the copper layer to penetrate into the TSV to a depth of about 3 microns and narrow the TSV to about 13.4 microns.

7. The method of claim 1 , wherein the second adhesion layer on the top of the silicon wafer and the bottom of the silicon wafer comprises at least one of a titanium tungsten layer having a thickness of about 2000 angstroms and a titanium nitride layer having a thickness of about 1000 angstroms deposited by atomic layer deposition (ALD).

8. The method according to claim 1, wherein: depositing the fourth silicon dioxide layer on the top of the silicon wafer and the bottom of the silicon wafer comprises plasma enhanced chemical vapor deposition using tetraethyl orthosilicate (TEOS) chemistry, thereby narrowing the through silicon via to about 3.4 microns and causing the fourth silicon dioxide layer to be about 5 microns thick; and The etching of the fourth silicon dioxide layer to remove a portion of the fourth silicon dioxide layer includes directional dry etching, thereby removing approximately 4.5 microns of the fourth silicon dioxide layer and causing the through-silicon via to be approximately 12.4 microns near the top of the silicon wafer and the through-silicon via to be approximately 4 microns near a midpoint of the through-silicon via and near the bottom of the silicon wafer.

9. The method according to claim 1, wherein: depositing the fifth silicon dioxide layer on the top of the silicon wafer and the bottom of the silicon wafer comprises plasma enhanced chemical vapor deposition using tetraethyl orthosilicate (TEOS) chemistry, thereby narrowing the through silicon via to about 2.4 microns at the top of the silicon wafer, closing the through silicon via near the top of the silicon wafer, a midpoint of the silicon wafer, and the bottom of the silicon wafer, and resulting in a fifth silicon dioxide layer that is about 5 microns thick; as well as Etching the fifth silicon dioxide layer to remove a portion of the fifth silicon dioxide layer includes directional dry etching, thereby removing approximately 4.5 microns of the fifth silicon dioxide layer and causing the through silicon via to have a thickness of approximately 12.4 microns at the top of the silicon wafer, and closing the through silicon via within the silicon wafer and at the bottom of the silicon wafer.

10. The method of claim 1 , wherein said depositing said sixth silicon dioxide layer on said top portion of said silicon wafer and said bottom portion of said silicon wafer comprises plasma enhanced chemical vapor deposition using tetraethyl orthosilicate (TEOS) chemistry, thereby closing said through silicon vias at said top portion of said silicon wafer, at a midpoint of said silicon wafer, and at said bottom portion of said silicon wafer, and resulting in a sixth silicon dioxide layer that is approximately 5 microns thick.

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