Stacked back-illuminated single-photon avalanche diode image sensor

Abstract

The present application discloses a stacked back-illuminated single-photon avalanche diode image sensor, comprising: an imaging wafer having a front surface and a rear surface, comprising; a SPAD array located between the front surface and the rear surface, the SPAD array comprising: a first type epitaxial layer: a cathode region located in the first type epitaxial layer and having a second type doped layer; a first type doped layer located above the cathode region, the junction between the first type doped layer and the second type doped layer being an avalanche region; an anode region surrounding the first type epitaxial layer and a side close to the rear surface and having a first type deeply doped layer; an isolation layer surrounding the anode region; a metal reflective layer, a dielectric layer and a top metal layer covering the front surface, the cathode region and the anode region respectively penetrating the metal reflective layer through through holes and connected to the top metal layer; a high-k dielectric layer, an infrared filter layer and an anti-reflection layer sequentially covering the rear surface; a logic wafer located below the front surface and attached to the imaging wafer.

Description

Technical Field

[0001] The present invention relates to the technical field of image sensors, and in particular to a stacked back-illuminated single-photon avalanche diode image sensor. Background Art

[0002] DTOF (Direct Time-of-Flight) is used in various electronic devices such as mobile phones, digital cameras, automobiles, medical imaging equipment, security systems, and AR and VR applications. DTOF typically includes an array of photodetectors that detect or respond to incident light. One type of photodetector that can be used for image sensors is the single-photon avalanche diode SPAD region. The SPAD region is a photosensitive area that is configured to detect low levels of light (as low as a single photon) and signal the arrival time of the photon.

[0003] At present, when used in mobile phones, DTOF requires high resolution. When the resolution is high, the pixel pitch will become smaller, for example, 1um, 2.5um, 5um, 10um, etc. When the pixel pitch becomes smaller, it will bring a series of problems such as low photon detection efficiency (PDE), severe crosstalk, and back pulse. Ultimately, the range of use is limited or the power consumption is too high, which cannot meet the needs of mobile phone applications. Summary of the invention

[0004] The object of the present invention is to provide a stacked back-illuminated single-photon avalanche diode image sensor to achieve DTOF with high PDE, low crosstalk, low pixel pitch, low back pulse and low power consumption.

[0005] An embodiment of the present application provides a stacked back-illuminated single-photon avalanche diode image sensor, comprising:

[0006] An imaging wafer having a front surface and a back surface, the imaging wafer comprising;

[0007] A SPAD array located between the front surface and the back surface, the SPAD array comprising:

[0008] Type I epitaxial layer:

[0009] a cathode region, located in the first type epitaxial layer and having a second type doped layer;

[0010] A first type doped layer is located above the cathode region and close to the rear surface, wherein a junction between the first type doped layer and the second type doped layer is an avalanche region;

[0011] an anode region, surrounding the first type epitaxial layer on all sides and one side close to the rear surface and having a first type deeply doped layer;

[0012] An isolation layer surrounding the anode region;

[0013] A metal reflective layer, a dielectric layer and a top metal layer covering the front surface, wherein the cathode region and the anode region penetrate the metal reflective layer and are connected to the top metal layer through through holes respectively;

[0014] A high-k dielectric layer, an infrared filter layer and an anti-reflection layer sequentially covering the rear surface;

[0015] A logic wafer is located below the front surface and attached to the imaging wafer.

[0016] In a preferred example, the logic wafer includes a voltage source and a quenching / charging and readout circuit, the anode region is connected to the voltage source, and the quenching / charging and readout circuit is connected to the cathode region.

[0017] In a preferred example, a grating layer is formed between the cathode region and the metal reflective layer.

[0018] In a preferred example, the grating layer includes any two of the following materials alternately formed on the same plane: polysilicon, silicon dioxide, silicon nitride, and Si3N4.

[0019] In a preferred example, a Bragg reflection layer is formed between the cathode region and the metal reflection layer.

[0020] In a preferred example, the Bragg reflection layer is formed by alternating any two of the following: polysilicon, silicon dioxide, silicon nitride, and Si3N4.

[0021] Another embodiment of the present application provides a stacked back-illuminated single-photon avalanche diode image sensor, comprising:

[0022] An imaging wafer having a front surface and a back surface, the imaging wafer comprising;

[0023] A SPAD array located between the front surface and the back surface, the SPAD array comprising:

[0024] Type I epitaxial layer:

[0025] a cathode region, located in the first type epitaxial layer and having a second type doped layer;

[0026] A first type doped layer is located above the cathode region and close to the rear surface, wherein a junction between the first type doped layer and the second type doped layer is an avalanche region;

[0027] An isolation layer, surrounding the first type epitaxial layer;

[0028] an anode region, a first type deeply doped layer located above the first type epitaxial layer and close to the rear surface and penetrating the isolation layer;

[0029] A metal reflective layer, a dielectric layer and a top metal layer covering the front surface, wherein the cathode region and the anode region penetrate the metal reflective layer and are connected to the top metal layer through through holes respectively;

[0030] A high-k dielectric layer, an infrared filter layer and an anti-reflection layer sequentially covering the rear surface;

[0031] A logic wafer is located below the front surface and attached to the imaging wafer.

[0032] Another embodiment of the present application provides a stacked back-illuminated single-photon avalanche diode image sensor, comprising:

[0033] An imaging wafer having a front surface and a back surface, the imaging wafer comprising;

[0034] A SPAD array located between the front surface and the back surface, the SPAD array comprising:

[0035] Type I epitaxial layer:

[0036] a cathode region, located in the first type epitaxial layer and having a second type doped layer;

[0037] A first type doped layer is located above the cathode region and close to the rear surface, wherein a junction between the first type doped layer and the second type doped layer is an avalanche region;

[0038] An isolation layer, surrounding the first type epitaxial layer;

[0039] an anode region, a first type deeply doped layer located above the first type epitaxial layer and close to the rear surface;

[0040] A metal reflective layer, a dielectric layer and a top metal layer covering the front surface, wherein the cathode region penetrates the metal reflective layer through a through hole and is connected to the top metal layer, and the anode region penetrates the metal reflective layer through a metal connecting layer and is connected to the top metal layer;

[0041] A high-k dielectric layer, an infrared filter layer and an anti-reflection layer sequentially covering the rear surface;

[0042] A logic wafer is located below the front surface and attached to the imaging wafer.

[0043] Compared with the prior art, the method of the present application has the following beneficial effects:

[0044] The SPAD provided by the present invention has a PDE several times higher in the 940nm band, and its emission power consumption can be greatly reduced, thereby reducing the power consumption of the system. In addition, the range and frame rate are optimized, which promotes the popularization of DTOF on mobile phones. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 Schematic diagram of a stacked back-illuminated single-photon avalanche diode image sensor in Embodiment 1 of the present invention.

[0046] Figure 2 FIG. 4 is a schematic diagram of a stacked back-illuminated single-photon avalanche diode image sensor with a grating according to an embodiment of the present invention.

[0047] Figure 3 FIG. 4 is a schematic diagram of a stacked back-illuminated single-photon avalanche diode image sensor with a Bragg reflection layer according to an embodiment of the present invention.

[0048] Figure 4 Schematic diagram of a stacked back-illuminated single-photon avalanche diode image sensor in Embodiment 2 of the present invention.

[0049] Figure 5 Schematic diagram of a stacked back-illuminated single-photon avalanche diode image sensor in Embodiment 3 of the present invention.

[0050] Figure 6 Schematic diagram of a back-illuminated single-photon avalanche diode image sensor in Embodiment 4 of the present invention.

[0051] Figure 7 4 is a simulation schematic diagram of the PDE of the stacked back-illuminated single-photon avalanche diode image sensor in the first embodiment of the present invention. DETAILED DESCRIPTION

[0052] In the following description, many technical details are provided to help readers better understand the present application. However, those skilled in the art can understand that even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the claims of the present application can be implemented.

[0053] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0054] Embodiment 1

[0055] An embodiment of the present application provides a stacked back-illuminated single-photon avalanche diode image sensor, Figure 1The schematic diagram of a stacked back-illuminated single-photon avalanche diode image sensor is shown, which includes: an imaging wafer 100, the imaging wafer 100 having a front surface and a rear surface; a logic wafer 200, the logic wafer 200 is located below the front surface and attached to the imaging wafer 100. A stacked packaging structure is formed between the imaging wafer and the logic wafer.

[0056] The imaging wafer 100 includes a SPAD array located between the front surface and the back surface, a metal reflective layer 109, a dielectric (ILD) layer 110 and a top metal (TM) layer 112 covering the front surface, and a high-k dielectric layer 113, an infrared filter layer 114, an anti-reflection layer 115 and a microlens 116 covering the back surface in sequence. The SPAD array includes: a first type (p--) epitaxial layer 101: a second type (n) doped layer 102 located in the first type epitaxial layer 101, used as the cathode region of the SPAD pixel, and the second type (n) doped layer 102 also has a second type deep (n+) doped layer 106 for reading out the cathode region; a first type (p) doped layer 103 located above the cathode region and close to the side of the rear surface, wherein the junction between the first type doped layer 103 and the second type doped layer 102 is an avalanche region 104, and a first type doped layer 105 is also provided above the first type doped layer 103; a first type deep (p++) doped layer 107 surrounding the first type epitaxial layer 101 and close to the side of the rear surface, used as the anode region of the SPAD pixel; and an isolation layer 108 surrounding the anode region 107.

[0057] The cathode region and the anode region penetrate the metal reflective layer 109 and are connected to the top metal layer 112 through vias 111 .

[0058] In one embodiment, the logic wafer 200 includes a voltage source 202 and a quenching / charging and readout circuit 203 located in a P-type substrate (PSUB layer) 201, the top metal layer 112 connected to the anode area is connected to the voltage source 202 through a top metal layer 204 located on the surface of the P-type substrate 201, and the top metal layer 112 connected to the cathode area is connected to the quenching / charging and readout circuit 203 through the top metal layer 204.

[0059] The present invention adopts two wafer stacking packaging. Figure 1Only a single SPAD pixel is shown in the figure. The SPAD array in the DTOF, for example, is composed of m*n repeated combinations of the minimum modules. The microlens 116 at the top of the imaging wafer is used to aggregate the light path to improve the fill factor. The anti-reflection layer 115 reduces the reflection of the incident band as much as possible. The infrared filter layer 114 only allows the emission band wavelength to pass, such as 940nm, and the high-k dielectric layer 113 is used for isolation and protection.

[0060] The bottom of the SPAD pixel is the N+ readout area 106, followed by the N-doped layer 102 surrounding the N+ readout area 106, which has a lower doping concentration than the N+ layer. The two constitute the cathode of the SPAD. Above the N-type doped layer is the P-type doped layer 103, and the junction of the two is the avalanche zone 104, which is also the core area. Above the P-doped layer 103 is a slightly lightly doped P-doped layer 105, which can reduce the impact of the back pulse. Above the P-doped layer 105 is the P- epitaxial layer 101. Directly above and on the side wall of the SPAD pixel is the P++ doped layer 107, which is used to lead out the anode of the SPAD pixel. The P++ doped layer 107 is finally led out through the P++ doped layer at the bottom of the side wall through the through hole 111. There is an isolation layer between the adjacent P++ doped layers of adjacent SPADs. The isolation layer is non-conductive and opaque, and its function can reduce the crosstalk between adjacent SPAD pixels. There is a reflective metal layer under the SPAD, which can return the light path to the avalanche zone, avoiding photon waste and improving PDE. The anode and cathode of the SPAD pixel are connected to the top metal layer of the imaging wafer through the through hole 111, and are connected to the relevant top metal layer TM layer of the logic wafer below it. Thereby, the cathode and anode of the SPAD pixel are introduced into the logic wafer below and controlled by it. The logic wafer below includes a voltage source module for controlling the SPAD anode, and a quenching / charging and readout circuit module for controlling the cathode of the SPAD, and senses the relevant signals for processing and output.

[0061] In one embodiment, reference Figure 2 As shown, a grating layer 117 is formed between the cathode region and the metal reflective layer. The function of the grating is to make the light incident on the bottom of the SPAD pixel be reflected back at various angles, and enter the avalanche region after colliding with the side wall to be effectively absorbed. In one embodiment, the grating layer 117 includes any two of the following formed alternately on the same plane: polysilicon, silicon dioxide, silicon nitride, Si3N4. For example, the grating can be composed of undoped polysilicon and silicon dioxide alternating on the same plane, which can reduce the difficulty of production without reducing the yield. The grating can also be composed of undoped polysilicon and SiN alternatingly. The grating can also be composed of silicon dioxide and Si3N4 alternatingly. The grating can also be composed of silicon dioxide and SiN alternatingly. The grating can also be composed of other combinations, which is not limited by the present invention.

[0062] In one embodiment, reference Figure 3 As shown, a Bragg reflection layer 118 is formed between the cathode region and the metal reflection layer, and its function is to return the light incident to the bottom to the avalanche region, thereby increasing the PDE. In one embodiment, the Bragg reflection layer 118 is formed by alternating any two of the following: polysilicon, silicon dioxide, silicon nitride, Si3N4. For example, the Bragg reflection layer is composed of undoped polysilicon and silicon dioxide alternately stacked. The Bragg reflection layer can also be composed of undoped polysilicon and SiN alternately stacked. The Bragg reflection layer can also be composed of silicon dioxide and Si3N4 alternately stacked. The Bragg reflection layer can also be composed of silicon dioxide and SiN alternately stacked. The Bragg reflection layer can also be composed of other combinations, which are not limited by the present invention.

[0063] Embodiment 2

[0064] In the second embodiment of the present application, a stacked back-illuminated single-photon avalanche diode image sensor is provided, referring to Figure 4 As shown, it includes: an imaging wafer 100 having a front surface and a back surface; and a logic wafer 200 , wherein the logic wafer 200 is located below the front surface and attached to the imaging wafer 100 .

[0065] The imaging wafer 100 includes a SPAD array located between the front surface and the back surface, a metal reflective layer 109, a dielectric (ILD) layer 110 and a top metal (TM) layer 112 covering the front surface, and a high-k dielectric layer 113, an infrared filter layer 114, an anti-reflection layer 115 and a microlens 116 covering the back surface in sequence. The SPAD array includes: a first type (p--) epitaxial layer 101: a second type (n) doped layer 102 located in the first type epitaxial layer 101, used as the cathode region of the SPAD pixel, the second type (n) doped layer 102 also has a second type deep (n+) doped layer 106 for reading out the cathode region; a first type (p) doped layer 103 located above the cathode region on the side close to the rear surface, wherein the junction between the first type doped layer 103 and the second type doped layer 102 is an avalanche region 104, and a first type doped layer 105 is also provided above the first type doped layer 103; an isolation layer 108 surrounding the first type epitaxial layer 101; a first type deep (p++) doped layer 107 located above the first type epitaxial layer 101 on the side close to the rear surface and penetrating the isolation layer 108.

[0066] The cathode region and the anode region penetrate the metal reflective layer 109 and are connected to the top metal layer 112 through vias 111 .

[0067] The logic wafer 200 includes a voltage source 203 and a quenching / charging and readout circuit 203 located in a P-type substrate (PSUB layer) 201. The top metal layer 112 connected to the anode area is connected to the voltage source 202 through a top metal layer 204 located on the surface of the P-type substrate 201. The top metal layer 112 connected to the cathode area is connected to the quenching / charging and readout circuit 203 through the top metal layer 204.

[0068] The stacked back-illuminated single-photon avalanche diode image sensors of Example 1 and Example 2 are basically the same, with the main difference being that the P++ doping layer surrounding the SPAD pixel sidewall in Example 1 is moved to the middle of the isolation layer, which can reduce the difficulty of manufacturing and improve process consistency.

[0069] It should be understood that the stacked back-illuminated single-photon avalanche diode image sensor in the second embodiment may also include a grating layer or a Bragg reflection layer as shown, and its function and structure are similar to those of the first embodiment, which will not be described in detail here.

[0070] Embodiment 3

[0071] Another embodiment of the present application provides a stacked back-illuminated single-photon avalanche diode image sensor, referring to Figure 5 As shown, it includes: an imaging wafer 100 having a front surface and a back surface; and a logic wafer 200 , wherein the logic wafer 200 is located below the front surface and attached to the imaging wafer 100 .

[0072] The imaging wafer 100 includes a SPAD array located between the front surface and the back surface, a metal reflective layer 109, a dielectric (ILD) layer 110 and a top metal (TM) layer 112 covering the front surface, and a high-k dielectric layer 113, an infrared filter layer 114, an anti-reflection layer 115 and a microlens 116 covering the back surface in sequence. The SPAD array includes: a first type (p--) epitaxial layer 101: a second type (n) doped layer 102 located in the first type epitaxial layer 101, used as the cathode region of the SPAD pixel, the second type (n) doped layer 102 also has a second type deep (n+) doped layer 106 for reading out the cathode region; a first type (p) doped layer 103 located above the cathode region and close to the back surface, wherein the junction between the first type doped layer 103 and the second type doped layer 102 is an avalanche region 104, and a first type doped layer 105 is also provided above the first type doped layer 103; an isolation layer 108 surrounding the first type epitaxial layer 101; and a first type deep (p++) doped layer 107 located above the first type epitaxial layer 101 and close to the back surface.

[0073] The anode region penetrates the metal reflective layer 109 through a metal connection layer 119 and is connected to the top metal layer 112 , and the cathode region penetrates the metal reflective layer 109 through a through hole 111 and is connected to the top metal layer 112 .

[0074] The logic wafer 200 includes a voltage source 202 and a quenching / charging and readout circuit 203 located in a P-type substrate (PSUB layer) 201. The top metal layer 112 connected to the anode area is connected to the voltage source 202 through a top metal layer 204 located on the surface of the P-type substrate 201. The top metal layer 112 connected to the cathode area is connected to the quenching / charging and readout circuit 203 through the top metal layer 204.

[0075] The stacked back-illuminated single-photon avalanche diode image sensors of Example 1 and Example 3 are basically the same, with the main difference being that the P++ doped layer surrounding the SPAD sidewall in Example 1 is removed, and the P++ doped layer at the top of the SPAD pixel is directly led out to the bottom of the SPAD pixel using a deep through hole, which improves conductivity, improves process robustness, and further reduces crosstalk.

[0076] It should be understood that the stacked back-illuminated single-photon avalanche diode image sensor in the third embodiment may also include a grating layer or a Bragg reflection layer as shown, and its function and structure are similar to those of the first embodiment, which will not be described in detail here.

[0077] Embodiment 4

[0078] Another embodiment of the present application provides a back-illuminated single-photon avalanche diode image sensor, referring to Figure 6 As shown, it comprises: an imaging wafer 100 having a front surface and a back surface; a substrate wafer 300, wherein the substrate carrier 300 is located below the front surface and attached to the imaging wafer 100'. In one embodiment, a buffer layer 301 is provided between the imaging wafer 100' and the substrate carrier 300.

[0079] The imaging wafer 100' includes a SPAD array located between the front surface and the back surface, a metal reflective layer 109', a dielectric (ILD) layer 110' and a top metal (TM) layer 112' covering the front surface, and a high-k dielectric layer 113', an infrared filter layer 114', an anti-reflection layer 115' and a microlens 116' covering the back surface in sequence. The SPAD array includes: a first type (p--) epitaxial layer 101': a second type (n) doped layer 102' located in the first type epitaxial layer 10'1, used as the cathode region of the SPAD pixel, and the second type (n) doped layer 102' also has a second type deep (n+) doped layer 106' for reading out the cathode region; a first type (p) doped layer 103' located above the cathode region and close to the side of the rear surface, wherein the junction between the first type doped layer 103' and the second type doped layer 102' is an avalanche region 104', and a first type doped layer 105' is also provided above the first type doped layer 103'; a first type deep (p++) doped layer 107' surrounding the first type epitaxial layer 101' and close to the side of the rear surface, used as the anode region of the SPAD pixel; an isolation layer 108' surrounding the anode region 107'.

[0080] The cathode region and the anode region penetrate the metal reflective layer 109 through vias 111 ′ and are connected to the top metal layer 112 ′.

[0081] In one embodiment, the imaging wafer 100' further includes a voltage source 202' and a quenching / charging and readout circuit 203' located on one side of the SPAD pixel, and the top metal layer 112' connected to the anode region is connected to the voltage source 202' via the top metal layer 204', and the top metal layer 112' connected to the cathode region is connected to the quenching / charging and readout circuit 203' via the top metal layer 204'.

[0082] In this embodiment,

[0083] Figure 7 A schematic diagram showing the comparison results of PDE between the SPAD in one embodiment of the present invention and the SPAD in the prior art is shown. It can be seen from the figure that the PDE in the present invention can be improved several times.

[0084] All documents mentioned in this specification are considered to be included in the disclosure of this application as a whole, so that they can be used as a basis for modification when necessary. In addition, it should be understood that the above are only preferred embodiments of this specification and are not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of this specification should be included in the scope of protection of one or more embodiments of this specification.

Claims

1. A stacked back-illuminated single-photon avalanche diode image sensor, characterized in that: include: An imaging wafer having a front surface and a back surface, the imaging wafer comprising; A SPAD array located between the front surface and the back surface, the SPAD array comprising: Type I epitaxial layer: A cathode region, located in the first type epitaxial layer and having a second type doped layer, wherein the second type doped layer is an N-type doped layer; A first type doped layer is located above the cathode region and on a side close to the rear surface, wherein the first type doped layer is a P type doped layer and a P-type doped layer located on a side of the P type doped layer away from the N type doped layer; wherein the junction between the first type doped layer and the second type doped layer is an avalanche region; an anode region, surrounding the first type epitaxial layer on all sides and one side close to the rear surface and having a first type deeply doped layer; An isolation layer surrounding the anode region; A metal reflective layer, a dielectric layer and a top metal layer covering the front surface, wherein the cathode region and the anode region respectively penetrate the metal reflective layer through through holes and are connected to the top metal layer, and the top metal layer and the cathode region are directly connected; A high-k dielectric layer, an infrared filter layer and an anti-reflection layer sequentially covering the rear surface; a logic wafer located below the front surface and attached to the imaging wafer; The widths of the N-type doping layer, the P-type doping layer and the P-type doping layer decrease in sequence.

2. The stacked back-illuminated single-photon avalanche diode image sensor according to claim 1, wherein: The logic wafer includes a voltage source and a quenching / charging and readout circuit, the anode region is connected to the voltage source, and the quenching / charging and readout circuit is connected to the cathode region.

3. The stacked back-illuminated single-photon avalanche diode image sensor according to claim 1, wherein: A grating layer is formed between the cathode region and the metal reflective layer.

4. The stacked back-illuminated single-photon avalanche diode image sensor according to claim 3, characterized in that: The grating layer includes any two of the following alternately formed on the same plane: polysilicon, silicon dioxide, silicon nitride, and Si3N4.

5. The stacked back-illuminated single-photon avalanche diode image sensor according to claim 1, wherein: A Bragg reflection layer is formed between the cathode region and the metal reflection layer.

6. The stacked back-illuminated single-photon avalanche diode image sensor according to claim 5, characterized in that: The Bragg reflection layer is formed by alternating any two of the following: polysilicon, silicon dioxide, silicon nitride, and Si3N4.

7. A stacked back-illuminated single-photon avalanche diode image sensor, characterized in that: include: An imaging wafer having a front surface and a back surface, the imaging wafer comprising; A SPAD array located between the front surface and the back surface, the SPAD array comprising: Type I epitaxial layer: A cathode region, located in the first type epitaxial layer and having a second type doped layer, wherein the second type doped layer is an N-type doped layer; A first type doped layer is located above the cathode region and on a side close to the rear surface, wherein the first type doped layer is a P type doped layer and a P-type doped layer located on a side of the P type doped layer away from the N type doped layer; wherein the junction between the first type doped layer and the second type doped layer is an avalanche region; An isolation layer, surrounding the first type epitaxial layer; an anode region, a first type deeply doped layer located above the first type epitaxial layer and close to the rear surface and penetrating the isolation layer; A metal reflective layer, a dielectric layer and a top metal layer covering the front surface, wherein the cathode region and the anode region respectively penetrate the metal reflective layer through through holes and are connected to the top metal layer, and the cathode region and the top metal layer are directly connected; A high-k dielectric layer, an infrared filter layer and an anti-reflection layer sequentially covering the rear surface; a logic wafer located below the front surface and attached to the imaging wafer; The widths of the N-type doping layer, the P-type doping layer and the P-type doping layer decrease in sequence.

8. A stacked back-illuminated single-photon avalanche diode image sensor, characterized in that: include: An imaging wafer having a front surface and a back surface, the imaging wafer comprising; A SPAD array located between the front surface and the back surface, the SPAD array comprising: Type I epitaxial layer: A cathode region, located in the first type epitaxial layer and having a second type doped layer, wherein the second type doped layer is an N-type doped layer; A first type doped layer is located above the cathode region and on a side close to the rear surface, wherein the first type doped layer is a P type doped layer and a P-type doped layer located on a side of the P type doped layer away from the N type doped layer; wherein the junction between the first type doped layer and the second type doped layer is an avalanche region; An isolation layer, surrounding the first type epitaxial layer; an anode region, a first type deeply doped layer located above the first type epitaxial layer and close to the rear surface; A metal reflective layer, a dielectric layer and a top metal layer covering the front surface, wherein the cathode region penetrates the metal reflective layer through a through hole and is directly connected to the top metal layer, and the anode region penetrates the metal reflective layer through a metal connecting layer and is connected to the top metal layer; A high-k dielectric layer, an infrared filter layer and an anti-reflection layer sequentially covering the rear surface; a logic wafer located below the front surface and attached to the imaging wafer; The widths of the N-type doping layer, the P-type doping layer and the P-type doping layer decrease in sequence.

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