A film layer structure of an array substrate and a method for preparing the same

Abstract

The present invention relates to the technical field of OLED panel array substrates, and in particular to an array substrate film structure and a preparation method thereof, comprising a glass substrate, wherein a first gate metal layer, a first gate insulating layer, a first active layer, a first source-drain metal layer, a first passivation layer, a first flat layer, a first anode layer, a first pixel definition layer and a first cathode layer are sequentially stacked on a normal area on one side of the glass substrate. By arranging the first gate metal layer, the first source-drain metal layer and the first anode layer, and the first gate metal layer, the first source-drain metal layer and the first anode layer in the normal area all adopt a sandwich structure, the normal area has a good display effect and lower power consumption; and the pixel density of the anti-transmittance area and the normal area of ​​the panel can be kept consistent, thereby improving the color difference in appearance caused by leaving some pixels blank and reducing the pixel density in order to ensure the transmittance of the camera area in the existing under-screen camera terminal equipment.

Description

Technical Field

[0001] The present invention relates to the technical field of OLED panel array substrates, and in particular to an array substrate film layer structure and a preparation method thereof. Background Art

[0002] Ever since the concept of "full screen" emerged, people have been moving towards this goal. After hard work, the navigation buttons, earpiece, sensors, fingerprint recognition modules, etc. have been successfully hidden, and the new packaging process has also reduced the width of the border. However, when victory is in sight, the front camera, a "nail house", has become the last obstacle; thus, special-shaped screens have become the mainstream, but have also caused dissatisfaction among a large number of users; although the mechanical structure ensures the integrity of the screen, it makes the body thick and heavy, and its reliability has also decreased.

[0003] The so-called under-screen camera requires that the screen display area above the front camera show a normal display state when the camera is turned off. When the camera is turned on, this area can ensure that the front camera has sufficient light input. Therefore, terminal products equipped with under-screen cameras must use an OLED (organic light-emitting diode) screen with very high light transmittance. Otherwise, insufficient light input will affect the imaging effect of the front camera.

[0004] Although OLED screens are light-transmissive, their transmittance is actually quite low. Optical fingerprint recognition can make up for the low transmittance by illuminating the subject with active high-brightness light from the screen. However, the front-facing camera used for taking photos can only passively receive ambient light in most cases. When the camera module itself is small and has low photosensitivity, transmittance becomes a big problem. The current mainstream approach is this type of "low PPI solution", which does not reduce the PPI (number of pixels per inch) of the entire screen, but only uses this low PPI design on a small part of the screen in the camera area. This also results in display differences with the surrounding screens. The current screen PPI is around 400, and at this level, the transmittance of light in the camera is very low, which seriously affects the photo effect. If the PPI is lowered and the transmittance is increased, there will be a large gap between the PPI of the display area and the PPI of the entire screen, resulting in color blocks in the display area.

[0005] At MWC19 Shanghai, OPPO exhibited its under-screen camera solution "Perspective Panoramic Screen" for the first time, which attracted everyone's attention. However, trial users found that the under-screen camera technology was not as mature as they had imagined: the image clarity was not high when taking pictures, and there was an obvious whitening problem; the display effect in the camera area had a significant color difference from other areas of the screen, which was more obvious when viewed up close. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide an array substrate film layer structure and a preparation method thereof, which can increase the light transmittance of a specific area of ​​a panel without adding an additional mask and reducing the number of pixels.

[0007] In order to solve the above technical problems, the first technical solution adopted by the present invention is:

[0008] An array substrate film layer structure comprises a glass substrate, wherein a first gate metal layer, a first gate insulating layer, a first active layer, a first source-drain metal layer, a first passivation layer, a first flat layer, a first anode layer, a first pixel definition layer and a first cathode layer are sequentially stacked on a normal area of ​​one side of the glass substrate;

[0009] A first via hole is provided on the first gate insulating layer, the first via hole is filled with a first source-drain metal layer, the first source-drain metal layer is in contact with the first gate metal layer, the first gate insulating layer, the first active layer and the first passivation layer respectively, a second via hole is provided on the first source-drain metal layer, the second via hole is filled with a first passivation layer, the first passivation layer is in contact with the first active layer and the first source-drain metal layer respectively, a third via hole is provided on the first passivation layer, a fourth via hole is provided on the first flat layer, the fourth via hole is arranged opposite to and communicates with the third via hole, the third via hole and the fourth via hole are both filled with a first anode layer, the first anode layer in the third via hole is in contact with the first source-drain metal layer and the first passivation layer respectively, the first anode layer in the fourth via hole is in contact with the first flat layer and the first pixel definition layer respectively, a fifth via hole is provided on the first pixel definition layer, the fifth via hole is filled with a first organic light-emitting layer, the first organic light-emitting layer is in contact with the first anode layer, the first pixel definition layer and the first cathode layer respectively;

[0010] The first gate metal layer, the first source and drain metal layer and the first anode layer are all sandwich structures.

[0011] The second technical solution adopted by the present invention is:

[0012] A method for preparing a film layer structure of an array substrate comprises the following steps:

[0013] S1, providing a glass substrate, wherein a first gate metal layer is covered on a normal area of ​​one side of the glass substrate;

[0014] S2, forming a first gate insulating layer covering the surface of the first gate metal layer, and forming a first via hole in the first gate metal layer;

[0015] S3, forming a first active layer, and covering the surface of the first gate metal layer;

[0016] S4, forming a first source-drain metal layer, wherein the first source-drain metal layer covers the surface of the first active layer and the first gate insulating layer respectively and the first via hole is filled with the first gate metal layer; forming a second via hole in the first source-drain metal layer;

[0017] S5, forming a first passivation layer, wherein the first passivation layer covers the surface of the first source and drain metal layer and the second via hole is filled with the first passivation layer; forming a third via hole in the first passivation layer;

[0018] S6, forming a first planar layer covering the surface of the first passivation layer, and forming a fourth via hole in the first planar layer;

[0019] S7, forming a first anode layer, wherein the first anode layer covers the surface of the first flat layer and the third via hole and the fourth via hole are filled with the first anode layer;

[0020] S8, forming a first pixel definition layer, and covering the surfaces of the first passivation layer and the first anode layer respectively, and forming a fifth via hole in the first pixel definition layer;

[0021] S9, forming a first organic light-emitting layer in the fifth via hole;

[0022] S10, forming a first cathode layer and covering the surface of the first pixel definition layer.

[0023] The beneficial effects of the present invention are:

[0024] By setting a first gate metal layer, a first source and drain metal layer and a first anode layer, and the first gate metal layer, the first source and drain metal layer and the first anode layer in the normal area all adopt a sandwich structure, so that the normal area has a good display effect and lower power consumption; and the pixel density of the anti-reflection area and the normal area of ​​the panel can be kept consistent, thereby improving the existing under-screen camera terminal equipment. In order to ensure the transmittance of the camera area, some pixels are left blank and the pixel density is reduced, resulting in color difference in appearance; the array substrate film layer structure designed in this scheme can increase the transmittance of a specific area of ​​the panel without adding an additional mask and without reducing the number of pixels. This can provide better working conditions for various components hidden under the screen, thereby better realizing the full screen. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a structural schematic diagram of a film layer structure of an array substrate according to the present invention;

[0026] Figure 2 is a structural schematic diagram of a film layer structure of an array substrate according to the present invention;

[0027] Figure 3 is a structural schematic diagram of a film layer structure of an array substrate according to the present invention;

[0028] Figure 4 A schematic structural diagram of an application example of an array substrate film layer structure according to the present invention;

[0029] Figure 5 A schematic structural diagram of an application example of an array substrate film layer structure according to the present invention;

[0030] Figure 6 A schematic structural diagram of an application example of an array substrate film layer structure according to the present invention;

[0031] Figure 7 A flowchart of the steps of a method for preparing a film layer structure of an array substrate according to the present invention;

[0032] Description of labels:

[0033] 1. Glass substrate;

[0034] 11. Normal area; 1101. First gate metal layer; 1102. First gate insulating layer; 1103. First active layer; 1104. First source and drain metal layer; 1105. First passivation layer; 1106. First flat layer; 1107. First anode layer; 1108. First pixel definition layer; 1109. First cathode layer; 1110. First organic light emitting layer;

[0035] 12. Anti-reflection region; 1201. Second gate metal layer; 1202. Second gate insulating layer; 1203. Second active layer; 1204. Second source and drain metal layer; 1205. Second passivation layer; 1206. Second flat layer; 1207. Second anode layer; 1208. Second pixel definition layer; 1209. Second cathode layer; 1210. Second organic light-emitting layer; 1211. Metal reflective layer. DETAILED DESCRIPTION

[0036] In order to explain the technical content, achieved objectives and effects of the present invention in detail, the following is an explanation in conjunction with the implementation modes and the accompanying drawings.

[0037] Please refer to Figure 1 , a technical solution provided by the present invention:

[0038] An array substrate film layer structure comprises a glass substrate, wherein a first gate metal layer, a first gate insulating layer, a first active layer, a first source-drain metal layer, a first passivation layer, a first flat layer, a first anode layer, a first pixel definition layer and a first cathode layer are sequentially stacked on a normal area of ​​one side of the glass substrate;

[0039] A first via hole is provided on the first gate insulating layer, the first via hole is filled with a first source-drain metal layer, the first source-drain metal layer is in contact with the first gate metal layer, the first gate insulating layer, the first active layer and the first passivation layer respectively, a second via hole is provided on the first source-drain metal layer, the second via hole is filled with a first passivation layer, the first passivation layer is in contact with the first active layer and the first source-drain metal layer respectively, a third via hole is provided on the first passivation layer, a fourth via hole is provided on the first flat layer, the fourth via hole is arranged opposite to and communicates with the third via hole, the third via hole and the fourth via hole are both filled with a first anode layer, the first anode layer in the third via hole is in contact with the first source-drain metal layer and the first passivation layer respectively, the first anode layer in the fourth via hole is in contact with the first flat layer and the first pixel definition layer respectively, a fifth via hole is provided on the first pixel definition layer, the fifth via hole is filled with a first organic light-emitting layer, the first organic light-emitting layer is in contact with the first anode layer, the first pixel definition layer and the first cathode layer respectively;

[0040] The first gate metal layer, the first source and drain metal layer and the first anode layer are all sandwich structures.

[0041] From the above description, it can be seen that the beneficial effects of the present invention are:

[0042] By setting a first gate metal layer, a first source and drain metal layer and a first anode layer, and the first gate metal layer, the first source and drain metal layer and the first anode layer all adopt a sandwich structure, the normal area has a good display effect and lower power consumption; and the pixel density of the anti-reflection area and the normal area of ​​the panel can be kept consistent, thereby improving the existing under-screen camera terminal equipment, which leaves some pixels blank and reduces the pixel density to ensure the transmittance of the camera area, resulting in color difference in appearance; the array substrate film layer structure designed in this scheme can increase the transmittance of a specific area of ​​the panel without adding an additional mask and reducing the number of pixels, thereby providing better working conditions for various components hidden under the screen, thereby better realizing the full screen.

[0043] Furthermore, the sandwich structure includes a first transparent layer and a first metal layer, and the first transparent layer and the first metal layer are stacked.

[0044] It can be seen from the above description that the sandwich structure adopts a stacked arrangement of the first transparent layer and the first metal layer, which can further increase the light transmittance of a specific area of ​​the panel.

[0045] Furthermore, the first transparent layer is made of indium tin oxide.

[0046] Furthermore, the sandwich structure includes a second transparent layer, a third transparent layer and a second metal layer, and the second metal layer is located between the second transparent layer and the third transparent layer and is in contact with the second transparent layer and the third transparent layer respectively.

[0047] It can be seen from the above description that the sandwich structure adopts the stacking arrangement of the second transparent layer, the third transparent layer and the second metal layer, which can further increase the light transmittance of a specific area of ​​the panel.

[0048] Furthermore, the second via hole is arranged at a position corresponding to the first active layer.

[0049] Furthermore, a sixth via hole is formed on the first source-drain metal layer, and the sixth via hole is filled with a first passivation layer, and the first passivation layer filled in the sixth via hole is in contact with the first gate insulating layer, the first gate metal layer and the first planar layer respectively.

[0050] Please refer to Figure 7 , another technical solution provided by the present invention:

[0051] A method for preparing a film layer structure of an array substrate, characterized by comprising the following steps:

[0052] S1, providing a glass substrate, wherein a first gate metal layer is covered on a normal area of ​​one side of the glass substrate;

[0053] S2, forming a first gate insulating layer covering the surface of the first gate metal layer, and forming a first via hole in the first gate metal layer;

[0054] S3, forming a first active layer, and covering the surface of the first gate metal layer;

[0055] S4, forming a first source-drain metal layer, wherein the first source-drain metal layer covers the surface of the first active layer and the first gate insulating layer respectively and the first via hole is filled with the first gate metal layer; forming a second via hole in the first source-drain metal layer;

[0056] S5, forming a first passivation layer, wherein the first passivation layer covers the surface of the first source and drain metal layer and the second via hole is filled with the first passivation layer; forming a third via hole in the first passivation layer;

[0057] S6, forming a first planar layer covering the surface of the first passivation layer, and forming a fourth via hole in the first planar layer;

[0058] S7, forming a first anode layer, wherein the first anode layer covers the surface of the first flat layer and the third via hole and the fourth via hole are filled with the first anode layer;

[0059] S8, forming a first pixel definition layer, and covering the surfaces of the first passivation layer and the first anode layer respectively, and forming a fifth via hole in the first pixel definition layer;

[0060] S9, forming a first organic light-emitting layer in the fifth via hole;

[0061] S10, forming a first cathode layer and covering the surface of the first pixel definition layer.

[0062] From the above description, it can be seen that the beneficial effects of the present invention are:

[0063] By setting a first gate metal layer, a first source and drain metal layer and a first anode layer, and the first gate metal layer, the first source and drain metal layer and the first anode layer in the normal area all adopt a sandwich structure, so that the normal area has a good display effect and lower power consumption; and the pixel density of the anti-reflection area and the normal area of ​​the panel can be kept consistent, thereby improving the existing under-screen camera terminal equipment. In order to ensure the transmittance of the camera area, some pixels are left blank and the pixel density is reduced, resulting in color difference in appearance; the array substrate film layer structure designed in this scheme can increase the transmittance of a specific area of ​​the panel without adding an additional mask and without reducing the number of pixels. This can provide better working conditions for various components hidden under the screen, thereby better realizing the full screen.

[0064] Furthermore, in the step S4, a sixth via hole is formed in the first source-drain metal layer while the second via hole is formed, and the sixth via hole is filled with the first passivation layer.

[0065] Furthermore, the sandwich structure includes a first transparent layer and a first metal layer, and the first transparent layer and the first metal layer are stacked.

[0066] Furthermore, the sandwich structure includes a second transparent layer, a third transparent layer and a second metal layer, and the second metal layer is located between the second transparent layer and the third transparent layer and is in contact with the second transparent layer and the third transparent layer respectively.

[0067] Please refer to Figures 1 to 6 , Embodiment 1 of the present invention is:

[0068] Please refer to Figure 1 , an array substrate film structure, comprising a glass substrate 1, wherein a first gate metal layer 1101, a first gate insulating layer 1102, a first active layer 1103, a first source-drain metal layer 1104, a first passivation layer 1105, a first flat layer 1106, a first anode layer 1107, a first pixel definition layer 1108 and a first cathode layer 1109 are sequentially stacked on a normal area 11 of one side of the glass substrate 1;

[0069] A first via hole is formed on the first gate insulating layer 1102, and the first via hole is filled with a first source-drain metal layer 1104, and the first source-drain metal layer 1104 is respectively in contact with the first gate metal layer 1101, the first gate insulating layer 1102, the first active layer 1103 and the first passivation layer 1105, a second via hole is formed on the first source-drain metal layer 1104, and the second via hole is filled with the first passivation layer 1105, and the first passivation layer 1105 is respectively in contact with the first active layer 1103 and the first source-drain metal layer 1104, a third via hole is formed on the first passivation layer 1105, and a fourth via hole is formed on the first flat layer 1106. , the fourth via hole is arranged opposite to and communicates with the third via hole, the third via hole and the fourth via hole are both filled with a first anode layer 1107, the first anode layer 1107 in the third via hole is in contact with the first source-drain metal layer 1104 and the first passivation layer 1105 respectively, the first anode layer 1107 in the fourth via hole is in contact with the first flat layer 1106 and the first pixel definition layer 1108 respectively, the first pixel definition layer 1108 is provided with a fifth via hole, the fifth via hole is filled with a first organic light-emitting layer 1110, the first organic light-emitting layer 1110 is in contact with the first anode layer 1107, the first pixel definition layer 1108 and the first cathode layer 1109 respectively;

[0070] The first gate metal layer 1101 , the first source and drain metal layer 1104 and the first anode layer 1107 are all sandwich structures.

[0071] The sandwich structure includes a first transparent layer and a first metal layer, and the first transparent layer and the first metal layer are stacked.

[0072] The material of the first transparent layer is indium tin oxide, and the material of the first metal layer can be one or more metals with good conductivity such as aluminum, molybdenum, titanium, nickel, copper, silver, chromium, and alloys.

[0073] The sandwich structure includes a second transparent layer, a third transparent layer and a second metal layer, wherein the second metal layer is located between the second transparent layer and the third transparent layer and contacts the second transparent layer and the third transparent layer respectively; the second metal layer can be one or more metals with excellent conductivity such as aluminum, molybdenum, titanium, nickel, copper, silver and chromium, as well as alloys; the second transparent layer and the third transparent layer are both made of indium tin oxide.

[0074] The second via hole is arranged at a position corresponding to the first active layer 1103 .

[0075] A sixth via hole is further formed on the first source-drain metal layer 1104 . The sixth via hole is filled with a first passivation layer 1105 . The first passivation layer 1105 filled in the sixth via hole is in contact with the first gate insulating layer 1102 , the first gate metal layer 1101 and the first planar layer 1106 , respectively.

[0076] Please refer to Figure 2 A second gate metal layer 1201, a second gate insulating layer 1202, a second active layer 1203, a second source-drain metal layer 1204, a second passivation layer 1205, a second flat layer 1206, a second anode layer 1207, a second pixel definition layer 1208, and a second cathode layer 1209 are sequentially stacked on the anti-reflection region 12 on one side of the glass substrate 1;

[0077] A first via hole is provided on the second gate insulating layer 1202, the first via hole is filled with a second source-drain metal layer 1204, the second source-drain metal layer 1204 is in contact with the second gate metal layer 1201, the second gate insulating layer 1202, the second active layer 1203 and the second passivation layer 1205 respectively, a second via hole is provided on the second source-drain metal layer 1204, the second via hole is filled with a second passivation layer 1205, the second passivation layer 1205 is in contact with the second active layer 1203 and the second source-drain metal layer 1204 respectively, a third via hole is provided on the second passivation layer 1205, and a fourth via hole is provided on the second flat layer 1206. The fourth via hole is arranged opposite to and communicates with the third via hole, and the third via hole and the fourth via hole are both filled with a second anode layer 1207, and the second anode layer 1207 in the third via hole is respectively in contact with the second source and drain metal layer 1204 and the second passivation layer 1205, and the second anode layer 1207 in the fourth via hole is respectively in contact with the second flat layer 1206 and the second pixel definition layer 1208, and a fifth via hole is opened on the second pixel definition layer 1208, and the fifth via hole is filled with a second organic light-emitting layer 1210, and the second organic light-emitting layer 1210 is respectively in contact with the second anode layer 1207, the second pixel definition layer 1208 and the second cathode layer 1209.

[0078] The second gate metal layer 1201, the second source-drain metal layer 1204 and the second anode layer 1207 are all made of transparent conductive materials. The transparent conductive material used in the anti-reflection region 12 can be transparent oxides such as ITO, CdO, In2O3, SnO2 and ZnO, as well as graphene and carbon nanotubes.

[0079] The light-emitting sub-pixel size of the first pixel definition layer 1108 of the normal area 11 of the present solution is larger than the light-emitting sub-pixel size of the second pixel definition layer 1208 of the anti-reflection area 12;

[0080] Please refer to Figure 3 In order to improve the light utilization rate of the light-emitting layer of the anti-reflection zone 12, a metal reflective layer 1211 can be provided between the second flat layer 1206 and the second anode layer 1207, and the metal reflective layer 1211 is in contact with the second flat layer 1206 and the second anode layer 1207 respectively, so that the anti-reflection zone 12 can achieve the same light utilization rate as the normal zone 11, which can further reduce color deviation.

[0081] The second organic light-emitting layer 1210 is a semi-transparent second organic light-emitting layer 1210 .

[0082] The second active layer 1203 is disposed at a position corresponding to the second gate metal layer 1201 .

[0083] The second via hole is arranged corresponding to the position of the second active layer 1203 .

[0084] A sixth via hole is further formed on the second source-drain metal layer 1204 . The sixth via hole is filled with a second passivation layer 1205 . The second passivation layer 1205 filled in the sixth via hole is in contact with the second gate insulating layer 1202 , the second gate metal layer 1201 , and the second planar layer 1206 , respectively.

[0085] The first gate metal layer 1101 and the second gate metal layer 1201 are the same gate metal layer distributed in different regions and are formed simultaneously during photoresist coating or chemical vapor deposition (CVD) or physical vapor deposition (PVD) processes;

[0086] The first gate insulating layer 1102 and the second gate insulating layer 1202 are the same gate insulating layer distributed in different areas, and are formed simultaneously during photoresist coating or chemical vapor deposition (CVD) or physical vapor deposition (PVD) processes; the material of the gate insulating layer can be selected from inorganic oxides or insulating compounds, such as SiOx, SiNx, titanium oxide and aluminum oxide, and a first via hole is etched on the gate insulating layer to expose the surface of the gate metal layer;

[0087] The first active layer 1103 and the second active layer 1203 are the same active layer distributed in different areas and are simultaneously manufactured and formed during a photoresist coating or chemical vapor deposition (CVD) or physical vapor deposition (PVD) process; the active layer can be made of transparent semiconductor materials such as oxide semiconductors, graphene and carbon nanotubes; the active layer is a transparent semiconductor layer.

[0088] The first source-drain metal layer 1104 and the second source-drain metal layer 1204 are the same source-drain metal layer distributed in different areas, and are simultaneously manufactured and formed during photoresist coating or chemical vapor deposition (CVD) or physical vapor deposition (PVD) processes; the material used for the source-drain metal layer is the same as that of the gate metal layer (the material selection and process are the same as those of the gate metal layer);

[0089] The first passivation layer 1105 and the second passivation layer 1205 are the same passivation layer distributed in different areas, and are formed simultaneously during photoresist coating or chemical vapor deposition (CVD) or physical vapor deposition (PVD) processes; the material used for the passivation layer is the same as that for the gate insulating layer (the material selection and process are the same as those for the gate insulating layer);

[0090] The first planar layer 1106 and the second planar layer 1206 are the same planar layer distributed in different areas and are simultaneously manufactured and formed during photoresist coating or chemical vapor deposition (CVD) or physical vapor deposition (PVD) processes; the material used for the planar layer is the same as that of the gate insulating layer (the material selection and process are the same as those of the gate insulating layer);

[0091] The first anode layer 1107 and the second anode layer 1207 are the same anode layers distributed in different areas, and are simultaneously manufactured and formed during photoresist coating or chemical vapor deposition (CVD) or physical vapor deposition (PVD) processes; the material used for the anode layer is the same as that of the gate metal layer (the material selection and process are the same as those of the gate metal layer);

[0092] The first pixel definition layer 1108 and the second pixel definition layer 1208 are the same pixel definition layer distributed in different areas and are formed simultaneously during photoresist coating or chemical vapor deposition (CVD) or physical vapor deposition (PVD) processes;

[0093] The first cathode layer 1109 and the second cathode layer 1209 are the same cathode layer distributed in different areas, and are formed simultaneously during photoresist coating or chemical vapor deposition (CVD) or physical vapor deposition (PVD) processes; the cathode layer is made of a magnesium-silver alloy or the like;

[0094] The first organic light-emitting layer 1110 and the second organic light-emitting layer 1210 are the same organic light-emitting layer distributed in different areas, and are simultaneously produced during a photoresist coating or chemical vapor deposition (CVD) or physical vapor deposition (PVD) process; the organic light-emitting layer includes a hole injection layer (HIL), a hole transport layer (HTL), an organic light-emitting layer (EM), an electron transport layer (ETL) and an electron injection layer (EIL); the organic light-emitting layer is a semi-transparent organic light-emitting layer.

[0095] The preferred thickness range of the first gate metal layer 1101 is (This thickness range is based on the first gate conductive layer being made of ITO material);

[0096] The preferred thickness range of the first gate insulating layer 1102 is

[0097] The preferred thickness range of the first active layer 1103 is

[0098] The preferred thickness range of the first source-drain conductive layer 1104 is (This thickness range is based on the first gate conductive layer being made of ITO material);

[0099] The preferred thickness range of the first passivation layer 1105 is

[0100] The preferred thickness range of the first planar layer 1106 is 1 μm-2.5 μm;

[0101] The preferred thickness range of the first anode layer 1107 is

[0102] The preferred thickness range of the first pixel definition layer 1108 is 1 μm-2.5 μm;

[0103] The preferred thickness range of the first cathode layer 1109 is

[0104] The preferred thickness range of the second gate metal layer 1201 is

[0105] The preferred thickness range of the second source-drain metal layer 1204 is

[0106] The preferred thickness range of the second anode layer 1207 is

[0107] The preferred thickness range of the metal reflective layer 1211 is

[0108] The thickness of the array film layer of the present invention is given an optimal film thickness range based on the existing substrate structure debugging, but is not limited to this. The thickness of each film layer can be adjusted accordingly to achieve the best requirements based on many considerations such as the basic physical properties of the material, TFT device size and performance design, capacitor charging rate and capacitance design, parasitic capacitance avoidance, panel size, panel transmittance, panel power consumption design, and production efficiency.

[0109] Please refer to the positions of the anti-reflection area 12 and the normal area 11 on the panel. Figure 4 , Figure 5 and Figure 6 There is no special limitation on the shape, size, position and number of the anti-reflection area 12. According to actual design requirements, the anti-reflection area 12 can be of any geometric shape, any size, at any position on the display panel, and in any number, depending on actual design requirements.

[0110] Please refer to Figure 7 , Embodiment 2 of the present invention is:

[0111] A method for preparing a film layer structure of an array substrate comprises the following steps:

[0112] S1, providing a glass substrate 1, wherein a first gate metal layer 1101 is covered on a normal area 11 of one side of the glass substrate 1;

[0113] S2, forming a first gate insulating layer 1102, covering the surface of the first gate metal layer 1101, and forming a first via hole in the first gate metal layer 1101;

[0114] S3, forming a first active layer 1103, and covering the surface of the first gate metal layer 1101;

[0115] S4, forming a first source-drain metal layer 1104, wherein the first source-drain metal layer 1104 covers the surfaces of the first active layer 1103 and the first gate insulating layer 1102 respectively, and the first via hole is filled with the first gate metal layer 1101; forming a second via hole in the first source-drain metal layer 1104;

[0116] S5, forming a first passivation layer 1105, wherein the first passivation layer 1105 covers the surface of the first source and drain metal layer 1104 and the second via hole is filled with the first passivation layer 1105; forming a third via hole in the first passivation layer 1105;

[0117] S6, forming a first planar layer 1106 and covering the surface of the first passivation layer 1105, and forming a fourth via hole in the first planar layer 1106;

[0118] S7, forming a first anode layer 1107, wherein the first anode layer 1107 covers the surface of the first flat layer 1106 and the third via hole and the fourth via hole are filled with the first anode layer 1107;

[0119] S8, forming a first pixel definition layer 1108, and covering the surfaces of the first passivation layer 1105 and the first anode layer 1107 respectively, and forming a fifth via hole in the first pixel definition layer 1108;

[0120] S9, forming a first organic light-emitting layer 1110 in the fifth via hole;

[0121] S10 , forming a first cathode layer 1109 , and covering the surface of the first pixel definition layer 1108 .

[0122] In the step S4 , a sixth via hole is formed in the first source-drain metal layer 1104 while the second via hole is formed. The sixth via hole is filled with the first passivation layer 1105 .

[0123] The sandwich structure includes a first transparent layer and a first metal layer, and the first transparent layer and the first metal layer are stacked.

[0124] The sandwich structure includes a second transparent layer, a third transparent layer and a second metal layer, wherein the second metal layer is located between the second transparent layer and the third transparent layer and contacts the second transparent layer and the third transparent layer respectively.

[0125] In summary, the present invention provides an array substrate film layer structure and a preparation method thereof, by setting a first gate metal layer, a first source and drain metal layer and a first anode layer, and the first gate metal layer, the first source and drain metal layer and the first anode layer in the normal area all adopt a sandwich structure, so that the normal area has a good display effect and lower power consumption; and the pixel density of the anti-transmittance area and the normal area of ​​the panel can be kept consistent, thereby improving the existing under-screen camera terminal equipment. In order to ensure the transmittance of the camera area, some pixels are left blank and the pixel density is reduced, resulting in color difference in appearance; the array substrate film layer structure designed in this scheme can increase the transmittance of a specific area of ​​the panel without adding an additional mask and reducing the number of pixels, thereby providing better working conditions for various components hidden under the screen, thereby better realizing the full screen.

[0126] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent transformations made using the contents of the present invention's specification and drawings, or directly or indirectly applied in related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. An array substrate film layer structure, characterized in that: The invention comprises a glass substrate, wherein a first gate metal layer, a first gate insulating layer, a first active layer, a first source-drain metal layer, a first passivation layer, a first flat layer, a first anode layer, a first pixel definition layer and a first cathode layer are sequentially stacked on a normal area of ​​one side of the glass substrate; A first via hole is provided on the first gate insulating layer, the first via hole is filled with a first source-drain metal layer, the first source-drain metal layer is in contact with the first gate metal layer, the first gate insulating layer, the first active layer and the first passivation layer respectively, a second via hole is provided on the first source-drain metal layer, the second via hole is filled with a first passivation layer, the first passivation layer is in contact with the first active layer and the first source-drain metal layer respectively, a third via hole is provided on the first passivation layer, a fourth via hole is provided on the first flat layer, the fourth via hole is arranged opposite to and communicates with the third via hole, the third via hole and the fourth via hole are both filled with a first anode layer, the first anode layer in the third via hole is in contact with the first source-drain metal layer and the first passivation layer respectively, the first anode layer in the fourth via hole is in contact with the first flat layer and the first pixel definition layer respectively, a fifth via hole is provided on the first pixel definition layer, the fifth via hole is filled with a first organic light-emitting layer, the first organic light-emitting layer is in contact with the first anode layer, the first pixel definition layer and the first cathode layer respectively; The first gate metal layer, the first source and drain metal layer and the first anode layer are all sandwich structures; The sandwich structure comprises a first transparent layer and a first metal layer, wherein the first transparent layer and the first metal layer are stacked; The second via hole is arranged at a position corresponding to the first active layer; A sixth via hole is also formed on the first source-drain metal layer. The sixth via hole is filled with a first passivation layer. The first passivation layer filled in the sixth via hole is in contact with the first gate insulating layer, the first gate metal layer and the first planar layer respectively.

2. The array substrate film layer structure according to claim 1, characterized in that: The material of the first transparent layer is indium tin oxide.

3. The array substrate film layer structure according to claim 1, characterized in that: The sandwich structure includes a second transparent layer, a third transparent layer and a second metal layer, wherein the second metal layer is located between the second transparent layer and the third transparent layer and contacts the second transparent layer and the third transparent layer respectively.

4. A method for preparing the array substrate film structure according to claim 1, characterized in that: The following steps are involved: S1, providing a glass substrate, wherein a first gate metal layer is covered on a normal area of ​​one side of the glass substrate; S2, forming a first gate insulating layer covering the surface of the first gate metal layer, and forming a first via hole in the first gate metal layer; S3, forming a first active layer, and covering the surface of the first gate metal layer; S4, forming a first source and drain metal layer, wherein the first source and drain metal layer respectively covers the surface of the first active layer and the first gate insulating layer, and the first via hole is filled with the first gate metal layer; forming a second via hole in the first source-drain metal layer; S5, forming a first passivation layer, wherein the first passivation layer covers the surface of the first source and drain metal layer and the second via hole is filled with the first passivation layer; forming a third via hole in the first passivation layer; S6, forming a first planar layer covering the surface of the first passivation layer, and forming a fourth via hole in the first planar layer; S7, forming a first anode layer, wherein the first anode layer covers the surface of the first flat layer and the third via hole and the fourth via hole are filled with the first anode layer; S8, forming a first pixel definition layer, and covering the surfaces of the first passivation layer and the first anode layer respectively, and forming a fifth via hole in the first pixel definition layer; S9, forming a first organic light-emitting layer in the fifth via hole; S10, forming a first cathode layer and covering the surface of the first pixel definition layer.

5. The method for preparing the array substrate film structure according to claim 4, characterized in that: In the step S4, a sixth via hole is formed in the first source-drain metal layer while the second via hole is formed. The first passivation layer is filled in the sixth via hole.

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