System and method for performing analog-to-digital conversion across multiple spatially separated stages

Abstract

The present invention provides a signal processing system for transmitting an analog signal from a probe to a remote processing unit. The system includes a first ASIC at the probe, the first ASIC being adapted to receive an analog probe signal. The first ASIC includes an asynchronous sigma-delta modulator, wherein the asynchronous sigma-delta modulator is adapted to: receive the analog probe signal; and output a binary bit stream. The system also includes a second ASIC at the remote processing unit, the second ASIC being adapted to receive the binary bit stream. The asynchronous may also include a time gain function circuit, the first ASIC may also include a multiplexer, and the second ASIC may also include a time to digital converter. The time to digital converter may be a pipelined time to digital converter.

Description

Technical Field

[0001] The present invention relates to the field of signal processing, and more particularly to the field of signal processing across multiple spatially separated stages within an ultrasound system. Background Art

[0002] In the construction of ultrasound probes, high voltage technologies are required to drive the acoustic transducer elements and amplify the received signals. However, these high voltage technologies are not suitable for the implementation of more complex functions such as analog-to-digital conversion (ADC) and digital signal processing (DSP) simply due to the large feature sizes of transistors in these technology nodes, which result in excessively high area, as well as power, consumption and low speed. This problem drives the system selection towards high voltage integrated circuits containing minimal functionality sufficient to transmit the signal to a separate low voltage integrated circuit capable of performing the required signal processing in order to generate an ultrasound image. Low voltage integrated circuits mean small feature size transistors capable of having the most advanced capabilities in terms of speed and power consumption while maintaining their small size.

[0003] Typically, the high voltage integrated circuit is located within the ultrasound probe itself, while the low voltage integrated circuit is located within a back-end processing unit that is connected to the probe via a cable. Therefore, the analog signal received by the high voltage integrated circuit must be propagated between the high voltage integrated circuit and the low voltage integrated circuit. Analog signal propagation is inherently difficult because signal integrity must be maintained in order to properly interpret it at the receiving end. This is further complicated by the variable propagation distance along the cable, signal dissipation within the interconnecting cable wires, and the presence of multiple interfering signals. In addition, emerging applications generally require an increased number of ultrasonic transducers in a 2D configuration, which in turn leads to an increase in the amount of required data channels that must be propagated to the back-end processing system.

[0004] Additionally, the limitations of analog beamforming, which is typically used at the front end to reduce the amount of data transmitted in an analog manner to the back end, must be considered. Analog beamforming introduces limitations on the achievable performance in terms of maximum dynamic range, spatial resolution, and maximum frame rate.

[0005] Finally, all the data must be transmitted to the beamformer in a robust manner. For many non-multiplexed channels, this can be a difficult and expensive process due to the need for many parallel cables. Due to the large number of channels in an acoustic probe, it is beneficial to multiplex as many channels as possible on a single wire; however, there are many difficulties associated with multiplexing of multiple analog signals.

[0006] Therefore, there is a need to provide a robust way to propagate analog signals from one integrated circuit to another without requiring significant additional hardware. Summary of the invention

[0007] The invention is defined by the claims.

[0008] According to an example according to one aspect of the present invention, there is provided a signal processing system for transmitting an analog signal from a probe to a remote processing unit, comprising:

[0009] A first ASIC at the probe, the first ASIC being adapted to receive an analog probe signal, wherein the first ASIC comprises:

[0010] An asynchronous sigma-delta modulator, wherein the asynchronous sigma-delta modulator is adapted to:

[0011] receiving the analog probe signal; and

[0012] Output binary bit stream;

[0013] A second ASIC at the remote processing unit, the second ASIC adapted to receive the binary bit stream.

[0014] The probe (e.g., an ultrasound probe) is adapted to receive analog signals. The probe forms part of a signal processing system, another part of which is a remote processing unit, which is typically separated from the probe by a variable distance. In some applications, the remote processing unit may be located in the same housing as the probe and may even occupy the same printed circuit board (PCB); in other applications, the remote processing unit may be separated from the probe by several meters of cable.

[0015] Maintaining the integrity of analog signals is extremely important for reliably interpreting the signals received by the probe using a remote processing unit. Accurate interpretation is particularly important for medical applications such as ultrasound. Maintaining signal integrity is often difficult when propagating analog signals, especially in cases where those analog signals are weak or where multiple analog signals are being propagated in parallel and subject to interference. In addition, propagating analog signals over considerable distances is expensive because this requires impedance matching, which in turn will depend on the type and length of the cable.

[0016] By performing asynchronous sigma-delta modulation on the analog signal, the analog signal is transformed into a digital time domain signal, wherein the amplitude information is encoded in the time domain, thereby allowing the signal to be propagated to a remote processing unit with greater robustness and with less susceptibility to interference. Furthermore, it is possible to implement a massively parallel readout of all individual transducers in a robust manner; however, the alternative of performing the analog readout and digitization in the first ASIC is much more difficult to implement.

[0017] According to an example according to one aspect of the present invention, there is provided a signal processing system (100) for transmitting an analog signal from a probe to a remote processing unit, comprising:

[0018] a first ASIC at the probe, the first ASIC being adapted to receive analog probe signals acquired from an imaging depth within the object, wherein the first ASIC comprises:

[0019] An asynchronous sigma-delta modulator, wherein the asynchronous sigma-delta modulator is adapted to:

[0020] receiving the analog probe signal; and

[0021] Output binary bit stream;

[0022] a second ASIC at the remote processing unit, the second ASIC being adapted to receive the binary bit stream, and wherein:

[0023] The asynchronous sigma-delta modulator comprises:

[0024] a time gain function circuit adapted to change a time gain function of the asynchronous sigma-delta modulator based on the imaging depth, wherein the time gain function is adapted to:

[0025] A feedback gain of the asynchronous sigma-delta modulator is controlled, thereby controlling the dynamic range of the asynchronous sigma-delta modulator.

[0026] Asynchronous sigma-delta modulators can usually be programmed to accommodate a large dynamic range of incoming signals. However, due to the nature of ultrasound signals, where longer signal acquisition windows result in smaller signal amplitudes, it is often impossible to cover all incoming signal amplitudes with a fixed dynamic range.

[0027] By providing a time gain function circuit with an adjustable time gain function within the feedback loop of the asynchronous sigma-delta modulator, the dynamic range of the asynchronous sigma-delta modulator can be controlled so that the instantaneous dynamic range (at each control setting) is adjusted for the expected incoming signal amplitude. Thus, the dynamic range of the asynchronous sigma-delta modulator can be adjusted over time by the time gain function circuit. Typically, the adjustment is performed over time due to the relationship between time and a given scan depth. However, the adjustment can also be done by the user, for example in a non-time synchronous manner, in order to optimize the current dynamic range to the desired observation properties, such as reducing the detectable signal level in order to image a smaller depth.

[0028] In an embodiment, the signal processing system further comprises a data channel adapted to propagate the binary bit stream from the first ASIC to the second ASIC.

[0029] The data channel may propagate a binary bit stream across a variable distance depending on the application. For example, in a typical ultrasound system, the remote processing unit may be located on the same PCB as the probe, meaning that the data channel will only cover a short distance. Alternatively, in the case of an ultrasound catheter, the data channel may be adapted to propagate a binary bit stream across several meters in order to reach the remote processing unit.

[0030] In some embodiments, the first ASIC operates at a voltage greater than or equal to 1.8V (eg, 2.5V), and wherein the second ASIC operates at a voltage less than or equal to 1.8V (eg, 1.1V).

[0031] In this manner, it is possible to accommodate components with higher voltage requirements on the first ASIC and components with lower voltage requirements on the second ASIC, thereby eliminating the need to sacrifice the efficiency of various components by having them all operate at the same voltage. In addition, this separation between the first ASIC and the second ASIC provides the ability to drive and bias the ultrasound transducer with the high voltage (e.g., 75V) required for its operation.

[0032] In one arrangement, the asynchronous sigma-delta modulator comprises a low noise amplifier.

[0033] In this way, low amplitude signals (such as deep ultrasound reflection signals acquired towards the end of the acquisition window) can be amplified without significantly reducing the signal-to-noise ratio. By integrating a low noise amplifier into an asynchronous sigma-delta modulator, the complexity and implementation cost of the signal processing system can be reduced.

[0034] In yet another arrangement, the asynchronous sigma-delta modulator further comprises a feedback capacitor connected to:

[0035] An output terminal of the low noise amplifier; and

[0036] The input terminal of the low noise amplifier.

[0037] Thus, the LNA can be configured as a charge or current integrator by means of the feedback capacitor.The feedback signal can be added at the LNA input in the form of current or charge, depending on the virtual ground provided by the LNA at this input node.

[0038] In one embodiment, the asynchronous sigma-delta modulator further comprises a low pass filter.

[0039] In various embodiments, the asynchronous sigma-delta modulator further includes an asynchronous binary quantizer.

[0040] In one arrangement, the asynchronous sigma-delta modulator comprises a feedback digital-to-analog converter.

[0041] In this way, through the characteristics of the low-pass filter and the hysteresis of the asynchronous quantizer, the phase shift of the signal within the asynchronous sigma-delta modulator loop can be controlled so that the self-oscillation reaches a frequency greater than or equal to 10 times the Nyquist frequency of the input signal band, thereby reducing the number of spurious signals entering the signal band due to high-amplitude input signals.

[0042] In some arrangements, the first ASIC further comprises an acoustic transducer element, wherein the acoustic transducer element is adapted to receive an incoming acoustic signal and output the acoustic signal.Alternatively, the acoustic transducer is a separate transducer element, such as a piezoelectric transducer, which is electrically connected to the first ASIC.

[0043] In one embodiment, the second ASIC includes a demodulator.

[0044] In this manner, the second ASIC can extract information such as the amplitude of the acoustic signal received by the first ASIC based on the binary bit stream generated by the asynchronous sigma-delta modulator.

[0045] In yet another embodiment, the demodulator is adapted to:

[0046] receiving the binary bit stream; and

[0047] outputting a reconstructed analog signal; and

[0048] The second ASIC further includes an analog-to-digital converter adapted to receive the reconstructed analog signal.

[0049] In various embodiments:

[0050] The probe is an ultrasound probe; and

[0051] The remote processing unit is a backend signal processing unit.

[0052] In this way, the acoustic ultrasound signal received by the probe can be reliably transmitted to the remote processing unit by converting the signal into a binary bit stream. This transmission can be performed over a variety of distances depending on the application. For example, in a conventional ultrasound system, the probe and the remote processing unit can be located in the same probe housing; however, in an ultrasound catheter, the probe and the remote processing unit can be separated by several meters of cable.

[0053] According to an example according to one aspect of the present invention, there is provided a method for transmitting an analog signal from a probe to a remote processing unit, the method comprising:

[0054] receiving an analog signal at a first ASIC at the probe;

[0055] performing asynchronous sigma-delta modulation on the analog signal, thereby generating a binary bit stream; and

[0056] The binary bit stream from the data channel is received at the second ASIC at the remote processing unit.

[0057] According to an example according to one aspect of the present invention, there is provided a method for transmitting an analog signal from a probe to a remote processing unit, the method comprising:

[0058] receiving, at a first ASIC at the probe, an analog signal from an imaging depth within a subject;

[0059] performing asynchronous sigma-delta modulation on the analog signal by an asynchronous sigma-delta modulator, thereby generating a binary bit stream; and

[0060] receiving the binary bit stream from the data channel at the second ASIC at the remote processing unit, and wherein:

[0061] Performing asynchronous sigma-delta modulation on the analog signal includes:

[0062] The time gain function of the asynchronous sigma-delta modulator is varied based on the imaging depth, wherein the time gain function is adapted to:

[0063] A feedback gain of the asynchronous sigma-delta modulator is controlled, thereby controlling the dynamic range of the asynchronous sigma-delta modulator.

[0064] In one embodiment, the analog signal comprises an ultrasonic signal.

[0065] According to an example according to an aspect of the present invention, a computer program is provided, comprising computer program code means, the computer program code means being adapted to implement the method described above when the computer program is run on a computer.

[0066] According to an example according to one aspect of the present invention, there is provided an asynchronous sigma-delta modulator, wherein the asynchronous sigma-delta modulator comprises:

[0067] A time gain function circuit adapted to change a time gain function of the asynchronous sigma-delta modulator, wherein the time gain function is adapted to:

[0068] A feedback gain of the asynchronous sigma-delta modulator is controlled, thereby controlling the dynamic range of the asynchronous sigma-delta modulator.

[0069] In one embodiment, the time gain function circuit comprises a digital-to-analog converter having a switch current array, wherein the switch current array comprises:

[0070] a plurality of current sources, wherein each current source provides a different current;

[0071] A plurality of switches, wherein each switch is connected to a current source, and wherein:

[0072] When the switch is in a closed position, an associated current source is enabled; and

[0073] When the switch is in the open position, the associated current source is disabled; and

[0074] A control interface is adapted to control the positions of the plurality of switches.

[0075] The feedback signal of the ASDM is typically implemented as a current discharged through an integrating capacitor in the LNA feedback controlled by the binary state of the output or by a source of charge (eg, a capacitor), the discharge process again being controlled by the binary state of the output.

[0076] In this way, the time gain function can be controlled by the number of switches in each position.By implementing the current sources so that each current is different, a wide variety of dynamic ranges for the asynchronous sigma-delta modulator can be achieved with the time gain function.

[0077] In yet another embodiment, the control interface comprises a user interface adapted to receive user input.

[0078] In yet another embodiment, the user input includes a specification of a position of each of a plurality of switches.

[0079] In another or further embodiment, the user input comprises a desired dynamic range of the asynchronous sigma-delta modulator.

[0080] In this way, the user may be able to manually change the dynamic range of the asynchronous sigma-delta modulator. This may occur directly, such as selecting which switches in the switch current array should be opened or closed, or it may occur indirectly through selection by the user, such as selecting a desired function that in turn results in a change in the switch position of the switch current array.

[0081] In one arrangement, the plurality of current sources each comprise a switched capacitor.

[0082] According to an example according to an aspect of the present invention, there is provided a system for controlling a dynamic range of an asynchronous sigma-delta modulator, the system comprising:

[0083] An asynchronous sigma-delta modulator as claimed in any preceding claim; and

[0084] An amplitude detector is adapted to provide a control signal to the asynchronous sigma-delta modulator, wherein the control signal is adapted to change the time gain function of the time gain function circuit.

[0085] In an embodiment, the asynchronous sigma-delta modulator comprises a controller adapted to automatically vary the time gain function of the time gain function circuit based on the control signal.

[0086] In this way, the change of the time gain function and thus the dynamic range of the asynchronous sigma-delta modulator can be fully automated.

[0087] In one arrangement, the amplitude detector comprises a counter.

[0088] In an embodiment, the amplitude detector is adapted to receive the output of the asynchronous sigma-delta modulator.

[0089] In yet another embodiment, the control signal is based on the amplitude of the output of the asynchronous sigma-delta modulator.

[0090] By directly detecting the amplitude of the output of the asynchronous sigma-delta modulator, the adjustment of the dynamic range of the asynchronous sigma-delta modulator in response to the incoming signal can be more accurately automated, thereby increasing the accuracy of the output signal. In addition, the asynchronous sigma-delta modulator feedback loop can also prevent overload from large input signals, or can be used in conjunction with gain boost to enable reception of small signals from greater depths.

[0091] Alternatively, amplitude detection may be performed on the signal before it is passed to the quantizer in the asynchronous sigma-delta modulator loop (since the signal amplitude at this point will be proportional to the amplitude of the input signal).

[0092] In some embodiments, the system further comprises a low pass filter connected in series with the asynchronous sigma-delta modulator and the amplitude detector.

[0093] In various arrangements, the system also includes an ultrasonic transducer.

[0094] According to an example according to one aspect of the present invention, there is provided a method for controlling a dynamic range of an asynchronous sigma-delta modulator, the method comprising:

[0095] Obtaining an analog signal;

[0096] performing asynchronous sigma-delta modulation on the analog signal, thereby generating a binary bit stream;

[0097] changing a time gain function of a time gain function circuit within the asynchronous sigma-delta modulator based on a signal of the asynchronous sigma-delta modulator;

[0098] A feedback gain of the asynchronous sigma-delta modulator is controlled based on the time gain function, thereby controlling the dynamic range of the asynchronous sigma-delta modulator.

[0099] In one embodiment, the controlling of the time gain function of the time gain function circuit comprises:

[0100] performing amplitude detection on the binary bit stream, thereby generating output amplitude data;

[0101] generating a control signal based on the output amplitude data; and

[0102] The time gain function of the time gain function circuit is varied based on the control signal.

[0103] According to an example according to one aspect of the present invention, there is provided a system for performing analog-to-digital conversion, the system comprising:

[0104] A probe having a first ASIC, wherein the first ASIC is adapted to:

[0105] receiving an analog signal; and

[0106] The output comprises a binary bit stream of asynchronous time-domain pulses;

[0107] A processing unit having a second ASIC, wherein the second ASIC comprises a time-to-digital converter adapted to:

[0108] receiving the binary bit stream; and

[0109] generating a digital output from the binary bit stream based on a time-to-digital conversion; and

[0110] A data channel is adapted to propagate the binary bit stream from the first ASIC to a second ASIC, wherein the first ASIC and the second ASIC are spatially separated.

[0111] The probe, such as an ultrasound probe, is adapted to receive analog signals. The probe forms part of a signal processing system, another part of which is a processing unit, which is usually separated from the probe by a variable distance. In some applications, the remote processing unit may be located in the same housing as the probe and may even occupy the same PCB; in other applications, the remote processing unit may be separated from the probe by several meters of cable.

[0112] Maintaining the integrity of analog signals is extremely important for reliably interpreting the signals received by the probe using a processing unit. This is particularly important in the case of medical applications such as ultrasound. Maintaining signal integrity is often difficult when propagating analog signals, especially in cases where those analog signals are weak or where multiple analog signals are being propagated in parallel and subject to interference. In addition, propagating analog signals over considerable distances is expensive because this requires impedance matching, which in turn will depend on the type and length of the cable.

[0113] By processing the analog signal to generate a digital time domain signal in which amplitude information can be encoded, the signal can be propagated to a remote processing unit with greater robustness and less susceptible to interference. The digital time domain signal can then be interpreted by the remote processing unit using time-to-digital conversion to generate digital data for interpreting the original analog signal without the difficulties of analog signal propagation. By performing decoding at the remote processing unit using time-to-digital conversion, the time domain signal can be digitized directly.

[0114] In one embodiment, the time-to-digital converter comprises a pipelined time-to-digital converter, and the pipelined time-to-digital converter comprises:

[0115] A coarse time digitizer, wherein the coarse time digitizer is adapted to:

[0116] receiving the binary bit stream; and

[0117] Output:

[0118] Rough digital output; and

[0119] Roughness Residual Time; and

[0120] a fine time digitizer block adapted to receive the coarse residual time, wherein the fine time digitizer block comprises:

[0121] One or more fine time digitizers connected in series, each fine time digitizer being adapted to:

[0122] receiving an incoming residual time from a previous fine or coarse time digitizer in the series;

[0123] outputting the egress residual time to a subsequent fine time digitizer in the series; and

[0124] Outputs fine digital output.

[0125] In one embodiment, the first ASIC includes an asynchronous sigma-delta modulator.

[0126] In this way, an analog signal can be converted into a binary bit stream without the need for a clock signal, thereby reducing the number of components required to transform the analog signal into a digital time domain signal.

[0127] In some embodiments, the asynchronous sigma-delta modulator includes a low noise amplifier.

[0128] In this way, low amplitude signals (such as deep ultrasound reflection signals acquired towards the end of the acquisition window) can be amplified without significantly reducing the signal-to-noise ratio.

[0129] In one arrangement, the asynchronous sigma-delta modulator comprises a low pass filter.

[0130] In various arrangements, the asynchronous sigma-delta modulator includes an asynchronous quantizer.

[0131] In one embodiment, the asynchronous sigma-delta modulator comprises a digital-to-analog converter.

[0132] In this way, the phase shift of the signal within the asynchronous sigma-delta modulator loop can be controlled so that the self-oscillation reaches a frequency greater than or equal to 10 times the Nyquist frequency of the input signal band, thereby reducing the number of spurious signals entering the signal band due to high amplitude input signals.

[0133] In one embodiment, the first ASIC operates at a voltage greater than or equal to 1.8V (eg, 2.5V).

[0134] In one arrangement, the second ASIC operates at a voltage less than or equal to 1.8V (eg, 1.1V).

[0135] In this way, it is possible to accommodate components with higher voltage requirements on a first ASIC and components with lower voltage requirements on a second ASIC, thereby eliminating the need to sacrifice the efficiency of various components by having them all operate at the same voltage.

[0136] In one embodiment, the data channel comprises a single-wire propagation channel.

[0137] According to an example according to one aspect of the present invention, there is provided a method for performing analog-to-digital conversion on an analog signal across a probe and a remote processing unit, the method comprising:

[0138] obtaining an analog signal at a first ASIC at the probe;

[0139] processing the analog signal using the first ASIC to thereby generate a binary bit stream based on the analog signal, wherein the binary bit stream includes asynchronous time-domain pulses;

[0140] propagating the binary bit stream from the first ASIC to a second ASIC at the processing unit, wherein the second ASIC is spatially separated from the first ASIC;

[0141] A time-to-digital conversion is performed on the binary bit stream by means of a time-to-digital converter housed on the second ASIC, thereby generating a digital output.

[0142] In an embodiment, the processing of the analog signal using a first ASIC includes performing asynchronous sigma-delta modulation on the analog signal.

[0143] In some embodiments, the propagation of the binary bit stream from the first ASIC to the second ASIC includes performing a single-wire propagation.

[0144] In one arrangement, the analog signal comprises an ultrasound signal.

[0145] According to an example according to an aspect of the present invention, a computer program is provided, comprising computer program code means, the computer program code means being adapted to implement the method described above when the computer program is run on a computer.

[0146] According to an example according to an aspect of the present invention, there is provided a method for multiplexing a plurality of analog signals each from a separate channel, the method comprising:

[0147] obtaining the plurality of analog signals, each analog signal being obtained from a separate channel, wherein each separate channel is associated with a channel identifier;

[0148] performing asynchronous sigma-delta modulation on each of the plurality of analog signals, thereby generating a plurality of quantized time-domain signals based on the plurality of analog signals, wherein each quantized time-domain signal includes one or more edge timing events associated with signal edges within the quantized time-domain signal; and

[0149] The plurality of quantized time-domain signals are multiplexed in an asynchronous manner based on the one or more edge timing events of each signal and the channel identifier, thereby generating a multiplexed signal in which edge timing events are associated with channel identifiers.

[0150] The parallel propagation of many signals can be difficult and expensive; however, multiplexing of multiple analog signals is extremely difficult to achieve.

[0151] Therefore, by processing the analog signal to generate a digital time domain signal, multiple signals can be more easily multiplexed. Performing this processing in an asynchronous manner allows multiplexing to be performed without the need for a clock. In addition, the inclusion of channel identifiers and edge timing events allows the multiplexed signals to be separated according to the channel after propagation, thereby allowing the multiplexed signals to be interpreted by the back-end processing system.

[0152] By performing asynchronous sigma-delta modulation, each of the multiple analog signals is transformed into a binary bit stream in the time domain. By performing sigma-delta modulation in an asynchronous manner, the need for a clock signal is eliminated, thereby reducing the number of components required to perform the multiplexing operation and the power consumption of the circuit itself.

[0153] In one embodiment, the multiplexing of the plurality of quantized time domain signals comprises:

[0154] For each quantized time domain signal:

[0155] Identify edge timing events; and

[0156] marking the edge timing event with a channel identifier based on the channel from which the associated analog signal was obtained; and

[0157] A multiplexed signal is generated based on the plurality of quantized time-domain signals, wherein the multiplexed signal includes the marked edge timing events.

[0158] By marking each edge timing event with a channel identifier, information can be extracted from the multiplexed signal on a per-channel basis. In this way, the multiplexed signal can carry both timing and channel signal data.

[0159] In some embodiments, the edge timing event comprises a rising signal edge.

[0160] In one arrangement, the edge timing event comprises a falling signal edge.

[0161] By identifying the rising and falling edges of the signal as edge timing events, a greater depth of information can be conveyed within the multiplexed signal, thereby allowing the multiplexed signal to be decoded at a later stage.

[0162] In one embodiment, the method further comprises decoding the multiplexed signal.

[0163] In yet another embodiment, decoding the multiplexed signal includes performing time-to-digital conversion on the multiplexed signal.

[0164] Decoding of the multiplexed signal allows the multiplexed signal to be interpreted, for example, after being propagated to a separate processing location. In this way, information from a plurality of different signal sources can be combined into a single signal, the signal is sent in a simple and robust manner and interpreted at a separate location.

[0165] In another embodiment, the decoding includes time stamping each edge timing event of the multiplexed signal.

[0166] In yet another embodiment, the decoding includes recording a time between each edge timing event of receiving the multiplexed signal.

[0167] By time stamping each edge timing event and / or measuring the time between receiving each edge timing event, the relative timing of each event can be determined. In this way, and taking into account the channel identifier of each of the edge timing events, the original analog signal from the multiplexed signal can be more accurately interpreted.

[0168] In one arrangement, the decoding comprises reconstructing the plurality of analog signals in the digital domain.

[0169] According to an example according to an aspect of the present invention, a computer program is provided, comprising computer program code means, the computer program code means being adapted to implement the method described above when the computer program is run on a computer.

[0170] According to an example according to one aspect of the present invention, there is provided a system for multiplexing a plurality of analog signals, the system comprising:

[0171] an analog signal receiver, wherein the receiver comprises a plurality of channels, each channel being adapted to obtain an analog signal, and wherein each channel is associated with a channel identifier;

[0172] a signal processor comprising an asynchronous sigma-delta modulator and adapted to perform asynchronous sigma-delta modulation on each of the plurality of analog signals, thereby generating a plurality of quantized time-domain signals based on the plurality of analog signals, wherein each quantized time-domain signal comprises one or more edge timing events associated with signal edges within the quantized time-domain signal; and

[0173] A multiplexer is adapted to multiplex the plurality of time domain signals in an asynchronous manner based on the one or more edge timing events of each signal and the channel identifier, thereby generating a multiplexed signal in which edge timing events are associated with channel identifiers.

[0174] In one embodiment, the analog signal receiver includes an ultrasonic transducer.

[0175] In one arrangement, the system further comprises a time to digitizer.

[0176] According to an example according to one aspect of the present invention, there is provided a pipelined time-to-digital converter, the pipelined time-to-digital converter comprising:

[0177] A coarse time digitizer, wherein the coarse time digitizer is adapted to:

[0178] receiving an incoming signal; and

[0179] Output:

[0180] Rough digital output; and

[0181] Roughness Residual Time; and

[0182] a fine time digitizer block adapted to receive the coarse residual time, wherein the fine time digitizer block comprises:

[0183] One or more fine time digitizers connected in series, each fine time digitizer being adapted to:

[0184] receiving an incoming residual time from a previous fine or coarse time digitizer in the series;

[0185] outputting the egress residual time to a subsequent fine time digitizer in the series; and

[0186] Outputs fine digital output.

[0187] Typically, in time-to-digital converter design, there is a trade-off between resolution and dead time (the time between the end of a measurement and the start of a new measurement). Both parameters can be maximized; however, this comes at the expense of excessive power consumption, which is not feasible in systems such as ultrasound systems.

[0188] The coarse time digitizer operates at a low frequency in order to maintain low power consumption. The error in the measurement performed by the coarse time digitizer then needs to be determined in order to achieve high resolution. This error (also known as the time residual) is measured by a subsequent fine time digitizer, which in turn produces an error measured by yet another fine time digitizer, and so on, until the desired resolution is reached.

[0189] Furthermore, while a block of the fine time digitizer is processing the residual time of the initial coarse time digitizer, the latter can start another time measurement, thereby reducing the dead time of the entire system.

[0190] In an embodiment, the coarse time-to-digital converter comprises a ring oscillator.

[0191] In yet another embodiment, the ring oscillator includes a plurality of inverters.

[0192] In another or further embodiment, the ring oscillator comprises a plurality of delay units.

[0193] By employing a ring oscillator within the coarse time digitizer, the time digitizer is able to generate its own clock signal, thereby eliminating the need to include a separate external clock for the system. In this way, the complexity and power requirements of the coarse time digitizer can be reduced.

[0194] The inclusion of a delay cell within a ring oscillator can result in higher resolution and reduction of noise for signals with a potential time resolution of less than 1 ps.

[0195] In one arrangement, the coarse time digitizer comprises a time amplifier.

[0196] In yet another arrangement, the time amplifier is adapted to generate a pulse sequence.

[0197] In yet another embodiment, the pulse train amplifier is a D-flip-flop pulse train time amplifier.

[0198] The time digitizer operates at a given time resolution, accepting the input signal once per given time interval according to its operating resolution. If an input signal (e.g., a pulse) with a width lower than the operating resolution of the time digitizer arrives at the input, the time digitizer will not be able to measure the signal.

[0199] By including a time amplifier within the time digitizer, the pulse width of an incoming signal can be artificially widened by a given factor, thereby enabling the signal to be measured by the time digitizer without requiring a significant increase in the time digitizer's hardware that would otherwise be required to significantly improve the resolution.

[0200] The pulse train amplifier allows for simple programming of accurate linear gain to a desired extension of the input time range. The pulse train amplifier can be implemented using a D flip-flop architecture.

[0201] The offset introduced to the pulse train generated by the pulse train amplifier can be reduced by implementing irregularly distributed delays between successive elements of a (gated) delay line forming part of the pulse train amplifier.The distribution ratio of the delays is technology dependent and may vary across implementations.

[0202] In an embodiment, the coarse time-to-digital converter comprises a selector unit.

[0203] In yet another embodiment, the selector unit comprises a D flip-flop.

[0204] In another or further embodiment, the selector unit comprises a 1-hot converter.

[0205] In another or further embodiment, the selector unit comprises a binary encoder.

[0206] In this way, the selector unit can be implemented in a relatively simple manner and can immediately generate a code word representing the delay.

[0207] In one arrangement, the series of one or more fine time digitizers each comprises:

[0208] 1.5-bit time-to-digital converter; and

[0209] Time amplifier.

[0210] The 1.5 bit time digitizer allows for a simple implementation of the fine time digitizer block.The type of time digitizer used to implement the fine time digitizer may vary depending on the implementation of the pipelined time digitizer.

[0211] According to an example according to one aspect of the present invention, there is provided a method for performing time-to-digital conversion, the method comprising:

[0212] Get incoming signals;

[0213] A coarse time-to-digital conversion is performed on the incoming signal, thereby generating:

[0214] Rough digital output; and

[0215] Roughness Residual Time; and

[0216] A series of one or more fine time digital conversions are performed on the incoming residual time, thereby generating:

[0217] Remaining time outside the home; and

[0218] Fine digital output;

[0219] Wherein, the incoming residual time includes:

[0220] the coarse residual time generated by the coarse time digitizer; or

[0221] The outgoing residual time is generated by a previous fine pipelined time digitizer in the series of one or more fine time digitizers.

[0222] In one embodiment, the incoming signal comprises a series of time-domain pulses.

[0223] According to an example according to an aspect of the present invention, a computer program is provided, comprising computer program code means, the computer program code means being adapted to implement the method described above when the computer program is run on a computer. BRIEF DESCRIPTION OF THE DRAWINGS

[0224] Examples of the present invention will now be described in detail with reference to the accompanying drawings, in which:

[0225] Figure 1 shows a schematic diagram of a signal processing system;

[0226] Figure 2 shows a schematic diagram of an asynchronous sigma-delta modulator;

[0227] Figure 3 Shows Figure 1 The processing chain of the signal processing system;

[0228] Figure 4 A schematic diagram showing an embodiment of an asynchronous sigma-delta modulator including a time gain function circuit is shown;

[0229] Figure 5 Shows Figure 4 An embodiment of the time gain function circuit shown in;

[0230] Figure 6 Shows Figure 1 An embodiment of the probe shown in;

[0231] Figure 7 shows a multiplexer Figure 1 Embodiments of a signal processing system;

[0232] Figure 8 shows a graph of several exemplary signals generated by an asynchronous sigma-delta modulator;

[0233] Fig. 9 shows a time-to-digital converter Figure 1 Embodiments of a signal processing system;

[0234] Fig.10 shows a schematic diagram of a pipelined time-to-digital converter;

[0235] Fig.11 A schematic diagram showing a coarse time digitizer; and

[0236] Fig.12 A schematic diagram of a fine time digitizer is shown. DETAILED DESCRIPTION

[0237] In a first aspect, a signal processing system for transmitting an analog signal from a probe to a remote processing unit is provided. The system includes a first ASIC at the probe adapted to receive the analog probe signal. The first ASIC includes an asynchronous sigma-delta modulator, wherein the asynchronous sigma-delta modulator is adapted to: receive the analog probe signal; and output a binary bit stream. The system also includes a second ASIC at the remote processing unit adapted to receive the binary bit stream.

[0238] Figure 1 A schematic diagram of a signal processing system 100 is shown. The signal processing system comprises a first ASIC 110 and a second ASIC 120, wherein the first ASIC is located on a probe 130 and the second ASIC is located on a remote processing unit.

[0239] exist Figure 1In the example shown in , the signal processing system forms part of an ultrasound system, wherein a probe 130 housing a first ASIC 110 further comprises an acoustic transducer array 140 adapted to transmit ultrasound signals and receive echo signals from an object. Within the first ASIC are a plurality of asynchronous sigma-delta modulators 150, each of which is connected to an associated transducer element 160 of the acoustic transducer array.

[0240] Figure 2 The asynchronous sigma-delta modulator 150 is shown in greater detail connected in series with the transducer element 160. In this example, an asynchronous sigma-delta modulator is provided for each transducer element or readout channel of the probe 130.

[0241] Asynchronous sigma-delta modulators are closed-loop nonlinear systems capable of maintaining inherent stable oscillations (represented as limit cycles) that transform information in terms of the amplitude of their input signal into time information in terms of their output signal. The limit cycle oscillations are due to self-oscillation mechanisms governed by components of the closed-loop asynchronous sigma-delta modulator, such as the loop filter 170 and the binary quantizer 180. For ultrasound systems, the input signal typically has a frequency in the range of 2.5–5 MHz. In this case, the self-oscillation of the asynchronous sigma-delta loop will have a frequency of 50 MHz, which is then modulated by the input signal.

[0242] The amplitude-to-time conversion performed by the asynchronous sigma-delta modulator 150 is free of quantization noise and can be achieved with very high accuracy due to the noise shaping properties of the loop. The achievable performance in a given low frequency band is determined by the self-oscillation frequency of the asynchronous sigma-delta modulator and the thermal noise of the implementation. The binary time domain signal generated by the asynchronous sigma-delta modulator is fed to the second ASIC 120 for further processing. In the second ASIC, the amplitude information can be decoded using simple low-pass filtering, or additional further processing can be performed on the binary time domain signal. In the absence of an input signal, the asynchronous sigma-delta modulator generates a sequence of positive and negative pulses with a 50% duty cycle at a frequency controlled by the structure of the closed loop (called the limit cycle idle frequency or center frequency).

[0243] In other words, the asynchronous sigma-delta modulator 150 encodes the amplitude information in the time domain in a binary bit stream. In this way, the signal propagation becomes binary (digital), which means that the signal can be propagated to subsequent processing elements between the first ASIC 110 and the second ASIC 120 with much higher robustness to interference and crosstalk and at a lower cost.

[0244] The first ASIC 110 may operate at 1.8V, 2.5V or 3.3V depending on the application, and the second ASIC 120 may operate at voltages from 1.8V down to 1.1V or lower. In the example of an ultrasound system, the transducer array may operate at voltages up to 75V.

[0245] exist Figure 2 In the example shown in , an asynchronous sigma-delta modulator is constructed in a specific manner using components tailored for signal acquisition from an ultrasound transducer. Specifically, an input low noise amplifier 190 (LNA) is included in the asynchronous sigma-delta modulator loop.

[0246] The LNA 190 can be configured as a charge or current integrator by means of a feedback capacitor 200. Depending on the virtual ground provided at the input node, the feedback signal of the capacitor can be added at the LNA input in the form of current or charge. An additional loop stage is required for controlling the phase shift in the asynchronous sigma-delta modulator loop in order to ensure that self-oscillation is achieved at a frequency exceeding the Nyquist frequency of the input signal band by at least 10 times. This high oscillation frequency is required to prevent parasitic components from entering the signal band when receiving high amplitude input signals. The loop filter 170 can also be implemented in a passive manner (for example, using resistors and capacitors).

[0247] The loop ends with an asynchronous binary quantizer 180 which produces a binary output signal. The quantizer can directly drive an inverter which in turn can drive a link to another processing step, such as a second ASIC, for example via a digital buffer.

[0248] The operation of asynchronous sigma-delta modulators is further discussed in Ouzounov, S. et al. (2006), Analysis and Design of High-Performance Asynchronous Sigma-Delta Modulators With a Binary Quantizer (IEEE Journal of Solid-State Circuits, 41(3), pp. 588-596).

[0249] exist Figure 3, a processing chain for one transducer element 160 is shown, wherein an acoustic ultrasound signal is received by the transducer element and propagated to an asynchronous sigma-delta modulator 150, which transforms the acoustic ultrasound signal into a binary time domain signal. The binary bit stream is then propagated to a second ASIC by means of a data channel 210, which may, for example, include a demodulator 220 and an analog-to-digital converter 230. In the typical case of an ultrasound imaging probe, the data channel may be a PCB trace connecting the two ASICs. In the case where the signal processing system is implemented into an ultrasound catheter, the first ASIC is at the top of the catheter. Thus, the data channel may be a current or optical link of several hundred centimeters, and the second ASIC may be located at a separate back-end processing unit or in the probe handle.

[0250] Figure 3 The example shown in shows the case where one asynchronous sigma-delta modulator 150 is provided for each transducer element 160. Alternatively, several transducer elements may be time multiplexed to one asynchronous sigma-delta modulator, or in another case, data from several transducer elements may be combined before or after each asynchronous sigma-delta modulator, for example using analog beamforming.

[0251] Embodiments of asynchronous sigma-delta modulators have been described in the context of ultrasound systems; however, this approach can be applied in any situation where it is beneficial to separate the sensor (such as a transducer array) from the post-processing circuitry (which may be due to technology, size, or cost constraints). An example of the latter is a DNA sequencing system, where the sensor array is disposable and produced using cheap and obsolete technology. On the other hand, signal processing is complex and consumes a lot of power, and is therefore best implemented in more advanced technology nodes. Yet another example is a sensor on a flexible substrate (e.g., foil) that does not support the high quality or small feature size devices required to perform signal processing.

[0252] In yet another example, an asynchronous sigma-delta modulator is provided, comprising a time gain function circuit adapted to change a time gain function of the asynchronous sigma-delta modulator. The time gain function is adapted to control a feedback gain of the asynchronous sigma-delta modulator, thereby controlling a dynamic range of the asynchronous sigma-delta modulator.

[0253] Figure 4An embodiment of an asynchronous sigma-delta modulator 150' is shown, where further power optimization can be achieved by adding additional functionality in the asynchronous sigma-delta modulator loop. This embodiment details the addition of a time gain control (TGC) function by means of a TGC circuit 240. In general, an asynchronous sigma-delta modulator can be designed to have a large dynamic range for receiving input signals; however, it may not cover the entire dynamic range required by an ultrasound system. The dynamic range can be controlled by the TGC function.

[0254] The time gain function can be used to compensate for the attenuation of the received echo signal according to the imaging depth. The attenuation of the received echo signal increases with increasing imaging depth and increasing transmission frequency. The imaging depth of the signal is related to the reflection time, which means that the signal will be increasingly attenuated as time goes by. If not compensated, the signal attenuation can cause severe signal loss.

[0255] In general, the TGC function requires an additional gain stage, such as a frequency-dependent sliding potentiometer that allows the gain to be interactively determined by the user, which in turn occupies chip area and consumes a lot of power. Control of the TGC gain stage is slow and is often performed at the back-end processing unit. The local control loop that detects the signal strength and adjusts the gain accordingly is too complex to be accurately implemented and will cause excessive power consumption. The simplest example of a time gain function is a linear increase over time, where a steeper linear function can be used in cases where the attenuation is higher, for example when a high-frequency transmit signal is used. In addition, the TGC function can be adapted to accommodate knowledge from the user about what is being imaged. In this way, the TGC function achieves further optimization of image quality.

[0256] As discussed above, as a principle of operation, the asynchronous sigma-delta modulator 150' encodes analog amplitude information in a binary time domain signal. The encoding is completely asynchronous, meaning there is no need for a local time reference. Dynamic Range The asynchronous sigma-delta modulator loop is typically scaled to the maximum expected amplitude of the input signal received at the transducer element 160 by sizing the feedback signal.

[0257] To avoid overloading, the feedback signal strength is designed to be approximately 25% stronger than the strongest input signal expected to appear at the input of the asynchronous sigma-delta modulator 150'. In ultrasound and other types of sensing signal acquisition, the input signal is expected to change in time with some known function. For example, in the case of ultrasound, the longer the acquisition time window, the lower the amplitude of the arriving signal due to deeper reflections of the signal in the body. The asynchronous sigma-delta modulator can be adjusted to accommodate expected changes in the input signal amplitude range by adjusting the strength of the feedback signal with the aid of the TGC circuit 240.

[0258] The implementation of the TGC functionality is based on a realization that the first operation of the asynchronous sigma-delta modulator loop is to subtract the feedback signal from the input signal. It should be noted that the feedback signal is a time-encoded representation of the input signal generated by the asynchronous sigma-delta modulator.

[0259] For zero input, the average feedback signal is also zero. As the input signal amplitude increases, the average feedback signal increases similarly. The point at which the feedback signal fails to match the input signal strength is called the overload point. The dynamic range of an asynchronous sigma-delta modulator lies between zero input and the overload point.

[0260] It should be noted that in actual implementations, there is always some noise present in the system due to the building blocks of the asynchronous sigma-delta modulator. The noise level determines the sensitivity of the asynchronous sigma-delta modulator, in other words, the minimum signal amplitude that the asynchronous sigma-delta modulator is able to encode and that therefore appears in the asynchronous sigma-delta modulator feedback signal. In order to detect very small signals (which in the context of ultrasound may mean signals coming from greater depths and / or having higher frequencies), the noise of the asynchronous sigma-delta modulator should be minimized.

[0261] The operation of the TGC circuit can be described in terms of various imaging depths.

[0262] For imaging at close depths, no additional gain is needed. The asynchronous sigma-delta modulator feedback is adapted to handle the maximum signal from the transducer without overloading under these conditions. This means that the maximum feedback signal is used. It should be noted that the minimum input signal that can be encoded taking into account noise also depends on the ratio between the input signal strength and the feedback strength. When the feedback is too strong (e.g. 1000 times stronger), the time required to accurately encode these inputs is too high, meaning that smaller amplitude signals become "invisible" to the asynchronous sigma-delta modulator.

[0263] When the imaging depth is increased, it means that more time has passed since the start of reception and the desired signal has become weaker. In a classical TGC circuit, additional gain is turned on to compensate for this. In the case of an asynchronous sigma-delta modulator, this means that the feedback signal can be attenuated, for example by scaling it. This means that the asynchronous sigma-delta modulator is able to detect smaller amplitude signals at the input, resulting in an overall extension of the dynamic range of the asynchronous sigma-delta modulator. Scaling of the feedback can be done multiple times and in a discrete or continuous manner to take into account larger imaging depths.

[0264] Figure 5 An example of a possible programmable feedback implementation of a TGC circuit 240 is shown. In this case, the TGC circuit includes a set of current sources (I1, I2, ..., I2) selected by the user of the system or by an automatic loop using a set of switches 250. n ), each current source having a different strength. Alternatively, a switched capacitor network may be used in an implementation of the TGC circuit, wherein feedback of the capacitor controls the dynamic range scaling of the asynchronous sigma-delta modulator. The charging and discharging of the capacitor is controlled by the binary output signal of the asynchronous sigma-delta modulator. In addition, the TGC circuit can control characteristics that determine when and how much the dynamic range of the asynchronous sigma-delta modulator will be adjusted. For example, in an ultrasound machine, this can be selected by the user. However, it is often practical to automatically adjust the dynamic range in order to avoid accidental overloading of the asynchronous sigma-delta modulator.

[0265] In the context of an asynchronous sigma-delta modulator, the digital-to-analog converter is typically a binary digital-to-analog converter, meaning that when the output of the asynchronous sigma-delta modulator is 1, the digital-to-analog converter generates a positive analog current. When the output of the asynchronous sigma-delta modulator is zero, the digital-to-analog converter generates a negative analog current. The value of the generated current (or the integrated charge in the case of a switched capacitor array) determines the amount of feedback and therefore the dynamic range of the asynchronous sigma-delta modulator. The minimum possible feedback current should be at least 25% greater than the maximum expected current from the ultrasound transducer when acquiring signals at the maximum depth. Similar rules apply when performing low depth imaging (where the input signal has a high amplitude). The asynchronous sigma-delta modulator feedback signal amplitude must exceed the maximum expected input signal amplitude by at least 25%.

[0266] The binary time-domain output signal of the asynchronous sigma-delta modulator is converted into an analog signal (usually a current) that is fed back and subtracted from the input signal. When the feedback signal is a current, the feedback implementation can, for example, take the form of a transistor that operates as a current source and is controlled in an on / off mode by a binary output. There are two feedback parameters: the first is the value of the current, which represents the feedback strength and encoding capability; and the second is how much time the current is intended to encode the input signal. The feedback is adjusted by scaling the value of the current source or by selecting the desired value from a library of current sources (such as a switched current array). Alternatively, the feedback can be implemented by a resistor that acts as a current source.

[0267] Figure 6 Shows Figure 1 The embodiment of the probe 130' shown in FIG. Figure 4 An asynchronous sigma-delta modulator 150' is shown in Figure 1 and a digital amplitude detector 260 used to estimate the signal amplitude at the input of the asynchronous sigma-delta modulator. The detector can be implemented by a simple counter that reports when more 1s or 0s are counted from the binary bit stream generated by the asynchronous sigma-delta modulator, which is a direct measure of the input signal strength. This can then be communicated to the asynchronous sigma-delta modulator and more specifically to the TGC circuit to change the TGC function of the asynchronous sigma-delta modulator loop, thereby controlling the dynamic range of the input. Since the feedback signal within the asynchronous sigma-delta modulator loop is subtracted from the input and the error from the subtraction is minimized in time by the loop operation, a stronger feedback signal means that a higher amplitude input signal can be processed by the loop. Similarly, if the processing of a lower amplitude signal is desired, the strength of the feedback signal needs to be reduced. In other words, the dynamic range of the asynchronous sigma-delta modulator loop is automatically scaled to fit the input signal.

[0268] In yet another example, a method for multiplexing multiple analog signals each from a separate channel is provided. The method includes: obtaining multiple analog signals, and generating multiple quantized time domain signals based on the multiple analog signals in an asynchronous manner. Finally, the multiple quantized time domain signals are multiplexed, thereby generating a multiplexed signal, in which edge timing events are associated with channel identifiers.

[0269] Replay Figure 1, it can be seen that large arrays of transducers may be required in various imaging and sensing applications. Typically, these generate large amounts of data that undergo complex signal processing before the final results are available. Sometimes, signal processing requires bulky and power-hungry equipment, while the sensing array needs to be kept small, especially in cases where freedom of movement of the probe is required. Two processing systems (in Figure 1 In the example shown in FIG. 1 , these are the first ASIC 110 and the second ASIC 120) and then mechanically separated and kept electrically connected by a cable. Typically, the cable contains a separate wire for each transducer element 160 of the transducer array 140. Cables with up to about 260 wires are known to have been used in the industry for such purposes. Each transducer element of the array generates an analog signal that can be converted into a specific (electrical) quantity by adjusting the electronic device. Typically, this conversion does not occur, and the analog signal is simply amplified before being propagated to the remote processing device. The disadvantage of having a dedicated electrical connection between each transducer element 160 of the transducer array 140 and the remote signal processing backend on the second ASIC 120 is that it cannot be well scaled for large array sizes. Cables with hundreds or even thousands of wires can be manufactured, but are too bulky and expensive. There are methods of combining signals from multiple elements and transmitting them through a single channel, resulting in a reduction in the number of cable wires. However, multiplexing analog signals is generally a complex, power-intensive and unreliable process.

[0270] Figure 7 Shows Figure 1 An embodiment of a signal processing system 100' is provided which includes a multiplexer 270 connected to a plurality of asynchronous sigma-delta modulators 150 housed on a first ASIC housed within a probe 130". In this case, the analog signals received by the transducer elements are passed through the asynchronous sigma-delta modulators, thereby generating a plurality of binary bit streams in the time domain, which can then be combined into a multiplexed signal. In this way, the cable wire count can be reduced and large array sizes are allowed. Furthermore, this can be implemented without using a sampling clock in the first ASIC 110, thereby reducing the number of components and the power consumption required to propagate signals between the first ASIC 110 and the second ASIC 120.

[0271] In other words, the asynchronous sigma-delta modulator 150 converts the acoustic signal from each transducer element 160 into the time domain. The multiplexer 270 then encodes each event from the transducer array and transmits it to the second ASIC 120 via the data channel 210. The exact number of conductors within the data channel depends on the implementation of the multiplexer. If full serial communication is selected, then in principle, the transmission can be achieved using a single transmission conductor and a reference conductor. The remote processing unit includes a second ASIC 120 adapted to interpret the multiplexed signal. In some examples, the ASIC includes a time-to-digital converter, the function of which is further described below. Using the measurement results from the second ASIC, the binary bit stream can be fully reconstructed in the digital domain.

[0272] Figure 8 A graph 280 is shown of several exemplary binary bit streams from the asynchronous sigma-delta modulator 150 of the probe 130″ arranged according to which channel (transducer element 160) the signal was initially received at. In this example, the signals are received for three channels (ch1, ch2, and ch n ) shows a signal, where n is the total number of channels and will vary depending on the application in question. The rising and falling edges of each binary bit stream waveform are not synchronous and can occur at any time.

[0273] Since the timing of the edge timing events of each waveform is significant, the multiplexer 270 can treat each rising edge or falling edge as a separate edge timing event. For example, the multiplexer can mark each edge timing event with a unique (digital) identifier and transmit them to the second ASIC in an asynchronous manner.

[0274] For example, Figure 8 As shown in: at time t1, the multiplexer sends a signal of the rising edge of channel 2; at time t2, the multiplexer sends a signal of the rising edge of channel 1; at time t3, the multiplexer sends a signal of the falling edge of channel 3; and so on.

[0275] Figure 8 The signaling scheme shown in can be implemented, for example, by sending a number corresponding to the channel number in combination with a number representing the edge type (ie, rising or falling) of the edge timing event at the appropriate moment in the multiplexed signal. Figure 8 In the example shown in , at the following times:

[0276] -t1: Send the number 2 corresponding to channel 2 and the number 1 corresponding to the rising edge,

[0277] -t2: Send the digital 1 corresponding to channel 1 and the digital 1 corresponding to the rising edge,

[0278] -t3: Sends the digital 3 corresponding to channel 3 and the digital 0 indicating a falling edge.

[0279] Depending on the architecture of the multiplexer and the link to the second ASIC, these combinations of numbers can be sent in parallel or serially. For example, should the total number of channels be three and parallel binary signaling be selected, at t1 the binary word sent would be 101 (i.e., the channel number, followed by the edge type identifier), at t2, 011, and at t3, 110. Any other suitable implementation may be selected depending on the application. The receiving end at the second ASIC is event driven and will react to each change of the input signal. Since the occurrence of two consecutive codes of the same value (i.e., two consecutive rising or falling edges on the same channel) is excluded, there will be no missed edge timing events.

[0280] Since the time of transmission of each edge timing event identifier by the multiplexer 270 coincides with the occurrence of the event it describes, the entire data stream can be reconstructed at the second ASIC 120 by time stamping each incoming event identifier or by measuring the time between received events. It is possible that two or more edge timing events can occur simultaneously, especially for systems with lower time resolution. Concurrent edge timing events can be detected concurrently but processed sequentially. The timing errors that this will cause will appear as random errors in the signal arriving at the second ASIC and will be filtered out by the noise shaping function. In other words, concurrent events can be buffered and transmitted sequentially with minimal penalty to accuracy.

[0281] In yet another example, a system for performing analog-to-digital conversion is provided, the system comprising: a probe having a first ASIC; a processing unit having a second ASIC; and a data channel. The first ASIC is adapted to: receive an analog signal and output a binary bit stream comprising asynchronous time domain pulses. The second ASIC is adapted to: receive the binary bit stream; and generate a digital output based on time-to-digital conversion. The data channel is adapted to propagate the binary bit stream from the first ASIC to the second ASIC, wherein the first ASIC and the second ASIC are spatially separated.

[0282] Fig. 9 Shows Figure 3, wherein the probe 130 comprises a transducer element 160 and an asynchronous sigma-delta modulator 150. Furthermore, a second ASIC 120 connected to the first ASIC within the probe by means of a data channel 210 comprises a time-to-digital converter 290. In other words, the signal processing system comprises asynchronous sigma-delta modulators and time-to-digital converters that are spatially distributed across two different technologies (the first ASIC 110 and the second ASIC 120) and at large distances from each other in some applications depending on the specific needs of the ultrasound system.

[0283] As discussed above, the asynchronous sigma-delta modulator encodes the incoming analog amplitude information in a binary time domain signal, and the encoding is completely asynchronous. Therefore, the time-to-digital converter 290 can be used to retrieve the encoded amplitude information from the binary bit stream generated by the asynchronous sigma-delta modulator 150. After the time-to-digital conversion, the retrieved data, now in digital form, can be used to analyze the original analog signal. If the signal processing system is included in the ultrasound system, the retrieved data can be used to construct an ultrasound image.

[0284] Since the data leaving the asynchronous sigma-delta modulator 150 is asynchronous, the time-to-digital converter 290 operates using an internal clock signal in order to properly sequence and correlate the incoming signals.

[0285] In the current embodiment, the clock frequency of the time-to-digital converter is a function of the required dead time. The dead time is determined by the maximum acceptable error during signal reconstruction while still being able to achieve the required SNR.

[0286] The time-to-digital converter can be configured to operate in a variety of ways, such as measuring the time between events or simply timestamping events as they arrive; however, in the case of interpreting asynchronous signals generated by asynchronous sigma-delta modulators, the preferred mode of operation is to measure the length of time between two events in the time domain. Therefore, it will not be possible to timestamp these events unless there is additional circuitry that accumulates the time differences and represents them as the total time elapsed from an arbitrary starting point. Of course, timestamping can be used instead of measuring the time between successive events, but will require a sufficiently accurate time reference, which will most likely be less power efficient.

[0287] In a system where each transducer element 160 is connected to an individual asynchronous sigma-delta modulator 150 (which is connected to an individual time digitizer 290), the first operating mode may be preferred. Alternatively, where multiple transducer elements are connected to a single asynchronous sigma-delta modulator, the time digitizer may be operated in the second mode. In yet another example, where the signals of multiple asynchronous sigma-delta modulators are multiplexed and received by a single time digitizer as described above, the time digitizer may be operated in the second mode.

[0288] In yet another example, a pipelined time digitizer is provided, comprising a coarse time digitizer and a fine time digitizer block. The coarse time digitizer is adapted to: receive an incoming signal and output both: a coarse digital output; and a coarse residual time. The fine time digitizer block receives the coarse residual time and comprises one or more fine time digitizers connected in series. Each of the one or more fine time digitizers is adapted to: receive an incoming residual time from a previous fine or coarse time digitizer in the series, and output both: an outgoing residual time to a subsequent fine time digitizer in the series; and a fine digital output.

[0289] Fig.10 Shown is a schematic representation of a pipelined time digitizer 300. The pipelined time digitizer comprises a coarse time digitizer 310 and a fine time digitizer block 320 comprising a plurality of fine time digitizers 330.

[0290] Typically, a time digitizer is needed to process information in the time domain, such as a binary bit stream generated by an asynchronous sigma-delta modulator as described above. In this case, the information signal at the input of the TDC consists of a sequence of events represented by pulses. The time digitizer can measure the time between two pulses and represent it as a digital signal. The time between these pulses must be determined with sufficient fidelity for correct signal processing to occur.

[0291] Several performance characteristics of the time-to-digital converter are extremely important to achieving this fidelity. First, each time segment must be measured with sufficient accuracy, and the converter must be able to start a subsequent measurement sufficiently quickly after the previous measurement. The time between the end of a measurement and the start of a new measurement is called the dead time. In an idealized case, the dead time of the time-to-digital converter is zero. Finally, the converter must be able to detect the entire range of time segments generated by the first ASIC 110 and more specifically by the asynchronous sigma-delta modulator 150. In other words, the time-to-digital converter must have sufficient dynamic range.

[0292] Typically, there is a trade-off between resolution and dead time in conventional time-to-digital converter designs. Increasing the resolution of the converter generally results in an increase in dead time. Of course, both parameters can be optimized, but at the expense of power consumption. For example, a high frequency converter running continuously will have a resolution proportional to the bit aperture and a dead time inversely proportional to the operating frequency. However, the power consumption will be proportional to both parameters, meaning that such a design is hardly feasible.

[0293] Fig.10 The pipelined time digitizer 300 shown in Figure 1 achieves both high resolution and low dead time without compromising on power consumption. The pipelined time digitizer consists of a plurality of cascaded individual time digitizer stages. The first stage is a low latency coarse time digitizer 310, for example based on a ring oscillator or a counter, which operates at a low frequency for low power consumption. The frequency of the ring oscillator is inversely proportional to the dead time of the time digitizer.

[0294] Each measurement made by the coarse time digitizer 310 generates an error called the residual time, which needs to be determined and taken into account in order to obtain high resolution. The residual is measured in a subsequent stage consisting of a fine time digitizer 330. The residual of this second stage is then fed to another fine time digitizer, and this is repeated until the desired resolution is reached.

[0295] Fig.11 The coarse time digitizer 310 is shown in more detail.

[0296] exist Fig.11In the embodiment shown in , the incoming signal is first received by a multiplexer 340, which may be adapted to combine the incoming signals from multiple channels into a single signal to be passed through the coarse time digitizer. The pulse generated by the multiplexer may serve as a trigger signal for the time digitizer. In the case where the time digitizer receives signals from only a single source, such as in the case where a multiplexer as described above is included on the first ASIC 110, the multiplexer 340 may not be included.

[0297] In order to measure the arrival time of an incoming signal (referred to as a trigger pulse) and generate a residual time, the time digitizer must both: store the state of the ring oscillator 350 when the trigger pulse arrives; and combine the output of the ring oscillator after the trigger pulse with the initial trigger pulse itself. This second operation generates the residual time of the coarse time digitizer. In addition, the ring oscillator is coupled to a counter 360, which is used to increase the dynamic range of the coarse time digitizer.

[0298] Both the signal from the ring oscillator and the trigger pulse from the multiplexer are passed to the selector 370, whose core component is the D flip-flop. The signal from the ring oscillator acts as a clock signal for the D flip-flop, and the trigger pulse from the multiplexer acts as a clear (CLR) signal. The D gate of the D flip-flop is kept at a high level. Only when both the ring oscillator signal and the trigger pulse are high, the output of the D flip-flop and therefore the output of the selector will rise to a high level. In this way, only the trigger pulse after the ring oscillator pulse will be passed through the selector.

[0299] The output of selector 370 is then passed to generate the rough residual time T cres time amplifier 380 and is passed to generate a rough digital output D cout The encoder 390. In this case, the time amplifier is a D flip-flop pulse train amplifier and the encoder is a binary encoder. The rough residual time T cres It is then passed to the fine time digitizer block 320 .

[0300] Fig.12 The fine time digitizer 330 is shown in more detail.

[0301] Each of the fine time digitizer 330 stages of the fine time digitizer block 320 is identical and comprises a low bandwidth converter 400 followed by a time amplifier 410. The low bandwidth converter comprises a time register 420 and a conventional time digitizer 430, both adapted to receive a coarse residual time T cres The conventional time-to-digital converter generates a fine digital output Dfout , which can then be output from the fine time digitizer and compared with the coarse digital output D cout are combined to generate the final digital output of the pipelined time-to-digital converter.

[0302] Fine digital output D fout It is then passed through a digital-to-time converter 440 and the rough time residual T measured by the time register is cres subtracted. Since the conversion is not exact, this subtraction will result in a small residual time. This is then passed through a time amplifier 410 to amplify the residual of the converter so that it matches the dynamic range of the subsequent stage, thereby generating a fine residual time T fres The time amplifier block amplifies the error signal of the corresponding stage in the pipeline to enable high-resolution comparison at the subsequent stage.

[0303] It should be noted that the maximum time period that should be detectable by the low bandwidth converter is the inverse of the operating frequency of the first stage and more specifically the inverse of the ring oscillator.

[0304] The residual time may be passed through any number of fine time digitizer 330 stages depending on the resolution of the final digital output required by a given application.

[0305] Other variations to the disclosed embodiments may be understood and effected by those skilled in the art in practicing the claimed invention by studying the drawings, the description and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. Although certain measures are recited in mutually different dependent claims, this does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope.

Claims

1. A method for multiplexing a plurality of analog signals each from a separate channel, the method comprising: obtaining the plurality of analog signals, each analog signal being obtained from a separate channel, wherein each separate channel is associated with a channel identifier; performing asynchronous sigma-delta modulation on each of the plurality of analog signals, thereby generating a plurality of quantized time-domain signals based on the plurality of analog signals, wherein each quantized time-domain signal includes one or more edge timing events associated with signal edges within the quantized time-domain signal; and multiplexing the plurality of quantized time domain signals in an asynchronous manner, And among them: The multiplexing of the plurality of quantized time domain signals comprises: For each quantized time domain signal: Identify edge timing events; labeling the identified edge timing event with a binary number based on the edge timing event type; and marking the edge timing event with a channel identifier based on a channel from which an associated analog signal was obtained, wherein the channel identifier comprises a binary number; and A multiplexed signal is generated based on the multiple quantized time domain signals, wherein the multiplexed signal includes the edge timing events marked with binary numbers indicating the edge timing event types and binary numbers indicating the channel identifiers, thereby generating a multiplexed signal in which the edge timing events are associated with the channel identifiers.

2. The method according to claim 1, wherein: The edge timing event includes a rising signal edge.

3. The method according to claim 1, wherein: The edge timing event includes a falling signal edge.

4. The method according to claim 1, wherein: The method also includes decoding the multiplexed signal.

5. The method according to claim 4, wherein: Decoding the multiplexed signal includes performing time-to-digital conversion on the multiplexed signal.

6. The method according to claim 4, wherein: The decoding includes time stamping each edge timing event of the multiplexed signal.

7. The method according to claim 4, wherein: The decoding includes recording the time between each edge timing event of receiving the multiplexed signal.

8. The method according to any one of claims 4 to 7, wherein: The decoding includes reconstructing the plurality of analog signals in the digital domain.

9. A computer program product comprising computer program code adapted to implement the method according to any preceding claim when said computer program code is run on a computer.

10. A system (100') for multiplexing a plurality of analog signals, the system comprising: an analog signal receiver comprising a plurality of channels, each channel adapted to obtain an analog signal, and wherein each channel is associated with a channel identifier; a signal processor comprising an asynchronous sigma-delta modulator (150) and adapted to perform asynchronous sigma-delta modulation on each of the plurality of analog signals, thereby generating a plurality of quantized time-domain signals based on the plurality of analog signals, wherein each quantized time-domain signal comprises one or more edge timing events associated with signal edges within the quantized time-domain signal; and a multiplexer (270) adapted to multiplex the plurality of quantized time domain signals in an asynchronous manner, And among them: The multiplexer is also suitable for: For each quantized time domain signal: Identify edge timing events; labeling the identified edge timing event with a binary number based on the edge timing event type; and marking the edge timing event with a channel identifier based on a channel from which an associated analog signal was obtained, wherein the channel identifier comprises a binary number; and A multiplexed signal is generated based on the multiple quantized time domain signals, wherein the multiplexed signal includes the edge timing events marked with binary numbers indicating the edge timing event types and binary numbers indicating the channel identifiers, thereby generating a multiplexed signal in which the edge timing events are associated with the channel identifiers.

11. The system (100') according to claim 10, wherein: The analog signal receiver includes an ultrasonic transducer (160).

12. The system (100') according to any one of claims 10 to 11, wherein: The system also includes a time-to-digital converter (290).

Images