Data processing device and method

Abstract

An apparatus is provided, comprising an input circuit that receives input data. The output circuit outputs a sequence of instructions to be executed by a data processing circuit, at least some of the instructions being grouped into functions, and a generation circuit performs a generation process to generate the sequence of instructions using the input data. The generation process causes at least one of the instructions in the sequence of instructions to store a state of control flow speculation performed during execution of the sequence of instructions, and the stored state of the control flow speculation is maintained between functions.

Description

Technical Field

[0001] The present technology relates to data processing and more particularly to the field of speculative execution. Background Art

[0002] Speculative execution is a technique in which a series of instructions are executed before it is known whether those instructions should be executed. At some later point in time, it is determined whether the speculatively executed instructions should be executed. If so, the process continues. If not, the execution is "rewound." This form of speculation is called control flow speculation. In some cases, such speculative execution has been found to lead to security vulnerabilities. For example, a processor can be caused to speculatively execute privileged code to load protected data into a cache unnecessarily. Since the cache may not be cleared after the rewind, the requested data can be probed using a side-channel attack. Another form of speculation is data value speculation, in which the resulting value produced by an instruction is speculated before all of the inputs to the instruction are known. Summary of the invention

[0003] The present technique recognizes that it is desirable to keep data safe where control flow speculation occurs.

[0004] From a first example configuration, a device is provided, comprising: an input circuit for receiving input data; an output circuit for outputting an instruction sequence to be executed by a data processing circuit, at least some of the instructions being grouped into functions; and a generation circuit for executing a generation process to generate the instruction sequence using the input data, wherein the generation process causes at least one of the instructions in the instruction sequence to store a state of control flow speculation performed during execution of the instruction sequence; and the stored state of control flow speculation is maintained between functions.

[0005] From a second example configuration, a method is provided, comprising: receiving input data; executing a generation process to generate an instruction sequence using the input data; and outputting an instruction sequence to be executed by a data processing circuit, at least some of the instructions being grouped into functions, wherein the generation process causes at least one of the instructions in the instruction sequence to store a state of control flow speculation performed during execution of the instruction sequence; and the stored state of control flow speculation is maintained between functions.

[0006] From a third example configuration, a device is provided, comprising: a device for receiving input data; a device for outputting a sequence of instructions to be executed by a data processing circuit, at least some of the instructions being grouped into functions; and a device for executing a generation process to generate the instruction sequence using the input data, wherein the generation process causes at least one of the instructions in the instruction sequence to store a state of control flow speculation performed during execution of the instruction sequence; and the stored state of control flow speculation is maintained between functions. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present technology will be further described, by way of example only, with reference to embodiments of the present technology as shown in the accompanying drawings, in which:

[0008] Figure 1 shows an apparatus according to some embodiments;

[0009] Figure 2 The behavior of branch instructions is shown and is used to demonstrate a form of speculative execution;

[0010] Figure 3 An example of a conditional select instruction is shown;

[0011] Figure 4a and Figure 4b shows a conversion of input data into an output instruction sequence including data value speculation restricted instructions, thereby enabling control flow miss-speculation tracking, according to some embodiments;

[0012] Figure 5a , Figure 5b and Figure 5c illustrates conversion of input data into an output instruction sequence containing ABI-compliant control flow miss speculation tracing across function call boundaries in accordance with some embodiments;

[0013] Figure 6 shows how several techniques involving transformations can be combined;

[0014] Figure 7 shows an apparatus according to some embodiments;

[0015] Figure 8 shows a data processing method in the form of a flowchart according to some embodiments; and

[0016] Fig. 9 A data processing method in the form of a flowchart according to some embodiments is shown. DETAILED DESCRIPTION

[0017] Before discussing the embodiments with reference to the accompanying drawings, the following description of the embodiments and associated advantages is provided.

[0018] According to one aspect, an apparatus is provided, comprising: an input circuit for receiving input data; an output circuit for outputting an instruction sequence to be executed by a data processing circuit, at least some of the instructions being grouped into functions; and a generation circuit for executing a generation process to generate the instruction sequence using the input data, wherein the generation process causes at least one of the instructions in the instruction sequence to store a state of control flow speculation performed during execution of the instruction sequence; and the stored state of the control flow speculation is maintained between functions.

[0019] The above device can take the form of a compiler that converts input instructions into output instructions. The input circuit receives input data, and the output circuit outputs an instruction sequence to be executed by the data processing circuit. The generating circuit performs a generating process on the input data to generate an instruction sequence. The generating process causes at least one instruction in the outputted instructions to be stored in a state of control flow speculation when the instruction is being executed. The state is maintained between functions, such as during a function call and a return from a function call. In this case, it is possible to access the speculation state established in one function in another function. The input data can be converted from a first language into a second language that can be executed by the data processing circuit (which can be the processing circuit itself) through the generating process. In other embodiments, the input data can be in the same language as the outputted instruction sequence, and the generating process can cause additional instructions to be added to establish a state of control flow speculation.

[0020] In some embodiments, the state of control flow speculation indicates whether control flow speculation occurred correctly. Control flow speculation can occur in the case of conditional branch instructions, where a branch prediction is made to determine whether the branch should be followed with respect to fetching, decoding, and starting execution of further instructions until the outcome of the branch is known. In these embodiments, an instruction is provided to indicate whether speculation occurred correctly.

[0021] In some embodiments, at least one of the instructions in the instruction sequence that stores a control flow speculation state is prevented from being subject to data value speculation by the data processing circuitry. This can be achieved, for example, by providing a "speculation barrier" that prohibits the use of speculated data values ​​in further instructions until those speculated data values ​​have been determined to be correct. As previously described, data speculation is a technique for estimating data values. Therefore, by prohibiting data value speculation from occurring when determining the state of control flow speculation, it can be determined whether a branch should actually be followed.

[0022] In some embodiments, at least one of the instructions in the instruction sequence that stores a control flow speculation state is adapted to cause the data processing circuit to perform a comparison and store the state of the control flow speculation based on the comparison result. The comparison is performed to determine whether the control flow speculation should cause a branch. The state of the control flow speculation is then stored so that it can be referenced or used in other computations elsewhere.

[0023] In some embodiments, the input data includes a conditional branch instruction, the conditional branch instruction including a condition and a target to which the branch is to be made when the condition is satisfied; and the instruction sequence includes at the target at least one instruction in the instruction sequence that stores a control flow speculation state. The instruction that stores the control flow speculation state occurs after the branch instruction that may be subject to control flow speculation. Therefore, in the event that control flow speculation occurs, it can be determined whether the branch decision is correct.

[0024] In some embodiments, the comparison logically corresponds to the condition. It will be appreciated that if the comparison performed by the instruction that determines the state of control flow speculation matches the condition in the conditional branch instruction, then the state of the control flow speculation matches whether the conditional branch should be taken. Here, the term "logically corresponds to..." means that the condition and the comparison have logical equivalence. As the skilled person will know, this can be established using a Boolean truth table.

[0025] In some embodiments, in response to the comparison result corresponding to the condition not being satisfied, the state of the control flow speculation indicates that the control flow speculation occurred incorrectly.

[0026] In some embodiments, at least a subset of the instruction sequence conforms to an application binary interface; and the state of the stored control flow speculation is maintained between functions by the following operation: an illegal value according to the application binary interface is stored in a storage circuit. The application binary interface (ABI) specifies how software should use certain hardware elements. For example, the ABI may specify a calling convention (e.g., how different values ​​will be stored in registers and / or stacks in order to perform a function call or return from a function call). Therefore, the ABI may specify that a specific register should / should not store a specific value. In any case, in such an embodiment, although at least a subset of the plurality of instructions conforms to the ABI, "illegal" (e.g., not allowed) values ​​(according to the ABI) are stored in the storage circuit to maintain the state of control flow speculation between functions. In this way, compatibility with existing systems can be maintained because the presence of "illegal" values ​​in the storage circuit should have no effect.

[0027] In some embodiments, the state of the stored control flow speculation is maintained within at least some functions by storing legal values ​​according to an application binary interface. In some embodiments, between functions, legal values ​​are stored in the same storage circuits in which illegal values ​​are stored. However, in some embodiments, within a function, legal values ​​are stored in different storage circuits.

[0028] In some embodiments, in response to the control flow speculation state indicating that a miss speculation occurred, an illegal value is stored in the storage circuit. Since a "rewind" is expected to occur as a result of the miss speculation, it may be considered acceptable to store the illegal value in the storage circuit until the rewind occurs. Note that in some other embodiments, the opposite may be true, i.e., an illegal value is stored in response to the control flow speculation state indicating that a miss speculation did not occur.

[0029] In some embodiments, the storage circuit includes a register. For example, in some embodiments, the storage circuit includes a stack pointer register; and the illegal value is 0. In some ABIs, the stack pointer register (which can be used to point to the address in memory where the end of the previous stack frame is stored) is not allowed to be 0 across function calls. Therefore, by storing the value 0 in the stack pointer register, it can be indicated that a miss speculation has occurred. In addition, since such a value is prohibited in the stack pointer register, storing such a value here should have no overall effect.

[0030] In some embodiments, the instruction sequence includes an access instruction, the access instruction including an access address; and the correct execution of the access instruction depends on the state of control flow speculation. In this way, access to data can be controlled according to whether control flow speculation should or should not occur. In some cases, the correct execution of the access instruction can be considered safe because in this way, the execution of the access instruction in an unsafe situation (such as where a control flow miss speculation has occurred and where access to the data value is inappropriate) can be prevented. This can help prevent privileged data from being leaked because the data may not actually be retrieved in the event of a miss speculation.

[0031] In some embodiments, the instruction sequence includes an instruction that performs an operation on the access address before the access instruction; and the operation depends on the state of control flow speculation. By performing an operation on the address that depends on the state of control flow speculation, the address can be affected depending on whether the control flow speculation is correct. This can make it possible to "corrupt" the address in the event that the access is inappropriate, so that the access does not occur, thereby preventing the data from being retrieved.

[0032] There are a number of ways to perform this operation. In some embodiments, the operation is a logical AND operation including operands; and in the event that the state of the control flow speculation indicates that a miss speculation has occurred, the operand is 0. Thus, when a miss speculation has occurred, the result of performing the AND operation is to effectively "invalidate" (zero) the access address, thereby preventing the access from occurring. In the event that a miss speculation has not occurred according to the state of the control flow speculation, the operand can be an all-one value (e.g., a '1' for each bit stored in the appropriate register), such that the result of ANDing with the access address is the access address itself.

[0033] Another way to protect data is to perform an operation on the data itself after the data has been retrieved. Thus, in some embodiments, the instruction sequence includes an instruction to perform an operation on the data retrieved from the access address by the access instruction; and the operation depends on the state of control flow speculation. Again, for example, in some embodiments, the operation is a logical AND operation including operands; and in the case where the state of control flow speculation indicates that a miss speculation occurred, the operand is 0. Thus, after the data is retrieved, it is immediately affected by an AND operation that invalidates (zeroes) the data in the case where a miss speculation occurs.

[0034] Specific embodiments will now be described with reference to the accompanying drawings.

[0035] Figure 1 An apparatus 100 according to some embodiments is shown. The apparatus may, for example, take the form of a pipeline for executing instructions. Figure 1 In the example of, an instruction fetcher 110 is provided. This obtains the instruction to be executed, for example, from a memory or from an instruction cache. The instruction fetcher then passes the acquired (one or more) instructions to an instruction decoder 120, which decodes the acquired instructions and generates one or more control signals for each instruction. These control signals are passed to one or more reservation stations 130a-130d. Each reservation station stores data corresponding to instructions for execution by execution units 140a-140d. Each reservation station 130 acts as a queue for decoded instructions, and the decoded instructions in a given reservation station 130a can be processed in any order by the corresponding execution unit 140a. Here, the execution unit 140 includes two arithmetic logic units (ALUs) 140a, 140b, a floating point unit 140c, and a load / store unit 140d. The decoded instructions are sent to the appropriate execution unit 140. For example, a floating point instruction is sent to the floating point unit 140c via the corresponding reservation station 130c.

[0036] Figure 2The behavior of branch instructions is shown and is used to demonstrate a form of speculative execution. Specifically, the first set of instructions 200 includes branch instruction A. This causes the flow to jump to the second set of instructions 210. In the case of a conditional branch instruction (a branch instruction with a condition associated therewith), the branch will only occur if the condition is met. If a branch occurs, execution will continue at the target B of the branch instruction. In this example, this involves the execution of instructions D, E, F, G, and H. Instruction H acts as a return instruction, which causes the branch to return. The flow then returns to instruction C in the first block of instructions 200, where recovery is performed.

[0037] In a typical execution, the instruction fetcher 110 may take one processor cycle to fetch the instruction, and the instruction decoder may take another processor cycle to decode the instruction. The instruction may then wait in the reservation station 130 until the necessary data has been obtained. For example, if the instruction operates on data in memory, it may take several processor cycles to retrieve the data from memory. Once the instruction has been passed, it may take another processor cycle to actually execute the instruction at the execution unit 140. In order to maintain high efficiency, a typical data processing system will continue to operate (e.g., fetch, decode and execute) other instructions at the same time. Here, conditional branch instructions may theoretically cause problems because it is not known which instructions should be fetched / decoded / executed next before the condition is actually evaluated. To help solve this problem, branch prediction is performed and it is assumed that the branch will go in a specific direction. Then, instructions in that direction are fetched / decoded / executed. If the prediction is correct, efficiency has been maintained. If not, a "rewind" occurs and execution resumes from the correct location. In this case, there is no significant loss of time compared to the case where execution stops just before the branch is executed. This is an example of speculative execution. Therefore, in Figure 2 In the example of , when the branch instruction at A is reached, some or all of instructions BH may be executed before knowing whether the branch at A should be followed (and even C if the return instruction at H is executed).

[0038] Figure 3 An example of a conditional select instruction 300 is shown. The instruction includes a destination 310 (e.g., register x20), a first source 320 (e.g., a special register xzr, which always contains the value "0"), a second source 330 (e.g., register x20), and a condition 340 (e.g., "ge", which indicates whether the greater than or equal flag is set). The greater than or equal flag may be set as a result of a previous instruction comparing two values. Alternatively, in some embodiments, the condition 340 that makes up the conditional select instruction may directly include a comparison of two values.

[0039] If the greater than or equal flag is not set, execution of this instruction causes the value 0 (in the xzr register) to be stored in register x20. Otherwise (if the greater than or equal flag is set), the value in register x20 is stored in register x20 (i.e., the value of register x20 remains unchanged). Note that if the condition 340 in the conditional select instruction corresponds to the condition of the conditional branch instruction, then as shown below, the value stored in register x20 can be changed depending on whether control flow speculative execution correctly occurs.

[0040] Figure 4a 4 shows how conditional select instructions may be used to determine whether a miss speculation has occurred by compiling (e.g., converting) an input instruction set 400 into an output instruction set 410. Note that the input instructions 400 may be in a language, and the output instructions 410 may be in a language intended for use in, for example, Figure 1 A second language is executed on the data processing circuit 100 shown.

[0041] The input instruction contains a typical conditional branch scenario. In this example, the condition 420 of the branch instruction is that the "greater than or equal to flag" is set. If this condition is met, a branch to the target label BB2 (which includes the instruction instr2) occurs. Otherwise, execution continues at label BB1 (which includes the instruction instr1). In the output instruction, register x20 is initially loaded with the value "-1". The branch then occurs as in the input instruction. At the target label BB2, as previously referenced Figure 3 As described, a conditional select instruction occurs. However, the condition of conditional select instruction 430 is the opposite of condition 420 in the branch instruction - it depends on the 'lt' ("less than") flag being set. As a result, the condition of the conditional select instruction corresponds to the condition of the branch instruction, because each of them depends on the same test and just takes different actions based on the possible results. The remaining instructions of branch BB2 (including instr2) are then executed. Similarly, at branch BB1, conditional select instruction 440 occurs. If branch instruction 420 is not followed, the code is executed. In this case, the condition in conditional select instruction 440 is the same as the condition of branch instruction 420.

[0042] In this way, at branch BB1, the value in register x20 will either remain unchanged ("-1") or will be changed (to "0"). Since the condition 420 in each conditional selection instruction 430, 440 is opposite to the condition in the branch instruction 420 required to reach the target containing the conditional selection instruction, the value of register x20 will be changed only in the case of a miss speculation. Otherwise, register x20 will remain unchanged. For example, assume that speculation occurs at BB2. This will turn out to be correct if the 'ge' flag is set. Here, the conditional selection instruction 420 determines whether the 'lt' flag is set. Assuming that the 'ge' and 'lt' flags are mutually exclusive, if the condition in the branch instruction 420 is satisfied (i.e., if the speculation occurs correctly), the conditional selection instruction 420 will leave the value in register x20 unchanged (e.g., by moving the value in register x20 to register x20), and similarly for the conditional selection instruction 440 at BB1. In each case, if the branch is correctly speculated, register x20 will maintain the value '-1'. In this example, the CSDB instruction prevents any instruction executed after the CSDB instruction from observing data value speculation that may have occurred on the CSEL instruction. This enables the value in register x20 to accurately represent the correctness of the control flow prediction for instructions executed after the CSDB has been executed. The CSDB instruction is a special instruction that is used to prevent instructions executed after the CSDB instruction from seeing data value miss speculation that occurred before the CSDB instruction. Therefore, the actual result of the CSEL instruction is established rather than estimated by data value speculation. Of course, if a miss speculation has occurred, at some point in the future, a "rewind" will occur. However, before that time, it is useful to know that a control flow miss speculation has occurred to prevent privileged data from being leaked.

[0043] It will be appreciated that in a related example, changes may be made if speculation occurred correctly, and remain unchanged if the branch was speculated miss. Similarly, it will be appreciated that specific values ​​(eg, '0' and '-1') may be arbitrarily chosen for each outcome.

[0044] Figure 4bIt is shown how the output produced by the conditional selection instruction can be used to protect access to specific data. It is assumed here that register x20 contains an indication of whether the speculation occurred correctly (all 1s) or incorrectly (all 0s). In input data 450, a load is performed to obtain data stored in the memory at a memory address, which is stored in register x1. The data is loaded into register x0. Here, the memory address stored in register x1 is considered to contain privileged information because it is related to secure data. Therefore, it is desirable not to load the data in register x0 when a control flow miss speculation is occurring (i.e., when the programmer does not intend to load the data). Output data 460 performs a logical "and" operation on the memory address in register x1 with the value stored in register x20. This causes x1 to have a value of 0 in the case of a control flow miss speculation, so the load is loaded from address 0 instead of the address of the privileged data.

[0045] Finally, a load occurs at the memory address now stored in register x1. If a miss speculation occurs, a logical AND operation with the all-zero value in register x20 will cause the memory address in register x1 to be erased, thereby preventing its access by the load instruction. If the speculation occurs correctly, the logical AND operation will ignore the value in register x20, thereby allowing it to be accessed by the load instruction. Therefore, the load is protected so that it can only occur if the speculation is executed correctly.

[0046] Note that the CSDB instruction may be placed anywhere between the last CSEL operation on register x20 and the first use of register x20 in an AND instruction to protect load instructions that load privileged data.

[0047] It is desirable for the indication as to whether a speculation miss occurred to persist across function calls. Figure 5a , Figure 5b and Figure 5c It is shown how further translation may be performed in order to enable miss speculation indicators to persist across function calls.

[0048] In these examples, it is assumed that the output instructions 510, 530, 550 conform to the application binary interface (ABI). This specifies how the underlying software should utilize the hardware. For example, it can specify calling conventions, which specify how to implement function calls (e.g., registers that should be used to pass parameters to the called function), how to return results, how and when to change the program counter and stack pointer, etc. In this example, it is assumed (as is often the case) that the ABI prohibits the value '0' from being stored in the stack pointer across functions (e.g., during a call or return). Therefore, by storing the value '0' in the stack pointer, a backward compatible system can be provided, which transmits the following facts across functions: either control flow speculation has occurred correctly, or miss speculation has occurred. Since this uses a value prohibited by the ABI in the register, it should not cause problems for any existing system. In other words, the presence of '0' in the stack pointer register should have no effect. This example uses the value '0' to refer to the fact that miss speculation has occurred. In addition, contrary to the previously used register x20, this example uses the register IP1 within the function to store the value indicating whether miss speculation has occurred.

[0049] Figure 5a How to convert a function call in an input instruction 500 into an output instruction 510 that executes the function call is shown. The output instruction moves the current stack pointer into a temporary register IP0. A logical AND operation is then performed between the stack pointer value in IP0 and the value of register IP1 containing the control flow miss speculation value (all 1s when the control flow is being correctly speculated, and 0 when the control flow is being incorrectly speculated), and the result is stored in a temporary register IP0. The AND operation causes IP0 to either contain the value of the stack pointer (in the case of correct control flow speculation) or to be 0 (in the case of incorrect control flow speculation). The result is then stored back to the stack pointer. Some architectures prohibit arithmetic / logical operations directly on the stack pointer. In this example, the MOV instruction moves the value of the stack pointer to a temporary register to allow it to be changed. On other architectures that allow direct operations on the stack pointer, it may be possible to set the value of the stack pointer directly to 0 (when a control flow miss speculation occurs) without the need for a mov instruction.

[0050] The branch and link instruction is then executed, which causes an unconditional function call to label "callee" to occur. Note that the branch and link instruction is not a conditional branch instruction, so a miss speculation will not occur due to the branch and link instruction itself. However, the function containing the branch and link instruction may be entered due to a miss speculation occurring. The present technique makes it possible to maintain the state of control flow speculation across functions, so in the function entered from the branch and link instruction, it is known whether a miss speculation has occurred (from a previous conditional branch instruction, not shown).

[0051] Figure 5b The behavior at the callee label is shown. In the input instruction 520, this may simply include the label "callee:". In the output instruction 530 generated thereby (e.g., via compilation or conversion), a comparison is made between the stack pointer and the value '0', followed by a conditional select instruction. When the stack pointer is zero, that is, when a control flow miss speculation occurs, the code sequence causes register IP1 to contain all zeros. If a control flow miss speculation has not occurred before this point, the stack pointer will have a non-zero value, and the code sequence causes IP1 to contain an all-one value. In this way, by using the ABI illegal value '0' in the stack pointer, the value of IP1 has been transferred from before the function call to "callee" to the function "callee".

[0052] Figure 5c The behavior at the return instruction that results in a return from a function call is shown. In the input instruction 540, this may simply include the instruction 'ret'. In the output instruction 550 generated thereby (e.g., via compilation or conversion), the stack pointer is moved into a temporary register IP0. A logical "AND" operation is then performed on the contents of IP0 and IP1. Finally, the result is moved back to the stack pointer and a return to the caller occurs. As described above, the temporary register IP0 is used in order to perform operations on the value stored in the stack pointer.

[0053] Reference Figure 5a , the last two lines of the output instruction 510 indicate what happens at the caller after the return. Specifically, the stack pointer is compared to the value '0' again. If the stack pointer is equal to '0', then '0' is stored in IP1 (i.e., indicating that a control flow miss speculation occurred), otherwise, an all-one value is stored in register IP1 via the CSETM instruction. Combined Figure 5a , Figure 5b and Figure 5c Demonstrates how a control flow miss speculation value in register IP1 can be propagated across a function call boundary by using an ABI illegal value for the stack pointer.

[0054] Figure 6How several of these techniques can be combined is shown. Here, input data 580 causes a branch to the label "function". At the label "function", the value stored in memory at the address listed in register x1 is then loaded into register x0. Then the instruction 'instr1' is executed before returning. In the output data 590, register IP1 is used again within the function to indicate whether a control flow miss speculation has occurred. The value is passed between functions by placing the value into the stack pointer. In the case of a miss speculation, the value in IP1 is '0', otherwise it is a full 1 value. For the stack pointer, when a miss speculation occurs, the value is '0', otherwise it is an unchanged stack pointer value (ABI rules prohibit it from being '0'). As before, the stack pointer is moved into register IP0 so that it can be adjusted. It is then "ANDed" with the current value of IP1 and then moved back to the stack pointer. At this stage, the stack pointer will now reflect the state of the control flow speculation. Then a function call (bl instruction) occurs. At the function 'function', the state of the control flow speculation is transferred back to IP1. As before, if control flow speculation has occurred correctly, the accessed address in register 'x1' remains unchanged, otherwise the value is 'corrupted', preventing access. The CSDB instruction just before the 'AND' instruction means that the value of IP1 will not be the data value speculated at this time (a miss), causing the address in x1 to be corrupted when control flow miss speculation occurs. Instruction 'instr1' is then executed. Finally, the state of control flow speculation is stored back to the stack pointer before returning. On return in the calling function, the control flow miss speculation indication in the stack pointer ('0' for a miss speculation, any non-zero value for a correct speculation) is converted back to register IP1 ('0' for a miss speculation, all ones for a correct speculation), and execution of the remaining instructions continues (after the return). Figure 6 '...').

[0055] Figure 7 An apparatus 600 for generating output instructions from input data according to some embodiments is shown. The apparatus comprises input circuitry 610 which receives input data (which may be in the form of instructions, perhaps in a different language than the output instructions). The input circuitry passes these instructions to generation circuitry 620 which generates a sequence of output instructions. The sequence of output instructions is based on the input instructions. In this example, the output instructions will achieve the same effect as the input instructions, but will cause the following additional instructions to be added (where at least some restrictions are added on data value speculation): These instructions cause control flow miss speculation to be tracked in registers, such as for example for Figure 4a , Figure 4b , Figure 5a , Figure 5b and Figure 5c These output instructions are then output by the output circuit 630. The instruction sequence output by the output circuit 630 is designed to be executed on the processing circuit 100. The instruction sequence is such that they implement the ABI, but with one specific exception. This one exception is that with respect to the storage circuit 640 such as the stack pointer register, the value that is prohibited from being stored in the storage circuit across function calls is actually stored in the storage circuit across function calls in order to indicate the fact that a miss speculation has occurred (or has not occurred).

[0056] Figure 8 700, and may be performed by, for example, Figure 1 The data processing apparatus 100 shown in FIG. 1 is executed. At step 710, the instruction is decoded and a control signal is generated. At step 720, the control signal is used to perform one or more data processing operations. At step 730, it is determined whether the control signal corresponding to the data processing operation (and therefore the corresponding instruction) is marked in some way to prevent data value speculation from being performed for those instructions. If not, speculation is allowed for those data processing operations at step 740. Otherwise, speculation is prohibited for those instructions at step 750.

[0057] Fig. 9 A data processing method according to some embodiments is shown. The method is shown in the form of a flow chart 800 and can be used, for example, as shown in FIG. Figure 7 In step 810, input data is received. In step 820, a generation process is performed. This can be similar to the process described in relation to Figure 4a , Figure 4b , Figure 5a , Figure 5b and Figure 5c Some or all of the processes shown correspond. One or more of the output instructions causes the state of control flow speculation to be stored during execution. Finally, the output of the generation process (a sequence of output instructions) is output at step 830.

[0058] In this application, the phrase "configured to..." is used to indicate that an element of a device has a configuration that enables the performance of a defined operation. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, a device may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not imply that the elements of the device need to be changed in any way in order to provide the defined operation.

[0059] Although illustrative embodiments of the present invention have been described in detail herein with reference to the accompanying drawings, it will be appreciated that the present invention is not limited to those precise embodiments and that various changes, additions and modifications may be implemented therein by those skilled in the art without departing from the scope and spirit of the present invention as defined by the appended claims. For example, various combinations of the features of the dependent claims with the features of the independent claims may be made without departing from the scope of the present invention.

Claims

1. A data processing device, comprising: An input circuit for receiving input data; output circuitry for outputting a sequence of instructions to be executed by the data processing circuitry, at least some of the instructions being grouped into functions; and A generating circuit is used to execute a generating process to generate the instruction sequence using the input data, wherein The generating process causes at least one instruction in the sequence of instructions to store a state of a control flow speculation that is performed during execution of the sequence of instructions, the state of the control flow speculation indicating whether the control flow speculation occurred correctly; The stored state of control flow speculation is maintained between the functions so that the state of control flow speculation established in another one of the functions is accessible in one of the functions; The instruction sequence includes an access instruction and an instruction for performing an operation on data retrieved from an access address by the access instruction or performing an operation on an access address included in the access instruction before the access instruction, wherein, when the state of control flow speculation indicates that a miss speculation occurs, the operation invalidates the data retrieved from the access address by the access instruction or invalidates the access address included in the access instruction.

2. The data processing device according to claim 1, wherein: The at least one instruction in the sequence of instructions storing the state of control flow speculation is prevented by the data processing circuitry from undergoing data value speculation.

3. The data processing device according to claim 1, wherein: The at least one instruction in the sequence of instructions that stores the state of control flow speculation is adapted to cause the data processing circuitry to perform a comparison and store the state of control flow speculation based on a result of the comparison.

4. The data processing device according to claim 3, wherein: The input data includes a conditional branch instruction including a condition and a target to branch to when the condition is satisfied; and The sequence of instructions includes, at the target, the at least one instruction in the sequence of instructions that stores the state of control flow speculation.

5. The data processing device according to claim 4, wherein: The comparison logically corresponds to the condition.

6. The data processing device according to claim 5, wherein: Responsive to a result of the comparison corresponding to the condition not being satisfied, the state of control flow speculation indicates that control flow speculation occurred incorrectly.

7. The data processing device according to claim 1, wherein: At least a subset of the sequence of instructions conforms to an application binary interface; and The stored state of control flow speculation is maintained between the functions by storing illegal values ​​according to the application binary interface in a storage circuit.

8. The data processing device according to claim 7, wherein: The stored state of control flow speculation is maintained within at least some of the functions by storing legal values ​​according to the application binary interface.

9. The data processing device according to any one of claims 7 to 8, wherein: In response to the status of control flow speculation indicating that a miss speculation occurred, the illegal value is stored in the storage circuit.

10. The data processing device according to any one of claims 7 to 8, wherein: The storage circuit includes a register.

11. The data processing device according to any one of claims 7 to 8, wherein: The storage circuit includes a stack pointer register; and The illegal value is 0.

12. The data processing device according to claim 1, wherein: The operation is a logical AND operation involving operands; and In the event that the state of control flow speculation indicates that a miss speculation occurred, the operand is zero.

13. A data processing method, comprising: Receive input data; executing a generation process to generate an instruction sequence using the input data; and outputting said sequence of instructions to be executed by the data processing circuit, at least some of these instructions being grouped into functions, wherein The generating process causes at least one instruction in the sequence of instructions to store a state of a control flow speculation that is performed during execution of the sequence of instructions, the state of the control flow speculation indicating whether the control flow speculation occurred correctly; The stored state of control flow speculation is maintained between the functions so that the state of control flow speculation established in another one of the functions is accessible in one of the functions; The instruction sequence includes an access instruction and an instruction for performing an operation on data retrieved from an access address by the access instruction or performing an operation on an access address included in the access instruction before the access instruction, wherein, when the state of control flow speculation indicates that a miss speculation occurs, the operation invalidates the data retrieved from the access address by the access instruction or invalidates the access address included in the access instruction.

14. A data processing device, comprising: means for receiving input data; means for outputting a sequence of instructions to be executed by the data processing circuitry, at least some of the instructions being grouped into functions; and means for executing a generation process to generate said sequence of instructions using said input data, wherein The generating process causes at least one instruction in the sequence of instructions to store a state of a control flow speculation that is performed during execution of the sequence of instructions, the state of the control flow speculation indicating whether the control flow speculation occurred correctly; The stored state of control flow speculation is maintained between the functions so that the state of control flow speculation established in another one of the functions is accessible in one of the functions; The instruction sequence includes an access instruction and an instruction for performing an operation on data retrieved from an access address by the access instruction or performing an operation on an access address included in the access instruction before the access instruction, wherein, when the state of control flow speculation indicates that a miss speculation occurs, the operation invalidates the data retrieved from the access address by the access instruction or invalidates the access address included in the access instruction.

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