Isolated Hall sensor structure
By adopting a carrier structure composed of substrate layer and oxide layer and a channel-filled doped polysilicon design in Hall sensor, the temporary depletion and drift of Hall sensor structure under low current conditions is solved, and the sensitivity is improved and on-off performance avoid threshold voltage injection.
Patent Information
- Application Number
- CN202010517228.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2019-06-11
- Filing Date
- 2020-06-09
- Publication Date
- 2024-12-20
- Estimated Expiration
- 2040-12-20
AI Technical Summary
The existing Hall sensor structure is prone to temporary depletion and measured value drift under low operating current conditions, and excessive doping leads to a decrease in sensitivity, making threshold voltage injection difficult to avoid.
Using a carrier structure composed of a substrate layer and an oxide layer, the first and second conductive types of semiconductor switch regions are constructed, the semiconductor region is divided into electrically isolated box regions through the channel, and the channel is filled with doped polysilicon and Connect to the reference potential to avoid crosstalk and threshold voltage injection and improve sensitivity.
It effectively avoids temporary depletion and drift of Hall sensors under low current conditions, improves transient characteristics and sensitivity, completely avoids threshold voltage injection, and enhances on-off performance.
Smart Images
Figure CN112071976B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to an isolated Hall sensor structure. Background Art
[0002] DE 10 2011 107 767 A1 discloses a Hall sensor structure consisting of a plurality of Hall sensor elements connected in series. Each Hall sensor element comprises three n-semiconductor contact regions in an n-slot region, wherein a p-type semiconductor contact region, for example, made of a highly doped semiconductor, is arranged between the n-semiconductor contact regions. + Isolation area composed of diffusion. Summary of the invention
[0003] Against this background, the object of the present invention is to specify a device which is a development of the prior art.
[0004] This object is achieved by a Hall sensor structure having the features according to the invention. Advantageous embodiments of the invention are preferred embodiments.
[0005] According to the subject matter of the present invention, an isolated Hall sensor structure is provided, which has a carrier structure composed of a substrate layer and an oxide layer.
[0006] A semiconductor region of the first conductivity type is formed on the upper side of the oxide layer and is cohesively connected to the oxide layer.
[0007] Furthermore, trenches are formed which extend from the top of the semiconductor region as far as the oxide layer, wherein at least one trench surrounds a box region of the semiconductor region.
[0008] Furthermore, at least three first semiconductor contact regions of the first conductivity type are formed, which in each case extend from an upper side of the semiconductor region into the semiconductor region.
[0009] The first semiconductor contact regions are each arranged in a manner spaced apart from one another in the box region of the semiconductor region.
[0010] A metallic connection layer is arranged on each first semiconductor connection region.
[0011] Furthermore, the isolated Hall sensor structure has at least one second semiconductor contact region of the second conductivity type, which extends in the box region from an upper side of the semiconductor region into the semiconductor region, wherein each second semiconductor contact region extends at least partially along the trench.
[0012] The second semiconductor contact regions are spaced apart from the first semiconductor contact regions, and a metallic connection layer is arranged on each second semiconductor contact region.
[0013] It is understood that the carrier structure together with the semiconductor region forms a so-called SOI structure. Here, the substrate layer and the semiconductor region are each composed of silicon, and the oxide layer is formed as a silicon dioxide layer. It is also understood that the semiconductor region is divided into individual sub-regions by means of a surrounding trench. The individual sub-regions are electrically isolated from each other in that the trench extends from the surface of the semiconductor region to the oxide layer. The individual sub-regions can be referred to as box regions.
[0014] It should be noted that the oxide layer is formed on the entire surface of the silicon wafer. The oxide layer is thus buried and is referred to as buried oxide.
[0015] It can also be understood that the box region of the semiconductor region surrounded by a trench (also called a trench or deep trench) forms the active region of the component. In other words, the trench isolates the active region (ie the box region) from the remaining semiconductor region (eg, adjacent active region).
[0016] It is understood that, except for the sidewalls, the trench is filled with doped polysilicon. Preferably, the doped polysilicon of the trench is connected to a reference potential, preferably to a ground potential. Thus, crosstalk between box regions is suppressed, especially when the potential between the boxes changes rapidly.
[0017] One advantage is that minority charge carriers are provided in the box region by means of the at least one second semiconductor contact region. Preferably, the second connecting contact layer of each second semiconductor contact region is clamped to a reference potential, for example ground.
[0018] Studies have shown that temporary draining can be avoided while the sensor is switched on, in particular at low operating currents of the Hall sensor (ie, currents in the range of 10 μA to 100 mA).
[0019] As a result, the transient behavior can be improved and, in particular, a drift of the measured values immediately after switching on can be suppressed.
[0020] Especially in the box area, it is less than 8·1015N / cm 3 In the case of low doping in the range of , the turn-on performance is improved.
[0021] It should be noted that the sensitivity of the Hall sensor structure can be at least partially increased by means of a lower doping of the box region.
[0022] Another advantage is that threshold voltage implantation can be completely avoided in the entire tank region. As a result, the sensitivity of the Hall sensor structure can be further increased by suppressing surface effects.
[0023] In a first embodiment, the second semiconductor contact region has a layer thickness of 0.1 μm to 4 μm. The width of the second semiconductor contact region on the top side preferably has a range between 1 μm and 20 μm, or between 2 μm and 10 μm, or between 3 μm and 5 μm.
[0024] In one embodiment, the doping concentration of the second semiconductor contact region is higher than 5·1017 N / cm 3 , or at 1·1017N / cm 3 and 1·1020N / cm 3 in the range between.
[0025] In a further embodiment, the Hall sensor structure has exactly one second semiconductor contact region, wherein the second semiconductor contact region has a closed frame-like shape extending along the circumference of the box region of the semiconductor region.
[0026] In an alternative specific embodiment, all second semiconductor contact regions comprised by the Hall sensor extend together along at least 50%, or at least 75%, or at least 95% of the circumference of the box region of the semiconductor region.
[0027] The Hall sensor structure comprises, for example, two second semiconductor contact regions which extend, for example, along opposite edges of the outer circumference of the box region, so that the first semiconductor contact region is located between the two second semiconductor contact regions.
[0028] According to another embodiment, the box region of the semiconductor region has a rectangular upper side, wherein at least one second semiconductor contact region extends along a first edge of the upper side of the rectangle and / or along a second edge of the upper side of the rectangle and / or along a third edge of the upper side of the rectangle and / or along a fourth edge of the upper side of the rectangle.
[0029] It is understood that the second semiconductor contact region preferably has a rectangular design, wherein the long sides are parallel to the edges of the box region. If the second semiconductor contact region is designed circumferentially along the edge of the box region, the second semiconductor contact region forms a frame.
[0030] In a further configuration, each second semiconductor contact region adjoins the trench or has a distance from the trench of at most 10 nm or at most 100 nm.
[0031] In another embodiment, the trench is filled with polysilicon. According to one embodiment, the sidewalls of the trench formed by the semiconductor region are coated with a second dielectric isolation layer, wherein the second dielectric isolation layer (for example oxide) has a thickness between 3 nm and 30 nm.
[0032] According to other embodiments, the first conductivity type is n-type and the second conductivity type is p-type, or the first conductivity type is p-type and the second conductivity type is n-type.
[0033] It is understood that due to the higher mobility of charge carriers, the semiconductor region in the box region preferably has an n-doping. Here, n is the majority carrier in the box region. Correspondingly, positive charge carriers form the majority carriers in the second semiconductor contact region.
[0034] In a further configuration, the first semiconductor contact regions each have a value of 5·10 18 N / cm 3 of dopant concentration.
[0035] According to another configuration, the semiconductor region has a value of 5·10 14 N / cm 3 Up to 5·1017N / cm 3 of dopant concentration.
[0036] According to another embodiment, at least the entire semiconductor region of the semiconductor region in the region extending between the first semiconductor contact regions or in the box region is free of threshold voltage implantation. "Free of threshold voltage implantation" is to be understood as not performing an implantation for adjusting the threshold voltage of the MOS transistor, in particular not performing a boron implantation.
[0037] In a further embodiment, the first semiconductor contact region is always spaced apart from the trench surrounding it.
[0038] In a further embodiment, the Hall sensor structure comprises a third dielectric isolation layer, wherein the third isolation layer covers parts of the upper side of the semiconductor region, in particular between the first semiconductor contact regions and preferably between the first semiconductor contact region and the second semiconductor contact region.
[0039] The dielectric isolation layer preferably comprises an oxide or consists of an oxide. In one embodiment, the oxide of the dielectric isolation layer has a thickness of at least 1 nm or a thickness in the range between 3 nm and 30 nm.
[0040] Preferably, the third insulating layer is designed as a gate oxide, ie in the case of a MOS transistor, as an oxide under the gate poly, with the same thickness and quality.
[0041] In one configuration, the first semiconductor contact region and / or the at least one second semiconductor contact region are produced by means of implantation and diffusion.
[0042] The second semiconductor contact region is preferably connected to a reference potential, preferably a ground potential. Furthermore, the two outermost first semiconductor contacts in the box region are preferably connected. BRIEF DESCRIPTION OF THE DRAWINGS
[0043] The invention is explained in more detail below with reference to the drawings. Components of the same type are marked with the same reference numerals. The embodiments shown are highly schematic, i.e. the distances, lateral and vertical extensions are not to scale and - unless otherwise indicated - do not have any derivable geometrical relationships with one another. The drawings show:
[0044] Figure 1 A cross-sectional view showing a first embodiment of an isolated Hall sensor structure according to the present invention;
[0045] Figure 2 A top view showing a second embodiment of an isolated Hall sensor structure according to the present invention;
[0046] Figure 3 A third specific embodiment of the Hall sensor structure according to the invention is shown in a plan view. DETAILED DESCRIPTION
[0047] Figure 1 The figure shows a cross-sectional view of a first embodiment of a Hall sensor structure HAL according to the present invention. The Hall sensor structure HAL comprises a substrate layer SUB, an oxide layer ISO1 and a semiconductor region HG of a first conductivity type formed on the oxide layer ISO1. A trench T is formed in the semiconductor region HG, wherein the trench separates the box region B (active region of the component) from the remaining semiconductor region HG.
[0048] The trench has side surfaces formed by the semiconductor region HG, wherein the side surfaces are covered by the second dielectric isolation layer. Furthermore, the trench is filled with polysilicon POL1.
[0049] Three first semiconductor contact regions HK1 of a first conductivity type are formed in the box region B of the semiconductor body HG, wherein each first semiconductor contact region HK1 extends from the top side of the box region B in a groove-like manner. A first contacting layer K1 , which is formed at least in regions, extends into the box region B of the semiconductor body HG and is formed on each first semiconductor contacting region HK1 in order to form an electrical operative connection.
[0050] The first semiconductor contact regions HK1 are respectively arranged spaced apart from one another and from the trench, wherein a third dielectric isolation layer ISO3 is respectively formed at least between in each case two adjacent first semiconductor contact regions HK1 on the upper side of the box region B of the semiconductor region HG.
[0051] Furthermore, the Hall sensor structure HAL has a second semiconductor contact region HK2 of the second conductivity type, wherein the second semiconductor contact region extends in a trench-like manner from the top side of the box region B into the box region B of the semiconductor body HG, adjoins the trench T and extends along the entire trench T.
[0052] In order to produce an electrical operative connection, a second connecting layer K2 is formed at least in regions on the top side of the second semiconductor contact region HK2 .
[0053] exist Figure 2 The top view of another embodiment is shown in the accompanying drawings. Figure 1 The difference between the attached drawings.
[0054] A metallic connection layer K1 is formed region-wise on the first semiconductor connection region HK1 .
[0055] The tank region B has a rectangular top side or a top side with a rectangular outer circumference, wherein the second semiconductor contact region HK2 and thus the trench T extend at intervals along the entire outer circumference of the top side of the tank region.
[0056] exist Figure 3 The top view of another embodiment is shown in the accompanying drawings. Figure 2 The difference between the attached drawings.
[0057] In the embodiment shown, the Hall sensor structure HAL includes five first semiconductor contact regions HK1, on which a first metallic connection layer is respectively constructed in an area-by-area manner, and two second semiconductor contact regions HK2, wherein the second semiconductor contact regions HK2 extend along two opposite sides of the rectangular upper side of the box region and to the trench T at a certain interval.
Claims
1. An isolated Hall sensor structure (HAL), the Hall sensor structure having: a carrier structure, the carrier structure consisting of a substrate layer (SUB) and an oxide layer (ISO1), a semiconductor region (HG) of a first conductivity type, which is connected to the upper side of the oxide layer (ISO1) in a material-bonded manner, a plurality of trenches (T), each extending from the upper side of the semiconductor region (HG) to the oxide layer (ISO1) of the carrier structure, at least three first semiconductor contact regions (HK1) of the first conductivity type, the at least three first semiconductor contact regions respectively extending from the upper side of the semiconductor region (HG) into the semiconductor region (HG), in, The plurality of trenches (T) surround a box region (B) of the semiconductor region (HG), a dielectric isolation layer constructed on a side of each of the plurality of trenches (T); The first semiconductor contact regions (HK1) are each arranged in a box region (B) of the semiconductor region (HG) and are each spaced apart from one another. A metallic connection layer (K1) is arranged on each first semiconductor connection region (HK1), It is characterized in that The isolated Hall sensor structure (HAL) has at least one second semiconductor contact region (HK2) of a second conductivity type, which extends in the box region (B) from the upper side of the semiconductor region (HG) into the semiconductor region (HG), Each second semiconductor contact region (HK2) extends at least partially along the channel and is spaced apart from the first semiconductor contact region (HK1), A metallic connection layer (K2) is arranged on each second semiconductor connection region (HK2), At least a region of the semiconductor region (HG) extending between the first semiconductor contact regions (HK1) or the entire semiconductor region (HG) is free of threshold voltage injection.
2. The Hall sensor structure (HAL) according to claim 1, It is characterized in that The second semiconductor contact region ( HK2 ) has a layer thickness of 0.1 μm to 4 μm.
3. The Hall sensor structure (HAL) according to claim 1 or 2, It is characterized in that The Hall sensor structure (HAL) has exactly one second semiconductor contact region (HK2), and the second semiconductor contact region (HK2) has a closed shape extending along the circumference of the box region (B) of the semiconductor region (HG).
4. The Hall sensor structure (HAL) according to claim 1 or 2, It is characterized in that All second semiconductor contact regions (HK2) included in the Hall sensor (HAL) extend together along at least 50%, or at least 75%, or at least 95% of the circumference of the box region (B) of the semiconductor region (HG).
5. The Hall sensor structure (HAL) according to claim 1 or 2, It is characterized in that The box region (B) of the semiconductor region (HG) has a rectangular upper side, and the at least one second semiconductor contact region (HK2) extends along a first edge of the upper side of the rectangle and / or along a second edge of the upper side of the rectangle and / or along a third edge of the upper side of the rectangle and / or along a fourth edge of the upper side of the rectangle.
6. The Hall sensor structure (HAL) according to claim 1 or 2, It is characterized in that Each second semiconductor contact region adjoins the trench (T) or is at a distance of at most 10 nm or at most 100 nm from the trench (T).
7. The Hall sensor structure (HAL) according to claim 1 or 2, It is characterized in that The trench (T) is filled with polysilicon (POL1).
8. The Hall sensor structure (HAL) according to claim 1 or 2, It is characterized in that The side walls of the trench (T) formed by the semiconductor region (HG) are coated with a second dielectric isolation layer (ISO2), and the second dielectric isolation layer (ISO2) has a thickness between 3 nm and 30 nm.
9. The Hall sensor structure (HAL) according to claim 1 or 2, It is characterized in that The first conductivity type is an n-type and the second conductivity type is a p-type, or the first conductivity type is a p-type and the second conductivity type is an n-type.
10. The Hall sensor structure (HAL) according to claim 1 or 2, It is characterized in that The first semiconductor contact regions (HK1) each have 5·10 18 N / cm 3 of dopant concentration.
11. The Hall sensor structure (HAL) according to claim 1 or 2, It is characterized in that The semiconductor region (HG) has a 5·10 14 N / cm 3 Until May 10 17 N / cm 3 of dopant concentration.
12. The Hall sensor structure (HAL) according to claim 1 or 2, It is characterized in that The plurality of channels (T) include two channels (T).
13. The Hall sensor structure (HAL) according to claim 1 or 2, It is characterized in that The first semiconductor contact regions (HK1) are respectively spaced apart from the trenches (T).