TFT array substrate and manufacturing method thereof

Abstract

The invention discloses a TFT array substrate and a manufacturing method thereof, wherein the substrate is divided into a first TFT region and a second TFT region; a first active layer is manufactured in the first TFT region, and the first active layer is divided into a channel region and a conductor region; a first gate insulating layer is manufactured on the channel region; a first metal layer is manufactured on the first gate insulating layer; an isolation layer is manufactured, and the isolation layer located on the second TFT region is etched; the isolation layer is etched to form two first through holes; a first source electrode, a first drain electrode, and a second metal layer are manufactured at the same time, and the first source electrode and the first drain electrode are connected to the conductor region on the active layer through the two first through holes; the second metal layer is placed on the second TFT region. By defining the TFT array substrate as two regions, the H ion diffusion in the second TFT annealing process is reduced, and the stability of the second TFT device is improved. At the same time, since the isolation layer is only retained in the first TFT region, the thickness of the second TFT film layer is reduced, and the transmittance is increased, which can improve the display effect.

Description

Technical Field

[0001] The present invention relates to the field of TFT array substrate manufacturing, and in particular to a TFT array substrate and a manufacturing method thereof. Background Art

[0002] Indium gallium zinc oxide IGZO (indium gallium zinc oxide) has a carrier mobility 20-30 times that of amorphous silicon, which can realize ultra-high resolution TFT-LCD. At the same time, due to its high transparency, low cost, low manufacturing temperature and other characteristics, it is widely used in industrial production.

[0003] Since low-temperature polysilicon (LTPS) has a higher carrier mobility as a channel layer material (about 3 to 10 times that of IGZO-TFT), it can be used as a driving TFT in the peripheral GIP area. By utilizing its high carrier mobility, a narrow frame design can be achieved. However, since IGZO-TFT has a smaller Ioff than LTPS-TFT, the use of IGZO-TFT in the display area only requires a single gate to suppress leakage problems, thereby achieving the purpose of low power consumption. With the existing LTPO technology, LTPS-TFT is used as the GIP area and IGZO-TFT is used as the display area (AA area). The high mobility characteristics of LTPS technology can be used to achieve a narrow frame, while the low Ioff characteristics of IGZO technology can be used to achieve low power consumption. Therefore, manufacturers in the industry have begun to invest in the development of LTPO TFTs to achieve narrow-frame, low-power display technology. In existing LTPO technologies, LTPSTFT1 usually adopts a top-gate self-aligned structure, and IGZOTFT2 usually adopts a BCE structure. In the LTPS process, the ILD layer usually uses a SiOx / SiNx double-layer structure, in which the SiNx film has a higher H ion content. In the subsequent annealing process, the movement of H ions can play a role in repairing the poly-Si channel lattice and improving the subthreshold swing of the device. The SiOx film can reduce parasitic capacitance due to its low dielectric constant; but the IGZO layer in TFT2 is more sensitive to H ions, and the movement of a large number of H ions can easily cause TFT2Vth drift, so it is necessary to reduce the diffusion of H ions in the annealing process of IGZOTFT2. Summary of the invention

[0004] Therefore, it is necessary to provide a TFT array substrate and a manufacturing method thereof to reduce H ion diffusion in the second TFT annealing process.

[0005] To achieve the above object, the present application provides a method for manufacturing a TFT array substrate, comprising the steps of:

[0006] dividing the substrate into a first TFT region and a second TFT region;

[0007] A first active layer is fabricated in the first TFT region, and the first active layer is divided into a channel region and a conductive region, wherein the conductive region is disposed on both sides of the channel region;

[0008] forming a first gate insulating layer on the channel region;

[0009] forming a first metal layer on the first gate insulating layer;

[0010] Making an isolation layer containing SiNx, and etching the isolation layer, removing the isolation layer located on the second TFT region and forming two first through holes with the conductive region as the bottom;

[0011] A first source electrode, a first drain electrode and a second metal layer are simultaneously manufactured, wherein the first source electrode and the first drain electrode are respectively connected to the conductive area on the active layer through the two first through holes; and the second metal layer is placed on the second TFT area;

[0012] A second gate insulating layer is manufactured. The second gate insulating layer is arranged on the first TFT region and the second TFT region, covers the first source electrode, the first drain electrode and the second metal layer, and has a SiOx structure.

[0013] Furthermore, the steps include:

[0014] Fabricating a second active layer on the second gate insulating layer, wherein the second active layer is located above the second metal layer;

[0015] A second source electrode and a second drain electrode are manufactured, wherein the second source electrode and the second drain electrode are respectively connected to two sides of the second active layer.

[0016] Furthermore, the method further comprises the steps of:

[0017] Manufacturing an insulating layer, wherein the insulating layer is disposed on the first TFT region and the second TFT region, and manufacturing a second through hole with a second source electrode or a second drain electrode as a bottom on the insulating layer;

[0018] Two ITOBCs are respectively formed on both sides of the second through hole;

[0019] Manufacturing a passivation layer, the passivation layer being disposed on the first TFT region and the second TFT region, and etching a third through hole on the passivation layer, the third through hole and the second through hole sharing a bottom surface;

[0020] An ITOPE is fabricated, and the ITOPE is connected to the second source or the second drain.

[0021] Furthermore, the step of respectively making two ITOBCs on both sides of the second through hole includes:

[0022] A flat layer is formed on the insulating layer, the flat layer is disposed on the first TFT region and the second TFT region and covers the insulating layer; and a fourth through hole is formed by etching on the flat layer, the fourth through hole is conductively connected to the second through hole;

[0023] Two ITOBCs are respectively manufactured on both sides of the fourth through hole.

[0024] Furthermore, before the step of manufacturing the first active layer in the first TFT region and dividing the first active layer into a channel region and a conductive region, wherein the conductive region is disposed on both sides of the channel region, the method further includes the following steps:

[0025] A buffer layer is fabricated on the substrate.

[0026] Furthermore, after the step of forming the second active layer on the second gate insulating layer, and the second active layer is located above the second metal layer, the method further includes the following steps:

[0027] forming an etching stopper layer on the second gate insulating layer, wherein the etching stopper layer is disposed on the first TFT region and the second TFT region;

[0028] The etching stopper layer is etched to form two fifth through holes with the second active layer as the bottom, and the second source electrode and the second drain electrode are respectively connected to the second active layer through one fifth through hole.

[0029] To achieve the above object, the present application also provides a TFT array substrate structure, wherein a first TFT region and a second TFT region are provided on the substrate, and a first active layer, a first gate insulating layer, a first metal layer, an isolation layer, a first source electrode and a first drain electrode are provided on the substrate;

[0030] A first active layer is disposed on the first TFT region of the substrate, and the first active layer is divided into a channel region and a conductive region, the first gate insulating layer is disposed on the channel region, the first metal layer is disposed on the first gate insulating layer, the isolation layer covers the first active layer, the first gate insulating layer and the first metal layer, and the first source electrode and the first drain electrode are connected to the conductive region through a first through hole on the isolation layer;

[0031] The second TFT includes: a second metal layer, a second gate insulating layer, a second active layer, a second source and a second drain; the second metal layer is disposed on a substrate, and the second gate insulating layer covers the second metal layer and the first TFT; the second active layer is disposed on the second gate layer and is located above the second metal layer; a second source and a second drain are respectively disposed on both sides of the second active layer, and the second source and the second drain are connected to the second active layer.

[0032] Furthermore, it also includes: an insulating layer, a passivation layer, an ITOBC, and an ITOPE;

[0033] The passivation layer is placed on the first TFT and the second TFT, and a second through hole with a second source or a second drain as the bottom is provided on the insulating layer, and the ITOBC is respectively placed on both sides of the second through hole; the passivation layer is placed on the insulating layer, and a third through hole is opened at the second through hole, the third through hole and the second through hole share a bottom surface, and the ITOPE is connected to the second source or the second drain at the bottom through the third through hole.

[0034] Furthermore, it also includes: a flat layer; the flat layer is arranged between the insulating layer and the passivation layer, and the flat layer is provided with a fourth through hole located on the second through hole, and the fourth through hole is conductively connected with the second through hole and the third through hole; the ITOBC is arranged on the flat layer and on both sides of the fourth through hole.

[0035] Furthermore, it also includes: ESL; the ESL is arranged between the insulating layer and the second gate insulating layer, and fifth through holes are arranged on both sides of the second active layer, and the second source and the second drain are connected to the second active layer through the fifth through holes.

[0036] Different from the prior art, the above technical solution is defined as two areas through the TFT array substrate, wherein the first TFT adopts a top gate self-aligned structure, which is the GIP area; the second TFT adopts a bottom gate structure (BCE / ESL structure), which is the display area (AA area). In the LTPS process, the isolation layer usually uses a SiOx / SiNx double-layer structure, and the SiNx film has a high H ion content. In the subsequent annealing process, the H ions move, which can play a role in repairing the lattice of the first active layer and improve the device SS. However, the second active layer in the second TFT is more sensitive to H ions, and a large amount of H ion movement can easily cause Vth drift. Therefore, the inter-isolation layer ILD of the first TFT is etched to be retained only in the first TFT area, reducing the H ion diffusion in the second TFT annealing process and improving the stability of the second TFT device. At the same time, since the isolation layer is only retained in the first TFT area, the thickness of the second TFT film layer in the AA area is thinned, the transmittance is increased, and the display effect can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic diagram of the structural cross-section of a LTPO array substrate of the background technology;

[0038] Figure 2 The first active layer structure diagram of the specific implementation method;

[0039] Figure 3 The first TFT structure diagram of the specific implementation method;

[0040] Figure 4 This is a structural diagram of the second TFT in a specific implementation manner;

[0041] Figure 5 This is a structural diagram of a TFT array substrate.

[0042] Figure 6 This is a structural diagram of the etching stop layer described in a specific implementation manner.

[0043] Description of reference numerals:

[0044] 1. Substrate; 2. First TFT region; 3. Second TFT region;

[0045] 21. The first TFT;

[0046] 31. second TFT; 32. insulating layer; 33. ITOBC; 34. passivation layer; 35. ITOPE; 36. planarization layer; 37. buffer layer; 38. etching stop layer;

[0047] 211, first active layer; 212, first gate insulating layer; 213, first metal layer; 214, isolation layer; 215, first through hole; 216, first source electrode; 217, first drain electrode;

[0048] 311, second metal layer; 312, second gate insulating layer; 313, second active layer; 314, second source electrode; 315, second drain electrode; 381, fifth through hole;

[0049] 321, second through hole; 341, third through hole; 361, fourth through hole;

[0050] 2111. Channel region; 2112. Conductive region. DETAILED DESCRIPTION

[0051] In order to explain the technical content, structural features, achieved objectives and effects of the technical solution in detail, the following is a detailed description in conjunction with specific embodiments and accompanying drawings.

[0052] See also Figures 1 to 6The present embodiment provides a method for manufacturing a TFT array substrate, comprising the steps of: dividing a substrate 1 into a first TFT region 2 and a second TFT region 3; manufacturing a first active layer 211 in the first TFT region 2, and dividing the first active layer 211 into a channel region 2111 and a conductive region 2112, wherein the conductive region 2112 is disposed on both sides of the channel region 2111; manufacturing a first gate insulating layer 212 on the channel region 2111; manufacturing a first metal layer 213 on the first gate insulating layer 212; and manufacturing The isolation layer 214 is formed, and the isolation layer 214 located on the second TFT region 3 is etched; the isolation layer 214 is etched to form two first through holes 215 with the conductive region 2112 as the bottom; a first source electrode 216, a first drain electrode 217 and a second metal layer 311 are manufactured, and the first source electrode 216 and the first drain electrode 217 are respectively connected to the conductive region 2112 on the active layer through the two first through holes 215; the second metal layer 311 is placed on the second TFT region 3; the substrate 1 is a glass substrate. It should be noted that in this embodiment, the first active layer 211 is a polysilicon active layer. In the actual process, the first active layer 211 is manufactured through a mask plate. After the first active layer 211 is manufactured, the first active layer 211 can be partially conductorized to divide the first active layer 211 into a conductorized area 2112 and a channel area 2111, and the conductorized area 2112 is arranged on both sides of the channel area 2111; the first gate insulating layer 212 is manufactured on the channel area 2111 through a mask plate. It should be noted that the first gate insulating layer 212 completely covers the channel area 2111, and the first metal layer 213 is manufactured on the first gate insulating layer 212. It should be further explained that the isolation layer 214 is an ILD isolation layer 214, and the material is SiNx. When manufacturing the isolation layer 214, the isolation layer 214 is first coated on all areas, and the isolation layer 214 located on the second TFT area 3 is etched away on the through-hole mask plate, and then two first through holes 215 are etched through the mask plate to connect the first source electrode 216 and the first drain electrode 217 to the conductive area 2112 of the first active layer 211. After the first TFT 21 is manufactured, the second TFT 31 is manufactured on the second TFT area 3. When manufacturing the first source electrode 216, the first drain electrode 217 and the second metal layer 311, a metal layer is prepared as a whole through a mask plate, and then after patterning, the first source electrode 216 and the first drain electrode 217 are formed on the isolation layer 214 on the first TFT area 2, and the second metal layer 311 is formed on the substrate 1 in the second TFT area 3. A layer of mask is used to manufacture the first source electrode 216, the first drain electrode 217 and the second metal layer 311, and the materials of the three are the same.The above technical solution is defined as two regions through the TFT array substrate 1, wherein the first TFT21 adopts a top gate self-aligned structure, which is a GIP region; the second TFT31 adopts a bottom gate structure (BCE / ESL structure), which is a display region (AA region). In the LTPS process, the isolation layer 214 usually uses a SiOx / SiNx double-layer structure, and the SiNx film has a high H ion content. In the subsequent annealing process, the H ions move, which can play a role in repairing the lattice of the first active layer 211 and improve the device SS. However, the second active layer 313 in the second TFT31 is more sensitive to H ions, and a large amount of H ion movement can easily cause Vth drift. Therefore, the inter-isolation layer 214ILD of the first TFT21 is etched to only remain in the first TFT region 2, reducing the H ion diffusion in the annealing process of the second TFT31, and improving the device stability of the second TFT31. At the same time, since the isolation layer 214 is only retained in the first TFT region 2, the film thickness of the second TFT31 in the AA region is thinned, and the transmittance is increased, which can improve the display effect. The H ions in the isolation layer are greater than the H ions in the second gate insulating layer.

[0053] In some embodiments, before the step of "fabricating a first active layer 211 in the first TFT region 2, and dividing the first active layer 211 into a channel region 2111 and a conductive region 2112, wherein the conductive region 2112 is disposed on both sides of the channel region 2111", the step further includes: fabricating a buffer layer 37 on the substrate 1.

[0054] See also Figure 4 In this embodiment, the steps further include: making a second gate insulating layer 312, the second gate insulating layer 312 is arranged on the first TFT region 2 and the second TFT region 3; making a second active layer 313 on the second gate insulating layer 312, and the second active layer 313 is located above the second metal layer 311; making a second source 314 and a second drain 315, the second source 314 and the second drain 315 are respectively connected to the two sides of the second active layer 313. It should be noted that the second gate insulating layer 312 covers the second metal layer 311 and the first TFT 21, and the material used for the second gate insulating layer 312 is SiOx; the height of the second gate insulating layer 312 located in the second TFT region 3 is less than the height of the second gate insulating layer 312 in the first TFT region 2. The second active layer 313 is IGZO, and the second active layer 313 is made on the second gate layer and is located above the second metal layer 311. The second source 314 and the second drain 315 are made on both sides of the second active layer 313. While preventing the Vth of the second TFT 31 from drifting, reducing the thickness of the second TFT 31 can further increase the transmittance and improve the display effect.

[0055] See also Figures 4 to 5 In this embodiment, an insulating layer 32 is manufactured, the insulating layer 32 is arranged on the first TFT region 2 and the second TFT region 3, and a second through hole 321 with the second source electrode 314 or the second drain electrode 315 as the bottom is manufactured on the insulating layer 32; two ITOBCs 33 are manufactured on both sides of the second through hole 321; a passivation layer 34 is manufactured, the passivation layer 34 is arranged on the first TFT region 2 and the second TFT region 3, and a third through hole 341 is etched on the passivation layer 34, and the third through hole 341 and the second through hole 321 share a bottom surface; an ITOPE 35 is manufactured, so that the ITOPE 35 is connected to the second source electrode 314 or the second drain electrode 315. It should be noted that, in this embodiment, the insulating layer 32 is an insulating layer 32PV; the second through hole 321 and the third through hole 341 share a bottom surface, the bottom surface is the second source 314 or the second drain 315, and the passivation layer 34 is placed on the insulating layer 32 and covers the side wall of the second through hole 321, and the ITOPE 35 is connected to the second source 314 or the second drain 315 through the third through hole 341. While preventing the second TFT 31 Vth from drifting, the thickness of the second TFT 31 can be reduced to further increase the transmittance and improve the display effect.

[0056] See also Figure 5 In this embodiment, the step of "making two ITOBC33 on both sides of the second through hole 321" is replaced by: making a flat layer 36 on the insulating layer 32, the flat layer 36 is arranged on the first TFT region 2 and the second TFT region 3, and covers the insulating layer 32; and etching a fourth through hole 361 on the flat layer 36, the fourth through hole 361 is arranged in conduction with the second through hole 321 and the third through hole 341; and making two ITOBC33 on both sides of the fourth through hole 361. It should be further explained that the fourth through hole 361 and the second through hole 321 are arranged in conduction, the passivation layer 34 is placed on the flat layer 36, and covers the side walls of the fourth through hole 361 and the second through hole 321; the passivation layer 34 is the passivation layer 34CH, and the flat layer 36 is the flat layer 36OC.

[0057] See also Figure 6In another embodiment, after the step of "making the second active layer 313 on the second gate insulating layer 312, and the second active layer 313 is located above the second metal layer 311", the steps further include: making an etching stopper layer 38 on the second gate insulating layer 312, the etching stopper layer 38 is arranged on the first TFT region 2 and the second TFT region 3, that is, completely covering the first TFT region 2 and the second TFT region 3; etching the etching stopper layer 38 to form two fifth through holes 381 with the second active layer 313 as the bottom, and the second source 314 and the second drain 315 are connected to the second active layer 313 through a fifth through hole 381 respectively. In this embodiment, the second active layer 313 can be protected from the influence of subsequent processes and the environment.

[0058] A first TFT21 is arranged on the first TFT area 2; a second TFT31 is arranged on the second TFT area 3; the first TFT21 is an LTPS type TFT, adopts a top gate self-aligned structure, and is a GIP area; the second TFT31 is an IGZO type TFT, adopts a BCE structure, and is a display area (AA area). Since two different types of TFTs are prepared before and after in different areas on the glass substrate, the preparation of the first TFT21 will not affect the preparation of the second TFT31, thereby reducing the process risk of the entire TFT array substrate, and further improving the stability of the devices on the TFT array substrate of the present application.

[0059] See also Figures 5 to 6In this embodiment, a TFT array substrate structure is further provided, wherein a first TFT region and a second TFT region are provided on the substrate, and a first TFT is provided on the first TFT region, and a second TFT is provided on the second TFT region; the first TFT21 comprises: a first active layer 211, a first gate insulating layer 212, a first metal layer 213, an isolation layer 214, a first source electrode 216 and a first drain electrode 217; the first active layer 211 is provided on the substrate 1, and the first active layer 211 is divided into a channel region 2111 and a conductive region 2112, the first gate insulating layer 212 is provided on the channel region 2111, the first metal layer 213 is provided on the first gate insulating layer 212, and the isolation layer 214 covers the first active layer 211, the first gate insulating layer 212, and the first drain electrode 217; The first source electrode 216 and the first drain electrode 217 are connected to the conductive area 2112 through the first through hole 215 on the isolation layer 214; the second TFT 31 comprises: a second metal layer 311, a second gate insulating layer 312, a second active layer 313, a second source electrode 314 and a second drain electrode 315; the second metal layer 311 is disposed on the substrate 1, and the second gate insulating layer 312 covers the second metal layer 311 and the first TFT 21; the second active layer 313 is disposed on the second gate layer and is located above the second metal layer 311; the second source electrode 314 and the second drain electrode 315 are respectively disposed on both sides of the second active layer 313, and the second source electrode 314 and the second drain electrode 315 are connected to the second active layer 313. It should be noted that the substrate 1 is a glass substrate. In this embodiment, the first active layer 211 is a polysilicon active layer. The first active layer 211 is partially a conductive region 2112, which divides the first active layer 211 into the conductive region 2112 and the channel region 2111, and the conductive region 2112 is arranged on both sides of the channel region 2111; it should be noted that the first gate insulating layer 212 completely covers the channel region 2111. It should be further noted that the isolation layer 214 is an ILD isolation layer 214, and the material is SiNx, and the isolation layer 214 is only located in the first TFT region 2, and two first through holes 215 are also arranged on the isolation layer 214, and the first source 216 and the first drain 217 are connected to the conductive region 2112 of the first active layer 211. The first source 216, the first drain 217 and the second metal layer 311 are made of the same material and are made together.A first TFT21 is arranged on the first TFT area 2; a second TFT31 is arranged on the second TFT area 3; the first TFT21 is an LTPS type TFT, adopts a top gate self-aligned structure, and is a GIP area; the second TFT31 is an IGZO type TFT, adopts a BCE structure, and is a display area (AA area). Since two different types of TFTs are prepared before and after in different areas on the glass substrate, the preparation of the first TFT21 will not affect the preparation of the second TFT31, thereby reducing the process risk of the entire TFT array substrate, and further improving the stability of the devices on the TFT array substrate of the present application.

[0060] See also Figure 5 In some implementations, it also includes: an insulating layer 32, a passivation layer 34, an ITOBC33, and an ITOPE35; the passivation layer 34 is placed on the first TFT21 and the second TFT31, and a second through hole 321 with a second source 314 or a second drain 315 as the bottom is provided on the insulating layer 32, and the ITOBC33 is respectively placed on both sides of the second through hole 321; the passivation layer 34 is placed on the insulating layer 32, and a third through hole 341 is opened at the second through hole 321, the third through hole 341 and the second through hole 321 share a bottom surface, and the ITOPE35 is connected to the second source 314 or the second drain 315 at the bottom through the third through hole 341. It should be noted that, in this embodiment, the insulating layer 32 is an insulating layer 32PV; the second through hole 321 and the third through hole 341 share a bottom surface, the bottom surface is the second source 314 or the second drain 315, and the passivation layer 34 is disposed on the insulating layer 32 and is also disposed on the sidewall of the second through hole 321, and the ITOPE 35 is connected to the second source 314 or the second drain 315 through the third through hole 341. While preventing the second TFT 31 Vth from drifting, the thickness of the second TFT 31 can be reduced to further increase the transmittance and improve the display effect.

[0061] See also Figure 5In this embodiment, it also includes: a flat layer 36; the flat layer 36 is disposed between the insulating layer 32 and the passivation layer 34, and the flat layer 36 is provided with a fourth through hole 361 on the second through hole 321, and the fourth through hole 361 is conductively connected with the second through hole 321 and the third through hole 341; the ITOBC 33 is disposed on the flat layer 36 and disposed on both sides of the fourth through hole 361. It should be further explained that the fourth through hole 361 and the second through hole 321 are conductively connected, the passivation layer 34 is disposed on the flat layer 36, and covers the side walls of the fourth through hole 361 and the second through hole 321; the passivation layer 34 is a passivation layer 34CH, and the flat layer 36 is a flat layer OC.

[0062] See also Figure 6 In this embodiment, it further includes: ESL; the ESL is disposed between the insulating layer 32 and the second gate insulating layer 312, and fifth through holes 381 are disposed on both sides of the second active layer 313, and the second source 314 and the second drain 315 are connected to the second active layer 313 through the fifth through holes 381. In this embodiment, the second active layer 313 can be protected from subsequent processes and environmental influences.

[0063] It should be noted that, although the above embodiments have been described in this article, the patent protection scope of the present invention is not limited thereby. Therefore, based on the innovative concept of the present invention, changes and modifications made to the embodiments described herein, or equivalent structures or equivalent process changes made using the contents of the present invention specification and drawings, directly or indirectly applying the above technical solutions to other related technical fields, are all included in the patent protection scope of the present invention.

Claims

1. A method for manufacturing a TFT array substrate, characterized in that: Includes steps: dividing the substrate into a first TFT region and a second TFT region; A first active layer is fabricated in the first TFT region, and the first active layer is divided into a channel region and a conductive region, wherein the conductive region is disposed on both sides of the channel region; forming a first gate insulating layer on the channel region; forming a first metal layer on the first gate insulating layer; Making an isolation layer containing SiNx, and etching the isolation layer, removing the isolation layer located on the second TFT region and forming two first through holes with the conductive region as the bottom; Simultaneously manufacturing a first source electrode, a first drain electrode and a second metal layer, wherein the first source electrode and the first drain electrode are respectively connected to the conductive region on the active layer through the two first through holes; The second metal layer is disposed on the second TFT region; A second gate insulating layer is manufactured. The second gate insulating layer is arranged on the first TFT region and the second TFT region, covers the first source electrode, the first drain electrode and the second metal layer, and has a SiOx structure.

2. The method for manufacturing a TFT array substrate according to claim 1, characterized in that: Also included are the steps of: Fabricating a second active layer on the second gate insulating layer, wherein the second active layer is located above the second metal layer; A second source electrode and a second drain electrode are manufactured, wherein the second source electrode and the second drain electrode are respectively connected to two sides of the second active layer.

3. The method for manufacturing a TFT array substrate according to claim 2, characterized in that: Also includes the steps: Manufacturing an insulating layer, wherein the insulating layer is disposed on the first TFT region and the second TFT region, and manufacturing a second through hole with a second source electrode or a second drain electrode as a bottom on the insulating layer; Two indium tin oxide BCs are respectively formed on both sides of the second through hole; Manufacturing a passivation layer, the passivation layer being disposed on the first TFT region and the second TFT region, and etching a third through hole on the passivation layer, the third through hole and the second through hole sharing a bottom surface; An indium tin oxide PE is manufactured, and the indium tin oxide PE is connected to the second source electrode or the second drain electrode.

4. The method for manufacturing a TFT array substrate according to claim 3, characterized in that: The step of respectively forming two indium tin oxide BCs on both sides of the second through hole comprises: A flat layer is formed on the insulating layer, the flat layer is disposed on the first TFT region and the second TFT region and covers the insulating layer; and a fourth through hole is formed by etching on the flat layer, the fourth through hole is conductively connected to the second through hole; Two indium tin oxide BCs are respectively manufactured on both sides of the fourth through hole.

5. The method for manufacturing a TFT array substrate according to claim 1, characterized in that: Before the step of manufacturing the first active layer in the first TFT region and dividing the first active layer into a channel region and a conductive region, wherein the conductive region is disposed on both sides of the channel region, the method further includes the following steps: A buffer layer is fabricated on the substrate.

6. The method for manufacturing a TFT array substrate according to claim 2, characterized in that: After the step of forming the second active layer on the second gate insulating layer, and the second active layer is located above the second metal layer, the method further includes the following steps: forming an etching stopper layer on the second gate insulating layer, wherein the etching stopper layer is disposed on the first TFT region and the second TFT region; The etching stopper layer is etched to form two fifth through holes with the second active layer as the bottom, and the second source electrode and the second drain electrode are respectively connected to the second active layer through one fifth through hole.

7. A TFT array substrate structure, characterized in that: A first TFT region and a second TFT region are arranged on the substrate, and a first active layer, a first gate insulating layer, a first metal layer, an isolation layer, a first source electrode and a first drain electrode are arranged on the substrate; A first active layer is disposed on the first TFT region of the substrate, and the first active layer is divided into a channel region and a conductive region, the first gate insulating layer is disposed on the channel region, the first metal layer is disposed on the first gate insulating layer, the isolation layer covers the first active layer, the first gate insulating layer and the first metal layer, and the first source electrode and the first drain electrode are connected to the conductive region through a first through hole on the isolation layer; The second TFT comprises: a second metal layer, a second gate insulating layer, a second gate layer, a second active layer, a second source electrode and a second drain electrode; the second metal layer is disposed on the substrate, and the second gate insulating layer covers the second metal layer and the first TFT; the second active layer is disposed on the second gate layer and is located above the second metal layer; a second source electrode and a second drain electrode are respectively disposed on both sides of the second active layer, and the second source electrode and the second drain electrode are connected to the second active layer; Insulation layer, passivation layer, indium tin oxide BC, indium tin oxide PE; The passivation layer is placed on the first TFT and the second TFT, and a second through hole with a second source or a second drain as the bottom is provided on the insulating layer, and the indium tin oxide BC is respectively placed on both sides of the second through hole; the passivation layer is placed on the insulating layer, and a third through hole is opened at the second through hole, the third through hole and the second through hole share a bottom surface, and the indium tin oxide PE is connected to the second source or the second drain at the bottom through the third through hole.

8. A TFT array substrate structure according to claim 7, characterized in that: Also includes: Flat layer; The planar layer is arranged between the insulating layer and the passivation layer, and a fourth through hole is arranged on the planar layer on the second through hole, and the fourth through hole is arranged to be conductively connected with the second through hole and the third through hole; the indium tin oxide BC is arranged on the planar layer and on both sides of the fourth through hole.

9. The TFT array substrate structure according to claim 7, characterized in that: Also includes: ESL; The ESL is disposed between the insulating layer and the second gate insulating layer, and fifth through holes are disposed on both sides of the second active layer, and the second source electrode and the second drain electrode are connected to the second active layer through the fifth through holes.

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