Integrated circuit device including vertical field effect transistor

Abstract

Integrated circuit devices are provided. An integrated circuit device can include a vertical field effect transistor (VFET) including a bottom source / drain region in a substrate, a channel region on the bottom source / drain region, a top source / drain region on the channel region, and a gate structure on sides of the channel region. The channel region can have a cross-shaped upper surface.

Description

Technical Field

[0001] This disclosure relates generally to the field of electronics, and more specifically to vertical field-effect transistor (VFET) devices. Background Technology

[0002] Various structures and fabrication processes for VFET devices have been studied due to their high scalability. However, it may be difficult to fabricate VFETs with structural stability. Summary of the Invention

[0003] According to some embodiments of the present invention, an integrated circuit device may include a vertical field-effect transistor (VFET) including a bottom source / drain region in a substrate, a channel region on the bottom source / drain region, a top source / drain region on the channel region, and a gate structure on the side of the channel region. The channel region may have a cross-shaped upper surface.

[0004] According to some embodiments of the present invention, an integrated circuit device may include a vertical field-effect transistor (VFET), the VFET including a bottom source / drain region in a substrate, a channel region on the substrate, a top source / drain region on the channel region, and a gate structure on the side of the channel region. The channel region may include a core portion, a first pair of protruding portions, and a second pair of protruding portions. The first pair of protruding portions may protrude from the core portion in opposite directions along a first horizontal direction, and the second pair of protruding portions may protrude from the core portion in opposite directions along a second horizontal direction. The first and second horizontal directions may be parallel to the upper surface of the substrate and may be different from each other. The channel region may be located between the bottom source / drain region and the top source / drain region.

[0005] According to some embodiments of the present invention, an integrated circuit device may include a vertical field-effect transistor (VFET) including a bottom source / drain region in a substrate, a channel region on the bottom source / drain region, a top source / drain region on the channel region, and a gate structure on the side of the channel region. The top source / drain region may include a cross-shaped upper surface, and the channel region may be located between the bottom source / drain region and the top source / drain region.

[0006] According to some embodiments of the present invention, a method of forming a vertical field-effect transistor (VFET) may include providing a substrate and forming a first mask layer and a second mask layer on the substrate. The first mask layer may include a plurality of first portions spaced apart from each other in a first horizontal direction, and each of the plurality of first portions may have a linear shape extending in a second horizontal direction. The first and second horizontal directions may be parallel to an upper surface of the substrate and may be different from each other. The second mask layer may include a plurality of second portions spaced apart from each other in the second horizontal direction and may be arranged along the second horizontal direction, each of the plurality of second portions may connect two adjacent first portions. The method may further include forming an etch mask layer by removing portions of the first mask layer and portions of the second mask layer. The etch mask layer may include a cross-shaped upper surface. The method also includes forming a channel region of the VFET by etching the substrate using the etch mask layer as an etch mask. Attached Figure Description

[0007] Figure 1 This is a perspective view of a VFET according to some embodiments of the present invention.

[0008] Figure 2 yes Figure 1 A cross-sectional view of the VFET taken along line A-A'.

[0009] Figure 3A and Figure 3B They are displayed separately. Figure 1 A perspective view of the VFET components.

[0010] Figure 4 yes Figure 1 A top view of the channel region of the VFET.

[0011] Figure 5A and Figure 5B These are some embodiments of the concept of the present invention. Figure 2 A detailed view of the sectional view.

[0012] Figure 6 It is a top view showing the channel region of the VFET in a single integrated circuit device.

[0013] Figure 7 This is a perspective view of a stacked VFET device according to some embodiments of the present invention.

[0014] Figure 8 yes Figure 7 A cross-sectional view taken along line B-B' of the stacked VFET devices.

[0015] Figure 9This is a flowchart illustrating a method for forming an integrated circuit device including a VFET according to some embodiments of the present invention.

[0016] Figure 10 This is a flowchart of a method for forming the channel region of a VFET according to some embodiments of the present invention.

[0017] Figures 11A to 20C It shows the basis Figure 10 The flowchart method view. Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A and Figure 20A It is a top view. Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B and Figure 20B They are along Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A and Figure 20A The sectional view taken by line C-C' in the middle. Figure 15C , Figure 16C , Figure 17C , Figure 18C , Figure 19C and Figure 20C They are along 15A, Figure 16A , Figure 17A , Figure 18A , Figure 19A and Figure 20A The sectional view taken by line D-D' in the middle.

[0018] Figures 21 to 23 This is a top view illustrating a method for forming etched mask layers of various shapes according to some embodiments of the present invention. Detailed Implementation

[0019] According to some embodiments of the invention, the channel region of the VFET may include a cross-shaped upper surface, thus allowing the VFET to have a wider channel width and greater structural stability. For example, the shape of the VFET's channel region can reduce the likelihood of structural collapse during the manufacturing process. This structural stability can be particularly beneficial when the VFET has a large height, for example, when the VFET is a stack of two transistors stacked vertically.

[0020] According to some embodiments of the present invention, a single etched mask layer can be used to form channel regions with various shapes (including cross-shaped and linear).

[0021] Figure 1 This is a perspective view of a VFET according to some embodiments of the present invention. Figure 2 yes Figure 1 A cross-sectional view of the VFET taken along line A-A'. For simplicity of explanation, Figure 1 Some components of the VFET are not shown (e.g., Figure 2 The first spacer 12 and the second spacer 14 in the middle.

[0022] Reference Figure 1 and Figure 2 The VFET may include a bottom source / drain region 42 in the substrate 10. The substrate 10 may include one or more semiconductor materials, such as Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP. In some embodiments, the substrate 10 may be a bulk substrate (e.g., a bulk silicon substrate) or a semiconductor-on-insulator (SOI) substrate.

[0023] Device isolation layer 16 may be provided between the bottom source / drain region 42 and the substrate 10 for electrical isolation therebetween. Device isolation layer 16 may include an insulating material (e.g., silicon oxide, silicon nitride, and / or silicon oxide nitride).

[0024] The VFET may further include a channel region 22 and a top source / drain region 44 sequentially stacked on the substrate 10 in the vertical direction Z. The vertical direction Z may be perpendicular to the upper surface 10_U of the substrate 10. The channel region 22 may be located between the bottom source / drain region 42 and the top source / drain region 44. The bottom source / drain region 42 and the top source / drain region 44 may be spaced apart from each other in the vertical direction Z. Each of the bottom source / drain region 42 and the top source / drain region 44 may include semiconductor material and / or dopant atoms (e.g., boron atoms, phosphorus atoms, arsenic atoms).

[0025] The VFET may also include a gate structure 24, a first spacer 12, and a second spacer 14 on the side of the channel region 22. The gate structure 24 may include a gate contact portion 24_C to which a conductive layer is connected to apply a gate voltage to the gate structure 24. Each of the first spacer 12 and the second spacer 14 may include an insulating material (e.g., silicon oxide, silicon nitride, and / or silicon nitride). The first spacer 12 may be provided for electrical isolation between the bottom source / drain region 42 and the gate structure 24, and the second spacer 14 may be provided for electrical isolation between the gate structure 24 and the top source / drain region 44.

[0026] Figure 3A and Figure 3B They are displayed separately. Figure 1 A perspective view of the VFET component. (Refer to...) Figure 1 and Figure 3A The channel region 22 may have a cross-shaped upper surface and may protrude from the bottom source / drain region 42 in the vertical direction Z. In some embodiments, the channel region 22 may also have a cross-shaped lower surface. The channel region 22 may comprise a material that is the same as or different from the substrate 10.

[0027] Refer again Figure 1 and Figure 2 The top source / drain region 44 may also have a cross-shaped upper surface. The top source / drain region 44 may overlap perpendicularly with the channel region 22. In some embodiments, the cross-shaped upper surface of the top source / drain region 44 may overlap perpendicularly with the entire cross-shaped upper surface of the channel region 22, such as... Figure 1 As shown. Although Figure 1 The diagram shows that the cross-shaped upper surface of the top source / drain region 44 has a larger area than the cross-shaped upper surface of the channel region 22, but the inventive concept is not limited thereto. In some embodiments, the cross-shaped upper surface of the top source / drain region 44 may have a smaller area than the cross-shaped upper surface of the channel region 22, and may not overlap perpendicularly with the entire cross-shaped upper surface of the channel region 22. In some embodiments, the cross-shaped upper surface of the top source / drain region 44 may have the same area as the cross-shaped upper surface of the channel region 22.

[0028] It will be understood that the phrase “component A overlaps perpendicularly with component B” (or similar language) refers to the existence of a perpendicular line that intersects both components A and B.

[0029] Reference Figure 1 and Figure 3B The gate structure 24 can surround (e.g., completely surround) the channel region 22. The gate structure 24 can have a uniform thickness along the side of the channel region 22, such as... Figure 3BAs shown. In some embodiments, the gate contact portion 24_C may be omitted.

[0030] Figure 4 This is a top view of trench area 22. (Refer to...) Figure 4 The channel region 22 may include a core portion 22_C, a first pair of protrusions 22_1, and a second pair of protrusions 22_2. The first pair of protrusions 22_1 may protrude from the core portion 22_C in opposite directions along a first horizontal direction X, and the second pair of protrusions 22_2 may protrude from the core portion 22_C in opposite directions along a second horizontal direction Y. The first horizontal direction X and the second horizontal direction Y may be parallel to the upper surface 10_U of the substrate 10. Figure 2 They can also be different from each other. In some implementations, the first horizontal direction X can be perpendicular to the second horizontal direction Y.

[0031] Figure 5A and Figure 5B These are some embodiments of the concept of the present invention. Figure 2 Detailed view of the sectional view. (Refer to...) Figure 5A and Figure 5B The gate structure 24 may include a gate insulator 25 and a gate electrode 27. The gate insulator 25 may be located between the channel region 22 and the gate electrode 27 to electrically isolate the channel region 22 from the gate electrode 27. Each of the gate insulator 25 and the gate electrode 27 may include multiple layers. The gate insulator 25 may include, for example, a silicon oxide layer, a silicon oxide nitride layer, and / or a high-k material layer having a dielectric constant greater than silicon dioxide. The gate electrode 27 may include a work function control layer (e.g., a titanium nitride layer, a tantalum nitride layer), a diffusion barrier layer, and / or a conductive layer (e.g., a semiconductor layer, a metal layer). In some embodiments, the gate electrode 27 may surround (e.g., completely surround) the channel region 22.

[0032] In some implementations, the channel region 22 may overlap perpendicularly with the bottom source / drain region 42, such as... Figure 5A As shown. In some embodiments, the channel region 22 may be connected to the substrate 10, and the bottom source / drain region 42 may be on the side of the channel region 22, such as... Figure 5B As shown.

[0033] Figure 6 This is a top view showing the channel region of a VFET in a single integrated circuit device. For simplicity, only the channel region of the VFET is shown, but it will be understood that each VFET includes... Figure 1 and Figure 2 Other components shown in the image.

[0034] Reference Figure 6Some channel regions (i.e., 22_L) of the VFET may have linear upper surfaces. Each of these linear channel regions (i.e., 22_L) consists of a portion extending longitudinally in a single direction (e.g., a first horizontal direction X or a second horizontal direction Y) and may not include protruding portions.

[0035] Some channel regions (i.e., 22_CS) of the VFET may include one or more portions having a cross-shaped upper surface. In some embodiments, these channel regions 22_CS may include two portions, each having a cross-shaped upper surface. For example, each channel region 22_CS may include a core portion 22_C, a first pair of protrusions 22_1, a second pair of protrusions 22_2, and a third pair of protrusions 22_3. The first pair of protrusions 22_1 may protrude from the core portion 22_C in opposite directions along a first horizontal direction X, the second pair of protrusions 22_2 may protrude from the core portion 22_C in opposite directions along a second horizontal direction Y, and the third pair of protrusions 22_3 may protrude from a portion of one of the second pair of protrusions 22_2 in opposite directions along the first horizontal direction X. In some embodiments, the second pair of protrusions 22_2 may have different lengths in the second horizontal direction Y, such as... Figure 6 As shown.

[0036] Figure 7 This is a perspective view of a stacked VFET device according to some embodiments of the present invention. Figure 8 yes Figure 7 A cross-sectional view taken along line B-B' of the stacked VFET devices. For simplicity of illustration, Figure 7 This shows some of the components in a stacked VFET device.

[0037] Reference Figure 7 and Figure 8 The stacked VFET device can include two VFETs (i.e., a lower VFET TR_L and an upper VFET TR_U) stacked in the vertical Z direction. In some implementations, the lower VFET TR_L and the upper VFET TR_U can be transistors of a single inverter. For example, the lower VFET TR_L can be an n-type transistor of an inverter, and the upper VFET TR_U can be a p-type transistor of an inverter. Therefore, by vertically stacking two VFETs, the inverter can have a smaller footprint. The lower VFET TR_L can have a... Figure 1 and Figure 2 The VFET shown has the same or similar structure.

[0038] The upper VFET TR_U may include an upper bottom source / drain region 72, an upper channel region 62, an upper gate structure 64, and an upper top source / drain region 74, sequentially stacked on the lower VFET TR_L. The upper VFET TR_U may also include a third spacer 52 and a fourth spacer 54. The third spacer 52 may be provided for electrical isolation between the upper bottom source / drain region 72 and the upper gate structure 64, and the fourth spacer 54 may be provided for electrical isolation between the upper gate structure 64 and the upper top source / drain region 74. The stacked VFET devices may also include an insulating layer 50 between the lower VFET TR_L and the upper VFET TR_U. The insulating layer 50 may be provided for electrical isolation between the channel region 22 and the upper channel region 62.

[0039] Each of the upper bottom source / drain region 72 and the upper top source / drain region 74 may include semiconductor material and / or dopant atoms (e.g., boron atoms, phosphorus atoms, arsenic atoms). The upper channel region 62 may include a material that is the same as or different from the substrate 10. In some embodiments, the upper channel region 62 may include the same material as the channel region 22. Each of the third spacer 52, the fourth spacer 54, and the insulating layer 50 may include an insulating material (e.g., silicon oxide, silicon nitride, and / or silicon oxide nitride).

[0040] In some embodiments, the upper channel region 62 may have a cross-shaped upper surface, and the cross-shaped upper surface of the upper channel region 62 and the upper surface of the insulating layer 50 may have the same shape and the same size. Therefore, the cross-shaped upper surface of the upper channel region 62 and the cross-shaped upper surface of the insulating layer 50 may have the same width in the first horizontal direction X and the second horizontal direction Y. In some embodiments, the upper surface of the upper channel region 62, the insulating layer 50, and the upper surface of the channel region 22 of the lower VFET TR_L may have the same shape and the same size. For example, the upper surface of the upper channel region 62 and the upper surface of the channel region 22 may have the same width in the first horizontal direction X and the second horizontal direction Y.

[0041] Figure 9 This is a flowchart illustrating a method for forming an integrated circuit device including a VFET according to some embodiments of the present invention. (Refer to...) Figure 2 and Figure 9 The method includes forming a bottom source / drain region 42 and a channel region 22 (block 910), forming a first spacer 12 (block 920), forming a gate structure 24 on the channel region 22 (block 930), forming a second spacer 14 (block 940), and forming a top source / drain region 44 on the channel region 22 (block 950). Each block can be performed using various processes known in the art.

[0042] Figure 10This is a flowchart illustrating a method for forming the channel region of a VFET according to some embodiments of the present invention. Figures 11A to 20C It shows the basis Figure 10 The flowchart method is a view. Specifically, Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A and Figure 20A It is a top view. Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B and Figure 20B They are along Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A and Figure 20A The sectional view taken by line C-C' in the middle. Figure 15C , Figure 16C , Figure 17C , Figure 18C , Figure 19C and Figure 20C They are along 15A, Figure 16A , Figure 17A , Figure 18A , Figure 19A and Figure 20A The sectional view taken by line D-D' in the middle.

[0043] Reference Figure 10 , Figure 11A and Figure 11B The method may include forming a first support layer 102 on a substrate 10 and forming a first mask layer 104 (block 1010) on the sidewalls of the first support layer 102. The first support layer 102 may have a linear shape extending longitudinally in a first horizontal direction X. The first horizontal direction X may be parallel to the upper surface 10_U of the substrate 10.

[0044] The first mask layer 104 can be formed on the sidewalls of the first support layer 102 by performing various processes. For example, the first mask layer 104 can be formed by conformally forming a first layer on the first support layer 102 and the substrate 10 and then performing an etching process (e.g., a blanket etch process). In some embodiments, the first mask layer 104 can have a uniform thickness on the sidewalls of the first support layer 102, such as... Figure 11A and Figure 11B As shown.

[0045] The first support layer 102 and the first mask layer 104 may comprise different materials. For example, the first support layer 102 may comprise polysilicon, silicon nitride, silicon oxide, and / or spin-coated organic hard mask material, and the first mask layer 104 may comprise polysilicon, silicon nitride, and / or silicon oxide. In some embodiments, the first support layer 102 may comprise polysilicon, and the first mask layer 104 may comprise silicon nitride.

[0046] Reference Figure 10 , Figure 12A and Figure 12B The method may include removing the first support layer 102 (block 1020) by performing, for example, a dry etching process and / or a wet etching process. The first support layer 102 may be selectively removed relative to the first mask layer 104, such that the first mask layer 104 may be retained, as... Figure 12A and Figure 12B As shown. After removing the first support layer 102, the first mask layer 104 can define a first opening OP1 on the substrate 10. The first opening OP1 can expose the upper surface 10_U of the substrate 10.

[0047] Reference Figure 10 , Figure 13A and Figure 13B The method may include forming a first initial mask layer 106 (block 1030) on a substrate 10. The first initial mask layer 106 may be formed in a first opening OP1 of a first mask layer 104 and on the substrate 10. In some embodiments, the first initial mask layer 106 may completely fill the first opening OP1 of the first mask layer 104, such as... Figure 13A and Figure 13B As shown. After forming the first initial mask layer 106, the upper surfaces of the first mask layer 104 and the first initial mask layer 106 can be coplanar, as shown. Figure 13A and Figure 13B As shown. In some embodiments, a planarization process may be performed to make the upper surfaces of the first mask layer 104 and the first initial mask layer 106 coplanar.

[0048] The first initial mask layer 106 may include polysilicon, silicon oxide, and / or spin-coated organic hard mask material. In some embodiments, the first initial mask layer 106 may include a material different from that of the first mask layer 104, such that the first initial mask layer 106 and the first mask layer 104 may have etch selectivity relative to each other when performing an etching process.

[0049] Reference Figure 10 , Figure 14A and Figure 14B The method may include forming a second support layer 202 on a first mask layer 104 and a first initial mask layer 106, and forming a second initial mask layer 204 (block 1040) on the sidewall of the second support layer 202. The second support layer 202 may have a linear shape extending longitudinally in a second horizontal direction Y. The second horizontal direction Y may be parallel to the upper surface 10_U of the substrate 10 and may be different from the first horizontal direction X. In some embodiments, the first horizontal direction X may be perpendicular to the second horizontal direction Y.

[0050] The second initial mask layer 204 can be formed on the sidewalls of the second support layer 202 by performing various processes. For example, the second initial mask layer 204 can be formed by conformally forming a second layer on the second support layer 202, the first mask layer 104, and the first initial mask layer 106, and then performing an etching process (e.g., blanket etching). In some embodiments, the second initial mask layer 204 can have a uniform thickness on the sidewalls of the second support layer 202, such as... Figure 14A and Figure 14B As shown.

[0051] The second support layer 202 may include, for example, polysilicon, silicon nitride, silicon oxide, and / or spin-coated organic hard mask layers, and the second initial mask layer 204 may include, for example, polysilicon, silicon nitride, and / or silicon oxide. In some embodiments, the second support layer 202 and the second initial mask layer 204 may include different materials, such that the second support layer 202 and the second initial mask layer 204 may have etch selectivity relative to each other when performing an etching process.

[0052] Reference Figure 10 , Figure 15A , Figure 15B and Figure 15C The method may include removing the second support layer 202 (block 1050) by performing, for example, a dry etching process and / or a wet etching process. After removing the second support layer 202, a second initial mask layer 204 may define a second opening OP2 on the first mask layer 104 and the first initial mask layer 106. The second support layer 202 may be selectively removed relative to the second initial mask layer 204, such that the second initial mask layer 204 may be retained, as... Figure 15A , Figure 15B and Figure 15C As shown. In some embodiments, the second opening OP2 can expose the upper surfaces of the first mask layer 104 and the first initial mask layer 106, such as... Figure 15B As shown.

[0053] Reference Figure 10 , Figure 16A , Figure 16B and Figure 16C The method may include forming a second mask layer 108 (block 1060) by performing, for example, a dry etching process and / or a wet etching process on a first initial mask layer 106 using a second initial mask layer 204 as an etching mask.

[0054] Reference Figure 10 , Figure 17A , Figure 17B and Figure 17C The method may include removing the second initial mask layer 204 (block 1070). In some embodiments, the first mask layer 104 may include first portions (e.g., 104a and 104b), and the second mask layer 108 may include second portions (e.g., 108a, 108b, and 108c). Each of the first portions 104a and 104b of the first mask layer 104 may extend longitudinally in a first horizontal direction X, and the first portions 104a and 104b of the first mask layer 104 may be spaced apart from each other in a second horizontal direction Y, such as... Figure 17A As shown. The second portions 108a, 108b, and 108c of the second mask layer 108 may be spaced apart from each other in the second horizontal direction Y, and each of the second portions 108a, 108b, and 108c of the second mask layer 108 may be connected to one or both of the adjacent first portions 104a and 104b, as shown. Figure 17A and Figure 17C As shown.

[0055] Reference Figure 10 , Figure 18A , Figure 18B and Figure 18C The method may include forming a third mask layer 302 (block 1080) on the first mask layer 104 and the second mask layer 108.

[0056] Reference Figure 10 , Figure 19A , Figure 19B and Figure 19C The method may include forming an etch mask layer 110 (block 1090) by removing portions of a first mask layer 104 and a second mask layer 108. Each etch mask layer 110 may include a portion of the first mask layer 104 and / or a portion of the second mask layer 108.

[0057] Reference Figure 9 , Figure 20A , Figure 20B and Figure 20C The method may include forming a channel region 22 by etching the substrate 10 using an etch mask layer 110.

[0058] Despite Figures 11A to 20C The substrate 10 is shown as a single layer, but it will be understood that the substrate 10 may include multiple layers. For example, the substrate 10 may include a stacked structure comprising a first semiconductor layer, an insulating layer, and a second semiconductor layer sequentially stacked in a vertical direction (e.g., vertical direction Z), and two channel regions (e.g., Figure 7 and Figure 8 The channel region 22 and upper channel region 62 of the stacked VFET in the substrate 10 can be formed by etching the stacked structure of the substrate 10 using an etch mask layer 110.

[0059] Figures 21 to 23 This is a top view illustrating a method for forming an etched mask layer 110 of various shapes according to some embodiments of the present invention. Figure 21 A first mask layer 104 and a second mask layer 108 formed on a substrate 10 are shown in the top view. The first mask layer 104 and the second mask layer 108 can be seen by referring to... Figure 10 and Figures 11A to 17C The method of description is formed.

[0060] Reference Figure 22 A third mask layer 302 can be formed on the first mask layer 104 and the second mask layer 108. (Refer to...) Figure 23 An etching mask layer 110 can be formed on the substrate 10 by etching the first mask layer 104 and the second mask layer 108 using the third mask layer 302 as an etching mask. It will be understood that etching mask layers 110 with various shapes can be formed by forming the third mask layer 302 with various shapes. Channel regions with various shapes can be formed by etching the substrate 10 using the etching mask layer 110 as an etching mask.

[0061] Example embodiments are described herein with reference to the accompanying drawings. Many different forms and embodiments are possible without departing from the spirit and teachings of this disclosure, and therefore this disclosure should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of this disclosure to those skilled in the art. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity. The same reference numerals always refer to the same elements.

[0062] Example embodiments of the inventive concept are described herein with reference to sectional or top views, which are schematic illustrations of intermediate structures between idealized and example embodiments. Therefore, variations in shape relative to the illustrations will be expected as a result of, for example, manufacturing techniques and / or tolerances. Thus, the example embodiments of the inventive concept should not be construed as limited to the particular shapes shown herein, but rather include, for example, deviations in shape due to manufacturing processes.

[0063] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. It will also be understood that terms (such as those defined in general dictionaries) should be interpreted as having meanings consistent with their meanings in the context of the relevant field and will not be interpreted in an idealized or overly formalized sense, unless expressly defined herein.

[0064] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concept. When used herein, the singular forms “a” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising,” “including,” “including,” and / or “comprising” indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. When used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0065] It will be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the inventive concept, a first element may be referred to as a second element.

[0066] It should be noted that in some alternative embodiments, the functions / actions written in the flowchart blocks may not occur in the order they are mentioned in the flowchart. For example, depending on the functions / actions involved, two blocks shown consecutively may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order. Furthermore, the function of a given block in the flowchart and / or block diagram may be divided into multiple blocks, and / or the functions of two or more blocks in the flowchart and / or block diagram may be at least partially integrated. Finally, other blocks may be added / inserted between the shown blocks, and / or blocks / operations may be omitted without departing from the scope of the inventive concept.

[0067] The subject matter disclosed above should be considered illustrative rather than restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments that fall within the true spirit and scope of the inventive concept. Therefore, the scope will be determined by the broadest permissible interpretation of the appended claims and their equivalents, to the maximum extent permitted by law, and should not be constrained or limited by the foregoing detailed description.

[0068] This application claims priority to U.S. Provisional Patent Application No. 62 / 862,946, entitled “VFET Structure with Cross-shaped Fin Array,” filed June 18, 2019, with the United States Patent and Trademark Office (USPTO), the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An integrated circuit device, comprising: Vertical field-effect transistors, including: Bottom source / drain region in the substrate; A channel region on the bottom source / drain region, wherein the channel region includes a cross-shaped upper surface; Top source / drain region on the channel region; A grid structure on the side of the channel region; A first spacer is vertically inserted between the bottom source / drain region and the gate structure; and The second spacer is vertically inserted between the gate structure and the top source / drain region.

2. The integrated circuit device according to claim 1, wherein, The gate structure includes a gate electrode, and the gate electrode surrounds the channel region.

3. The integrated circuit device according to claim 1, wherein, The top source / drain region includes a cross-shaped upper surface that overlaps perpendicularly with the cross-shaped upper surface of the channel region.

4. The integrated circuit device according to claim 3, wherein, The cross-shaped upper surface of the top source / drain region overlaps vertically with the cross-shaped upper surface of the channel region.

5. The integrated circuit device according to claim 1, wherein, The cross-shaped upper surface of the channel region includes a first cross-shaped portion and a second cross-shaped portion.

6. The integrated circuit device according to claim 1, wherein, The vertical field-effect transistor is a first vertical field-effect transistor, and the integrated circuit device further includes a second vertical field-effect transistor, and The second vertical field-effect transistor includes a second channel region, which includes a linear upper surface.

7. The integrated circuit device according to claim 1, wherein, The vertical field-effect transistor is a first vertical field-effect transistor, and the integrated circuit device further includes a third vertical field-effect transistor, the third vertical field-effect transistor being located on the top source / drain region of the first vertical field-effect transistor and including a third channel region. The third channel region includes a cross-shaped upper surface and overlaps perpendicularly with the cross-shaped upper surface of the channel region of the first vertical field-effect transistor.

8. The integrated circuit device of claim 7, further comprising an insulating layer between the channel region of the first vertical field-effect transistor and the third channel region of the third vertical field-effect transistor and including a cross-shaped upper surface.

9. The integrated circuit device according to claim 8, wherein, The cross-shaped upper surface of the third channel region of the third vertical field-effect transistor overlaps perpendicularly with the cross-shaped upper surface of the insulating layer and the cross-shaped upper surface of the channel region of the first vertical field-effect transistor.

10. An integrated circuit device, comprising: Vertical field-effect transistors, including: Bottom source / drain region in the substrate; The trench region on the substrate includes a core portion, a first pair of protruding portions and a second pair of protruding portions, wherein the first pair of protruding portions protrude from the core portion in opposite directions along a first horizontal direction, and the second pair of protruding portions protrude from the core portion in opposite directions along a second horizontal direction, wherein the first horizontal direction and the second horizontal direction are parallel to the upper surface of the substrate and are different from each other. The top source / drain region on the channel region, wherein the channel region is between the bottom source / drain region and the top source / drain region; A grid structure on the side of the channel region; A first spacer is vertically inserted between the bottom source / drain region and the gate structure; and The second spacer is vertically inserted between the gate structure and the top source / drain region.

11. The integrated circuit device according to claim 10, wherein, The channel region also includes a third pair of protrusions, which protrude along the first horizontal direction from a portion of one of the second pair of protrusions in opposite directions.

12. The integrated circuit device according to claim 10, wherein, The second pair of protruding portions have different lengths in the second horizontal direction.

13. The integrated circuit device according to claim 10, wherein, The vertical field-effect transistor is a first vertical field-effect transistor, and the integrated circuit device further includes a second vertical field-effect transistor, and The second vertical field-effect transistor includes a second channel region, which includes a linear upper surface.

14. The integrated circuit device according to claim 10, wherein, The gate structure includes a gate electrode, and the gate electrode surrounds the channel region.

15. The integrated circuit device according to claim 10, wherein, The top source / drain region is vertically overlapped with the core portion of the channel region and also vertically overlapped with the first pair of protrusions and the second pair of protrusions.

16. The integrated circuit device according to claim 15, wherein, The top source / drain region overlaps vertically with the entirety of the first pair of protrusions and the entirety of the second pair of protrusions.

17. An integrated circuit device, comprising: Vertical field-effect transistors, including: Bottom source / drain region in the substrate; The channel region on the bottom source / drain region; A top source / drain region on the channel region, wherein the top source / drain region includes a cross-shaped upper surface, and the channel region is between the bottom source / drain region and the top source / drain region; A grid structure on the side of the channel region; A first spacer is vertically inserted between the bottom source / drain region and the gate structure; and The second spacer is vertically inserted between the gate structure and the top source / drain region.

18. The integrated circuit device according to claim 17, wherein, The top source / drain region overlaps vertically with the entire channel region.

19. The integrated circuit device according to claim 17, wherein, The channel region includes a cross-shaped upper surface, and The cross-shaped upper surface of the top source / drain region overlaps perpendicularly with the cross-shaped upper surface of the channel region.

20. The integrated circuit device according to claim 19, wherein, The gate structure includes a gate electrode, and the gate electrode surrounds the channel region.

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