Semiconductor components and power amplifiers

Abstract

The present invention provides a semiconductor element and a power amplifier device capable of improving heat dissipation characteristics. The semiconductor element comprises: a semiconductor substrate; a first amplifier and a second amplifier, which are arranged on the semiconductor substrate and are adjacent to each other in a first direction; a first reference potential bump, which is arranged on the main surface of the semiconductor substrate and connects the first amplifier and the reference potential; a second reference potential bump, which is arranged on the main surface of the semiconductor substrate and is adjacent to the first reference potential bump in the first direction and connects the second amplifier and the reference potential; and a rectangular bump, which is arranged on the main surface of the semiconductor substrate and is arranged between the first reference potential bump and the second reference potential bump when viewed from above, and a second width in a second direction orthogonal to the first direction is larger than the first width in the first direction, and a second width of the rectangular bump is larger than a width in the second direction of at least one of the first reference potential bump and the second reference potential bump.

Description

Technical Field

[0001] The present invention relates to a semiconductor element and a power amplifier device. Background Art

[0002] Patent document 1 describes a high-frequency power amplifier module having a first power amplifier and a second power amplifier provided on a semiconductor chip. In the high-frequency power amplifier module of Patent document 1, a plurality of trap bumps are provided between the first power amplifier and the second power amplifier on the main surface of the semiconductor chip. In the high-frequency power amplifier module of Patent document 1, electromagnetic coupling can be suppressed by trapping the high-frequency signal propagating between the first power amplifier and the second power amplifier by the trap bumps.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2005-33350

[0004] In a semiconductor element and a power amplifier device provided with a plurality of power amplifiers, it is required to improve the heat dissipation characteristics in order to improve the performance and ensure the reliability. In Patent Document 1, the plurality of capture bumps are circular in plan view and are arranged at intervals. Therefore, heat may be transferred between the first power amplifier and the second power amplifier through the plurality of capture bumps. Summary of the invention

[0005] An object of the present invention is to provide a semiconductor element and a power amplifier device capable of improving heat dissipation characteristics.

[0006] A semiconductor element of one embodiment of the present invention comprises: a semiconductor substrate; a first amplifier and a second amplifier, which are arranged on the semiconductor substrate, and the first amplifier and the second amplifier are adjacent to each other in a first direction; a first reference potential bump, which is arranged on the main surface of the semiconductor substrate, and connects the first amplifier and the reference potential; a second reference potential bump, which is arranged on the main surface of the semiconductor substrate, and the second reference potential bump is adjacent to the first reference potential bump in the first direction, and connects the second amplifier and the reference potential; and a rectangular bump, which is arranged on the main surface of the semiconductor substrate, and when viewed from above from a direction perpendicular to the main surface, the rectangular bump is arranged between the first reference potential bump and the second reference potential bump, and the second width in a second direction orthogonal to the first direction is larger than the first width in the first direction, and the second width of the rectangular bump is larger than the width of at least one of the first reference potential bump and the second reference potential bump in the second direction.

[0007] A power amplifier device according to one embodiment of the present invention comprises: the semiconductor element described above; and a module substrate, which is opposite to the semiconductor element and electrically connected to the semiconductor element, and the module substrate comprises: an insulating substrate, which has a first surface opposite to the main surface of the semiconductor substrate, and a second surface opposite to the first surface; and a plurality of first wirings, which are arranged on the first surface of the insulating substrate, are respectively connected to the first reference potential bump, the second reference potential bump and the rectangular bump, and are separated from each other.

[0008] According to the semiconductor element and the power amplifier device of the present invention, it is possible to improve the heat dissipation characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a block diagram showing the structure of the power amplifier device according to the first embodiment.

[0010] Figure 2 It is a plan view showing the power amplifier device according to the first embodiment.

[0011] Figure 3 It is a top view showing transistors included in the power amplifier device.

[0012] Figure 4 It is a plan view showing, in an enlarged manner, a rectangular bump, a first amplifier, and a second amplifier according to the first embodiment.

[0013] Figure 5 yes Figure 2 V-V' cross-sectional view.

[0014] Figure 6 yes Figure 2 VI-VI' cross-sectional view.

[0015] Figure 7 This is a graph for explaining the relationship between the width of the rectangular bump in the second direction and the temperature drop in the power amplifier device of the first embodiment.

[0016] Figure 8 This is a graph for explaining the relationship between the center position in the second direction of the rectangular bump and the temperature drop in the power amplifier device of the first embodiment.

[0017] Fig. 9 is a cross-sectional view showing a power amplifier device according to a second embodiment.

[0018] Fig.10 It is a plan view showing a power amplifier device according to a third embodiment.

[0019] Fig.11 It is a plan view showing a power amplifier device according to a fourth embodiment.

[0020] Fig.12 This is a graph for explaining the relationship between the center position in the second direction of the rectangular bump and the temperature drop in the power amplifier device of the second embodiment.

[0021] Fig.13 It is a block diagram showing the structure of a power amplifier device according to a fifth embodiment.

[0022] Fig.14 It is a plan view showing a power amplifier device according to a fifth embodiment.

[0023] Description of reference numerals:

[0024] 1…semiconductor substrate; 1a…recess; 2…subcollector layer; 3…collector layer; 4…base layer; 5…emitter layer; 7…collector electrode; 8…base electrode; 9…emitter electrode; 10…driver amplifier; 11…first amplifier; 12…second amplifier; 13…distributor; 14…coupler; 15…rectangular bump; 16, 16A, 16B, 17, 17A, 17B…terminal; 18…metal layer; 21…first reference potential bump; 31…second reference potential bump; 50…insulation Substrate; 51, 51-1, 51-2, 51-3…first wiring; 52, 52-1, 52-2, 52-3…second wiring; 53…third wiring; 54…fourth wiring; 57…through hole; 100, 100A, 100B, 100C, 100D…power amplifier; 101, 101A, 101B, 101C, 101D…semiconductor element; 105…module substrate; Tr…transistor; HP…heat conduction path; Q1…first transistor group; Q2…second transistor group. DETAILED DESCRIPTION

[0025] Hereinafter, the embodiments of the semiconductor element and the power amplifier device of the present invention are described in detail based on the accompanying drawings. In addition, this embodiment does not limit the present invention. Each embodiment is an example, and of course, partial replacement or combination of the structures shown in different embodiments can be performed. In the second embodiment and after the second embodiment, the description of matters common to the first embodiment is omitted, and only the differences are described. In particular, the same effects based on the same structure are not mentioned in sequence in each embodiment.

[0026] (First Embodiment)

[0027] Figure 1 1 is a block diagram showing the structure of the power amplifier device according to the first embodiment. Figure 1As shown, the power amplifier device 100 includes: a semiconductor element 101 and a module substrate 105. The semiconductor element 101 includes: a driver stage amplifier 10, a distributor 13, a first amplifier 11, a second amplifier 12, and a rectangular bump 15. The module substrate 105 includes a coupler 14. The semiconductor element 101 is mounted on the module substrate 105, and the first amplifier 11 and the second amplifier 12 of the semiconductor element 101 are electrically connected to the coupler 14.

[0028] The driver amplifier 10 amplifies the input high frequency input signal RFin-d and outputs the amplified signal RFout-d. The driver amplifier 10 is, for example, an amplifier circuit including a heterojunction bipolar transistor (HBT). Although the frequency of the high frequency input signal RFin-d is illustrated as being about several hundred MHz (megahertz) to several tens of GHz (gigahertz), the present invention is not limited thereto.

[0029] The distributor 13 separates the amplified signal RFout-d supplied from the driver stage amplifier 10 into a first high frequency signal RFin1 and a second high frequency signal RFin2. The distributor 13 is formed by, for example, a transformer. The first high frequency signal RFin1 and the second high frequency signal RFin2 are differential signals, for example, the first high frequency signal RFin1 is a high frequency signal of positive polarity, and the second high frequency signal RFin2 is a high frequency signal of negative polarity.

[0030] The first amplifier 11 and the second amplifier 12 form a differential amplifier circuit. The first amplifier 11 amplifies the first high frequency signal RFin1 and outputs a first output signal RFout1. The second amplifier 12 amplifies the second high frequency signal RFin2 and outputs a second output signal RFout2.

[0031] The coupler 14 converts the first output signal RFout1 and the second output signal RFout2 as a pair of differential signals into a high-frequency output signal RFout, and outputs the high-frequency output signal RFout. The coupler 14 is formed of, for example, a transformer.

[0032] The rectangular bump 15 is disposed between the first amplifier 11 and the second amplifier 12. The rectangular bump 15 is provided on the semiconductor element 101 to be separated from the first amplifier 11 and the second amplifier 12 so as to dissipate or conduct heat generated by the semiconductor element 101 to the outside.

[0033] Figure 2 FIG. 1 is a top view showing the power amplifier device of the first embodiment. Figure 2 In FIG. 1 , the semiconductor substrate 1 of the semiconductor element 101 is indicated by a dashed line for easy understanding of the drawing.

[0034] like Figure 2 As shown, the driver stage amplifier 10 , the first amplifier 11 , the second amplifier 12 , the distributor 13 , the rectangular bumps 15 , and the terminals 16 are provided on the semiconductor substrate 1 . The coupler 14 and the terminals 17 are provided on the module substrate 105 .

[0035] In the following description, a direction in a plane parallel to the surface of the semiconductor substrate 1 is referred to as a first direction Dx. In addition, in a plane parallel to the surface of the semiconductor substrate 1, a direction orthogonal to the first direction Dx is referred to as a second direction Dy. In addition, a direction orthogonal to the first direction Dx and the second direction Dy is referred to as a third direction Dz. The third direction Dz is a direction perpendicular to the semiconductor substrate 1. In this specification, a top view indicates a positional relationship when viewed from the third direction Dz.

[0036] A high-frequency input signal RFin-d is input to the terminal 16. The terminal 16 is connected to the driver-stage amplifier 10. The driver-stage amplifier 10 is connected to the input terminal 22 of the first amplifier 11 and the input terminal 32 of the second amplifier 12 via the distributor 13. The output terminal 23 of the first amplifier 11 and the output terminal 33 of the second amplifier 12 are connected to the terminal 17 via the coupler 14. The terminal 17 outputs the high-frequency output signal RFout.

[0037] The first amplifier 11 includes: a first transistor group Q1 having a plurality of transistors Tr, a first reference potential bump 21, an input terminal 22, an output terminal 23, a first connection wiring 24, and a second connection wiring 25. The plurality of transistors Tr are arranged in a first direction Dx. The plurality of transistors Tr are, for example, heterojunction bipolar transistors. In addition, the transistor Tr is not limited thereto, and other structures such as field effect transistors (FET) can also be used.

[0038] Figure 3 FIG. 1 is a top view showing a transistor included in the power amplifier. Figure 3 , a top view of a transistor Tr is schematically and enlargedly shown. Figure 3 As shown, the transistor Tr includes: a subcollector layer 2, a collector layer 3, a base layer 4, an emitter layer 5, various electrodes and wiring. The subcollector layer 2, the collector layer 3, the base layer 4, and the emitter layer 5 are sequentially stacked on the semiconductor substrate 1. Two emitter layers 5 are adjacently arranged in the first direction Dx.

[0039] Two collector electrodes 7 are arranged along the first direction Dx on the sub-collector layer 2, and a collector layer 3 is arranged between the two collector electrodes 7. Figure 3Although one transistor Tr is shown in FIG. 1 , the collector electrode 7 may be shared by adjacent transistors Tr. That is, one collector electrode 7 may be provided between adjacent transistors Tr.

[0040] The base electrode 8 is provided on the base layer 4 . In a plan view, the base electrode 8 is arranged between the emitter layers 5 adjacent to each other in the first direction Dx. The emitter electrode 9 is provided on the emitter layer 5 .

[0041] like Figure 2 The first connection wiring 24 shown connects the input terminal 22 and the base electrodes 8 of the plurality of transistors Tr. The second connection wiring 25 connects the output terminal 23 and the collector electrodes 7 of the plurality of transistors Tr. The first reference potential bump 21 is arranged to overlap with the plurality of transistors Tr, and the width in the first direction Dx is larger than the width in the second direction Dy. The first reference potential bump 21 connects the reference potential and the emitter electrodes 9 of the plurality of transistors Tr of the first amplifier 11. The reference potential is, for example, a ground potential.

[0042] The second amplifier 12 is arranged adjacent to the first amplifier 11 in the first direction Dx. The second amplifier 12 includes a second transistor group Q2 having a plurality of transistors Tr, a second reference potential bump 31, an input terminal 32, an output terminal 33, a first connection wiring 34, and a second connection wiring 35. The plurality of transistors Tr are arranged in the first direction Dx.

[0043] The first connection wiring 34 connects the input terminal 32 and the base electrodes 8 of the plurality of transistors Tr of the second transistor group Q2. The input terminal 22 of the first amplifier 11 and the input terminal 32 of the second amplifier 12 are connected to the distributor 13. The second connection wiring 35 connects the output terminal 33 and the collector electrodes 7 of the plurality of transistors Tr. The output terminal 23 of the first amplifier 11 and the output terminal 33 of the second amplifier 12 are connected to the coupler 14. The second reference potential bump 31 is arranged to overlap with the plurality of transistors Tr, and the width in the first direction Dx is larger than the width in the second direction Dy. The second reference potential bump 31 connects the reference potential and the emitter electrodes 9 of the plurality of transistors Tr of the second amplifier 12.

[0044] The second amplifier 12 has a similar structure to the first amplifier 11. However, the second amplifier 12 may also have a different structure from the first amplifier 11. For example, the number of the plurality of transistors Tr included in the second transistor group Q2 may also be different from the number of the plurality of transistors Tr included in the first transistor group Q1. In addition, the arrangement direction of the plurality of transistors Tr included in the second transistor group Q2 may also be different from the arrangement direction of the plurality of transistors Tr included in the first transistor group Q1.

[0045] The rectangular bump 15 is disposed between the first reference potential bump 21 and the second reference potential bump 31 adjacent to each other in the first direction Dx when viewed from above. The rectangular bump 15 is separated from the first reference potential bump 21 and the second reference potential bump 31 on the semiconductor substrate 1. The rectangular bump 15 is roughly rectangular when viewed from above. However, the rectangular bump 15 can be any other shape, such as an oblong, elliptical, or rectangular, as long as it is a long shape in the second direction Dy. The rectangular bump 15 is made of a metal material having good thermal conductivity, such as copper (Cu) or gold (Au).

[0046] Figure 4 FIG. 2 is a plan view showing an enlarged rectangular bump, a first amplifier, and a second amplifier of the first embodiment. Figure 4 As shown, the second width W2 of the rectangular protrusion 15 in the second direction Dy is greater than the first width W1 in the first direction Dx. The rectangular protrusion 15 is provided continuously from one end to the other end in the second direction Dy without any slits or the like.

[0047] In addition, the position of the rectangular bump 15 in the second direction Dy overlaps the position of the first reference potential bump 21 and the second reference potential bump 31 in the second direction Dy. That is, the rectangular bump 15 intersects the imaginary line L. The imaginary line L is an imaginary line connecting the center C1 of the width W3 of the first reference potential bump 21 in the second direction Dy and the center C2 of the width W4 of the second reference potential bump 31 in the second direction Dy. The second width W2 of the rectangular bump 15 is larger than the width W3 of the first reference potential bump 21 in the second direction Dy. In addition, the second width W2 of the rectangular bump 15 is larger than the width W4 of the second reference potential bump 31 in the second direction Dy.

[0048] In this way, since the rectangular bump 15 is provided in a substantially rectangular shape or a substantially oblong shape, heat dissipation can be improved compared to the case where a substantially circular bump having an aspect ratio of about 1 is provided (for example, the second width W2 and the first width W1 are of the same magnitude). In addition, since the rectangular bump 15 is provided between the first amplifier 11 and the second amplifier 12, the rectangular bump 15 can suppress heat transfer between the first transistor group Q1 and the second transistor group Q2.

[0049] Next, the cross-sectional structure of the power amplifier device 100 will be described. Figure 5 yes Figure 2 V-V' cross-sectional view. Figure 6 yes Figure 2 VI-VI' section view. Figure 5As shown, the main surface of the semiconductor element 101 is arranged opposite to the upper surface of the module substrate 105. The first reference potential bump 21, the second reference potential bump 31 and the rectangular bump 15 are arranged on the same main surface of the semiconductor element 101. The height of the rectangular bump 15 in the third direction Dz is equal to the height of the first reference potential bump 21 and the second reference potential bump 31 in the third direction Dz. The lower surfaces of the first reference potential bump 21, the second reference potential bump 31 and the rectangular bump 15 are connected to the first wirings 51-1, 51-2, and 51-3 provided on the upper surface of the module substrate 105, respectively.

[0050] The module substrate 105 includes an insulating substrate 50, first wirings 51-1, 51-2, 51-3, second wirings 52-1, 52-2, 52-3, third wirings 53, fourth wirings 54, and vias 57. The insulating substrate 50 is a ceramic substrate or a printed substrate, and is formed by stacking a plurality of dielectric layers. In the following description, when it is not necessary to distinguish the first wirings 51-1, 51-2, 51-3, they are sometimes simply represented as the first wirings 51. The second wirings 52-1, 52-2, 52-3 are also sometimes simply represented as the second wirings 52.

[0051] The insulating substrate 50 has a first surface 50a and a second surface 50b on the opposite side of the first surface 50a. The first surface 50a faces the main surface of the semiconductor substrate 1. A first wiring 51, a second wiring 52, a third wiring 53, and a fourth wiring 54 are stacked in order from the first surface 50a side to the second surface 50b side of the insulating substrate 50. The first wiring 51 is provided on the first surface 50a of the insulating substrate 50 and is provided in a layer closest to the semiconductor element 101.

[0052] The second wiring 52 is provided in an inner layer of the insulating substrate 50. Specifically, the second wiring 52 is provided in the second layer from the first surface 50a of the insulating substrate 50. That is, the second wiring 52 is stacked with the first wiring 51 via a dielectric layer. The third wiring 53 is provided in the third layer from the first surface 50a of the insulating substrate 50. The third wiring 53 is stacked with the second wiring 52 via a dielectric layer. The fourth wiring 54 is provided on the second surface 50b of the insulating substrate 50 and is provided in the layer farthest from the semiconductor element 101. The fourth wiring 54 is connected to a reference potential.

[0053] The first wirings 51-1, 51-2, and 51-3 are provided separately from each other. The first reference potential bump 21 is connected to the first wiring 51-1. The second reference potential bump 31 is connected to the first wiring 51-2. The rectangular bump 15 is connected to the first wiring 51-3.

[0054] The second wirings 52-1, 52-2, and 52-3 are also provided separately from each other. The second wiring 52-1 is provided at a position overlapping with the first wiring 51-1, and is electrically connected to the first wiring 51-1 via the via 57. The second wiring 52-2 is provided at a position overlapping with the first wiring 51-2, and is electrically connected to the first wiring 51-2 via the via 57. The second wiring 52-3 is provided at a position overlapping with the first wiring 51-3, and is electrically connected to the first wiring 51-3 via the via 57.

[0055] The third wiring 53 is provided to be shared with the first wirings 51-1, 51-2, 51-3 and the second wirings 52-1, 52-2, 52-3. In other words, the third wiring 53 is continuously provided in the region overlapping with the first reference potential bump 21, the second reference potential bump 31 and the rectangular bump 15. The third wiring 53 is provided at a position farther from the first surface 50a than the plurality of second wirings 52-1, 52-2, 52-3. The third wiring 53 is electrically connected to the second wirings 52-1, 52-2, 52-3 via a plurality of vias 57.

[0056] The fourth wiring 54 is provided in a region overlapping with the third wiring 53, and is electrically connected to the third wiring 53 via a plurality of vias 57. By connecting the fourth wiring 54 to the reference potential, the plurality of transistors Tr of the first transistor group Q1 and the plurality of transistors Tr of the second transistor group Q2 are connected to the reference potential, respectively. The third wiring 53 and the fourth wiring 54 have a larger area than the first wiring 51-1, 51-2, 51-3 and the second wiring 52-1, 52-2, 52-3. Thus, the reference potential of the power amplifier device 100 can be ensured.

[0057] With such a structure, a heat conduction path HP is formed from the rectangular bump 15 through the first wiring 51-3, the via 57, the second wiring 52-3, the via 57, the third wiring 53, the via 57, and the fourth wiring 54. The heat generated by each transistor Tr of the semiconductor element 101 is transferred to the second surface 50b side of the insulating substrate 50 through the heat conduction path HP. In the present embodiment, the first wiring 51-3 and the second wiring 52-3 provided in the layer close to the semiconductor element 101 are separated from the first wiring 51-1, 51-2 and the second wiring 52-1, 52-2, respectively. Therefore, in the same layer as the first wiring 51-3 and the second wiring 52-3, a heat conduction path that is transferred in the horizontal direction is not formed, and it is possible to suppress the heat from the rectangular bump 15 from returning to the semiconductor element 101.

[0058] In addition, the module substrate 105 has 4 layers of wiring, but is not limited thereto, and may have 3 layers of wiring, or may have 5 or more layers of wiring. For example, 3 or more layers of wiring arranged separately may be provided so as to overlap with the first reference potential bump 21, the second reference potential bump 31, and the rectangular bump 15, respectively. In addition, 3 or more layers of wiring provided in common with the first wiring 51-1, 51-2, 51-3 and the second wiring 52-1, 52-2, 52-3 may be provided.

[0059] like Figure 6 As shown, the first wiring 51-3 and the second wiring 52-3 extend in the second direction Dy and are arranged to overlap with the rectangular bump 15. The first wiring 51-3 and the second wiring 52-3 are connected through a plurality of vias 57 arranged in the second direction Dy. In addition, the second wiring 52-3 and the third wiring 53 are also connected through a plurality of vias 57 arranged in the second direction Dy. As a result, the heat from the semiconductor element 101 is efficiently transferred to the lower side (the fourth wiring 54 side) in the third direction Dz.

[0060] (First embodiment)

[0061] Figure 7 This is a graph for explaining the relationship between the width of the rectangular bump in the second direction and the temperature drop in the power amplifier device of the first embodiment. Figure 7 The horizontal axis of the graph shown is the second width W2 (μm) of the rectangular bump 15, and the vertical axis is the temperature drop ΔT (K). The first width W1 of the rectangular bump 15 is constant (for example, W1 = 75 μm). The temperature drop ΔT (K) is based on the temperature when the rectangular bump 15 is not provided (W2 = 0 μm). In addition, regarding the temperature, the center C1 (refer to Figure 4 ) temperature.

[0062] like Figure 7 As shown, the larger the second width W2 of the rectangular bump 15, the larger the temperature drop ΔT. More specifically, it is shown that when the second width W2 is greater than 150 μm, that is, when the aspect ratio (W2 / W1) of the second width W2 to the first width W1 is greater than 2, the temperature drop ΔT becomes less than -20°, and good heat dissipation is obtained.

[0063] Figure 8 This is a graph for explaining the relationship between the center position in the second direction of the rectangular bump and the temperature drop in the power amplifier device of the first embodiment. Figure 8 The temperature drop ΔT when the position of the rectangular bump 15 in the second direction Dy is changed is shown. Figure 8The horizontal axis of the graph shown shows the center position of the rectangular bump 15 in the second direction Dy, with the position of the center C1 of the first reference potential bump 21 in the second direction Dy as a reference.

[0064] like Figure 8 As shown, the temperature drop ΔT is maximum when the center position of the rectangular bump 15 in the second direction Dy is 0 μm, that is, the center position of the rectangular bump 15 in the second direction Dy coincides with the center C1 in the second direction Dy of the first reference potential bump 21. As the center position in the second direction Dy shifts, the temperature drop ΔT decreases.

[0065] (Second Embodiment)

[0066] Fig. 9 1 is a cross-sectional view showing a power amplifier device according to a second embodiment. In the second embodiment, a structure in which a recess 1a is provided on the main surface of a semiconductor substrate 1, which is different from the first embodiment described above, is described. In addition, in the following description, the same reference numerals are given to the same structural elements as those in the above-mentioned embodiment, and the description thereof is omitted.

[0067] like Fig. 9 As shown, the recess 1a is provided on the main surface of the semiconductor substrate 1 on which the plurality of transistors Tr are provided. The recess 1a is provided with a metal layer 18. The thickness of the metal layer 18 is greater than the depth of the recess 1a. The metal layer 18 fills the recess 1a and is also provided to overlap with the main surface around the recess 1a.

[0068] The rectangular bump 15 is provided so as to overlap with the metal layer 18. In the present embodiment, the height of the rectangular bump 15 is lower than the first reference potential bump 21 and the second reference potential bump 31. By adjusting the height of the rectangular bump 15, the rectangular bump 15 can connect the metal layer 18 and the first wiring 51-3. In addition, the first width W1 of the rectangular bump 15 is smaller than the width of the concave portion 1a and the metal layer 18 in the first direction Dx.

[0069] In the present embodiment, the total height of the metal layer 18 and the rectangular bump 15 is higher than the height of each of the first reference potential bump 21 and the second reference potential bump 31. That is, the total height of the metal layer 18 and the rectangular bump 15 is higher than the rectangular bump 15 of the first embodiment. Therefore, the power amplifier device 100A and the semiconductor element 101A can improve heat dissipation.

[0070] (Third Embodiment)

[0071] Fig.101 is a plan view showing a power amplifier device according to a third embodiment. In the third embodiment, a configuration is described in which, unlike the first and second embodiments, the first amplifier 11A and the second amplifier 12A each include a plurality of transistors Tr arranged in the second direction Dy.

[0072] like Fig.10 As shown, the first amplifier 11A and the second amplifier 12A respectively arrange a plurality of transistors Tr in the second direction Dy, and the plurality of transistors Tr arranged in the second direction Dy are arranged in the first direction Dx. Fig.10 In the embodiment, two columns of a plurality of transistors Tr are arranged in the first direction Dx, but three or more columns may be provided.

[0073] The first reference potential bump 21 and the second reference potential bump 31 are respectively arranged in regions overlapping with a plurality of transistors Tr arranged in the second direction Dy, and widths W3 a and W4 a in the second direction Dy are larger than the width in the first direction Dx.

[0074] In the first amplifier 11A, a plurality of first reference potential bumps 21 are arranged in a row in the first direction Dx. In the second amplifier 12A, a plurality of second reference potential bumps 31 are arranged in a row in the first direction Dx. However, each of the first reference potential bump 21 and the second reference potential bump 31 may be provided one each, or three or more may be arranged in a row.

[0075] In the present embodiment as well, the second width W2 of the rectangular bump 15 is larger than the width W3a of the first reference potential bump 21 in the second direction Dy and the width W4a of the second reference potential bump 31 in the second direction Dy. Thus, the power amplifier device 100B and the semiconductor element 101B can improve heat dissipation. In addition, since the transistors Tr are arranged in the second direction Dy, the widths of the power amplifier device 100B and the semiconductor element 101B in the first direction Dx can be reduced.

[0076] (Fourth Embodiment)

[0077] Fig.11 1 is a plan view showing a power amplifier device according to a fourth embodiment. In the fourth embodiment, a configuration in which the arrangement directions of the plurality of transistors Tr in the first amplifier 11 and the second amplifier 12A are different from those in the first to third embodiments will be described.

[0078] like Fig.11As shown, the first amplifier 11 includes a plurality of transistors Tr arranged in the first direction Dx as in the first embodiment. The first reference potential bump 21 is arranged in a region overlapping the plurality of transistors Tr arranged in the first direction Dx, and the width in the first direction Dx is greater than the width W3 in the second direction Dy.

[0079] Also, similar to the third embodiment, the second amplifier 12A includes a plurality of transistors Tr arranged in the second direction Dy. The second reference potential bump 31 is disposed in a region overlapping the plurality of transistors Tr, and has a width W4a in the second direction Dy greater than the width in the first direction Dx.

[0080] Similarly, in the present embodiment, the second width W2 of the rectangular bump 15 is larger than the width W3 of the first reference potential bump 21 in the second direction Dy and the width W4a of the second reference potential bump 31 in the second direction Dy. As a result, the power amplifier device 100C and the semiconductor element 101C can improve heat dissipation. In addition, since the first amplifier 11 and the second amplifier 12A can adopt different structures, the degree of freedom of configuration of the circuit structure is increased. In addition, the first amplifier 11 and the second amplifier 12A can be applied to an amplifier circuit different from the differential amplifier circuit.

[0081] (Second embodiment)

[0082] Fig.12 1 is a graph for explaining the relationship between the center position of the rectangular bump in the second direction and the temperature drop in the power amplifier device of the second embodiment. As shown in the fourth embodiment, Fig.12 The graph shown shows a temperature drop ΔT when the position of the rectangular bump 15 in the second direction Dy is changed in a configuration in which the arrangement directions of the plurality of transistors Tr are different in the first amplifier 11 and the second amplifier 12A. Fig.12 The horizontal axis of the graph shown shows the center position of the rectangular bump 15 in the second direction Dy, with the position of the center C1 of the first reference potential bump 21 in the second direction Dy as a reference.

[0083] As in the first embodiment, Fig.12 As shown, the temperature drop ΔT is maximum when the center position of the second direction Dy of the rectangular bump 15 is 0 μm, that is, the center position of the second direction Dy of the rectangular bump 15 is consistent with the center C1 of the second direction Dy of the first reference potential bump 21. As the center position of the second direction Dy shifts to the + direction and the - direction, the temperature drop ΔT becomes smaller.

[0084] (Fifth Embodiment)

[0085] Fig.13It is a block diagram showing the structure of a power amplifier device according to a fifth embodiment. Fig.14 The fifth embodiment is a top view of a power amplifier device according to the fifth embodiment. In the fifth embodiment, a first amplifier 11 and a second amplifier 12 respectively output a first output signal RFout1 and a second output signal RFout2 as outputs of a power amplifier device 100D, which are different from the first to fourth embodiments.

[0086] like Fig.13 As shown, the semiconductor element 101D included in the power amplifier device 100D includes a first driver stage amplifier 10A and a second driver stage amplifier 10B in addition to the first amplifier 11 , the second amplifier 12 and the rectangular bump 15 .

[0087] The first driver stage amplifier 10A amplifies the input first high frequency input signal RFin1-d and outputs a first high frequency signal RFin1. The first amplifier 11 amplifies the first high frequency signal RFin1 and outputs a first output signal RFout1.

[0088] The second driver stage amplifier 10B amplifies the input second high frequency input signal RFin2-d and outputs a second high frequency signal RFin2. The second amplifier 12 amplifies the second high frequency signal RFin2 and outputs a second output signal RFout2.

[0089] The second high-frequency input signal RFin2-d input to the second driver-stage amplifier 10B is another signal independent of the first high-frequency input signal RFin1-d. In addition, the second high-frequency signal RFin2 input to the second amplifier 12 is another signal independent of the first high-frequency signal RFin1. The power amplifier device 100D outputs the first output signal RFout1 and the second output signal RFout2 as independent output signals.

[0090] like Fig.14 As shown, a first driver stage amplifier 10A, a second driver stage amplifier 10B, and terminals 16A and 16B are provided on a semiconductor substrate 1. Terminals 17A and 17B are provided on a module substrate 105.

[0091] The first high frequency input signal RFin1-d is input to the terminal 16A. The terminal 16A is connected to the first driver stage amplifier 10A, and the first driver stage amplifier 10A is connected to the input terminal 22 of the first amplifier 11. The output terminal 23 of the first amplifier 11 is connected to the terminal 17A. The terminal 17A outputs the first output signal RFout1.

[0092] The second high frequency input signal RFin2-d is input to the terminal 16B. The terminal 16B is connected to the second driver stage amplifier 10B, and the second driver stage amplifier 10B is connected to the input terminal 32 of the second amplifier 12. The output terminal 33 of the second amplifier 12 is connected to the terminal 17B. The terminal 17B outputs the second output signal RFout2.

[0093] In this embodiment, the first amplifier 11 and the second amplifier 12 can operate independently. Even when the first amplifier 11 and the second amplifier 12 operate simultaneously, the power amplifier device 100D and the semiconductor element 101D can improve heat dissipation characteristics because the rectangular bumps 15 are provided.

[0094] The power amplifier device 100D and the semiconductor element 101D according to the fifth embodiment can be appropriately combined with the structures of the second to fourth embodiments described above.

[0095] The above-described embodiments are intended to facilitate understanding of the present invention and are not intended to limit the present invention. The present invention can be modified and improved without departing from the gist thereof, and equivalents thereof are also included in the present invention.

Claims

1. A semiconductor element having: Semiconductor substrates; A first amplifier and a second amplifier are disposed on the semiconductor substrate, the first amplifier and the second amplifier are adjacent to each other in a first direction; A first reference potential bump is provided on the main surface of the semiconductor substrate and connects the first amplifier and a reference potential; A second reference potential bump is provided on the main surface of the semiconductor substrate, the second reference potential bump is adjacent to the first reference potential bump in the first direction, and is connected to the second amplifier and a reference potential; as well as a rectangular bump disposed on the main surface of the semiconductor substrate, wherein when viewed from a direction perpendicular to the main surface, the rectangular bump is disposed between the first reference potential bump and the second reference potential bump, and a second width in a second direction orthogonal to the first direction is greater than a first width in the first direction, The second width of the rectangular bump is greater than the width of at least one of the first reference potential bump and the second reference potential bump in the second direction. The rectangular bump is separated from the first amplifier and the second amplifier and is disposed between the first amplifier and the second amplifier so as to dissipate or conduct heat generated by the semiconductor element to the outside.

2. The semiconductor element according to claim 1, wherein The rectangular bump intersects an imaginary line connecting a center of the width of the first reference potential bump in the second direction and a center of the width of the second reference potential bump in the second direction.

3. The semiconductor element according to claim 1, wherein The height of the rectangular bump in the direction perpendicular to the main surface of the semiconductor substrate is equal to the height of the first reference potential bump and the second reference potential bump in the direction perpendicular to the main surface of the semiconductor substrate.

4. The semiconductor element according to claim 2, wherein: The height of the rectangular bump in the direction perpendicular to the main surface of the semiconductor substrate is equal to the height of the first reference potential bump and the second reference potential bump in the direction perpendicular to the main surface of the semiconductor substrate.

5. The semiconductor device according to claim 1, wherein The first amplifier and the second amplifier each include a plurality of transistors arranged along the first direction, The first reference potential bump and the second reference potential bump are respectively arranged in regions overlapping with the plurality of transistors, and have a width in the first direction greater than a width in the second direction.

6. The semiconductor element according to claim 2, wherein: The first amplifier and the second amplifier each include a plurality of transistors arranged along the first direction, The first reference potential bump and the second reference potential bump are respectively arranged in regions overlapping with the plurality of transistors, and have a width in the first direction greater than a width in the second direction.

7. The semiconductor element according to claim 3, wherein: The first amplifier and the second amplifier each include a plurality of transistors arranged along the first direction, The first reference potential bump and the second reference potential bump are respectively arranged in regions overlapping with the plurality of transistors, and have a width in the first direction greater than a width in the second direction.

8. The semiconductor device according to claim 1, wherein The first amplifier and the second amplifier each include a plurality of transistors arranged along the second direction, The first reference potential bump and the second reference potential bump are respectively arranged in regions overlapping with the plurality of transistors, and have a width in the second direction greater than a width in the first direction.

9. The semiconductor device according to claim 2, wherein: The first amplifier and the second amplifier each include a plurality of transistors arranged along the second direction, The first reference potential bump and the second reference potential bump are respectively arranged in regions overlapping with the plurality of transistors, and have a width in the second direction greater than a width in the first direction.

10. The semiconductor element according to claim 3, wherein The first amplifier and the second amplifier each include a plurality of transistors arranged along the second direction, The first reference potential bump and the second reference potential bump are respectively arranged in regions overlapping with the plurality of transistors, and have a width in the second direction greater than a width in the first direction.

11. The semiconductor device according to claim 1, wherein The first amplifier includes a plurality of transistors arranged along the first direction, The second amplifier includes a plurality of transistors arranged along the second direction, The first reference potential bump is arranged in a region overlapping with a plurality of transistors arranged along the first direction, and has a width in the first direction greater than a width in the second direction. The second reference potential bump is arranged in a region overlapping with a plurality of transistors arranged along the second direction, and has a width in the second direction greater than a width in the first direction.

12. The semiconductor device according to claim 2, wherein: The first amplifier includes a plurality of transistors arranged along the first direction, The second amplifier includes a plurality of transistors arranged along the second direction, The first reference potential bump is arranged in a region overlapping with a plurality of transistors arranged along the first direction, and has a width in the first direction greater than a width in the second direction. The second reference potential bump is arranged in a region overlapping with a plurality of transistors arranged along the second direction, and has a width in the second direction greater than a width in the first direction.

13. The semiconductor device according to claim 3, wherein The first amplifier includes a plurality of transistors arranged along the first direction, The second amplifier includes a plurality of transistors arranged along the second direction, The first reference potential bump is arranged in a region overlapping with a plurality of transistors arranged along the first direction, and has a width in the first direction greater than a width in the second direction. The second reference potential bump is arranged in a region overlapping with a plurality of transistors arranged along the second direction, and has a width in the second direction greater than a width in the first direction.

14. The semiconductor element according to any one of claims 1 to 13, wherein have: A recessed portion is provided on the main surface of the semiconductor substrate; as well as a metal layer disposed in the recessed portion, The rectangular convex block is arranged to overlap with the metal layer.

15. The semiconductor element according to any one of claims 5 to 13, wherein: A plurality of the transistors are heterojunction bipolar transistors.

16. A power amplifier device, comprising: The semiconductor element according to any one of claims 1 to 15; and a module substrate, which is opposite to the semiconductor element and is electrically connected to the semiconductor element; The module substrate comprises: an insulating substrate having a first surface facing the main surface of the semiconductor substrate and a second surface opposite to the first surface; and A plurality of first wirings are provided on the first surface of the insulating substrate, are connected to the first reference potential bump, the second reference potential bump, and the rectangular bump, respectively, and are separated from each other.

17. The power amplifying device according to claim 16, wherein: have: a plurality of second wirings, which are provided in an inner layer of the insulating substrate, are stacked with the plurality of first wirings via a dielectric layer, and are separated from each other; as well as a common third wiring, which is stacked on the plurality of second wirings via a dielectric layer and is provided at a position farther from the first surface than the plurality of second wirings; The rectangular bump is electrically connected to the first reference potential bump and the second reference potential bump via the common third wiring.

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