Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate and a fin protruding from the substrate, the substrate comprising a first region and a second region; forming a first work function layer on the fins of the first region and the second region; forming a second work function layer on the first work function layer; forming a third work function layer on the second work function layer; forming a protective layer on the third work function layer; forming a photoresist coating on the substrate of the first region and the second region, the photoresist coating covering the protective layer; removing the photoresist coating of the first region to expose the protective layer of the first region; removing the exposed protective layer; removing the third work function layer of the first region. The present invention helps to protect the second work function layer of the first region and prevent the second work function layer of the first region from being etched during the process of removing the photoresist coating of the first region.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] The miniaturization of transistor size is a trend in the development of semiconductor structures. However, the continuous reduction in the size of transistors also brings about a series of technical problems. For example, the gate dielectric layer is too thin, resulting in a high leakage current between the gate and the channel, and the size reduction causes a significant increase in the resistance of the polysilicon gate.

[0003] Researchers have found that transistors made of high-k metal gate (HKMG) transistors can effectively solve the above problems by replacing silicon oxide or silicon oxynitride materials with high-k gate dielectric layers and replacing traditional polysilicon gate materials with metal gates. On the one hand, the high-k gate dielectric layer can reduce the tunneling current between the gate and the channel; on the other hand, the resistivity of the metal gate is extremely small, which can effectively prevent the increase of gate resistance.

[0004] However, the performance of semiconductor structures in the prior art still needs to be improved. Summary of the invention

[0005] The problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can avoid damaging the second work function layer in the first region, thereby improving the electrical performance of the semiconductor structure.

[0006] To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate and a fin protruding from the substrate, the substrate comprising a first region and a second region; forming a first work function layer on the fins of the first region and the second region; forming a second work function layer on the first work function layer; forming a third work function layer on the second work function layer; forming a protective layer on the top and sidewalls of the third work function layer; forming a photoresist coating on the substrate of the first region and the second region, the photoresist coating covering the protective layer; removing the photoresist coating in the first region to expose the protective layer in the first region; removing the exposed protective layer; and removing the third work function layer in the first region.

[0007] Optionally, the material of the protective layer is amorphous silicon, polycrystalline silicon, silicon germanium or silicon phosphide.

[0008] Optionally, a dry etching process is used to remove the photoresist coating in the first area.

[0009] Optionally, after forming the photoresist coating and before removing the photoresist coating in the first area, the method further includes: forming an oxide layer on top of the photoresist coating.

[0010] Optionally, after forming the oxide layer and before removing the photoresist coating in the first area, the method further includes: forming a mask layer on top of the oxide layer; patterning the mask layer to expose the surface of the oxide layer in the first area; and removing the oxide layer in the first area.

[0011] Optionally, a wet etching process is used to remove the exposed protective layer.

[0012] Optionally, in the wet etching process, ammonia water is used as the etching solution.

[0013] Optionally, in the process of providing the substrate and the fins, an isolation layer is provided between adjacent fins, and the isolation layer covers the top of the substrate and a portion of the sidewalls of the fins.

[0014] Optionally, before forming the first work function, the method further includes: forming an interface layer covering the top and side wall surfaces of the fin; and forming a high-k gate dielectric layer covering the top and side wall surfaces of the interface layer.

[0015] Correspondingly, the present invention also provides a semiconductor structure, comprising: a substrate, the substrate comprising a first region and a second region; a first work function layer, the first work function layer being located on the top and side walls of the fins in the first region and the second region; a second work function layer, the second work function layer being located on the first work function layer in the first region and the second region; a third work function layer, the third work function layer being located on the second work function layer in the second region; a protective layer, the protective layer being located on the third work function layer; and a photoresist coating, the photoresist coating being located on the substrate in the second region, the photoresist coating covering the protective layer.

[0016] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0017] After forming the third work function layer on the second work function layer, forming a protective layer on the third work function layer. In the process of removing the photoresist coating of the first region, the protective layer of the first region is exposed. The protective layer has high etching resistance and can protect the third work function layer of the first region, and further can protect the second work function layer of the first region, so as to avoid the second work function layer of the first region from being damaged, thereby ensuring the quality of the second work function layer of the first region, so as to improve the electrical performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figures 1 to 3 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0019] Figures 4 to 16It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0020] Now we analyze it in combination with a method for forming a semiconductor structure. Figures 1 to 3 The schematic diagram is a schematic diagram of the structure corresponding to each step in the method for forming a semiconductor structure. The process steps for forming a semiconductor structure mainly include: Figure 1 , providing a substrate 10 and a fin 20 protruding from the substrate 10, the substrate 10 including a first region i and a second region ii; forming an interface layer 31 on the top and sidewalls of the fin 20; forming a high-k gate dielectric layer 32 on the interface layer 31; forming a first work function layer 41 on the high-k gate dielectric layer 32; forming a second work function layer 42 on the first work function layer 41; forming a third work function layer 43 on the second work function layer 42; referring to Figure 2 , forming a photoresist coating 61 on the substrate 10, wherein the photoresist coating 61 covers the third work function layer 43; Figure 3 , remove the photoresist coating 61 in the first region i to expose the third work function layer 43 in the first region i.

[0021] like Figure 3 As shown, in the process of removing the photoresist coating 61 of the first region i, the third work function layer 43 of the first region i is easily etched, exposing the second work function layer 42 of the first region i. The exposed second work function layer 42 of the first region i is also easily etched, resulting in damage to the second work function layer 42 of the first region i, so that the formation quality of the second work function layer 42 of the first region i is reduced, thereby affecting the electrical performance of the semiconductor structure.

[0022] The inventors have studied the method for forming the above-mentioned semiconductor structure. Through creative work, the inventors noticed that by forming a protective layer on the third work function layer, in the process of removing the photoresist coating in the first area, the high etching resistance of the protective layer can be utilized to protect the third work function layer and the second work function layer in the first area.

[0023] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0024] refer to Figure 4 , providing a substrate 100 and a fin 200 protruding from the substrate 100 , wherein the substrate 100 includes a first region I and a second region II.

[0025] The material of the substrate 100 is silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate 100 can also be a silicon on insulator substrate or a germanium on insulator substrate. In this embodiment, the material of the substrate 100 is silicon.

[0026] In this embodiment, the substrate 100 includes a first region I and a second region II. The substrate 100 in the first region I is suitable for forming a first transistor. The substrate 100 in the second region II is suitable for forming a second transistor, and the type of the second transistor is opposite to that of the first transistor.

[0027] In this embodiment, the first transistor is an NMOS transistor, and the second transistor is a PMOS transistor. In other embodiments, the first transistor is a PMOS transistor, and the second transistor is an NMOS transistor.

[0028] The material of the fin 200 includes silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. In this embodiment, the material of the fin 200 is also silicon.

[0029] In this embodiment, the sidewall of the fin 200 is perpendicular to the surface of the substrate 100, that is, the top size of the fin 200 is equal to the bottom size. In other embodiments, the top size of the fin may be smaller than the bottom size.

[0030] In this embodiment, an isolation layer 210 is disposed between adjacent fins 200 , and the isolation layer 210 covers the top of the substrate 100 and a portion of the sidewall surface of the fin 200 .

[0031] The material of the isolation layer 210 is silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the material of the isolation layer 210 is silicon oxide.

[0032] refer to Figure 5 , a first work function layer 410 is formed on the top and sidewalls of the fin 200 in the first region I and the second region II.

[0033] In this embodiment, before forming the first work function layer, the process further includes: forming an interface layer 310 covering the top and sidewall surfaces of the fin 200; and forming a high-k gate dielectric layer 320 covering the top and sidewall surfaces of the interface layer 310. The first work function layer 410 covers the top and sidewall surfaces of the high-k gate dielectric layer 320.

[0034] The interface layer 310 is beneficial to improving the bonding ability between the high-k gate dielectric layer 320 and the fin 200 , and improving the quality of the formed high-k gate dielectric layer 320 .

[0035] In this embodiment, the material of the interface layer 310 is silicon oxide. In other embodiments, the material of the interface layer may also be germanium oxide.

[0036] In this embodiment, the material of the high-k gate dielectric layer 320 is a high-k dielectric material (with a dielectric constant greater than 3.9). In this embodiment, the material of the high-k gate dielectric layer 320 is HfO2; in other embodiments, the material of the high-k gate dielectric layer may also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or ZrO2.

[0037] In this embodiment, the high-k gate dielectric layer 320 is formed by an atomic layer deposition process. The high-k gate dielectric layer 320 formed by the atomic layer deposition process has a uniform thickness and has good step coverage at the bottom corner of the fin 200 .

[0038] In this embodiment, the material of the first work function layer 410 is TiN. In other embodiments, the material of the first work function layer may also be TaN, TiSiN or TaSiN.

[0039] In this embodiment, the first work function layer 410 is formed by an atomic layer deposition process. In other embodiments, a chemical vapor deposition process may also be used.

[0040] refer to Figure 6 , a second work function layer 420 is formed on the top and sidewalls of the first work function layer 410 .

[0041] In this embodiment, the material of the second work function layer 420 is TaN. In other embodiments, the material of the second work function layer may also be TaSiN.

[0042] In this embodiment, the second work function layer 420 is formed by an atomic layer deposition process. In other embodiments, a chemical vapor deposition process may also be used.

[0043] refer to Figure 7 , a third work function layer 430 is formed on the second work function layer 420 .

[0044] In this embodiment, the material of the third work function layer 430 is TiN. In other embodiments, the material of the third work function layer may also be TiN, TiSiN or TaSiN.

[0045] In this embodiment, the third work function layer 430 is formed by an atomic layer deposition process. In other embodiments, a chemical vapor deposition process may also be used.

[0046] refer to Figure 8, forming a protective layer 500 on the third work function layer 430 .

[0047] In this embodiment, the material of the protective layer 500 is amorphous silicon. In other embodiments, the material of the protective layer may also be polysilicon, silicon germanium or silicon phosphide.

[0048] In this embodiment, an atomic layer deposition process is used to form the protective layer 500. In other embodiments, a chemical vapor deposition process may also be used.

[0049] The protective layer 500 is located on the third work function layer 430 in the first region I and the second region II. Subsequently, a photoresist coating covering the protective layer 500 is formed on the substrate 100, and the photoresist coating in the first region I is removed. In the process of removing the photoresist coating 610 in the first region I, the protective layer 500 can protect the third work function layer 430 in the first region I, preventing the second work function layer 420 from being exposed to the etching environment, thereby preventing the second work function layer 420 in the first region I from being etched.

[0050] If the thickness of the protective layer 500 is too thick, the subsequent process of removing the protective layer 500 will take too long. If the thickness of the protective layer 500 is too thin, the protective effect of the protective layer 500 will be affected. In this embodiment, the thickness of the protective layer 500 is

[0051] refer to Fig. 9 , a photoresist coating 610 is formed on the substrate 100 in the first region I and the second region II, and the photoresist coating 610 covers the protective layer 500 .

[0052] In this embodiment, the photoresist coating 610 is located on the isolation layer 210 in the first region I and the second region II.

[0053] In this embodiment, a spin coating process is used to form the photoresist coating 610. In other embodiments, a chemical vapor deposition process or a physical vapor deposition process may be used to form the photoresist coating.

[0054] In this embodiment, after the photoresist coating 610 is formed, the process further includes: forming an oxide layer 620 on the top of the photoresist coating 610 .

[0055] In this embodiment, an atomic layer deposition process is used to form the oxide layer 620. In other embodiments, a chemical vapor deposition process or a physical vapor deposition process may also be used to form the oxide layer 620.

[0056] The photoresist coating 610 in the first region I is subsequently removed, and the oxide layer 620 can protect the photoresist coating 610 in the second region II, thereby preventing the photoresist coating 610 in the second region II from being etched.

[0057] refer to Figures 10 to 12 , remove the photoresist coating 610 in the first region I to expose the protection layer 500 in the first region I.

[0058] Before removing the photoresist coating 610 in the first region I, the method further includes: Fig.10 As shown, a mask layer 630 is formed on top of the oxide layer 620; Fig.11 As shown, the mask layer 630 is patterned to expose the surface of the oxide layer 620 in the first region I; Fig.12 As shown, the oxide layer 620 in the first region I is removed.

[0059] In this embodiment, a dry etching process is used to remove the photoresist coating 610 in the first region I.

[0060] In the dry etching process, high-energy plasma is used to bombard the photoresist coating 610 in the first region I. The protective layer 500 can play a buffering role to reduce the bombardment speed of plasma. The protective layer 500 protects the third work function layer 430 in the first region I, ensuring that the third work function layer 430 covers the entire second work function layer 420, preventing the second work function layer 420 in the first region I from being etched, thereby improving the quality of the second work function layer 420 in the first region I.

[0061] refer to Fig.13 , remove the exposed protection layer 500.

[0062] In this embodiment, a wet etching process is used to remove the protection layer 500 in the first region I.

[0063] In this embodiment, in the wet etching process, ammonia water is used as an etching solution, the volume ratio of NH4OH to H2O in the ammonia water is 1:5, and the temperature of the ammonia water is 25° C.-80° C. In other embodiments, the etching solution can also be an alkaline mixed solution such as TMAH (Tetramethylammonium hydroxide), KOH or NaOH.

[0064] The ammonia water has a high etching selectivity ratio for the protective layer 500 and the second work function layer 420 and the third work function layer 430 in the first region I. Therefore, in the wet etching process, the second work function layer 420 and the third work function layer 430 in the first region I are not easily etched.

[0065] Ammonia water has a high etching selectivity ratio to the protection layer 500 and the third work function layer 430 in the first region I. Therefore, in the wet etching process, the third work function layer 430 in the first region I is not easily etched.

[0066] In addition, compared with the third work function layer 430, the etching rate of the second work function layer 420 in ammonia water is lower. Therefore, even if part of the third work function layer 430 in the first region I is etched and part of the second work function layer 420 is exposed, it is still difficult for ammonia water to damage the exposed second work function layer 420.

[0067] refer to Fig.14 , remove the third work function layer 430 in the first region I.

[0068] In this embodiment, a wet etching process is used to remove the third work function layer 430 of the first region I, and the etching solution includes: HCl, H2O2 and H2O, wherein the volume ratio of HCl, H2O2 and H2O is 1:1:5, and the etching solution temperature is 25°C-80°C. In other embodiments, the etching solution may also include: NH4OH, H2O2 and H2O, wherein the volume ratio of NH4OH, H2O2 and H2O is 1:1:5.

[0069] The third work function layer 430 in the first region I is removed, thereby ensuring that the work function value and threshold voltage of the semiconductor structure in the first region I meet the requirements.

[0070] refer to Fig.15 , remove the photoresist coating 610 (reference Fig.14 ).

[0071] In this embodiment, before removing the photoresist coating 610 in the second region II, the process further includes: removing the mask layer 630 in the second region II (refer to Fig.14 ) and oxide layer 620 (reference Fig.14 ).

[0072] In this embodiment, a dry etching process is used to remove the photoresist coating 610 in the second region II. In other embodiments, a wet etching process may also be used.

[0073] refer to Fig.16, remove the protective layer 500 of the second region II (refer to Fig.15 ).

[0074] In this embodiment, a wet etching process is used to remove the protective layer 500 in the second region II. In the wet etching process, ammonia water is used as an etching solution, the volume ratio of NH4OH to H2O in the ammonia water is 1:5, and the temperature of the ammonia water is 25° C.-80° C. In other embodiments, the etching solution can also be an alkaline mixed solution such as TMAH, KOH or NaOH.

[0075] In this embodiment, in the first region I, the first work function layer 410 and the second work function layer 420 are used as work function layers. In the second region II, the first work function layer 410, the second work function layer 420 and the third work function layer 430 are used as work function layers. Therefore, the thickness of the work function layer in the first region I is not equal to the thickness of the work function layer in the second region II, so that the threshold voltage difference between the first region I and the second region II meets the process requirements.

[0076] In other embodiments, after removing the protective layer in the second region, the method further includes: forming a fourth work function layer on the second work function layer in the first region; forming a fifth work function layer on the third work function layer in the second region, wherein the material of the fifth work function layer is different from that of the fourth work function layer. For example, the material of the fourth work function layer is TiAlC, and the material of the fifth work function layer is TiN.

[0077] Reference Fig.14 The present invention also provides a semiconductor structure obtained by the above-mentioned formation method, the semiconductor structure comprising: a substrate 100, the substrate 100 comprising a first region I and a second region II; a first work function layer 410, the first work function layer 410 being located on the fin 200 in the first region I and the second region II; a second work function layer 420, the second work function layer 420 being located on the first work function layer 410 in the first region I and the second region II; a third work function layer 430, the third work function layer 430 being located on the second work function layer 420 in the second region II; a protective layer 500, the protective layer 500 being located on the third work function layer 430; a photoresist coating 610, the photoresist coating 610 being located on the substrate 100 in the second region II, the photoresist coating 610 covering the protective layer 500.

[0078] In this embodiment, the semiconductor structure further includes an isolation layer 210, the isolation layer 210 is located between adjacent fins 200, and the isolation layer 210 covers the top of the substrate 100 and part of the sidewall surface of the fin 200. The photoresist coating 610 is located on the isolation layer 210 in the second region II.

[0079] In this embodiment, the semiconductor structure further includes: an interface layer 310, the interface layer 310 covers the surface of the fin 200 in the first region I and the second region II; a high-k gate dielectric layer 320, the high-k gate dielectric layer 320 covers the top and sidewall surfaces of the interface layer 310. The first work function layer 410 covers the top and sidewall surfaces of the high-k gate dielectric layer 320 in the first region I and the second region II.

[0080] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate and a fin protruding from the substrate, wherein the substrate includes a first area and a second area; forming a first work function layer on the fins in the first region and the second region; forming a second work function layer on the first work function layer; forming a third work function layer on the second work function layer; forming a protective layer on the third work function layer; forming a photoresist coating on the substrate of the first region and the second region, wherein the photoresist coating covers the protective layer; removing the photoresist coating in the first area to expose the protective layer in the first area; removing the exposed protective layer; removing the third work function layer in the first region; removing the photoresist coating in the second area; removing the protective layer from the second area; forming a fourth work function layer on the second work function layer in the first region, and forming a fifth work function layer on the third work function layer in the second region; The protective layer is used to protect the third work function layer of the first region during the process of removing the photoresist coating, thereby protecting the second work function layer of the first region and preventing the second work function layer of the first region from being damaged; After forming the photoresist coating and before removing the photoresist coating in the first area, the method further includes: forming an oxide layer on top of the photoresist coating.

2. The method for forming a semiconductor structure according to claim 1, wherein: The material of the protective layer is amorphous silicon, polycrystalline silicon, silicon germanium or silicon phosphide.

3. The method for forming a semiconductor structure according to claim 1, wherein: The photoresist coating in the first area is removed by a dry etching process.

4. The method for forming a semiconductor structure according to claim 1, wherein: After forming the oxide layer and before removing the photoresist coating in the first area, the method further includes: forming a mask layer on top of the oxide layer; patterning the mask layer to expose the surface of the oxide layer in the first area; and removing the oxide layer in the first area.

5. The method for forming a semiconductor structure according to claim 1, wherein: The exposed protection layer is removed by a wet etching process.

6. The method for forming a semiconductor structure according to claim 5, wherein: In the wet etching process, ammonia water is used as etching solution.

7. The method for forming a semiconductor structure according to claim 1, wherein: In the process of providing the substrate and the fins, an isolation layer is provided between adjacent fins, and the isolation layer covers the top of the substrate and a portion of the sidewalls of the fins.

8. The method for forming a semiconductor structure according to claim 7, wherein: Before forming the first work function, the method further includes: forming an interface layer covering the top and side wall surfaces of the fin; and forming a high-k gate dielectric layer covering the top and side wall surfaces of the interface layer.

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