A sub-monolayer quantum dot vertical cavity laser and its manufacturing method

Abstract

The present invention provides a sub-monolayer quantum dot vertical cavity laser and a manufacturing method thereof, which can realize the advantages of strained quantum wells without introducing additional non-radiative recombination losses, improve the laser quantum efficiency and temperature stability and other aspects of performance; solve the shortcomings of quantum well VCSEL laser quantum efficiency, temperature stability and other aspects in the prior art. The preparation method provided by the present invention adopts a special sub-monolayer quantum dot preparation technology. Compared with the conventional quantum well active area, the sub-monolayer quantum dots in the present invention have three-dimensional quantum confinement, and the material luminescence performance and photoelectric properties are greatly improved. At the same time, compared with conventional quantum dots, the sub-monolayer quantum dots in the present invention have the advantages of high uniformity of quantum wells. The present invention improves material quality through in-situ heat treatment, thereby realizing a vertical cavity laser chip or VCSEL chip with high quantum efficiency.

Description

Technical Field

[0001] The invention relates to the technical field of lasers, and in particular to a sub-monolayer quantum dot vertical cavity laser and a manufacturing method thereof. Background Art

[0002] Vertical cavity lasers (VCSELs) play an increasingly important role in applications such as optical communications and 3D sensing due to their advantages such as low current threshold, superior beam characteristics, and high packaging density. Vertical cavity lasers are usually composed of two upper and lower Bragg reflectors of different doping types and an active region. The active region of a vertical cavity laser usually includes multiple strained quantum wells formed by materials such as InGaAs / (Al)GaAs and InAlGaAs / (Al)GaAs. Strained quantum wells usually play a major role in improving device efficiency and speed while reducing current threshold and line width. However, defects will be generated during the stress release process of multi-layer strained quantum well materials, introducing additional non-radiative recombination losses, thereby reducing device performance and limiting the improvement of inventive performance such as laser efficiency. On the other hand, quantum wells are only bound in one dimension, and the electronic band structure shows a step state density. As a result, quantum well lasers often have disadvantages such as poor temperature stability and hole burning under high injection. Summary of the invention

[0003] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a sub-monolayer quantum dot vertical cavity laser and a manufacturing method thereof, so as to solve the technical problems existing in the prior art.

[0004] To achieve the above-mentioned and other related purposes, the present invention provides a sub-monolayer quantum dot vertical cavity laser, which is applied to a vertical cavity laser VCSEL chip; comprising:

[0005] substrate;

[0006] epitaxially depositing a buffer layer, an N-type DBR layer, an N-type waveguide confinement layer, a sub-monolayer quantum dot, a P-type waveguide confinement layer, an oxide layer, a P-type DBR layer and a P-type ohmic contact layer on the substrate in sequence to form an epitaxial layer structure;

[0007] Performing photolithography and etching on the epitaxial layer structure to form a chip mesa;

[0008] It also includes two metal electrodes; one of the metal electrodes is deposited on the back side of the substrate, and the other metal electrode is deposited on the P-type ohmic contact layer on the chip table; wherein the back side of the substrate is the side of the substrate where no epitaxial growth is performed.

[0009] Optionally, the sub-monolayer quantum dots form a sub-monolayer quantum dot source region on the substrate; wherein the sub-monolayer quantum dot source region comprises: a GaAs barrier layer, an InGaAs sub-monolayer quantum dot and an AlGaAs waveguide confinement layer potential well;

[0010] The specific process of forming the sub-monolayer quantum dot source region includes:

[0011] Growing an N-type AlGaAs waveguide confinement layer on the surface of the N-type DBR layer;

[0012] Growing a first GaAs barrier layer on the surface of the N-type AlGaAs waveguide confinement layer, and lowering the growth temperature to a preset temperature;

[0013] Growing the InGaAs sub-monolayer quantum dots on the surface of the first GaAs barrier layer; and continuously depositing one or more atomic layers of GaAs after the growth;

[0014] Two GaAs barrier layers with different temperatures are sequentially grown to cover the InGaAs sub-monolayer quantum dots; wherein the growth temperature of the first-grown GaAs barrier layer is lower than the later-grown GaAs barrier layer.

[0015] Optionally, growing the InGaAs sub-monolayer quantum dots on the surface of the first GaAs barrier layer includes: growing a plurality of cycles of alternate epitaxial deposition of InAs and GaAs, and epitaxially growing less than a monoatomic layer of InAs material on the GaAs surface.

[0016] Optionally, the overall structural thickness of the active region of the InGaAs sub-monolayer quantum dots is λ, wherein λ is the emission center wavelength of the vertical cavity laser chip.

[0017] Optionally, the structure of the InGaAs sub-monolayer quantum dots may be repeated in one or more cycles.

[0018] Optionally, the N-type DBR layer and the P-type DBR layer each include one or more periods of heterojunction;

[0019] The heterojunction includes two semiconductor layers with different refractive indices; the refractive index of one semiconductor layer is higher than that of the other semiconductor layer.

[0020] Optionally, the electrode deposited on the P-type ohmic contact layer on the chip mesa is a ring-shaped metal electrode.

[0021] Optionally, the substrate is an N-type doped single crystal.

[0022] The present invention also provides a method for manufacturing a sub-monolayer quantum dot vertical cavity laser, comprising the following steps:

[0023] Epitaxially depositing a buffer layer, an N-type DBR layer, an N-type waveguide confinement layer, a sub-monolayer quantum dot, a P-type waveguide confinement layer, an oxide layer, a P-type DBR layer and a P-type ohmic contact layer on a preset substrate in sequence to form an epitaxial layer structure;

[0024] Photolithography and etching of the epitaxial layer structure to form a chip mesa;

[0025] It also includes two metal electrodes; one of which is deposited on the back side of the substrate, and the other is deposited on the P-type ohmic contact layer on the chip table; wherein the back side of the substrate is the side of the substrate where no epitaxial growth is performed;

[0026] Wherein, the sub-monolayer quantum dots form a sub-monolayer quantum dot source region on the substrate; the sub-monolayer quantum dot source region includes: a GaAs barrier layer, an InGaAs sub-monolayer quantum dot and an AlGaAs waveguide confinement layer potential well; the specific process of forming the sub-monolayer quantum dot source region includes:

[0027] Growing an N-type AlGaAs waveguide confinement layer on the surface of the N-type DBR layer;

[0028] Growing a first GaAs barrier layer on the surface of the N-type AlGaAs waveguide confinement layer, and lowering the growth temperature to a preset temperature;

[0029] Growing the InGaAs sub-monolayer quantum dots on the surface of the first GaAs barrier layer; and continuously depositing one or more atomic layers of GaAs after the growth;

[0030] Two GaAs barrier layers with different temperatures are sequentially grown to cover the InGaAs sub-monolayer quantum dots; wherein the growth temperature of the first-grown GaAs barrier layer is lower than the later-grown GaAs barrier layer.

[0031] Optionally, growing the InGaAs sub-monolayer quantum dots on the surface of the first GaAs barrier layer includes: growing a plurality of cycles of alternate epitaxial deposition of InAs and GaAs, and epitaxially growing less than a monoatomic layer of InAs material on the GaAs surface.

[0032] As described above, the present invention provides a sub-monolayer quantum dot vertical cavity laser and a method for manufacturing the same, which have the following beneficial effects: the present invention can realize the advantages of strained quantum wells without introducing additional non-radiative recombination losses, and improve the laser quantum efficiency and temperature stability and other aspects of performance; it solves the deficiencies in the quantum well VCSEL laser quantum efficiency, temperature stability and other aspects of performance in the prior art. The preparation method provided by the present invention adopts a special sub-monolayer quantum dot preparation technology. Compared with the conventional quantum well active area, the sub-monolayer quantum dots in the present invention have three-dimensional quantum confinement, and the luminescence performance and photoelectric properties of the material are greatly improved. At the same time, compared with conventional quantum dots, the sub-monolayer quantum dots in the present invention have the advantages of high uniformity of quantum wells. The present invention improves material quality through in-situ heat treatment, thereby realizing a vertical cavity laser chip or VCSEL chip with high quantum efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Schematic diagram of the structure of a sub-monolayer quantum dot vertical cavity laser;

[0034] Figure 2 It is a schematic diagram of the structure of the sub-monolayer quantum dot source region;

[0035] Figure 3 Schematic diagram of spectrum comparison between sub-monolayer quantum dots and quantum wells in the present invention. DETAILED DESCRIPTION

[0036] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0037] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0038] See also Figures 1 to 3 The present invention provides a sub-monolayer quantum dot vertical cavity laser, which is applied to a vertical cavity laser VCSEL chip; comprising:

[0039] Substrate 2: As an example, substrate 2 may be a highly N-type doped (100) oriented single crystal, wherein 100 represents the crystal plane orientation of the wafer.

[0040] A buffer layer, an N-type DBR layer 3, an N-type waveguide limiting layer 41, a sub-monolayer quantum dot 43, a P-type waveguide limiting layer 44, an oxide layer 5, a P-type DBR layer 6 and a P-type ohmic contact layer 7 are sequentially epitaxially deposited on the substrate 2 to form an epitaxial layer structure;

[0041] Performing photolithography and etching on the epitaxial layer structure to form a chip mesa;

[0042] There are also two metal electrodes; one of which is deposited on the back side of the substrate 2, namely the back side metal electrode 1. The other metal electrode is deposited on the P-type ohmic contact layer of the chip table; wherein the back side of the substrate 2 is the side of the substrate 2 that is not subjected to epitaxial growth. As an example, the electrode deposited on the P-type ohmic contact layer 7 of the chip table is a ring-shaped metal electrode 8.

[0043] The present invention can realize the advantages of strained quantum wells without introducing additional non-radiative recombination losses, thereby improving the quantum efficiency and temperature stability of the laser and solving the problems in the quantum efficiency and temperature stability of quantum well VCSEL lasers in the prior art.

[0044] According to the above records, the sub-monolayer quantum dots 43 form a sub-monolayer quantum dot source region on the substrate 2; wherein the sub-monolayer quantum dot source region includes: a GaAs barrier layer 42, an InGaAs sub-monolayer quantum dot 43 and an AlGaAs waveguide confinement layer potential well. Specifically, the specific process of forming the sub-monolayer quantum dot source region includes:

[0045] Growing an N-type AlGaAs waveguide confinement layer on the surface of the N-type DBR layer 3;

[0046] Growing a first GaAs barrier layer 42 on the surface of the N-type AlGaAs waveguide confinement layer, and lowering the growth temperature to a preset temperature;

[0047] The InGaAs sub-monolayer quantum dots 43 are grown on the surface of the first GaAs barrier layer 42 ; and one or more atomic layers of GaAs are continuously deposited after the growth; wherein the structure of the InGaAs sub-monolayer quantum dots 43 can be repeated in one or more cycles.

[0048] Two GaAs barrier layers 42 with different temperatures are sequentially grown to cover the InGaAs sub-monolayer quantum dots 43 ; wherein the growth temperature of the first-grown GaAs barrier layer 42 is lower than the later-grown GaAs barrier layer 42 .

[0049] According to the above records, when the InGaAs sub-monolayer quantum dots 43 are grown on the surface of the first GaAs barrier layer 42, it includes: growing multiple cycles of alternating epitaxial deposition of InAs and GaAs, and epitaxially growing less than a single atomic layer of InAs material on the GaAs surface.

[0050] In some exemplary embodiments, the overall structural thickness of the active region 4 of the InGaAs sub-monolayer quantum dot 43 is λ; wherein λ is the emission center wavelength of the vertical cavity laser chip.

[0051] In some exemplary embodiments, the N-type DBR layer 3 and the P-type DBR layer 6 each include one or more periodic heterojunctions; the heterojunction includes two semiconductor layers with different refractive indices; the refractive index of one semiconductor layer is higher than that of the other semiconductor layer. That is, the N-type DBR layer 3 and the P-type DBR layer 6 in the present invention each include one or more periodic heterojunctions, and each periodic heterojunction includes a low refractive index semiconductor layer and a high refractive index semiconductor layer.

[0052] The present invention also provides a method for manufacturing a sub-monolayer quantum dot vertical cavity laser, comprising the following steps:

[0053] A buffer layer, an N-type DBR layer 3, an N-type waveguide limiting layer 41, a sub-monolayer quantum dot 43, a P-type waveguide limiting layer 44, an oxide layer 5, a P-type DBR layer 6 and a P-type ohmic contact layer 7 are sequentially epitaxially deposited on a preset substrate 2 to form an epitaxial layer structure. As an example, the substrate 2 may be a (100) oriented single crystal with high N-type doping.

[0054] Performing photolithography and etching on the epitaxial layer structure to form a chip mesa;

[0055] There are also two metal electrodes; one of which is deposited on the back side of the substrate 2, namely the back side metal electrode 1. The other metal electrode is deposited on the P-type ohmic contact layer of the chip table; wherein the back side of the substrate 2 is the side of the substrate 2 that is not subjected to epitaxial growth. As an example, the electrode deposited on the P-type ohmic contact layer 7 of the chip table is a ring-shaped metal electrode 8.

[0056] According to the above records, the sub-monolayer quantum dots 43 form a sub-monolayer quantum dot source region on the substrate 2; wherein the sub-monolayer quantum dot source region includes: a GaAs barrier layer 42, an InGaAs sub-monolayer quantum dot 43 and an AlGaAs waveguide confinement layer potential well. Specifically, the specific process of forming the sub-monolayer quantum dot source region includes:

[0057] Growing an N-type AlGaAs waveguide confinement layer on the surface of the N-type DBR layer 3;

[0058] Growing a first GaAs barrier layer 42 on the surface of the N-type AlGaAs waveguide confinement layer, and lowering the growth temperature to a preset temperature;

[0059] The InGaAs sub-monolayer quantum dots 43 are grown on the surface of the first GaAs barrier layer 42 ; and one or more atomic layers of GaAs are continuously deposited after the growth; wherein the structure of the InGaAs sub-monolayer quantum dots 43 can be repeated in one or more cycles.

[0060] Two GaAs barrier layers 42 with different temperatures are sequentially grown to cover the InGaAs sub-monolayer quantum dots 43 ; wherein the growth temperature of the first-grown GaAs barrier layer 42 is lower than the later-grown GaAs barrier layer 42 .

[0061] According to the above records, when the InGaAs sub-monolayer quantum dots 43 are grown on the surface of the first GaAs barrier layer 42, it includes: growing multiple cycles of alternating epitaxial deposition of InAs and GaAs, and epitaxially growing less than a single atomic layer of InAs material on the GaAs surface.

[0062] In some exemplary embodiments, the overall structural thickness of the active region 4 of the InGaAs sub-monolayer quantum dot 43 is λ; wherein λ is the emission center wavelength of the vertical cavity laser chip.

[0063] In some exemplary embodiments, the N-type DBR layer 3 and the P-type DBR layer 6 each include one or more periodic heterojunctions; the heterojunction includes two semiconductor layers with different refractive indices; the refractive index of one semiconductor layer is higher than that of the other semiconductor layer. That is, the N-type DBR layer 3 and the P-type DBR layer 6 in the present invention each include one or more periodic heterojunctions, and each periodic heterojunction includes a low refractive index semiconductor layer and a high refractive index semiconductor layer.

[0064] The preparation method provided by the present invention adopts a special preparation technology. Compared with the conventional quantum well active area, the sub-monolayer quantum dots in the present invention have three-dimensional quantum confinement, and the luminescence performance and photoelectric properties of the material are greatly improved. At the same time, compared with conventional quantum dots, the sub-monolayer quantum dots in the present invention have the advantages of high uniformity of quantum wells. The present invention improves material quality through in-situ heat treatment, thereby realizing a vertical cavity laser chip or VCSEL chip with high quantum efficiency.

[0065] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A sub-monolayer quantum dot vertical cavity laser, applied to a vertical cavity laser VCSEL chip; characterized in that: include: substrate; epitaxially depositing a buffer layer, an N-type DBR layer, an N-type waveguide confinement layer, a sub-monolayer quantum dot, a P-type waveguide confinement layer, an oxide layer, a P-type DBR layer and a P-type ohmic contact layer on the substrate in sequence to form an epitaxial layer structure; Performing photolithography and etching on the epitaxial layer structure to form a chip mesa; Also included are two metal electrodes; One of the metal electrodes is deposited on the back side of the substrate, and the other metal electrode is deposited on the P-type ohmic contact layer on the chip table; wherein the back side of the substrate is the side of the substrate where no epitaxial growth is performed.

2. The sub-monolayer quantum dot vertical cavity laser according to claim 1, characterized in that: The sub-monolayer quantum dots form a sub-monolayer quantum dot source region on the substrate; wherein the sub-monolayer quantum dot source region comprises: a GaAs barrier layer, an InGaAs sub-monolayer quantum dot and an AlGaAs waveguide confinement layer potential well; The specific process of forming the sub-monolayer quantum dot source region includes: Growing an N-type AlGaAs waveguide confinement layer on the surface of the N-type DBR layer; Growing a first GaAs barrier layer on the surface of the N-type AlGaAs waveguide confinement layer, and lowering the growth temperature to a preset temperature; Growing the InGaAs sub-monolayer quantum dots on the surface of the first GaAs barrier layer; and continuously depositing one or more atomic layers of GaAs after the growth; Two GaAs barrier layers with different temperatures are sequentially grown on the InGaAs sub-monolayer quantum dots; wherein the growth temperature of the first-grown GaAs barrier layer is lower than the later-grown GaAs barrier layer.

3. The sub-monolayer quantum dot vertical cavity laser according to claim 2, characterized in that: When the InGaAs sub-monolayer quantum dots are grown on the surface of the first GaAs barrier layer, it includes: growing multiple cycles of alternate epitaxial deposition of InAs and GaAs, and epitaxially growing less than a monoatomic layer of InAs material on the GaAs surface.

4. The sub-monolayer quantum dot vertical cavity laser according to claim 2 or 3, characterized in that: The overall structure thickness of the active region of the InGaAs sub-monolayer quantum dot is λ, wherein λ is the emission center wavelength of the vertical cavity laser chip.

5. The sub-monolayer quantum dot vertical cavity laser according to claim 2 or 3, characterized in that: The structure of the InGaAs sub-monolayer quantum dots may be repeated in one or more cycles.

6. The sub-monolayer quantum dot vertical cavity laser according to claim 1, characterized in that: The N-type DBR layer and the P-type DBR layer each include one or more periods of heterojunction; The heterojunction includes two semiconductor layers with different refractive indices; the refractive index of one semiconductor layer is higher than that of the other semiconductor layer.

7. The sub-monolayer quantum dot vertical cavity laser according to claim 1, characterized in that: The electrode deposited on the P-type ohmic contact layer on the chip table is a ring-shaped metal electrode.

8. The sub-monolayer quantum dot vertical cavity laser according to claim 1, characterized in that: The substrate is an N-type doped single crystal.

9. A method for manufacturing a sub-monolayer quantum dot vertical cavity laser, characterized in that: The following steps are involved: Epitaxially depositing a buffer layer, an N-type DBR layer, an N-type waveguide confinement layer, a sub-monolayer quantum dot, a P-type waveguide confinement layer, an oxide layer, a P-type DBR layer and a P-type ohmic contact layer on a preset substrate in sequence to form an epitaxial layer structure; Photolithography and etching of the epitaxial layer structure to form a chip mesa; Also included are two metal electrodes; One of the metal electrodes is deposited on the back side of the substrate, and the other metal electrode is deposited on the P-type ohmic contact layer on the chip table; wherein the back side of the substrate is the side of the substrate where no epitaxial growth is performed; Wherein, the sub-monolayer quantum dots form a sub-monolayer quantum dot source region on the substrate; the sub-monolayer quantum dot source region includes: a GaAs barrier layer, an InGaAs sub-monolayer quantum dot and an AlGaAs waveguide confinement layer potential well; the specific process of forming the sub-monolayer quantum dot source region includes: Growing an N-type AlGaAs waveguide confinement layer on the surface of the N-type DBR layer; Growing a first GaAs barrier layer on the surface of the N-type AlGaAs waveguide confinement layer, and lowering the growth temperature to a preset temperature; Growing the InGaAs sub-monolayer quantum dots on the surface of the first GaAs barrier layer; and continuously depositing one or more atomic layers of GaAs after the growth; Two GaAs barrier layers with different temperatures are sequentially grown to cover the InGaAs sub-monolayer quantum dots; wherein the growth temperature of the first-grown GaAs barrier layer is lower than the later-grown GaAs barrier layer.

10. The sub-monolayer quantum dot vertical cavity laser according to claim 9, characterized in that: When the InGaAs sub-monolayer quantum dots are grown on the surface of the first GaAs barrier layer, it includes: growing multiple cycles of alternate epitaxial deposition of InAs and GaAs, and epitaxially growing less than a monoatomic layer of InAs material on the GaAs surface.

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