Neuronal circuits

Abstract

A neuron circuit includes a neuron array. The neuron array includes a plurality of semiconductor elements, each of which stores a weight value to generate a corresponding output current, output voltage or output resistance. The main reason is that the semiconductor element array receives a plurality of input signals respectively, and generates different output currents, output voltages or output resistances respectively by changing the size of the semiconductor elements in the neuron array, the coupling relationship of the semiconductor elements or by controlling the voltage, so as to achieve the calculation results required by the neural network.

Description

Technical Field

[0001] The present invention relates to the field of circuits, and in particular to a neural circuit. Background Art

[0002] In today's life, artificial intelligence (AI) is widely used in different technical fields to achieve applications such as identification, warning, and operation assistance. However, due to the rapid development of AI, various new networks have been proposed, and the demand for hardware performance has been continuously raised. In order to meet the needs of the development of artificial intelligence, efficient artificial intelligence computing hardware has also become a major development goal.

[0003] Furthermore, the computing hardware for realizing artificial intelligence can be mainly realized through the Von Neumann structure, which mainly stores weight values ​​through memory, and processes input signals through the processing unit and accesses the memory weight values ​​to generate computing results for neuron computing. However, since the processing unit needs to access the weight information in the memory for computing, it will consume a lot of power and cause computing delays. The Von Neumann structure will face the Von Neumann bottleneck, which will limit the power consumption and computing speed performance of the neuron hardware. Summary of the invention

[0004] In order to solve the above technical problems, the present invention aims to provide a neuron circuit, which can improve the performance of the neuron circuit in terms of power consumption and computing speed.

[0005] The neuron circuit of the present invention includes a neuron array. The neuron array includes a plurality of semiconductor elements, each of which stores a weight value to generate a corresponding output current or a corresponding equivalent resistance value. The neuron array receives a plurality of input signals to control the semiconductor elements in the neuron array and respectively generate output currents or change equivalent resistances. Since the semiconductor elements are coupled to each other, the output of the neuron array can generate a total current or a total equivalent resistance value related to the input signal and the weight state, so as to achieve a high-energy-efficiency operation result.

[0006] Therefore, the neuron circuit provided by the present invention does not need to store weight values ​​in an additional storage device, and the corresponding weight values ​​can be stored through each semiconductor element in the neuron circuit proposed by the present invention, thereby further improving the shortcomings of computing power and computing delay caused by accessing weight values ​​in the prior art, and effectively reducing manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic diagram of a neuron array according to a first embodiment of the present invention;

[0008] Figure 2 is a schematic diagram of another neuron array according to an embodiment of the present invention;

[0009] Figure 3 is a schematic diagram of another neuron array according to an embodiment of the present invention;

[0010] Figure 4 is a schematic diagram of another neuron array according to an embodiment of the present invention;

[0011] Figure 5 is a schematic diagram of another neuron array according to an embodiment of the present invention;

[0012] Figure 6 is a schematic diagram of another neuron array according to an embodiment of the present invention;

[0013] Figure 7 is a schematic diagram of another neuron array according to an embodiment of the present invention;

[0014] Figure 8 A partial layout diagram of another neuron array according to an embodiment of the present invention;

[0015] Fig. 9A is a schematic diagram of another neuron array according to an embodiment of the present invention;

[0016] Fig. 9B , 9C , 9D shows Fig. 9A The dashed circles indicate different metal layer connection embodiments;

[0017] Fig.10 is a schematic diagram of another neuron array according to an embodiment of the present invention;

[0018] Fig.11 This is an equivalent schematic diagram of a neuron array generating a calculation result according to a first embodiment of the present invention;

[0019] Fig.12 This is a conceptual schematic diagram of the output signal processing of a neuron array according to the first embodiment of the present invention;

[0020] Fig.13 This is a conceptual schematic diagram of the output signal processing of a neuron array according to the first embodiment of the present invention;

[0021] Fig.14 FIG. 1 is a conceptual diagram of a neuron array output signal processing according to an embodiment of the present invention.

[0022] Explanation of symbols:

[0023] 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14: Neuron array

[0024] 110, 120, 130, 140: Operational circuit

[0025] 141: Current sensor

[0026] CL: Capacitance

[0027] Gnd: Ground voltage

[0028] In1~Inm: input signal

[0029] L1, L2, L3, L4: Metal layer

[0030] M11~Mmn、MS1:Semiconductor components

[0031] R12, R13: resistors

[0032] S1~Sn:output terminal

[0033] Wt1~Wtm: weight adjustment signal

[0034] VD11~VDmn、VG11~VGmn:Interface window plug (contact plug)

[0035] Vdd: operating voltage

[0036] Vout: output voltage

[0037] Vref3: reference voltage

[0038] D11~Dmn:Diffusion layer DETAILED DESCRIPTION

[0039] In order to make the above features and effects of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings.

[0040] Please refer to Figure 1 , Figure 1Schematic diagram of a neuron array 1 according to an embodiment of the present invention. Neuron array 1 includes a plurality of semiconductor elements M11-Mmn, each of which has a corresponding weight value to generate a corresponding output current or equivalent resistance when enabled or turned on. In this embodiment, semiconductor elements M11-Mmn can be divided into n rows and m columns, and semiconductor elements in each row (e.g., semiconductor elements M11, M21-Mm1, M12, M22-Mm2, etc.) can be divided into the same neuron subgroup (the description in the specification below refers to M11, M21-Mm1 as the first neuron subgroup, M12, M22-Mm2 as the second neuron subgroup, etc., and so on), and are commonly coupled to an output terminal (e.g., output terminals S1-Sn), and semiconductor elements in each column (e.g., semiconductor elements M11-1n, M21-M2n, etc.) will commonly receive an input signal (e.g., input signal In1-Inm) to control the current size or equivalent resistance of the semiconductor element in that column. Therefore, each semiconductor element M11-Mmn in the neuron array 1 can be designed as a neuron cell to store a corresponding weight value so that each semiconductor element M11-Mmn generates a corresponding current or equivalent resistance. The current of all semiconductor elements in each neuron subgroup will flow through each output terminal S1-Sn. By judging the current or voltage on the output terminal, the operation result corresponding to each neuron subgroup can be generated. Among them, the number of rows and columns of the neuron array 1 can be adjusted according to different design requirements and are not limited to the contents recorded in this embodiment. According to different design concepts and user requirements, semiconductor elements can have different implementation methods. In one embodiment, the semiconductor element can be a metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor Field-Effect-Transistor, MOSFET). In one embodiment, the semiconductor element can be a bipolar junction transistor (Bipolar Junction Transistor, BJT). In one embodiment, the semiconductor element can be a vacuum tube (Vacuum Tube). In one embodiment, the semiconductor element can be a quantum gate. The following description is provided in an exemplary manner with respect to an implementation in which the semiconductor element is a metal oxide semiconductor field effect transistor, but a person skilled in the art will appreciate that the scope of the invention is not limited thereto.

[0041] Further, each semiconductor element in the neuron subgroup has a first end, a second end and a control end. The semiconductor element stores a corresponding weight value according to different setting relationships and received signals. In one embodiment, the gate width-to-length ratio in each semiconductor element is adjusted according to the corresponding weight value of each semiconductor element. For example, the gate width-to-length ratio in the semiconductor element can be increased or decreased according to the weight value required by the design, thereby adjusting the output current or equivalent resistance of each semiconductor element. In other words, each semiconductor element can store a corresponding weight value according to the width-to-length ratio of the set gate to generate a corresponding output current or equivalent resistance. In one embodiment, the threshold voltage of each semiconductor element is set according to its corresponding weight value. For example, the threshold voltage of the semiconductor element can be increased or decreased according to the designed weight value. When the voltage of the input signal is the same, the voltage difference between the control end and the second end (e.g., the gate and the source) of each semiconductor element remains unchanged, but the threshold voltage of each semiconductor element can be generated according to the corresponding weight value so that each semiconductor element generates a corresponding output current or equivalent resistance. In other words, each semiconductor element can store a corresponding weight value according to the set threshold voltage. In one embodiment, the semiconductor elements M11-Mmn can be manufactured by different manufacturing methods such as low threshold voltage (LVT) or ultra-low threshold voltage (ULVT), so the voltage difference between the control end and the second end (such as the gate and the source) of the semiconductor element can produce different output currents or equivalent resistance values. Therefore, the neuron array 1 can adjust the weight value of the semiconductor element according to the different threshold voltages set for the semiconductor element.

[0042] Therefore, each semiconductor element can receive the corresponding input signal In1~Inm at the control end (such as the gate) to control the current value or equivalent resistance value generated by each semiconductor element. The first end (such as the drain) of each semiconductor element of each neuron subgroup will be commonly coupled to an output end (one of the output ends S1~Sn), and the second end (such as the source) of each semiconductor element will be coupled to a first reference voltage (such as a ground voltage Gnd). Therefore, each neuron subgroup can operate according to the input signal In1~Inm and generate a calculation result at the output end (for example, the first neuron subgroup generates a calculation result at the output end S1, the second neuron subgroup generates a calculation result at the output end S2... etc.), thereby realizing the multiplication and addition operation of the neuron circuit. The details of how each semiconductor element stores the weight value (for example, based on the width-to-length ratio of the gate, the gate-source voltage difference, and the threshold voltage, etc.) to generate the corresponding output current or equivalent resistance value should be well known to those skilled in the art, so they will not be elaborated here.

[0043] In short, without the need for additional storage devices to store weight values, the neuron array 1 can store corresponding weight values ​​through each semiconductor element, further improving the shortcomings of computing power and computing delay caused by accessing weight values ​​in the prior art, and effectively reducing manufacturing costs.

[0044] Please refer to Figure 2 , Figure 2 FIG. 2 is a schematic diagram of another neuron array 2 according to an embodiment of the present invention. The neuron array 2 is similar to Figure 1 The neuron array 1 is shown, so the same elements are marked with the same symbols. The difference between the neuron array 2 and the neuron array 1 is that the neuron array 2 receives multiple weight adjustment signals Wt1~Wtm and transmits them to the second end (e.g., source) of each column of semiconductor elements. Therefore, the first end (e.g., drain) of all semiconductor elements of each neuron subgroup in the neuron array 2 is coupled to the same output end, the control end (e.g., gate) of each semiconductor element of each neuron subgroup receives the input signal respectively, and the second end (e.g., source) of each semiconductor element of each neuron subgroup receives the weight adjustment signal respectively. In other words, in addition to adjusting the output current or equivalent resistance according to the gate width-to-length ratio and the threshold voltage, each semiconductor element also adjusts the output current or equivalent resistance generated according to a difference between the input signal received by each semiconductor element and the weight adjustment signal. Each neuron subgroup receives the input signals In1~Inm and the weight adjustment signals Wt1~Wtm, and generates a calculation result at the corresponding output end accordingly.

[0045] Please refer to Figure 3 , Figure 3 It is a schematic diagram of another neuron array 3 of an embodiment of the present invention. The first end (e.g., drain) of each semiconductor element of each neuron subgroup in the neuron array 3 receives the corresponding input signal respectively, the gate of each semiconductor element of each neuron subgroup receives the corresponding weight adjustment signal respectively, and the second end (e.g., source) of all semiconductor elements of each neuron subgroup is commonly coupled to the same output end (one of the output ends S1~Sn). Therefore, the neuron array 3 can control the opening or closing of each semiconductor element according to the weight adjustment signal Wt1~Wtm, and adjust the output current or equivalent resistance generated by each semiconductor element according to the input signal In1~Inm, so that each neuron subgroup generates a corresponding calculation result at the corresponding output end.

[0046] Please refer to Figure 4 , Figure 4It is a schematic diagram of another neuron array 4 according to an embodiment of the present invention. The first end (e.g., drain) of all semiconductor elements of each neuron subgroup in the neuron array 4 is commonly coupled to the same output end (one of the output ends S1 to Sn), and the control end (e.g., gate) of each semiconductor element of each neuron subgroup receives the corresponding input signal respectively, and the second end (e.g., source) of all semiconductor elements of each neuron subgroup receives the same weight adjustment signal (e.g., the first neuron subgroup receives the weight adjustment signal Wt1, the second neuron subgroup receives the weight adjustment signal Wt2... etc.). Therefore, the neuron array 4 can control the opening or closing of each semiconductor element according to the input signals In1 to Inm, and adjust the output current or equivalent resistance of each neuron subgroup according to the weight adjustment signals Wt1 to Wtn, so that each neuron subgroup generates a corresponding calculation result at the corresponding output end.

[0047] Please refer to Figure 5 , Figure 5 Schematic diagram of another neuron array 5 according to an embodiment of the present invention. The first end (e.g., drain) of all semiconductor elements of each neuron subgroup in the neuron array 5 will receive the same weight adjustment signal (one of the weight adjustment signals Wt1~Wtn), the control end (e.g., gate) of each semiconductor element of each neuron subgroup will receive the corresponding input signal, and the second end (e.g., source) of all semiconductor elements of each neuron subgroup will be coupled to the same output end (one of the output ends S1~Sn). Therefore, the neuron array 5 can control the opening or closing of each semiconductor element according to the input signals In1~Inm, and adjust the output current or equivalent resistance of the corresponding neuron subgroup according to the weight adjustment signals Wt1~Wtn, so that each neuron subgroup generates a calculation result at the corresponding output end.

[0048] Please refer to Figure 6 , Figure 6 FIG. 6 is a schematic diagram of another neuron array 6 according to an embodiment of the present invention. The neuron array 6 is similar to Figure 1The neuron array 1 is shown, so the same elements are marked with the same symbols. In the neuron array 6, the first ends (e.g., drains) of some semiconductor elements are connected to or disconnected from the wires on the metal layer through via plugs (for example, the drains of semiconductor elements M11, M1n, M21, M2n, Mm2, and Mmn are connected to the wires through via plugs VD11, VD1n, VD21, VD2n, VDm2, and VDmn, respectively). When there is no via plug on the first end (e.g., drain) of the semiconductor element, the semiconductor element cannot reflect the generated output current or equivalent resistance to the output end (for example, the drains of semiconductor elements M12, M22, and Mm1 are not provided with via plugs). In other words, each semiconductor element in the neuron array 6 adjusts the corresponding weight value of the semiconductor element through the via plug on the first end (e.g., drain). For example, if Figure 6 As shown, there is no via plug at the dotted circle on the first end (eg, drain) of the semiconductor element M12, so the weight value of the semiconductor element M12 can be considered to be adjusted to zero, and the weight value of each semiconductor element is further adjusted.

[0049] Please refer to Figure 7 , Figure 7 FIG. 7 is a schematic diagram of another neuron array 7 according to an embodiment of the present invention. The neuron array 7 is similar to Figure 1 The neuron array 1 is shown, so the same elements are marked with the same symbols. In the neuron array 7, the control end (e.g., gate) of each semiconductor element receives an input signal or a first reference voltage (e.g., ground voltage Gnd) through the via plugs VG11 to VGmn, respectively. For example, the control ends (e.g., gates) of the semiconductor elements M11, M1n, M21, M22, Mm1, Mm2, and Mmn can receive corresponding input signals through the via plugs VG11, VG1n, VG21, VG22, VGm1, VGm2, and VGmn, respectively, so that the semiconductor elements can generate output currents or equivalent resistances accordingly. For example, the control ends (e.g., gates) of the semiconductor elements M12 and M2n can receive the first reference voltage (e.g., ground voltage Gnd) through the via plugs VG12 and VG2n, and the semiconductor elements can generate corresponding output currents or equivalent resistances according to the settings of the via plugs, so the weight values ​​of the semiconductor elements can be considered to be adjusted to zero. In other words, the neuron array 7 can adjust the corresponding weight value of each semiconductor element through the via plug on the control end (such as the gate) of each semiconductor element.

[0050] Please refer to Figure 8 , Figure 8This is a partial layout diagram of another neuron array 8 according to an embodiment of the present invention. For ease of reading, some component structures of the neuron array 8 are not illustrated (e.g., the coupling relationship between the drain and source of each semiconductor element in each neuron group, metal layer routing, etc.). In the neuron array 8, each semiconductor element will adjust the weight value of each semiconductor element through the diffusion layer. For example, the semiconductor elements M11, M1n, M21, M22, M2n, and Mm1 include diffusion layers D11, D1n, D21, D22, D2n, and Dm1, respectively, so these semiconductor elements can generate corresponding output currents or equivalent resistances for calculations. For example, the semiconductor elements M12, Mm2, and Mmn do not include diffusion layers, so these semiconductor elements will not generate corresponding output currents or equivalent resistances for calculations, and the weight values ​​of these semiconductor elements can be regarded as being adjusted to zero. In other words, the neuron array 8 can adjust the weight value of each semiconductor element by whether each semiconductor element has a diffusion layer.

[0051] Please refer to Fig. 9A , Fig. 9A FIG. 9 is a schematic diagram of another neuron array 9 according to an embodiment of the present invention. The neuron array 9 is similar to Figure 7 The neuron array 7 is shown, so the same elements are marked with the same symbols. For each neuron group in the neuron array, the first terminals (such as drains) of all semiconductor elements are connected to the output terminal (one of the output terminals S1 to Sn) through one or more metal layers. For example, Fig. 9B , 9C , 9D shows Fig. 9A The dotted circle in FIG. 1 shows an embodiment of connecting different metal layers at the output terminal Sn. Generally speaking, a metal layer at a higher layer has a greater thickness, and thus has a greater parasitic capacitance and a smaller parasitic resistance. By setting different connected metal layers, the weight value of each neuron subgroup can be adaptively adjusted. For example, Fig. 9B As shown, the semiconductor elements M1n-Mmn are connected at the output terminal Sn through the metal layers L1 and L2. Fig. 9C As shown, the semiconductor elements M1n-Mmn are connected at the output end Sn through the metal layers L1 and L3. Fig.9D As shown, the semiconductor elements M1n-Mmn are connected at the output terminal Sn through metal layers L1-L4. In one embodiment, changing the connection method of the metal layer on the output terminal can adjust the overall weight value of the neuron subgroup by 5%-30%. In other words, by Figures 9B to 9D The different metal layers shown are connected to the semiconductor devices M1n-Mmn at the output terminal Sn, and the overall weight value of the neuron subgroup can be adaptively adjusted according to different design requirements, thereby adjusting the weight value of the semiconductor device in the neuron group.

[0052] Please refer to Fig.10 , Fig.10 FIG. 1 is a schematic diagram of another neuron array 10 according to an embodiment of the present invention. The neuron array 10 is similar to Figure 7 The neuron array 7 is shown, so the same elements are marked with the same symbols. The difference between the neuron array 10 and the neuron array 7 is that the semiconductor element in the neuron array 10 includes one or more parallel sub-semiconductor elements. For example, the semiconductor element M11 includes four parallel sub-semiconductor elements, so the semiconductor element M11 can adjust the output current or equivalent resistance generated according to its parallel number. Therefore, the neuron array 10 can adjust the weight value according to the number of parallel sub-semiconductor elements included in each semiconductor element.

[0053] Please refer to Fig.11 , Fig.11 FIG. 1 is an equivalent schematic diagram of a neuron array 11 generating a calculation result according to an embodiment of the present invention. In this embodiment, the first neuron subgroup in the neuron array 11 generates a calculation result by determining the voltage on the output terminal S1 through the calculation circuit 110. Fig.11 Only the circuit structure for generating the calculation result of the first neuron subgroup is shown, but those with ordinary knowledge in the art should be able to infer the calculation circuits of other neuron subgroups based on the first neuron subgroup. In detail, in the present embodiment, the first neuron subgroup will generate a corresponding output current or equivalent resistance value according to the input signal and the weight value, and charge and discharge the capacitor CL on the output terminal S1 to generate a corresponding calculation result. In order to obtain the corresponding calculation result on the output terminal S1, the output terminal S1 is coupled to one end of the capacitor CL, and the other end of the capacitor CL is coupled to the first reference voltage (for example, the ground voltage Gnd). The output terminal S1 can be pre-charged to a specific voltage. When the input signal In1~Inm is input to the semiconductor elements M11~Mm1 in the first neuron subgroup, the semiconductor elements M11~Mm1 will generate a corresponding output current or equivalent resistance value, and charge and discharge the cross-voltage of the capacitor CL to generate a corresponding output voltage. Therefore, the neuron array 11 can judge the weight value in the neuron subgroup based on the change in the measured output voltage Vout, and then generate the calculation result of the neuron subgroup.

[0054] Please refer to Fig.12 , Fig.12Schematic diagram of the concept of the output signal processing generated by the neuron array 12 according to an embodiment of the present invention. In this embodiment, the operation circuit 120 of the neuron array 12 uses resistor voltage division to control the semiconductor element to generate the operation result of the first neuron subgroup. In detail, the output terminal S1 is coupled to one end of the resistor R12, and the other end of the resistor R12 receives the second reference voltage (e.g., the operating voltage Vdd), and the output terminal S1 is coupled to the control terminal (e.g., the gate) of the semiconductor element MS1. Therefore, the resistance value of the resistor R12 and the equivalent resistance value of the semiconductor elements M11~Mm1 in parallel in the neuron subgroup, the resistance value ratio of the two can bias the voltage of the output terminal S1, and control the output current or equivalent resistance of the semiconductor element MS1 accordingly. Therefore, when the voltage on the output terminal S1 is greater than or equal to the preset voltage (in this embodiment, the difference between the voltage of the output terminal S1 and the third reference voltage Vref3 is greater than or equal to the threshold voltage of the semiconductor element MS1), the semiconductor element MS1 will be controlled to output the third reference voltage Vref3 as the output voltage Vout. When the voltage on the output terminal S1 is less than the preset voltage, the semiconductor element MS1 will generate a corresponding output current or equivalent resistance (for example, the output current generated by the semiconductor element MS1 may be close to zero or the equivalent resistance may be close to infinity). Therefore, by measuring the output voltage Vout of the operation circuit 120 in the neuron array 12, the operation result of the first neuron subgroup can be determined.

[0055] Please refer to Fig.13 , Fig.13 This is a conceptual schematic diagram of an output signal generated by a neuron array 13 according to an embodiment of the present invention. The neuron array 13 is similar to the neuron array 12, so the same elements are indicated by the same symbols. The difference between the neuron array 13 and the neuron array 12 is that one end of the semiconductor element MS1 in the operation circuit 130 is coupled to a capacitor CL, and the other end of the semiconductor element MS1 receives a first reference voltage (e.g., ground voltage Gnd). The other end of the capacitor CL receives the first reference voltage (e.g., ground voltage Gnd). Similar to the neuron array 12, the neuron array 13 also uses the resistor voltage divider on the output end to control the semiconductor element MS1, and discharges the pre-charged capacitor CL through the output current or equivalent resistance of the semiconductor element MS1, so the neuron array 13 can generate the operation result of the neuron subgroup based on the voltage change of the measured output voltage Vout.

[0056] In one embodiment, the gate width-to-length ratio of the semiconductor element MS1 can be adaptively changed to adjust the weight value of the corresponding neuron subgroup. For example, when the gate width-to-length ratio of the semiconductor element MS1 increases, the ability to drive the capacitor CL to discharge is enhanced, which can be regarded as increasing the weight value of the overall neuron subgroup semiconductor elements M11-Mm1.

[0057] Please refer to Fig.14 , Fig.14 This is a conceptual diagram of an output signal generated by a neuron array 14 according to an embodiment of the present invention. The neuron array 14 is similar to the neuron array 13, so the same elements are marked with the same symbols. The difference between the neuron array 14 and the neuron array 13 is that the operation circuit 140 further includes a current sensor 141 connected in series between the semiconductor element MS1 and the capacitor CL, and generates a corresponding output according to the magnitude of the driving current generated by the semiconductor element MS1. In one embodiment, the current sensor 141 can generate an analog or digital output signal according to the output current as a calculation result. In one embodiment, the output signal generated by the current sensor 141 can drive a counter, and the number of times the counter is driven by the current sensor 141 is used as the calculation result.

[0058] In summary, the neuron circuit can achieve computing in memory (CIM) through the gate width-to-length ratio and threshold voltage of the semiconductor element, and further adjust the stored weight value through different implementation methods, which can effectively overcome the shortcomings of power consumption and computing speed of the neuron circuit in the prior art.

Claims

1. A neuron circuit, comprising: A neuron array includes a plurality of semiconductor elements, wherein each of the semiconductor elements stores a weight value to generate a corresponding output current, and the plurality of semiconductor elements are divided into a plurality of neuron subgroups. The plurality of neuron subgroups respectively receive a plurality of input signals to control the output currents respectively generated by the plurality of semiconductor elements, and each of the neuron subgroups sums the plurality of output currents of the plurality of semiconductor elements through an output terminal to generate a calculation result; wherein the weight value of each of the plurality of semiconductor elements corresponds to at least one of a gate width-to-length ratio and a threshold voltage of each of the plurality of semiconductor elements; Each of the semiconductor elements receives one of the plurality of input signals and a weight adjustment signal through two of the first terminal, the second terminal and the control terminal.

2. The neuron circuit according to claim 1, characterized in that The first end of each of the semiconductor elements is coupled to the output end, the second end is coupled to a first reference voltage, and the control end receives one of the plurality of input signals.

3. The neuron circuit according to claim 1, characterized in that: The first end of each of the semiconductor elements is coupled to the output end, the second end receives the weight adjustment signal, and the control end receives one of the plurality of input signals.

4. The neuron circuit according to claim 1, characterized in that: The first end of each of the semiconductor elements receives one of the plurality of input signals, the second end is coupled to the output end, and the control end receives the weight adjustment signal.

5. The neuron circuit according to claim 1, characterized in that: The first end of each of the semiconductor elements receives the weight adjustment signal, the second end is coupled to the output end, and the control end receives one of the plurality of input signals.

6. The neuron circuit according to claim 1, characterized in that: Each of the semiconductor elements adjusts the weight value of each of the plurality of semiconductor elements through a via plug connected to the first end.

7. The neuron circuit according to claim 1, characterized in that: Each of the semiconductor elements adjusts the weight value of each of the plurality of semiconductor elements through a via plug connected to the control end.

8. The neuron circuit according to claim 1, characterized in that: Each of the semiconductor elements adjusts the weight value of each of the plurality of semiconductor elements through a diffusion layer.

9. The neuron circuit according to claim 1, characterized in that: The output end has at least one metal layer, and the weight value of each of the semiconductor elements in the plurality of neuron subgroups is adjusted by the at least one metal layer.

10. The neuron circuit according to claim 1, characterized in that: Each of the semiconductor elements includes at least one parallel-connected sub-semiconductor element, and the weight value of each of the plurality of semiconductor elements is adjusted according to the number of the at least one parallel-connected sub-semiconductor element.

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