Chip wafer, chip packaging structure and packaging method

Abstract

The present invention discloses a chip wafer, a chip packaging structure and a packaging method, the packaging method comprising: providing a semiconductor wafer, the semiconductor wafer comprising a plurality of chip substrates, and a scribe line between adjacent chip substrates; the chip substrate having a first side and a second side opposite to each other; forming a first interconnection structure on the active layer of the first side; forming a first plastic encapsulation layer, the first plastic encapsulation layer covering the first edge region, the first interconnection structure and the active layer; forming a second interconnection structure, the second interconnection structure covering the middle region and exposing the second edge region; forming a second plastic encapsulation layer, the second plastic encapsulation layer covering the second interconnection structure, the second edge region and the first plastic encapsulation layer; dividing based on the scribe line to form a plurality of single-chip chip packaging structures. The application of the technical solution provided by the present invention avoids the problems of warping and hidden cracks caused by cutting, thereby improving the reliability of product packaging.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a chip wafer, a chip packaging structure and a packaging method. Background Art

[0002] With the continuous development of science and technology, various electronic devices have been widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable and important tool for people today.

[0003] The core component of electronic devices to achieve various functions is the control chip. In order to ensure the safe and reliable operation of the chip and avoid damage, the chip needs to be packaged and protected to form a packaging structure. In the existing chip packaging structure, metal layer warping and hidden cracking problems are prone to occur, resulting in low reliability of the packaging structure. Summary of the invention

[0004] In view of this, the present invention provides a chip wafer, a chip packaging structure and a packaging method, which avoid the problems of metal layer warping and hidden cracks caused by cutting and improve the reliability of product packaging.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] A chip packaging method, the packaging method comprising:

[0007] A semiconductor wafer is provided, the semiconductor wafer comprising a plurality of chip substrates, wherein a dicing road is provided between adjacent chip substrates; the chip substrate comprises a first side and a second side opposite to each other; the first side comprises a functional area and a first edge area surrounding the functional area; the second side comprises a middle area and a second edge area surrounding the middle area;

[0008] forming a first interconnect structure on the active layer on the first side; the active layer covers the functional area and exposes the first edge area;

[0009] forming a first plastic encapsulation layer, wherein the first plastic encapsulation layer covers the first edge region, the first interconnect structure, and the active layer; on a surface of a side of the semiconductor wafer having the active layer, the scribe line has a groove of a preset depth; and the first plastic encapsulation layer fills the groove;

[0010] Thinning the side of the semiconductor wafer away from the active layer to expose the first plastic sealing layer at the bottom of the groove;

[0011] forming a second interconnect structure on the thinned second side, wherein the second interconnect structure covers the middle area and exposes the second edge area;

[0012] forming a second plastic encapsulation layer, wherein the second plastic encapsulation layer covers the second interconnect structure, the second edge region, and the first plastic encapsulation layer exposed on the second side;

[0013] The chip packaging structures are divided based on the dicing lines to form a plurality of single-chip chip packaging structures.

[0014] Preferably, in the above packaging method, the method for forming the first interconnect structure includes:

[0015] forming a first metal layer covering the active layer;

[0016] Solder balls are formed on the first metal layer.

[0017] Preferably, in the above packaging method, before forming the first plastic encapsulation layer, the groove of a set depth is formed in the scribe line;

[0018] Wherein, the depth of the groove is less than the thickness of the semiconductor wafer.

[0019] Preferably, in the above packaging method, the method for forming the second interconnect structure includes:

[0020] forming a patterned seed layer on the thinned second side, wherein the seed layer covers the middle area and exposes the second edge area and the first plastic encapsulation layer;

[0021] A patterned back metal layer is formed, wherein the back metal layer covers the seed layer and exposes the second edge region and the first plastic encapsulation layer.

[0022] Preferably, in the above packaging method, the method for forming the seed layer and the back metal layer includes:

[0023] forming an unpatterned seed layer and a photoresist layer covering the seed layer on the thinned second side;

[0024] Patterning the photoresist layer, removing the photoresist layer corresponding to the middle area, and retaining the photoresist layer corresponding to the groove and the second edge area;

[0025] Based on the patterned photoresist layer, forming a patterned back metal layer on the surface of the seed layer corresponding to the middle area;

[0026] The photoresist layer is removed, and based on the patterned back metal layer, the seed layer corresponding to the groove and the second edge region is removed.

[0027] Preferably, in the above encapsulation method, before segmentation, the method further comprises:

[0028] A planarization process is performed on a surface of the second plastic packaging layer that is away from the semiconductor wafer.

[0029] Preferably, in the above packaging method, the first plastic encapsulation layer and the second plastic encapsulation layer are resin layers made of the same material.

[0030] The present invention also provides a chip packaging structure, the chip packaging structure comprising:

[0031] A chip substrate, the chip substrate having a first side and a second side opposite to each other; the first side having a functional area and a first edge area surrounding the functional area; the second side including a middle area and a second edge area surrounding the middle area;

[0032] an active layer, wherein the active layer covers the functional area and exposes the first edge area;

[0033] a first interconnect structure, wherein the first interconnect structure is located on a surface of the active layer;

[0034] a first plastic encapsulation layer, wherein the first plastic encapsulation layer covers the first edge region, the first interconnect structure, and the active layer;

[0035] a second interconnect structure, the second interconnect structure covering the middle area;

[0036] a second plastic sealing layer, wherein the second plastic sealing layer covers the second edge area and the second interconnection structure;

[0037] Wherein, the first plastic packaging layer also surrounds the side surfaces of the chip substrate.

[0038] Preferably, in the above chip packaging structure, the first plastic encapsulation layer located on the side of the chip substrate is flush with the second side;

[0039] The second plastic encapsulation layer covers a surface of the first plastic encapsulation layer that is flush with the second side, and covers a side surface of the second interconnect structure.

[0040] Preferably, in the above chip packaging structure, the first interconnect structure includes:

[0041] a first metal layer covering the active layer;

[0042] A solder ball is located on the first metal layer.

[0043] Preferably, in the above chip packaging structure, the second interconnect structure includes:

[0044] a seed layer covering the intermediate region;

[0045] A second metal layer covers the seed layer.

[0046] Preferably, in the above chip packaging structure, the first plastic encapsulation layer and the second plastic encapsulation layer are resin layers made of the same material.

[0047] Preferably, in the above chip packaging structure, the first plastic encapsulation layer and the first interconnection structure are flush with each other on a side facing away from the chip substrate.

[0048] The present invention also provides a chip wafer, which includes the multiple chip packaging structures described in any one of the above items.

[0049] It can be known from the above description that in the chip wafer, chip packaging structure and packaging method provided by the technical solution of the present invention, a first interconnection structure is formed on the active layer on the first side of the chip substrate, and a first plastic sealing layer covering the first edge area, the active layer and the first interconnection structure is formed on the first side, and a second plastic sealing layer covering the second edge area, the second interconnection structure and the first plastic sealing layer is formed on the second side. The first plastic sealing layer and the second plastic sealing layer form a six-sided sealing protection for the chip, thereby increasing the strength of the product. Compared with the prior art, the present invention adopts a six-sided sealing protection method, which not only encapsulates and protects the side of the chip, but also, through the creative groove design in the dicing path, when each chip packaging structure is finally divided, only the plastic sealing layer is divided at the dicing path position, thereby avoiding the risk of back collapse and fracture caused by cutting the metal layer and the semiconductor wafer at the same time, thereby increasing the reliability of the product packaging process. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0051] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which the present invention can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by the present invention, should still fall within the scope of the technical contents disclosed by the present invention.

[0052] Figure 1 A schematic diagram of a chip packaging structure;

[0053] Figure 2 It is a schematic diagram of another chip packaging structure;

[0054] Figure 3-Figure 18A process schematic diagram of a chip packaging method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0055] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the embodiments in the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0056] Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), also known as MOS tube, is a field effect transistor that can be widely used in analog and digital circuits. Power MOSFET refers to MOSFET devices at the power output stage, usually with an operating current greater than 1A. How to reduce power consumption is also the main driving force for the development of power discrete semiconductors. As far as power MOSFET is concerned, new demands are mainly met by reducing on-resistance and developing new packaging forms. However, for wafer-level packaging, the thinner the chip, the greater the stress challenge, the higher the requirements for subsequent applications, and the larger the chip size, the greater the stress during patching, the higher the risk of hidden cracks and breakage, and the lower the reliability of actual patch applications.

[0057] refer to Figure 1 , Figure 1 Figure 1 is a schematic diagram of a chip packaging structure. Figure 1 As shown, a front metal layer 111 is provided on a first side of a chip substrate 112, and a back metal layer 113 is provided on a second side of the chip substrate 112. Currently, MOSFET wafer-level packaging products use the following Figure 1 The chip packaging structure shown in the figure has a structure in which the thinner the grinding sheet is, the greater the warping is, which poses a greater challenge to the subsequent packaging process, and the reliability after packaging is difficult to meet product requirements.

[0058] refer to Figure 2 , Figure 2 Figure 1 is a schematic diagram of another chip packaging structure. Figure 2 As shown, a front metal layer 121, solder balls 123 and a first resin protection layer 122 are formed on the first side of the chip substrate 124, and a back metal layer 125 and a second resin protection layer 126 are formed on the second side of the chip substrate 124. The sidewalls are not adequately protected in this packaging structure, and the back metal layer 125 is cut simultaneously during dicing, which may cause cracks or warping in the back metal layer 125 after dicing, resulting in chip failure.

[0059] Therefore, in order to solve the above problems, the present invention provides a chip wafer, a chip packaging structure and a packaging method, the packaging method comprising:

[0060] A semiconductor wafer is provided, the semiconductor wafer comprising a chip substrate, a plurality of chips are provided on the chip substrate, and a dicing road is provided between adjacent chips; the chip substrate comprises a first side and a second side opposite to each other; the first side comprises a functional area and a first edge area surrounding the functional area; the second side comprises a middle area and a second edge area surrounding the middle area;

[0061] forming a first interconnect structure on the active layer on the first side; the active layer covers the functional area and exposes the first edge area;

[0062] forming a first plastic encapsulation layer, wherein the first plastic encapsulation layer covers the first edge region, the first interconnect structure, and the active layer; on a surface of a side of the semiconductor wafer having the active layer, the scribe line has a groove of a preset depth; and the first plastic encapsulation layer fills the groove;

[0063] Thinning the side of the semiconductor wafer away from the active layer to expose the first plastic sealing layer at the bottom of the groove;

[0064] forming a second interconnect structure on the thinned second side, wherein the second interconnect structure covers the middle area and exposes the second edge area;

[0065] forming a second plastic encapsulation layer, wherein the second plastic encapsulation layer covers the second interconnect structure, the second edge region, and the first plastic encapsulation layer exposed on the second side;

[0066] The chip packaging structures are divided based on the dicing lines to form a plurality of single-chip chip packaging structures.

[0067] It can be known from the above description that in the chip wafer, chip packaging structure and packaging method provided by the technical solution of the present invention, a first interconnection structure is formed on the active layer on the first side of the chip substrate, and a first plastic encapsulation layer covering the first edge area, the active layer and the first interconnection structure is formed on the first side, and a second plastic encapsulation layer covering the second edge area, the second interconnection structure and the first plastic encapsulation layer is formed on the second side. The first plastic encapsulation layer and the second plastic encapsulation layer form a six-sided encapsulation protection for the chip, thereby increasing the strength of the product. Compared with the prior art, the present invention adopts a six-sided encapsulation protection method, which can reduce the risk of back collapse and fracture caused by cutting thick back gold, thereby increasing the reliability of the product packaging process.

[0068] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0069] refer to Figure 3-Figure 18 , Figure 3-Figure 18 A process schematic diagram of a chip packaging method provided by an embodiment of the present invention. The chip packaging method comprises:

[0070] Step S11: Figure 3 As shown, a semiconductor wafer 213 is provided, and the semiconductor wafer 213 includes a plurality of chip substrates 101, and a dicing road 100 is provided between adjacent chip substrates 101; the chip substrate 101 has a first side S1 and a second side S2 opposite to each other; the first side S1 has a functional area S11 and a first edge area S12 surrounding the functional area S11; the second side S2 includes a middle area S21 and a second edge area S22 surrounding the middle area S21.

[0071] The semiconductor wafer 213 may be a silicon wafer. The first side S1 is a side corresponding to the upper surface of the chip substrate 101 , and the second side S2 is a side corresponding to the lower surface of the chip substrate 101 .

[0072] Step S12: Figure 4-Figure 6 As shown, a first interconnect structure 200 is formed on the active layer 214 of the first side S1 ; the active layer 214 covers the functional area S11 and exposes the first edge area S12 ; and the first interconnect structure 200 is located on the surface of the active layer 214 .

[0073] In an embodiment of the present invention, the method for forming the first interconnect structure 200 includes:

[0074] First, if Figure 5 As shown, a first metal layer 211 covering the active layer 214 is formed.

[0075] Then, if Figure 6 As shown, solder balls 212 are formed on the first metal layer 211. In the embodiment of the present invention, the first metal layer 211 and the solder balls 212 can be sequentially formed on the active layer 214 by chemical plating or electroplating to form the following: Figure 4 The structure shown.

[0076] Step S13: Figure 7-Figure 9 As shown, a first plastic encapsulation layer 231 is formed, and the first plastic encapsulation layer 231 covers the first edge area S12, the first interconnect structure 200 and the active layer 214; on the side surface of the semiconductor wafer 213 having the active layer 214, the dicing street 100 has a groove 221 of a preset depth; the first plastic encapsulation layer 231 fills the groove 221.

[0077] It should be noted that before forming the first plastic encapsulation layer 231 , the groove 221 of a set depth is formed in the dicing street 100 , such as by pre-cutting the groove 221 of a set depth in the dicing street 100 by a blade; wherein the depth of the groove 221 is less than the thickness of the semiconductor wafer 213 .

[0078] In the embodiment of the present invention, the method for forming the first plastic encapsulation layer 231 includes:

[0079] First, if Figure 7 As shown, a groove 221 is formed at a position corresponding to the dicing road 100 , and the groove 221 is located on a side surface of the semiconductor wafer 213 where the active layer 214 and the first interconnect structure 200 are formed; the depth of the groove 221 is less than the thickness of the semiconductor wafer 213 .

[0080] Then, if Figure 8 As shown, a first molding layer 231 is formed to cover the first edge region S12, the first interconnect structure 200 and the active layer 214, and the first molding layer 231 fills the groove 221. The first molding layer 231 may be resin.

[0081] Finally, if Fig. 9 As shown, the first plastic encapsulation layer 231 is thinned to expose the surface of the first interconnection structure 200. In the embodiment of the present invention, the thinning process is a grinding process. In order to ensure that the solder ball 212 is fully exposed, the thinning process removes the upper end of the solder ball 212 to expose the solder ball 212 for circuit interconnection.

[0082] It should be noted that after the first plastic encapsulation layer 231 is thinned, a backside grinding (BG) may be further applied to a surface of the first plastic encapsulation layer 231 facing away from the semiconductor wafer 213 to protect the surface of the solder ball 212 .

[0083] Step S14: Fig.10 As shown, the side of the semiconductor wafer 213 facing away from the active layer 214 is thinned to expose the first plastic packaging layer 231 at the bottom of the groove 221 .

[0084] Step S15: Figure 10-12 As shown, a second interconnect structure 261 / 271 is formed on the thinned second side, and the second interconnect structure 261 / 271 covers the middle area S21 and exposes the second edge area S22 .

[0085] In an embodiment of the present invention, a method for forming the second interconnect structure 261 / 271 includes:

[0086] First, if Fig.10 As shown, the surface of the semiconductor wafer 213 facing away from the first interconnect structure 200 is thinned to expose the first plastic encapsulation layer 231 in the groove 221. The semiconductor wafer 213 may be thinned by grinding.

[0087] Then, if Fig.11 As shown, a patterned seed layer 261 is formed on the thinned second side S2, and the seed layer 261 covers the middle area S21, exposing the second edge area S22 and the first plastic encapsulation layer 231. The patterned seed layer 261 may be formed by photolithography technology.

[0088] Finally, if Fig.12 As shown, a patterned back metal layer 271 is formed, and the back metal layer 271 covers the seed layer 261, exposing the second edge region S22 and the first plastic encapsulation layer 231. The patterned back metal layer 271 can be formed by photolithography technology.

[0089] In the embodiment of the present invention, the method for forming the seed layer 261 and the back metal layer 271 includes:

[0090] First, if Fig.13 As shown, an unpatterned seed layer 261 and a photoresist layer 262 covering the seed layer 261 are formed on the second side S2 after thinning. In the embodiment of the present invention, after the semiconductor wafer 213 is ground and thinned, the seed layer 261 is firstly sputtered on the second side S2 of the semiconductor wafer 213. The thickness of the seed layer 261 can be The titanium layer and After the seed layer 261 is sputtered to form a copper layer with the above thickness, a photoresist layer 262 is coated on the surface of the semiconductor wafer 213 .

[0091] Then, if Fig.14 As shown, the photoresist layer 262 is patterned, the photoresist layer 262 corresponding to the middle area S21 is removed, and the photoresist layer 262 corresponding to the groove 221 and the second edge area S22 is retained.

[0092] Then, if Fig.15 As shown, based on the patterned photoresist layer 262, a patterned back metal layer 271 is formed on the surface of the seed layer 261 corresponding to the middle area S21. The back metal layer 271 can be formed by electroplating or evaporation process.

[0093] Finally, if Fig.16As shown, the photoresist layer 262 is removed, and the seed layer 261 corresponding to the groove 221 and the second edge region S22 is removed based on the patterned back metal layer 271. The seed layer 261 corresponding to the groove 221 and the second edge region S22 may be removed by wet etching.

[0094] Step S16: Fig.17 As shown, a second plastic encapsulation layer 291 is formed, and the second plastic encapsulation layer 291 covers the second interconnect structure 261 / 271 , the second edge region S22 , and the first plastic encapsulation layer 231 exposed on the second side S2 .

[0095] Step S17: Fig.18 As shown, the chip is divided based on the dicing road 100 to form a plurality of single-chip packaging structures.

[0096] Before the division, the method further includes: planarizing the surface of the second plastic encapsulation layer 291 which is away from the semiconductor wafer 213. The planarizing may be performed by a grinding process.

[0097] In the embodiment of the present invention, the first plastic encapsulation layer 231 and the second plastic encapsulation layer 291 can be resin layers made of the same material. The first plastic encapsulation layer 231 and the second plastic encapsulation layer 291 are made of the same material to form an integrated plastic encapsulation structure with good adhesion. Moreover, when cutting based on the scribe line position, the same material resin is cut without cutting transition of different materials, and the cutting force is uniform, which can avoid problems such as edge collapse. Fig.18 The horizontal dotted lines in the figure represent the delamination of the first plastic sealing layer 231 and the second plastic sealing layer 291. In actual products, since the two are made of the same material, they form an integrated structure with good adhesion after being bonded and cured.

[0098] It can be seen from the above description that in the chip packaging method provided by the technical solution of the present invention, a first interconnection structure is formed on the active layer on the first side of the chip substrate, and a first plastic encapsulation layer covering the first edge area, the active layer and the first interconnection structure is formed on the first side, and a second plastic encapsulation layer covering the second edge area, the second interconnection structure and the first plastic encapsulation layer is formed on the second side. The first plastic encapsulation layer and the second plastic encapsulation layer form a six-sided encapsulation protection for the chip, thereby increasing the strength of the product. Compared with the prior art, the present invention adopts a six-sided encapsulation protection method, which can reduce the risk of back collapse and fracture caused by cutting thick back gold, thereby increasing the reliability of the product packaging process.

[0099] Based on the above embodiment, another embodiment of the present invention further provides a chip packaging structure. Fig.18 As shown, Fig.18The schematic diagram of a chip packaging structure provided by an embodiment of the present invention. The chip packaging structure adopts the packaging method described in the above embodiment, which can reduce the risk of back collapse and fracture caused by cutting thick back gold, thereby increasing the reliability of the product packaging process.

[0100] like Fig.18 As shown, the chip packaging structure includes:

[0101] The chip substrate 213 has a first side and a second side opposite to each other; the first side has a functional area and a first edge area surrounding the functional area; the second side includes a middle area and a second edge area surrounding the middle area.

[0102] An active layer 214 covers the functional area and exposes the first edge area.

[0103] A first interconnect structure, wherein the first interconnect structure is located on the surface of the active layer 214 ; wherein the first interconnect structure comprises: a first metal layer 211 covering the active layer 214 ; and solder balls 212 located on the first metal layer 211 .

[0104] A first plastic encapsulation layer 231 , wherein the first plastic encapsulation layer 231 covers the first edge region, the first interconnection structure, and the active layer 214 .

[0105] A second interconnect structure, wherein the second interconnect structure covers the middle region; wherein the second interconnect structure comprises: a seed layer 261 covering the middle region; and a second metal layer 271 covering the seed layer 261 .

[0106] A second plastic encapsulation layer, wherein the second plastic encapsulation layer covers the second interconnection structure and the second edge region.

[0107] The first plastic packaging layer 231 also surrounds the side surfaces of the chip substrate 213 .

[0108] The chip substrate 213 includes a side surface connecting the periphery of the first side and the periphery of the second side; and the first plastic encapsulation layer 231 also covers the side surface of the chip substrate 213 .

[0109] like Fig.18 As shown, the first plastic encapsulation layer 231 located on the side of the chip substrate 213 is flush with the second side; the second plastic encapsulation layer covers the surface of the first plastic encapsulation layer 231 flush with the second side, and covers the side of the second interconnect structure.

[0110] The first side has a groove surrounding the first edge area, and the first plastic sealing layer 231 fills the groove; the sidewall of the groove surrounds the side of the chip substrate 213; based on the thinning process of the second side, the second side exposes the first plastic sealing layer 231 located on the side of the chip substrate 213. In the embodiment of the present invention, the first plastic sealing layer 231 and the second plastic sealing layer 291 can be resin layers of the same material. The first plastic sealing layer 231 and the second plastic sealing layer 291 are made of the same material, which can form an integrated plastic sealing structure with good adhesion.

[0111] Furthermore, the first plastic encapsulation layer 231 and the first interconnection structure are planarized on a side away from the chip substrate 213 , so that the surfaces of the first plastic encapsulation layer 231 and the first interconnection structure on a side away from the chip substrate 213 are flush.

[0112] In the embodiment of the present invention, for 2mΩ or 5mΩ MOSFET power devices, thinner chips and thicker back metal layers can be made, and the warpage of the semiconductor wafer is very small when cutting, which can prevent chipping and cracking caused by cutting the back metal layer, and can automatically operate during testing and laser printing, thereby improving production capacity. In the solution of the present invention, only the plastic sealing layer needs to be cut at the end, avoiding the problems of warping and hidden cracks caused by cutting.

[0113] It can be known from the above description that in the chip packaging structure provided by the technical solution of the present invention, a first interconnection structure is formed on the active layer on the first side of the chip substrate, and a first plastic encapsulation layer covering the first edge area, the active layer and the first interconnection structure is formed on the first side, and a second plastic encapsulation layer covering the second edge area, the second interconnection structure and the first plastic encapsulation layer is formed on the second side. The first plastic encapsulation layer and the second plastic encapsulation layer form a six-sided encapsulation protection for the chip, thereby increasing the strength of the product. Compared with the prior art, the present invention adopts a six-sided encapsulation protection method, which can reduce the risk of back collapse and fracture caused by cutting thick back gold, thereby increasing the reliability of the product packaging process.

[0114] Based on the above embodiment, another embodiment of the present invention further provides a chip wafer, the structure of which can refer to the above embodiment. Fig.17 As shown, the chip wafer includes the multiple chip packaging structures described in the above embodiments. The chip wafer adopts the chip packaging structure provided in the above embodiments, which can reduce the risk of back collapse and fracture caused by cutting thick back gold, thereby improving the reliability of chip packaging.

[0115] The structure of the chip wafer can refer to the above embodiment. Fig.17 As shown, multiple single-chip packaging structures can be formed by cutting.

[0116] In this specification, each embodiment is described in a progressive, parallel, or progressive and parallel manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. As for the chip wafer and chip packaging structure disclosed in the embodiment, since it corresponds to the packaging method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the packaging method part.

[0117] It should be noted that in the description of the present invention, it should be understood that the terms "upper", "lower", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, which are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. When a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally arranged component at the same time.

[0118] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the article or device including the above elements.

[0119] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A chip packaging method, characterized in that: The packaging method comprises: A semiconductor wafer is provided, the semiconductor wafer comprising a plurality of chip substrates, wherein a dicing road is provided between adjacent chips; the chip substrate comprises a first side and a second side opposite to each other; the first side comprises a functional area and a first edge area surrounding the functional area; the second side comprises a middle area and a second edge area surrounding the middle area; forming a first interconnect structure on the active layer on the first side; the active layer covers the functional area and exposes the first edge area; forming a first plastic encapsulation layer, wherein the first plastic encapsulation layer covers the first edge region, the first interconnect structure, and the active layer; on a surface of a side of the semiconductor wafer having the active layer, the scribe line has a groove of a preset depth; and the first plastic encapsulation layer fills the groove; Thinning the side of the semiconductor wafer away from the active layer to expose the first plastic sealing layer at the bottom of the groove; forming a second interconnect structure on the thinned second side, wherein the second interconnect structure covers the middle area and exposes the second edge area; forming a second plastic encapsulation layer on the second side, wherein the second plastic encapsulation layer covers the second interconnect structure, the second edge region, and the first plastic encapsulation layer exposed on the second side; Dividing based on the dicing road to form a plurality of single-chip packaging structures; The method for forming the first interconnect structure includes: forming a first metal layer covering the active layer; forming solder balls on the first metal layer; The method for forming the second interconnect structure includes: forming a patterned seed layer on the thinned second side, the seed layer covering the middle area and exposing the second edge area and the first plastic encapsulation layer; forming a patterned back metal layer, the back metal layer covering the seed layer and exposing the second edge area and the first plastic encapsulation layer.

2. The packaging method according to claim 1, characterized in that: Before forming the first plastic encapsulation layer, the groove of a set depth is formed in the scribe line; wherein the depth of the groove is less than the thickness of the semiconductor wafer.

3. The packaging method according to claim 1, characterized in that: The method for forming the seed layer and the back metal layer comprises: forming an unpatterned seed layer and a photoresist layer covering the seed layer on the thinned second side; Patterning the photoresist layer, removing the photoresist layer corresponding to the middle area, and retaining the photoresist layer corresponding to the groove and the second edge area; Based on the patterned photoresist layer, forming a patterned back metal layer on the surface of the seed layer corresponding to the middle area; The photoresist layer is removed, and based on the patterned back metal layer, the seed layer corresponding to the groove and the second edge region is removed.

4. The packaging method according to claim 1, characterized in that: Before the split, it also includes: A planarization process is performed on a surface of the second plastic packaging layer that is away from the semiconductor wafer.

5. The packaging method according to any one of claims 1 to 4, characterized in that: The first plastic encapsulation layer and the second plastic encapsulation layer are resin layers made of the same material.

6. A chip packaging structure, characterized in that: The chip packaging structure comprises: A chip substrate, the chip substrate having a first side and a second side opposite to each other; the first side having a functional area and a first edge area surrounding the functional area; the second side including a middle area and a second edge area surrounding the middle area; an active layer, wherein the active layer covers the functional area and exposes the first edge area; a first interconnect structure, wherein the first interconnect structure is located on a surface of the active layer; a first plastic encapsulation layer, wherein the first plastic encapsulation layer covers the first edge region, the first interconnect structure, and the active layer; a second interconnect structure, the second interconnect structure covering the middle area; a second plastic sealing layer, wherein the second plastic sealing layer covers the second edge area and the second interconnection structure; Wherein, the first plastic sealing layer also surrounds the side surface of the chip substrate; The first interconnect structure comprises: a first metal layer covering the active layer; a solder ball located on the first metal layer; The second interconnect structure includes: a seed layer covering the middle region; a second metal layer covering the seed layer; Wherein, the chip packaging structure is packaged using the packaging method described in any one of claims 1-5.

7. The chip packaging structure according to claim 6, characterized in that: The first plastic encapsulation layer located on the side of the chip substrate is flush with the second side; The second plastic encapsulation layer covers a surface of the first plastic encapsulation layer that is flush with the second side, and covers a side surface of the second interconnect structure.

8. The chip packaging structure according to claim 6, characterized in that: The first plastic encapsulation layer and the second plastic encapsulation layer are resin layers made of the same material.

9. The chip packaging structure according to claim 6, characterized in that: The first plastic encapsulation layer and the first interconnection structure are flush with each other on a side facing away from the chip substrate.

10. A chip wafer, characterized in that: The chip wafer includes a plurality of chip packaging structures as described in any one of claims 6 to 9.

Images