Camera device, operating method thereof, and electronic device

Abstract

Provided is an imaging device capable of acquiring imaging data corresponding to a high-resolution image at short time intervals. The imaging device includes a pixel provided with a photoelectric conversion element and n (n is an integer greater than 2) holding circuits. The photoelectric conversion element and the n holding circuits are stacked on each other. One electrode of the photoelectric conversion element is electrically connected to the first to nth holding circuits. The holding circuit includes an OS transistor having an extremely low off-state current characteristic, which can hold imaging data for a long period of time. During the first to nth periods, the imaging device acquires the first to nth imaging data and holds it in the first to nth holding circuits. Then, the first to nth imaging data held by the first to nth holding circuits are read out. The read imaging data is AD-converted and output to the outside of the imaging device.

Description

Technical Field

[0001] One embodiment of the present invention relates to an imaging device, an operating method thereof, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of one embodiment of the invention disclosed in this specification, etc., relates to an object, a method, or a manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, a product, or a composition of matter. Therefore, more specifically, as examples of the technical field of one embodiment of the present invention disclosed in this specification, semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, lighting devices, power storage devices, storage devices, camera devices, their driving methods, or their manufacturing methods can be cited.

[0003] Note that in this specification and the like, a semiconductor device refers to any device that can operate by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one form of a semiconductor device. In addition, a storage device, a display device, a camera device, and an electronic device may include a semiconductor device. Background Art

[0004] A technique for forming a transistor using an oxide semiconductor thin film formed on a substrate has attracted attention. For example, Patent Document 1 discloses an imaging device having a structure in which a transistor including an oxide semiconductor and having a very low off-state current is used for a pixel circuit.

[0005] Patent Document 2 discloses an imaging device that can be used in a high-speed camera and that can capture images at short time intervals.

[0006] [Prior technical literature]

[0007] [Patent Document]

[0008] [Patent Document 1] Japanese Patent Application Publication No. 2011-119711

[0009] [Patent Document 2] Japanese Patent Application Publication No. 2017-55401 Summary of the invention

[0010] Technical problem to be solved by the invention

[0011] In the imaging device described in Patent Document 2, two or more imaging data are acquired and stored in different pixels, and then the stored imaging data are sequentially read out, thereby realizing imaging at short time intervals. Therefore, the more imaging data are acquired at one time, the fewer pixels can be used when acquiring and storing one imaging data, and the image resolution corresponding to the acquired imaging data decreases.

[0012] One of the purposes of one embodiment of the present invention is to provide an imaging device capable of acquiring a plurality of imaging data at short time intervals. Another purpose of one embodiment of the present invention is to provide an imaging device that operates at high speed. Another purpose of one embodiment of the present invention is to provide an imaging device capable of acquiring imaging data corresponding to a high-resolution image. Another purpose of one embodiment of the present invention is to provide an imaging device capable of acquiring imaging data corresponding to a high-quality image. Another purpose of one embodiment of the present invention is to provide an imaging device with a high aperture ratio. Another purpose of one embodiment of the present invention is to provide an imaging device with high sensitivity. Another purpose of one embodiment of the present invention is to provide an imaging device with low power consumption. Another purpose of one embodiment of the present invention is to provide an inexpensive imaging device. Another purpose of one embodiment of the present invention is to provide an imaging device with high reliability. Another purpose of one embodiment of the present invention is to provide a novel imaging device. Another purpose of one embodiment of the present invention is to provide a novel semiconductor device, etc.

[0013] In addition, one of the purposes of one embodiment of the present invention is to provide a method for operating an image pickup device capable of acquiring a plurality of image pickup data at short time intervals. In addition, one of the purposes of one embodiment of the present invention is to provide a method for operating an image pickup device that operates at high speed. In addition, one of the purposes of one embodiment of the present invention is to provide a method for operating an image pickup device capable of acquiring image pickup data corresponding to high-resolution image pickup data. In addition, one of the purposes of one embodiment of the present invention is to provide a method for operating an image pickup device capable of acquiring image pickup data corresponding to high-quality images. In addition, one of the purposes of one embodiment of the present invention is to provide a method for operating an image pickup device with a high aperture ratio. In addition, one of the purposes of one embodiment of the present invention is to provide a method for operating an image pickup device with high sensitivity. In addition, one of the purposes of one embodiment of the present invention is to provide a low-power image pickup device. In addition, one of the purposes of one embodiment of the present invention is to provide a method for operating an inexpensive image pickup device. In addition, one of the purposes of one embodiment of the present invention is to provide a method for operating an image pickup device with high reliability. In addition, one of the purposes of one embodiment of the present invention is to provide a method for operating a novel image pickup device. In addition, one of the purposes of one embodiment of the present invention is to provide a method for operating a novel semiconductor device, etc.

[0014] Note that the recording of these purposes does not prevent the existence of other purposes. In addition, one mode of the present invention does not need to achieve all of the above purposes. Purposes other than the above can be obvious from the description of the specification, drawings, claims, etc., and can be extracted from the description of the specification, drawings, claims, etc.

[0015] Solutions to technical problems

[0016] One embodiment of the present invention is a stacked imaging device including a first layer, a second layer and a third layer, wherein the first layer includes a photoelectric conversion element, the second layer includes a first circuit, and the third layer includes a second circuit, an electrode of the photoelectric conversion element is electrically connected to the first circuit, and an electrode of the photoelectric conversion element is electrically connected to the second circuit, the first circuit has a function of maintaining first imaging data, the first imaging data is data corresponding to the illumination of light irradiating the photoelectric conversion element, and the second circuit has a function of maintaining second imaging data, the second imaging data is data corresponding to the illumination of light irradiating the photoelectric conversion element.

[0017] In the above method, the first circuit may also include a first transmission transistor, the second circuit may also include a second transmission transistor, an electrode of the photoelectric conversion element may also be electrically connected to one of the source and the drain of the first transmission transistor, and an electrode of the photoelectric conversion element may also be electrically connected to one of the source and the drain of the second transmission transistor.

[0018] In the above manner, one of the source and the drain of the first transmission transistor may also have an area overlapping with one of the source and the drain of the second transmission transistor, the other of the source and the drain of the second transmission transistor may also have an area overlapping with the other of the source and the drain of the second transmission transistor, and the gate of the first transmission transistor may also have an area overlapping with the gate of the second transmission transistor.

[0019] In the above aspect, the first and second transfer transistors may include a metal oxide in the channel formation region, and the metal oxide may include elements M (M is Al, Ga, Y, or Sn) and Zn.

[0020] In the above aspect, the first circuit and the second circuit may have the same structure.

[0021] In the above embodiment, the second layer may include the first AD conversion circuit, the third layer may include the second AD conversion circuit, and the first AD conversion circuit and the second AD conversion circuit may have overlapping areas.

[0022] In the above method, the first layer may also include a multiplexer circuit and an AD conversion circuit, the first input terminal of the multiplexer circuit may also be electrically connected to the first circuit, the second input terminal of the multiplexer circuit may also be electrically connected to the second circuit, and the output terminal of the multiplexer circuit may also be electrically connected to the AD conversion circuit.

[0023] In the above manner, the first circuit may also include a first transmission transistor, a first reset transistor, a first amplifier transistor and a first selection transistor, the other of the source and the drain of the first transmission transistor may also be electrically connected to one of the source and the drain of the first reset transistor, one of the source and the drain of the first reset transistor may also be electrically connected to the gate of the first amplifier transistor, and one of the source and the drain of the first amplifier transistor may also be electrically connected to one of the source and the drain of the first selection transistor.

[0024] In the above aspect, the first transfer transistor, the first reset transistor, the first amplifier transistor, and the first selection transistor may include a metal oxide in the channel formation region, and the metal oxide may include elements M (M is Al, Ga, Y, or Sn) and Zn.

[0025] In the above manner, the second circuit may also include a second transmission transistor, a second reset transistor, a second amplifying transistor and a second selection transistor, the other of the source and the drain of the second transmission transistor may also be electrically connected to one of the source and the drain of the second reset transistor, one of the source and the drain of the second reset transistor may also be electrically connected to the gate of the second amplifying transistor, and one of the source and the drain of the second amplifying transistor may also be electrically connected to one of the source and the drain of the second selection transistor.

[0026] In the above aspect, the second transfer transistor, the second reset transistor, the second amplification transistor, and the second selection transistor may include a metal oxide in the channel formation region, and the metal oxide may include elements M (M is Al, Ga, Y, or Sn) and Zn.

[0027] In the above aspect, the period during which the imaging device acquires the first imaging data and the period during which the imaging device acquires the second imaging data may be different.

[0028] An electronic device including the imaging device and the display device according to one embodiment of the present invention is also one embodiment of the present invention.

[0029] One embodiment of the present invention is a method for operating an imaging device, the imaging device comprising a stack of a first layer having a photoelectric conversion element, a second layer having a first circuit, and a third layer having a second circuit, wherein first imaging data is acquired during a first period and maintained in the first circuit, the first imaging data being data corresponding to the illumination of light irradiating the photoelectric conversion element, second imaging data is acquired during a second period and maintained in the second circuit, the second imaging data being data corresponding to the illumination of light irradiating the photoelectric conversion element, and the first imaging data maintained by the first circuit and the second imaging data maintained by the second circuit are read out during a third period.

[0030] In the above method, a first AD conversion circuit may be provided in the second layer, and a second AD conversion circuit may be provided in the third layer. During the third period, the first AD conversion circuit may convert the first camera data as analog data into digital data, and the second AD conversion circuit may convert the second camera data as analog data into digital data.

[0031] One embodiment of the present invention is a method for operating an imaging device, the imaging device including a stack of a photoelectric conversion element, a first circuit, and a second circuit, wherein first imaging data is acquired during a first period and maintained in the first circuit, the first imaging data being data corresponding to the illumination of light irradiating the photoelectric conversion element, second imaging data is acquired during a second period and maintained in the second circuit, the second imaging data being data corresponding to the illumination of light irradiating the photoelectric conversion element, the first imaging data maintained by the first circuit is read out during a third period, and the second imaging data maintained by the second circuit is read out during a fourth period.

[0032] In the above method, the camera device may also include an AD conversion circuit in the first layer, and during the third period the AD conversion circuit may also convert the first camera data as analog data into digital data, and during the fourth period the AD conversion circuit may also convert the second camera data as analog data into digital data.

[0033] In the above-described embodiment, the first imaging data may be acquired in the first period using the global shutter method, and the second imaging data may be acquired in the second period using the global shutter method.

[0034] Effects of the Invention

[0035] According to one embodiment of the present invention, a camera device capable of acquiring a plurality of camera data at short time intervals can be provided. In addition, a camera device operating at high speed can be provided. In addition, a camera device capable of acquiring camera data corresponding to a high-resolution image can be provided. In addition, a camera device capable of acquiring camera data corresponding to a high-quality image can be provided. In addition, a camera device with a high aperture ratio can be provided. In addition, a camera device with high sensitivity can be provided. In addition, a camera device with low power consumption can be provided. In addition, an inexpensive camera device can be provided. In addition, a camera device with high reliability can be provided. In addition, a novel camera device can be provided. In addition, a novel semiconductor device can be provided, etc.

[0036] In addition, a method for operating an imaging device capable of acquiring a plurality of imaging data at short time intervals may be provided. In addition, a method for operating an imaging device that operates at high speed may be provided. In addition, a method for operating an imaging device capable of acquiring imaging data corresponding to high-resolution imaging data may be provided. In addition, a method for operating an imaging device capable of acquiring imaging data corresponding to high-quality images may be provided. In addition, a method for operating an imaging device with a high aperture ratio may be provided. In addition, a method for operating an imaging device with high sensitivity may be provided. In addition, an imaging device with low power consumption may be provided. In addition, a method for operating an inexpensive imaging device may be provided. In addition, a method for operating an imaging device with high reliability may be provided. In addition, a method for operating a novel imaging device may be provided. In addition, a method for operating a novel semiconductor device or the like may be provided.

[0037] Note that the description of these effects does not prevent the existence of other effects. In addition, one mode of the present invention does not need to have all of the above effects. Effects other than the above are obvious from the description of the specification, claims, drawings, etc., and can be extracted from the description of the specification, claims, drawings, etc.

[0038] BRIEF DESCRIPTION OF THE DRAWINGS

[0039] [ Figure 1 ] is a block diagram showing a structural example of a camera device.

[0040] [ Figure 2 ] is a circuit diagram showing a structural example of a camera device.

[0041] [ Figure 3 ] is a circuit diagram showing a structural example of a camera device.

[0042] [ Figure 4 ] is a timing diagram showing an example of the working method of the camera device.

[0043] [ Figure 5 ] is a block diagram showing a structural example of a camera device.

[0044] [ Figure 6 ] is a timing diagram showing an example of the working method of the camera device.

[0045] [ Figure 7 ] is a block diagram showing a structural example of a camera device.

[0046] [Fig. 8] A and B are diagrams for explaining the operation of the rolling shutter method and the global shutter method.

[0047] [ Fig. 9 ] is a cross-sectional view showing a structural example of a camera device.

[0048] [Figure 10] A and B are cross-sectional views showing structural examples of a transistor.

[0049] [ Fig. 11] A is a cross-sectional view showing a structural example of an imaging device. B is a cross-sectional view showing a structural example of a photoelectric conversion element.

[0050] [Figure 12] A, B and C are stereoscopic diagrams showing structural examples of the camera device.

[0051] [Fig. 13] A is a top view showing a structural example of a transistor. B and C are cross-sectional views showing a structural example of a transistor.

[0052] [Fig. 14] A is a top view showing a structural example of a transistor. B and C are cross-sectional views showing a structural example of a transistor.

[0053] [Fig. 15] A is a top view showing a structural example of a transistor. B and C are cross-sectional views showing a structural example of a transistor.

[0054] [Fig. 16] A is a top view showing a structural example of a transistor. B and C are cross-sectional views showing a structural example of a transistor.

[0055] [Fig. 17] A is a top view showing a structural example of a transistor. B and C are cross-sectional views showing a structural example of a transistor.

[0056] [Fig. 18] A1, A2, and A3 are perspective views of a package for storing an imaging device. B1, B2, and B3 are perspective views of a module for storing an imaging device.

[0057] [Fig. 19]A, B, C, D, and E are diagrams for explaining an electronic device.

[0058] [Fig. 20]A, B, C, and D are diagrams for explaining an electronic device.

[0059] Modes for Carrying Out the Invention

[0060] The following describes the embodiments with reference to the accompanying drawings. It should be noted that a person skilled in the art can easily understand that the embodiments can be implemented in a plurality of different forms, and the methods and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments shown below.

[0061] The plurality of embodiments described below can be combined as appropriate. In addition, when a plurality of configuration examples are described in one embodiment, these configuration examples can be combined as appropriate with each other.

[0062] The block diagrams in this specification show components classified according to their functions in independent blocks; however, actual components are difficult to be clearly divided according to their functions, and one component may have a plurality of functions.

[0063] In the drawings, for the sake of convenience, the size, thickness of the layer or the region are sometimes exaggerated. Therefore, the present invention is not limited to the dimensions in the drawings. In the drawings, ideal examples are schematically shown, so the present invention is not limited to the shapes or numerical values ​​shown in the drawings.

[0064] In the drawings and the like, the same reference numerals may be used to indicate the same components, components having the same functions, components formed of the same material, components formed at the same time, and the like, and repeated descriptions may be omitted.

[0065] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be interchanged with "conductive film". Also, "insulating film" may be interchanged with "insulating layer".

[0066] In this specification, etc., expressions such as "on" or "below" that express arrangement are not limited to the positional relationship of components being "directly above" or "directly below". For example, "a gate (gate terminal, gate region or gate electrode) on a gate insulating layer" includes a case where another component is included between the gate insulating layer and the gate electrode.

[0067] In addition, ordinal numbers such as “first”, “second”, and “third” in this specification and the like are provided to avoid confusion among constituent elements and are not used to limit the number.

[0068] In this specification, "electrical connection" includes connection through "an element having some kind of electrical function". Here, "an element having some kind of electrical function" is not particularly limited as long as it can transmit and receive electrical signals between the connected objects. For example, "an element having some kind of electrical function" includes not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0069] Note that in this specification, etc., "voltage" often refers to a potential difference between a certain potential and a reference potential (eg, ground potential). Therefore, voltage and potential difference can be interchanged.

[0070] In this specification, etc., a transistor refers to an element including at least three terminals: a gate, a drain, and a source. The transistor has a channel formation region between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the drain and the source through the channel formation region. Note that in this specification, etc., the channel formation region refers to a region where current mainly flows.

[0071] In addition, when transistors with different polarities are used or when the direction of current changes during circuit operation, the functions of the source and the drain may be interchanged. Therefore, in this specification, etc., the source and the drain may be interchanged.

[0072] In addition, in this specification, etc., unless otherwise specified, the off-state current refers to the drain current when the transistor is in the off state (also referred to as the non-conducting state or the blocking state). Unless otherwise specified, in an n-channel transistor, the off state refers to a state where the voltage Vgs of the gate to the source is lower than the threshold voltage Vth, and in a p-channel transistor, the off state refers to a state where the voltage Vgs of the gate to the source is higher than the threshold voltage Vth. In other words, the off-state current of an n-channel transistor sometimes refers to the drain current when the voltage Vgs of the gate to the source is lower than the threshold voltage Vth.

[0073] In the above description of the off-state current, the drain can be referred to as the source. That is, the off-state current sometimes refers to the source current when the transistor is in the off state. In addition, the leakage current sometimes means the same as the off-state current. In this specification, etc., the off-state current sometimes refers to the current flowing between the source and the drain when the transistor is in the off state.

[0074] In this specification, etc., metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also called oxide semiconductors), and the like.

[0075] For example, when a metal oxide is used in the channel formation region of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, when the metal oxide has at least one of an amplification function, a rectification function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor (metal oxide semiconductor). That is, a transistor containing a metal oxide in a channel formation region can be referred to as an "oxide semiconductor transistor" or "OS transistor". Similarly, the above-mentioned "transistor using an oxide semiconductor" is also a transistor containing a metal oxide in a channel formation region.

[0076] In addition, in this specification, etc., a metal oxide containing nitrogen may also be referred to as a metal oxide. In addition, a metal oxide containing nitrogen may also be referred to as a metal oxynitride. The details of the metal oxide will be described later.

[0077] (Implementation Method 1)

[0078] In this embodiment, an imaging device according to one embodiment of the present invention is described with reference to the drawings.

[0079] One embodiment of the present invention is an imaging device including a pixel provided with a photoelectric conversion element and n (n is an integer greater than or equal to 2) holding circuits. The photoelectric conversion element and the n holding circuits are stacked on each other. One electrode of the photoelectric conversion element is electrically connected to the first to nth holding circuits. The holding circuit has a function of holding imaging data. The holding circuit includes an OS transistor having a characteristic of extremely low off-state current, and can hold imaging data for a long period of time.

[0080] In this specification, etc., image data refers to data corresponding to the illumination of light irradiated to the photoelectric conversion element. An image pickup device according to one embodiment of the present invention has a function of acquiring image pickup data and writing it into a holding circuit. In addition, an image pickup device according to one embodiment of the present invention has a function of reading the image pickup data held by the holding circuit, performing analog-to-digital conversion (hereinafter, AD conversion), and then outputting the image pickup data to the outside of the image pickup device.

[0081] The working method of the camera device of one embodiment of the present invention is as follows. First, in the first period, the camera device obtains the first camera data and writes it to the first holding circuit. Similarly, in the second to nth periods, the camera device obtains the second to nth camera data and writes it to the second to nth holding circuits. Then, the first to nth camera data held by the first to nth holding circuits are read out. As described above, the read camera data is AD converted and output to the outside of the camera device. The above is the working method of the camera device of one embodiment of the present invention.

[0082] As described above, the holding circuit included in the camera device of one embodiment of the present invention can hold the camera data for a long period of time. Therefore, it is not necessary to read the camera data from the holding circuit immediately after the camera device obtains one camera data and writes it into the holding circuit, but these camera data can be read after obtaining n camera data (first to nth camera data). That is, n camera data can be read out at one time. Therefore, compared with the case where the acquisition and reading of one camera data are performed alternately, multiple camera data can be obtained at short time intervals. Therefore, the camera device of one embodiment of the present invention can be used for a high-speed camera, for example. In addition, by reading out the camera data at one time, n camera data can be obtained at short time intervals even without high-speed reading. Therefore, the camera device of one embodiment of the present invention can be made low in power consumption while obtaining multiple camera data at short time intervals.

[0083] As described above, the first to n-th holding circuits included in the imaging device of one embodiment of the present invention are stacked one on another. Therefore, even when n imaging data are read out at once, imaging data corresponding to an image having a resolution equal to that of the case where imaging data are read out one by one can be obtained. Thus, the imaging device of one embodiment of the present invention can obtain a plurality of imaging data at short time intervals and obtain imaging data corresponding to an image with a high resolution.

[0084] <Configuration Example 1 of Imaging Device>

[0085] Figure 1 1 is a block diagram showing a configuration example of an imaging device 10 as an imaging device of one embodiment of the present invention. The imaging device 10 includes a layer 20 and n layers (n is an integer greater than or equal to 2) of layers 30 provided above the layer 20. That is, the layer 20 and n layers 30 are stacked.

[0086] In this specification, etc., the n-layer layers 30 are respectively recorded as layers 30_1 to 30_n to distinguish each other. For example, the lowest layer 30 among the n-layer layers 30 is recorded as layer 30_1, and layers 30_2 to 30_n are sequentially arranged upward. In addition, the uppermost layer 30 among the n-layer layers 30 may be recorded as layer 30_1, and layers 30_2 to 30_n may be sequentially arranged downward. In addition, "_i" is attached to the symbol of the component element such as the circuit provided in the layer 30_i (i is an integer greater than 1 and less than n), thereby indicating the layer 30 provided with the component element.

[0087] Photoelectric conversion elements 21 are arranged in a matrix in the layer 20. Photodiodes can be used as the photoelectric conversion elements 21. When the photoelectric conversion elements 21 are irradiated with light, they store electric charges corresponding to the illuminance of the light.

[0088] The layer 30 includes an imaging unit 31, a gate driver circuit 33, a source driver circuit 34, and an AD conversion circuit 35. The imaging unit 31 has holding circuits 32 arranged in a matrix. The gate driver circuit 33 and the source driver circuit 34 may include, for example, a shift register circuit.

[0089] For example, the layer 30 is provided with the same number of holding circuits 32 as the number of rows and columns as the number of photoelectric conversion elements 21. Since the imaging device 10 includes n layers of the layer 30, the imaging device 10 can be provided with n times the number of holding circuits 32 as the number of photoelectric conversion elements 21. The holding circuits 32 may have a region overlapping with the photoelectric conversion element 21.

[0090] For example, one gate driver circuit 33, one source driver circuit 34, and one AD conversion circuit 35 are provided in one layer 30. In this case, n gate driver circuits 33, n source driver circuits 34, and n AD conversion circuits 35 are provided in the imaging device 10. In addition, two or more gate driver circuits 33, source driver circuits 34, and AD conversion circuits 35 may be provided in one layer 30.

[0091] One electrode of the photoelectric conversion element 21 is electrically connected to the holding circuits 32_1 to 32_n. For example, one electrode of the photoelectric conversion element 21 is electrically connected to the holding circuits 32_1 to 32_n having a region overlapping with the photoelectric conversion element 21.

[0092] The gate driver circuit 33 is electrically connected to the holding circuit 32. The AD conversion circuit 35 is electrically connected to the holding circuit 32 via the wiring 40. The source driver circuit 34 is electrically connected to the AD conversion circuit 35.

[0093] The holding circuits 32_1 to 32_n may have regions overlapping each other. One photoelectric conversion element 21 and the holding circuits 32_1 to 32_n having regions overlapping each other form one pixel.

[0094] The gate driver circuits 33_1 to 33_n may have mutually overlapping regions. The source driver circuits 34_1 to 34_n may have mutually overlapping regions. The AD conversion circuits 35_1 to 35_n may have mutually overlapping regions.

[0095] The holding circuit 32 has a function of holding the image data. The gate driver circuit 33 has a function of generating a selection signal for controlling the operation of the holding circuit 32. By supplying the selection signal to the holding circuit 32, for example, the holding circuit 32 for writing the image data and the holding circuit 32 for reading the held image data can be selected. The gate driver circuit 33 can select the holding circuit 32 for each row.

[0096] The source driver circuit 34 has, for example, a function of selecting and reading the held imaging data of the holding circuit 32. The source driver circuit 34 can select the holding circuit 32 for each column. Thus, the imaging data held by the holding circuit 32 on the row selected by the gate driver circuit 33 and on the column selected by the source driver circuit 34 can be read.

[0097] The AD conversion circuit 35 has a function of converting the image pickup data as analog data read from the holding circuit 32 into digital data and outputting it as a signal OUT to the outside of the image pickup device 10. The signal OUT can be output to a display device, a storage device, a communication device, etc., for example.

[0098] The image pickup data read out from the holding circuit 32 is supplied to the AD conversion circuit 35 through the wiring 40. That is, the wiring 40 can be used as a data line.

[0099] <Configuration Example of Holding Circuit>

[0100] Figure 2 1 is a circuit diagram for explaining a configuration example of the holding circuit 32 and a connection relationship between the holding circuit 32 and the photoelectric conversion element 21. The holding circuit 32 includes a transistor 12, a transistor 13, a transistor 14, a transistor 15, and a capacitor 16. The capacitor 16 may not be provided.

[0101] One electrode of the photoelectric conversion element 21 is electrically connected to one of the source and drain of the transistor 12. The other of the source and drain of the transistor 12 is electrically connected to one of the source and drain of the transistor 13. One of the source and drain of the transistor 13 is electrically connected to the gate of the transistor 14. The gate of the transistor 14 is electrically connected to one electrode of the capacitor 16. One of the source and drain of the transistor 14 is electrically connected to one of the source and drain of the transistor 15. Note that although Figure 2 The structure shown is that the cathode of the photoelectric conversion element 21 is electrically connected to one of the source and the drain of the transistor 12, and the anode of the photoelectric conversion element 21 is electrically connected to the wiring 47, but the anode of the photoelectric conversion element 21 can also be electrically connected to one of the source and the drain of the transistor 12, and the cathode of the photoelectric conversion element 21 can also be electrically connected to the wiring 47.

[0102] Here, a node to which the other of the source and the drain of the transistor 12 , one of the source and the drain of the transistor 13 , the gate of the transistor 14 , and one electrode of the capacitor 16 are electrically connected is referred to as a node FD.

[0103] The gate of the transistor 12 is electrically connected to the wiring 41. The gate of the transistor 13 is electrically connected to the wiring 42. The gate of the transistor 15 is electrically connected to the wiring 43. The other of the source and the drain of the transistor 13 is electrically connected to the wiring 44. The other of the source and the drain of the transistor 14 is electrically connected to the wiring 40. The other of the source and the drain of the transistor 15 is electrically connected to the wiring 45. The other electrode of the capacitor 16 is electrically connected to the wiring 46. The other electrode of the photoelectric conversion element 21 is electrically connected to the wiring 47.

[0104] Wiring 41, wiring 42, and wiring 43 respectively function as scanning lines for controlling the on / off of transistors 12, 13, and 15. Figure 2 Although not shown in the figure, the wiring 41 , the wiring 42 , and the wiring 43 are electrically connected to the gate driver circuit 33 .

[0105] A constant potential may be supplied to the wiring 44 to the wiring 47. For example, a power supply potential may be supplied. In this case, the wiring 44 to the wiring 47 are used as a power supply line. For example, a high potential may be supplied to the wiring 44 and the wiring 45, and a low potential may be supplied to the wiring 46 and the wiring 47. Here, the potential supplied to the wiring 44 is set to the potential VR. In addition, when the anode of the photoelectric conversion element 21 is electrically connected to one of the source and the drain of the transistor 12 and the cathode of the photoelectric conversion element 21 is electrically connected to the wiring 47, a high potential may be supplied to the wiring 45 and the wiring 47, and a low potential may be supplied to the wiring 44 and the wiring 46.

[0106] In this specification, etc., the low potential may be, for example, a ground potential or a negative potential. In addition, the high potential may be a potential higher than the low potential.

[0107] The transistor 12 is used as a transfer transistor that controls the transfer of the charge stored in the photoelectric conversion element 21 when the photoelectric conversion element 21 is exposed to light to the node FD. By turning on the transistor 12, the charge stored in the photoelectric conversion element 21 is transferred to the node FD. Therefore, the potential of the node FD becomes a potential corresponding to the illuminance of the light irradiated to the photoelectric conversion element 21, and the imaging data is written to the holding circuit 32. Then, by turning off the transistor 12, the imaging data written to the holding circuit 32 is held.

[0108] The transistor 13 is used as a reset transistor, which controls the resetting of the potential of the node FD. Before starting to expose the photoelectric conversion element 21, the transistors 12 and 13 are turned on, thereby resetting the charge stored in the photoelectric conversion element 21 and the node FD. Therefore, the potential of the node FD can be reset, for example, to the potential VR.

[0109] The transistor 14 is used as an amplifier transistor that amplifies the image pickup data held by the holding circuit 32 .

[0110] The transistor 15 has a function of controlling the reading of the imaging data held by the holding circuit 32. When the transistor 15 is in an on state, the potential of the wiring 45 is supplied to one of the source and the drain of the transistor 14, and a current corresponding to the potential of the node FD flows through the transistor 14. Therefore, the imaging data held by the holding circuit 32 is read out. Thus, the transistor 15 can be used as a selection transistor for selecting the holding circuit 32 from which the imaging data is read out.

[0111] The transistor 12 and the transistor 13 are preferably transistors with extremely low off-state current. Therefore, the leakage of the charge stored in the node FD can be suppressed, so that the potential of the node FD can be maintained for a long period of time. As a result, the imaging data can be maintained in the holding circuit 32 for a long period of time. Therefore, it is not necessary to read the imaging data immediately after writing the imaging data to the holding circuit 32.

[0112] As a transistor with extremely low off-state current, an OS transistor can be cited. In addition, an OS transistor also has a high withstand voltage feature. Therefore, in particular, by using an OS transistor as the transistor 12, a high voltage can also be supplied to the photoelectric conversion element 21.

[0113] Here, the transistors 12 to 15 are all provided in the layer 30. That is, the transistors 12 to 15 can be provided in the same layer. Thus, the transistors 12 to 15 can have the same structure. For example, OS transistors can be used as all the transistors in the transistors 12 to 15.

[0114] Figure 3 1 shows an example of a stacked structure of the photoelectric conversion element 21 and the holding circuit 32, and also shows an example of a structure of a pixel included in the imaging device 10. Figure 3 In order to facilitate understanding of the drawings and their descriptions, n is 2. That is, Figure 3 The photoelectric conversion element 21, the holding circuit 32_1 and the holding circuit 32_2 are shown. Figure 3 In the following drawings and the like, n may be 2.

[0115] like Figure 3 As shown, the holding circuit 32_1 and the holding circuit 32_2 can have the same structure. In addition, because the holding circuits 32_1 to 32_n can have the same structure, the holding circuits 32_1 to 32_n can be manufactured using the same mask. Therefore, even if n is increased, the increase in the number of masks used when manufacturing the camera device 10 can be suppressed. That is, even if the number of layers 30 is increased, the increase in the number of masks used when manufacturing the camera device 10 can be suppressed. Therefore, even if the number of layers 30 is increased, the significant increase in the manufacturing cost of the camera device 10 can be suppressed, and a cheap camera device 10 can be realized.

[0116] <Example 1 of the method of operation of the imaging device>

[0117] Figure 4 It shows that the pixel has Figure 3 A timing chart showing an example of the operating method of the imaging device 10 in the structure shown. Figure 4 In FIG. 1 , “H” indicates a high potential and “L” indicates a low potential. Note that the same description may be made for other drawings.

[0118] In addition, Figure 4 In the working method shown, although transistors 12 to 15 are all n-channel transistors, any or all of them may be p-channel transistors. Figure 4 The working method shown.

[0119] During the period T01, the potential of the wiring 41_1 and the potential of the wiring 42_1 are set to high potential. In addition, the potentials of the wiring 41_2, the wiring 42_2, the wiring 43_1, and the wiring 43_2 are set to low potential. As a result, the transistors 12_1 and 13_1 are turned on, and the charges stored in the photoelectric conversion element 21 and the node FD_1 are reset. Therefore, the potential of the node FD_2 is reset to the potential VR (reset operation).

[0120] During the period T02, the potential of the wiring 42_1 is set to a low potential. Therefore, the transistor 13_1 is in an off state, and the charge stored in the photoelectric conversion element 21 is transferred to the node FD_1 according to the illumination of the light irradiated to the photoelectric conversion element 21. Thus, the potential of the node FD_1 changes according to the illumination of the light irradiated to the photoelectric conversion element 21 (exposure operation). Therefore, the imaging device 10 obtains the imaging data, and the imaging data is written to the holding circuit 32_1. Specifically, one imaging data is written to the holding circuit 32_1.

[0121] In this specification and the like, for example, imaging data written to the holding circuit 32_1 may be described as first imaging data.

[0122] During the period T03, the potential of the wiring 41_1 is set to a low potential. Therefore, the transistor 12_1 is turned off, the exposure operation is completed, and the potential of the node FD_1 is held. That is, the image data is held in the holding circuit 32_1 (holding operation).

[0123] During the period T04, the potential of the wiring 41_2 and the potential of the wiring 42_2 are set to high potential. Therefore, the transistor 12_2 and the transistor 13_2 are turned on, and the charges accumulated in the photoelectric conversion element 21 and the node FD_2 are reset. Therefore, the potential of the node FD_2 is reset to the potential VR (reset operation).

[0124] During the period T05, the potential of the wiring 42_2 is set to a low potential. Therefore, the transistor 13_2 is in an off state, and the charge stored in the photoelectric conversion element 21 is transferred to the node FD_2 according to the illumination of the light irradiated to the photoelectric conversion element 21. Thus, the potential of the node FD_2 changes according to the illumination of the light irradiated to the photoelectric conversion element 21 (exposure operation). Therefore, the imaging device 10 obtains the imaging data, and the imaging data is written to the holding circuit 32_2.

[0125] During the period T06, the potential of the wiring 41_2 is set to a low potential. Therefore, the transistor 12_2 is turned off, the exposure operation is completed, and the potential of the node FD_2 is held. That is, the image data is held in the holding circuit 32_2 (holding operation).

[0126] During period T07, the potential of wiring 43_1 and the potential of wiring 43_2 are set to high potential. Therefore, transistor 15_1 and transistor 15_2 are in the on state, the potential of wiring 40_1 becomes a potential corresponding to the potential of node FD_1, and the potential of wiring 40_2 becomes a potential corresponding to the potential of node FD_2. That is, the imaging data held by the holding circuit 32_1 and the imaging data held by the holding circuit 32_2 are read out (reading operation). The imaging data read out from the holding circuit 32_1 is converted into digital data by the AD conversion circuit 35_1, and the digital data is output to the outside of the imaging device 10 as a signal OUT_1. In addition, the imaging data read out from the holding circuit 32_2 is converted into digital data by the AD conversion circuit 35_2, and the digital data is output to the outside of the imaging device 10 as a signal OUT_2.

[0127] exist Figure 4 In FIG. 1 , a digital signal corresponding to the image data read out from the holding circuit 32_1 is described as a signal IS_1, and a digital signal corresponding to the image data read out from the holding circuit 32_2 is described as a signal IS_2. Note that the same description may be made for other drawings.

[0128] In the period T08, the potential of the wiring 43_1 and the potential of the wiring 43_2 are set to low potentials. Therefore, the transistor 15_1 and the transistor 15_2 are turned off, and the read operation is completed. The above is an example of the operation method of the imaging device 10.

[0129] As described above, in period T07, the image data held by the holding circuit 32_1 and the image data held by the holding circuit 32_2 are read out. Figure 4 In the operation method shown, the image data held by the holding circuit 32_1 and the image data held by the holding circuit 32_2 can be read out at the same time.

[0130] As described above, the holding circuit 32 can hold the image data for a long period of time. Therefore, it is not necessary to read the image data from the holding circuit 32_1 immediately after the image pickup device 10 acquires one image data and writes it to the holding circuit 32_1, but it is possible to acquire n image data (in Figure 4 In other words, n pieces of image data can be read out at one time. Therefore, in the image pickup device 10, a plurality of image data can be acquired at short time intervals, compared with a case where acquisition and reading of one image data are performed alternately. Therefore, the image pickup device 10 can be used, for example, as a high-speed camera. In addition, by reading out the image data at one time, n pieces of image data can be acquired at short time intervals even without high-speed reading. Thus, the image pickup device 10 can be made low in power consumption while acquiring a plurality of image data at short time intervals.

[0131] As described above, the holding circuits 32_1 to 32_n are stacked one on another. Therefore, even when n pieces of image data are read out at once, image data corresponding to an image having the same resolution as when the image data are read out one by one can be obtained. Thus, the imaging device 10 can obtain a plurality of image data at short time intervals and obtain image data corresponding to an image with a high resolution.

[0132] <Configuration Example 2 of Imaging Device>

[0133] Figure 5 is a block diagram showing a configuration example of the imaging device 10, and is Figure 1 An example of a deformation of . Figure 1 In the imaging device 10 shown in FIG. 1 , the gate driver circuit 33, the source driver circuit 34, and the AD conversion circuit 35 are provided in the layer 30. Figure 5 In the illustrated imaging device 10 , the gate driver circuit 33 , the source driver circuit 34 , and the AD conversion circuit 35 are provided in the layer 20 .

[0134] In addition, Figure 5 The imaging device 10 of the structure shown in FIG. 1 includes a demultiplexer circuit 36 ​​and a multiplexer circuit 37 in the layer 20. The input terminal of the demultiplexer circuit 36 ​​is electrically connected to the gate driver circuit 33. The output terminal of the demultiplexer circuit 36 ​​is electrically connected to the holding circuit 32. Specifically, the output terminal of the demultiplexer circuit 36 ​​is electrically connected to the gate driver circuit 33. Figure 3 The wiring 41 to the wiring 43 shown in the figure are electrically connected. Therefore, the demultiplexer circuit 36 ​​can be provided between the gate driver circuit 33 and the holding circuit 32.

[0135] An input terminal of the multiplexer circuit 37 is electrically connected to the holding circuit 32 through a wiring 40. An output terminal of the multiplexer circuit 37 is electrically connected to the AD conversion circuit 35. Therefore, the multiplexer circuit 37 can be provided between the holding circuit 32 and the AD conversion circuit 35.

[0136] The demultiplexer circuit 36 ​​has a function of outputting the selection signal generated by the gate driver circuit 33 to any one of the holding circuits 32_1 to 32_n. In addition, the multiplexer circuit 37 has a function of selecting the imaging data to be supplied to the AD conversion circuit 35 from the imaging data read out from the holding circuits 32_1 to 32_n. Figure 5 , n=2.

[0137] When the camera device 10 includes the demultiplexer circuit 36 ​​and the multiplexer circuit 37, the number of gate driver circuits 33, the number of source driver circuits 34, and the number of AD conversion circuits 35 can be less than n. Figure 5As shown, one gate driver circuit 33, one source driver circuit 34, and one AD conversion circuit 35 can be provided in layer 20. In addition, any or all of the gate driver circuit 33, the source driver circuit 34, and the AD conversion circuit 35 can be provided in layer 20 as two or more circuits.

[0138] By reducing the number of gate driver circuits 33 , the number of source driver circuits 34 , and the number of AD conversion circuits 35 included in the imaging device 10 , it is possible to reduce power consumption of the imaging device 10 .

[0139] In addition, any of the gate driver circuit 33, the source driver circuit 34, and the AD conversion circuit 35 may be provided in the layer 30. For example, the gate driver circuit 33 may be provided in the layer 30, and the source driver circuit 34 and the AD conversion circuit 35 may be provided in the layer 20. In this case, the demultiplexer circuit 36 ​​does not necessarily need to be provided in the imaging device 10.

[0140] <An example of the operating method of the imaging device 2>

[0141] Figure 6 It shows that the pixel has Figure 3 The camera device 10 has the structure shown in FIG. Figure 5 A timing chart showing an example of the operating method of the imaging device 10 in the structure shown. Figure 6 The operation during period T11 to period T16 shown is similar to Figure 4 The operations in the periods T01 to T06 shown are the same.

[0142] During the period T17, the potential of the wiring 43_1 is set to a high potential. Therefore, the transistor 15_1 is in an on state, and the potential of the wiring 40_1 becomes a potential corresponding to the potential of the node FD_1. That is, the imaging data held by the holding circuit 32_1 is read out (reading operation). The imaging data read out from the holding circuit 32_1 is supplied to the AD conversion circuit 35 through the multiplexer circuit 37, and the imaging data is converted into digital data by the AD conversion circuit 35. The digital data is output to the outside of the imaging device 10 as the signal OUT. That is, the signal IS_1 is output from the AD conversion circuit 35 to the outside of the imaging device 10.

[0143] In the period T18, the potential of the wiring 43_1 is set to a low potential. Therefore, the transistor 15_1 is turned off, and the reading operation of the imaging data held by the holding circuit 32_1 is completed.

[0144] During period T19, the potential of wiring 43_2 is set to a high potential. Therefore, transistor 15_2 is in an on state, and the potential of wiring 40_2 becomes a potential corresponding to the potential of node FD_2. That is, the imaging data held by holding circuit 32_2 is read out (reading operation). The imaging data read out from holding circuit 32_2 is supplied to AD conversion circuit 35 through multiplexer circuit 37, and the imaging data is converted into digital data through AD conversion circuit 35. The digital data is output to the outside of imaging device 10 as signal OUT. That is, signal IS_2 is output from AD conversion circuit 35 to the outside of imaging device 10.

[0145] During the period T20, the potential of the wiring 43_2 is set to a low potential. Therefore, the transistor 15_2 is turned off, and the reading operation of the image data held by the holding circuit 32_2 is completed. The above is an example of the operation method of the image pickup device 10.

[0146] As described above, during the period T17, the image data held by the holding circuit 32_1 is read out, and during the period T18, the image data held by the holding circuit 32_2 is read out. Figure 6 In the operation method shown, the image data held by the holding circuit 32_1 and the image data held by the holding circuit 32_2 can be read out in sequence.

[0147] exist Figure 6 In the working method shown in FIG. 1 , since the image data is read out sequentially, the reading of the image data is similar to that of Figure 4 It takes more time than the case where the camera data is read out simultaneously as shown. Figure 4 The working method is the same as shown, Figure 6 The working method shown in FIG. 1 can also read out the image data after acquiring n image data. Figure 4 The working method shown in the figure makes the camera device 10 work in the same way. Figure 6 Even when the imaging device 10 is operated by the operating method shown, a plurality of imaging data can be acquired at short time intervals.

[0148] As described above, the holding circuit 32 can hold the image data for a long period of time. Therefore, even when the image data is read out sequentially, it is possible to suppress a decrease in the image quality corresponding to the read image data compared to the case where the image data is read out simultaneously.

[0149] <Configuration Example 3 of Imaging Device>

[0150] Figure 7 is a block diagram showing a configuration example of the imaging device 10, and is Figure 1 An example of a deformation of . Figure 1In the imaging device 10 shown in the figure, the layer 30 including the holding circuit 32 is provided above the layer 20 including the photoelectric conversion element 21. On the other hand, Figure 7 The camera device 10 shown is Figure 1 The camera device 10 shown differs in that a layer 30 including a holding circuit 32 is arranged below the layer 20 .

[0151] <How the camera works>

[0152] Fig. 8A and Figure 8B 1 is a diagram for explaining the operation of the holding circuits 32_i (i is an integer greater than 1 and less than n) provided in a matrix in the imaging device 10. That is, Fig. 8A and Figure 8B This is a diagram for explaining an operation method of the holding circuit 32 when focusing on the holding circuits 32 provided in a matrix in one layer 30 .

[0153] Fig. 8A This is a diagram for explaining the operation of the rolling shutter method, in which an exposure operation 51, a holding operation 52, and a read operation 53 are performed for each row of the holding circuit 32_i. Figure 8B 3 is a diagram for explaining the operation of the global shutter method. The exposure operation 51 is performed on all rows of the holding circuit 32_i at the same time, and the reading operation 53 is performed on each row in sequence. When the rolling shutter method is adopted, the simultaneity of imaging is lost, so the image distortion occurs when the photographed object moves. On the other hand, when the global shutter method is adopted, the simultaneity of imaging can be ensured, so it is easy to obtain an image with less distortion even when the photographed object moves. Therefore, by adopting the global shutter method, the camera device 10 can obtain imaging data corresponding to a high-quality image.

[0154] On the other hand, when using the global shutter method, Figure 8B As shown, the more rows of the holding circuit 32_i, the longer the period of holding operation 52. However, as described above, when the holding circuit 32 includes a transistor with an extremely low off-state current such as an OS transistor, the holding circuit 32 can hold the image data for a long period of time. Therefore, a global shutter method can be adopted. As a result, the camera device 10 can obtain image data corresponding to a high-quality image.

[0155] <Pixel Structure Example 1>

[0156] Fig. 9 1 is a diagram for explaining a specific structural example of a pixel included in the imaging device 10, and shows a cross-sectional structural example of the photoelectric conversion element 21 and a cross-sectional structural example of the transistor 12_1, the transistor 13_1, the transistor 12_2, and the transistor 13_2 in the channel length direction. Fig. 9In FIG. 1 , transistors 12 and 13 are OS transistors. Note that a part of the conductive layer and insulating layer shown in the figure may not be provided, and each layer may include a conductive layer and insulating layer not shown in the figure.

[0157] exist Fig. 9 In the embodiment, layer 30 is arranged above layer 20. Thus, for example, Fig. 9 The structure shown is used for Figure 1 The camera device 10 is shown.

[0158] exist Fig. 9 In the pixel shown, the photoelectric conversion element 21 is provided on the insulating layer 102. As the insulating layer 102, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, and aluminum nitride can be used. Fig. 9 The other insulating layers shown may also be made of the same material as the insulating layer 102 .

[0159] As the photoelectric conversion element 21, for example, a photodiode having two terminals can be used. As the photodiode, a pn-type photodiode using single-crystal silicon, a pin-type photodiode using an amorphous silicon thin film, a microcrystalline silicon thin film, or a polycrystalline silicon thin film can be used.

[0160] Fig. 9 A structural example is shown in which the photoelectric conversion element 21 is a pn-type photodiode using a single crystal silicon substrate. Fig. 9 The photoelectric conversion element 21 shown may have regions 104, 106, 108, and 110. For example, region 104 may be a p+ region, region 106 may be a p- region, region 108 may be an n- region, and region 110 may be a p+ region.

[0161] An insulating layer 112 is provided on the photoelectric conversion element 21, and an insulating layer 114 is provided on the insulating layer 112. The insulating layer 112 can be used as a planarization film for planarizing a step generated by the photoelectric conversion element 21 provided thereunder. For example, in order to improve the planarity of the top surface of the insulating layer 112, the top surface can also be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like.

[0162] As the insulating layer 114, a film having a barrier property that can prevent impurities such as hydrogen from diffusing from the photoelectric conversion element 21 and the like into the transistors 12_1 to 15_1 and the like provided in the holding circuit 32_1 is preferably used. Fig. 9 The transistor 14_1 and the transistor 15_1 are not shown.

[0163] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a chemical vapor deposition (CVD) method can be used. Here, by diffusing hydrogen into the OS transistor used as the transistor 12 and the transistor 13, the characteristics of the OS transistor may be degraded. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the photoelectric conversion element 21 and the transistor 12_1 and the transistor 13_1. Specifically, the film that suppresses the diffusion of hydrogen can be a film with a small amount of hydrogen released.

[0164] The amount of hydrogen released can be measured, for example, by thermal desorption spectroscopy (TDS). For example, when the amount of hydrogen released in the insulator 324 is converted to the amount per unit area of ​​the insulating layer 114 when the film surface temperature in the TDS analysis is in the range of 50°C to 500°C, the amount of hydrogen released in the insulator 324 is 10×10 15 atoms / cm 2 Below, preferably 5×10 15 atoms / cm 2 The following is enough.

[0165] An insulating layer 116_1 is disposed on the insulating layer 114 , and a transistor 12_1 and a transistor 13_1 are disposed on the insulating layer 116_1 .

[0166] Fig. 10A is a cross-sectional view in the channel length direction of a transistor 300 which can be used as the transistor 12 and the transistor 13. Fig. 10B It is a cross-sectional view of the transistor 300 in the channel width direction. The transistor 300 includes an insulating layer 118 arranged on the insulating layer 116, an insulating layer 120 arranged on the insulating layer 118, an insulating layer 122 arranged on the insulating layer 120, a metal oxide 330a arranged on the insulating layer 122, a metal oxide 330b arranged on the metal oxide 330a, a conductive layer 342a and a conductive layer 342b arranged to be separated from each other on the metal oxide 330b, an insulating layer 124 arranged on the conductive layer 342a and the conductive layer 342b and overlapping to form an opening between the conductive layer 342a and the conductive layer 342b, a conductive layer 360 arranged in the opening, an insulating layer 350 arranged between the metal oxide 330b, the conductive layer 342a, the conductive layer 342b, and the insulating layer 124 and the conductive layer 360, and a metal oxide 330c arranged between the metal oxide 330b, the conductive layer 342a, the conductive layer 342b, and the insulating layer 124 and the insulating layer 350.

[0167] In addition, if Fig. 10A and Fig. 10BAs shown in FIG. 1 , an insulating layer 123 is preferably disposed between the metal oxide 330a, the metal oxide 330b, the conductive layer 342a, the conductive layer 342b, and the insulating layer 124. Fig. 10A and Fig. 10B As shown in FIG. 3 , the conductive layer 360 preferably includes a conductive layer 360a disposed inside the insulating layer 350 and a conductive layer 360b embedded inside the conductive layer 360a. Fig. 10A and Fig. 10B As shown, an insulating layer 126 is preferably disposed on the insulating layer 124 , the conductive layer 360 , and the insulating layer 350 .

[0168] Note that hereinafter, the metal oxide 330a, the metal oxide 330b, and the metal oxide 330c may be collectively referred to as a metal oxide 330. Also, the conductive layer 342a and the conductive layer 342b may be collectively referred to as a conductive layer 342.

[0169] In transistor 300, three layers of metal oxide 330a, metal oxide 330b, and metal oxide 330c are stacked in the region where the channel is formed and in the vicinity thereof, but the present invention is not limited to this. For example, a single layer of metal oxide 330b, a two-layer structure of metal oxide 330b and metal oxide 330a, a two-layer structure of metal oxide 330b and metal oxide 330c, or a stacked structure of four or more layers may be provided. In addition, in transistor 300, conductive layer 360 has a two-layer structure, but the present invention is not limited to this. For example, conductive layer 360 may also have a single-layer structure or a stacked structure of three or more layers. Note that, Fig. 10A , Fig. 10B The structure of the transistor 300 shown is only an example and is not limited to the above structure, and an appropriate transistor can be used according to the circuit structure or driving method.

[0170] Here, the conductive layer 360 is used as the gate of the transistor 300. In addition, the conductive layer 342a is used as one of the source and drain of the transistor 300, and the conductive layer 342b is used as the other of the source and drain of the transistor 300. As described above, the conductive layer 360 is buried in the opening of the insulating layer 124 and in the area sandwiched between the conductive layer 342a and the conductive layer 342b. The configuration of the conductive layer 360, the conductive layer 342a, and the conductive layer 342b relative to the opening of the insulating layer 124 is selected in a self-aligned manner. In other words, in the transistor 300, the gate can be configured in a self-aligned manner between the source and the drain. Thus, the conductive layer 360 can be formed in a manner without providing room for alignment, so that the occupied area of ​​the transistor 300 can be reduced. Thus, miniaturization and high integration of the camera device can be achieved.

[0171] Furthermore, since the conductive layer 360 is formed in a self-aligned manner in the region between the conductive layer 342a and the conductive layer 342b, the conductive layer 360 does not include a region overlapping with the conductive layer 342a or the conductive layer 342b. Thus, the parasitic capacitance formed between the conductive layer 360 and the conductive layer 342a and the conductive layer 342b can be reduced. Therefore, the switching speed of the transistor 300 can be increased, thereby improving the frequency characteristics of the imaging device of one embodiment of the present invention.

[0172] The insulating layer 350 serves as a gate insulating film.

[0173] Here, an insulator containing oxygen exceeding the stoichiometric composition is preferably used for the insulating layer 122 in contact with the metal oxide 330. In other words, it is preferable to form an excess oxygen region in the insulating layer 122. By providing the insulator containing excess oxygen in contact with the metal oxide 330, oxygen vacancies in the metal oxide 330 can be reduced, thereby improving the reliability of the transistor 300.

[0174] Specifically, as an insulator having an excess oxygen region, an oxide material from which a portion of oxygen is released by heating is preferably used. An oxide from which oxygen is released by heating means that the amount of oxygen released in terms of oxygen atoms in TDS analysis is 1.0×10 18 atoms / cm 3 Above, preferably 1.0×10 19 atoms / cm 3 More preferably, 2.0×10 19 atoms / cm 3 Above, or 3.0×10 20 atoms / cm 3 In addition, the surface temperature of the film when performing the above-mentioned TDS analysis is preferably in the range of 100° C. to 700° C., or 100° C. to 400° C.

[0175] When the insulating layer 122 has an excess oxygen region, the insulating layer 120 preferably has a function of suppressing diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (making it difficult for the oxygen to permeate).

[0176] When the insulating layer 120 has a function of suppressing diffusion of oxygen or impurities, oxygen included in the metal oxide 330 is preferably not diffused toward the insulating layer 118 .

[0177] As the insulating layer 120, for example, a single layer or a stack of insulators containing so-called high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3) or (Ba, Sr)TiO3 (BST) is preferably used. When miniaturization and high integration of transistors are carried out, problems such as leakage current sometimes occur due to the thin film of the gate insulating film. By using a high-k material as an insulator used as a gate insulating film, the gate potential when the transistor is operating can be reduced while maintaining the physical thickness.

[0178] In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium as an insulating material having a function of suppressing the diffusion of impurities and oxygen (not allowing the above oxygen to permeate easily). As an insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. are preferably used. When the insulating layer 120 is formed using such a material, the insulating layer 120 is used as a layer that suppresses the release of oxygen from the metal oxide 330 or the entry of impurities such as hydrogen into the metal oxide 330 from the surrounding part of the transistor 300.

[0179] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. In addition, the insulator may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the insulator.

[0180] The insulating layer 118 preferably has thermal stability. For example, silicon oxide and silicon oxynitride are preferred because they have thermal stability. In addition, by combining an insulator of a high-k material with silicon oxide or silicon oxynitride, an insulating layer 118 having a stacked structure with thermal stability and a high relative dielectric constant can be formed.

[0181] The insulating layer 118, the insulating layer 120, and the insulating layer 122 may have a stacked structure of two or more layers. In this case, the stacked structure is not limited to a stacked structure composed of the same material, and a stacked structure composed of different materials may be used.

[0182] In the transistor 300, a metal oxide used as an oxide semiconductor is preferably used for the metal oxide 330 including the channel formation region. For example, a metal oxide such as In-M-Zn oxide (the element M is one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium) is preferably used as the metal oxide 330. In addition, In-Ga oxide and In-Zn oxide may also be used as the metal oxide 330.

[0183] The metal oxide used as the channel formation region in the metal oxide 330 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0184] In the metal oxide 330, when the metal oxide 330a is provided below the metal oxide 330b, impurities can be prevented from diffusing from the structure formed below the metal oxide 330a to the metal oxide 330b. When the metal oxide 330c is provided above the metal oxide 330b, impurities can be prevented from diffusing from the structure formed above the metal oxide 330c to the metal oxide 330b.

[0185] In addition, the metal oxide 330 preferably has a stacked structure of metal oxides in which the atomic number ratios of each metal atom are different from each other. Specifically, the atomic number ratio of the element M in the constituent elements of the metal oxide used for the metal oxide 330a is preferably greater than the atomic number ratio of the element M in the constituent elements of the metal oxide used for the metal oxide 330b. In addition, the atomic number ratio of the element M relative to In in the metal oxide used for the metal oxide 330a is preferably greater than the atomic number ratio of the element M relative to In in the metal oxide used for the metal oxide 330b. In addition, the atomic number ratio of In in the metal oxide used for the metal oxide 330b is preferably greater than the atomic number ratio of In in the metal oxide used for the metal oxide 330a. In addition, the metal oxide 330c can use a metal oxide that can be used for the metal oxide 330a or the metal oxide 330b.

[0186] It is preferred that the energy of the conduction band bottom of metal oxide 330a and metal oxide 330c is higher than the energy of the conduction band bottom of metal oxide 330b. In other words, the electron affinity of metal oxide 330a and metal oxide 330c is preferably lower than the electron affinity of metal oxide 330b.

[0187] Here, in the junction of metal oxide 330a, metal oxide 330b and metal oxide 330c, the energy level of the conduction band bottom changes smoothly. In other words, the above situation can also be expressed as the energy level of the conduction band bottom of the junction of metal oxide 330a, metal oxide 330b and metal oxide 330c continuously changes or continuously joins. For this reason, it is preferred to reduce the defect state density of the mixed layer formed at the interface between metal oxide 330a and metal oxide 330b and the interface between metal oxide 330b and metal oxide 330c.

[0188] Specifically, by making the metal oxide 330a and the metal oxide 330b, and the metal oxide 330b and the metal oxide 330c contain a common element (as a main component) in addition to oxygen, a mixed layer with a low defect state density can be formed. For example, when the metal oxide 330b is an In-Ga-Zn oxide, In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, etc. are preferably used as the metal oxide 330a and the metal oxide 330c.

[0189] At this time, the main path of the carrier is the metal oxide 330b. By making the metal oxide 330a and the metal oxide 330c have the above structure, the defect state density at the interface between the metal oxide 330a and the metal oxide 330b and the interface between the metal oxide 330b and the metal oxide 330c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the on-state current of the transistor 300 can be increased.

[0190] A conductive layer 342 a used as one of a source electrode and a drain electrode and a conductive layer 342 b used as the other of the source electrode and the drain electrode are provided on the metal oxide 330 b .

[0191] As the conductive layer 342, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum, an alloy containing the above metal elements as a component, or an alloy of the above metal elements in combination. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. In addition, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are conductive materials that are not easily oxidized or materials that maintain conductivity even when absorbing oxygen, so they are preferable.

[0192] In addition, if Fig. 10A As shown, a region 343 (region 343a and region 343b) is sometimes formed as a low resistance region at the interface between the metal oxide 330 and the conductive layer 342 and in the vicinity thereof. In this case, the region 343a is used as one of the source region and the drain region, and the region 343b is used as the other of the source region and the drain region. In addition, a channel formation region is formed in a region sandwiched between the region 343a and the region 343b.

[0193] By forming the conductive layer 342 in contact with the metal oxide 330, the oxygen concentration in the region 343 may be reduced. In addition, a metal compound layer including a component of the metal contained in the conductive layer 342 and the metal oxide 330 may be formed in the region 343. In this case, the carrier density in the region 343 increases, and the region 343 becomes a low resistance region.

[0194] The insulating layer 123 is provided so as to cover the conductive layer 342 and suppress oxidation of the conductive layer 342. In this case, the insulating layer 123 may be provided so as to cover the side surface of the metal oxide 330 and to be in contact with the insulating layer 122.

[0195] As the insulating layer 123, a metal oxide containing one or two or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like can be used.

[0196] In particular, as the insulating layer 123, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc., which are insulators containing an oxide of one or both of aluminum and hafnium, are preferably used. In particular, hafnium aluminate has higher heat resistance than the hafnium oxide film. Therefore, it is not easy to crystallize in the heat treatment of the subsequent process, so it is preferred. In addition, when the conductive layer 342 is a material with oxidation resistance or its conductivity does not significantly decrease even if oxygen is absorbed, it is not necessary to provide the insulating layer 123. It can be designed appropriately according to the required transistor characteristics.

[0197] The insulating layer 350 is used as a gate insulating film. The insulating layer 350 is preferably arranged in contact with the inner side (top surface and side surface) of the metal oxide 330c. The insulating layer 350 is preferably formed using an insulator that releases oxygen by heating. For example, the amount of oxygen released in thermal desorption spectroscopy (TDS analysis) is 1.0×10 18 atoms / cm 3 Above, preferably 1.0×10 19 atoms / cm 3 More preferably, 2.0×10 19 atoms / cm 3 Above, or 3.0×10 20 atoms / cm 3 In addition, the surface temperature of the film when performing the above-mentioned TDS analysis is preferably in the range of 100° C. to 700° C.

[0198] Specifically, silicon oxide containing excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, and silicon oxide having pores can be used. In particular, silicon oxide and silicon oxynitride are preferred because they have thermal stability.

[0199] By providing an insulator that releases oxygen by heating in contact with the top surface of the metal oxide 330c as the insulating layer 350, oxygen can be efficiently supplied from the insulating layer 350 to the channel formation region of the metal oxide 330b through the metal oxide 330c. In addition, as with the insulating layer 122, it is preferable to reduce the concentration of impurities such as water and hydrogen in the insulating layer 350. The thickness of the insulating layer 350 is preferably not less than 1 nm and not more than 20 nm.

[0200] In addition, in order to efficiently supply excess oxygen contained in the insulating layer 350 to the metal oxide 330, a metal oxide may be provided between the insulating layer 350 and the conductive layer 360. The metal oxide preferably suppresses the diffusion of oxygen from the insulating layer 350 to the conductive layer 360. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of excess oxygen from the insulating layer 350 to the conductive layer 360 is suppressed. In other words, the reduction of excess oxygen supplied to the metal oxide 330 can be suppressed. In addition, oxidation of the conductive layer 360 due to excess oxygen can be suppressed. As the metal oxide, a material that can be used for the insulating layer 123 can be used.

[0201] exist Fig. 10A and Fig. 10B In the embodiment, the conductive layer 360 used as the gate has a two-layer structure, but may also have a single-layer structure or a stacked-layer structure of three or more layers.

[0202] As the conductive layer 360a, it is preferred to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. In addition, it is preferred to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). By making the conductive layer 360a have a function of suppressing the diffusion of oxygen, it is possible to suppress the decrease in conductivity due to oxidation of the conductive layer 360b caused by the oxygen contained in the insulating layer 350. As a conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide, etc., are preferably used.

[0203] As the conductive layer 360b, a conductive material mainly composed of tungsten, copper or aluminum is preferably used. Since the conductive layer 360b is also used as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material mainly composed of tungsten, copper or aluminum can be used. The conductive layer 360b can also have a laminated structure, for example, a laminated structure of titanium, titanium nitride and the above conductive materials can be used.

[0204] The insulating layer 124 is provided on the conductive layer 342 via the insulating layer 123. The insulating layer 124 preferably has an excess oxygen region. For example, the insulating layer 124 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide with pores, or resin. In particular, silicon oxide and silicon oxynitride are thermally stable and therefore are preferred. In particular, silicon oxide and silicon oxide with pores are preferred because they are easy to form an excess oxygen region in the subsequent process.

[0205] The insulating layer 124 preferably has an excess oxygen region. By providing the insulating layer 124 that releases oxygen by heating in contact with the metal oxide 330c, the oxygen in the insulating layer 124 can be efficiently supplied to the metal oxide 330b through the metal oxide 330c. In addition, it is preferable to reduce the concentration of impurities such as water or hydrogen in the insulating layer 124.

[0206] The opening of the insulating layer 124 is formed so as to overlap with the region between the conductive layer 342a and the conductive layer 342b. Thus, the conductive layer 360 is embedded in the opening of the insulating layer 124 and the region between the conductive layer 342a and the conductive layer 342b.

[0207] When miniaturizing the imaging device, the gate length needs to be shortened, but it is necessary to prevent the conductivity of the conductive layer 360 from decreasing. For this reason, when the thickness of the conductive layer 360 is increased, the conductive layer 360 may have a shape with a high aspect ratio. In this embodiment, since the conductive layer 360 is buried in the opening of the insulating layer 124, even if the conductive layer 360 has a shape with a high aspect ratio, the conductive layer 360 does not collapse during the process.

[0208] The insulating layer 126 is preferably provided so as to be aligned with the top surface of the insulating layer 124, the top surface of the conductive layer 360, and the top surface of the insulating layer 350. By forming the insulating layer 126 by sputtering, an excess oxygen region can be formed in the insulating layer 350 and the insulating layer 124. Thus, oxygen can be supplied to the metal oxide 330 from the excess oxygen region.

[0209] For example, as the insulating layer 126, a metal oxide containing one or two or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like can be used.

[0210] In particular, aluminum oxide has high barrier properties and can inhibit the diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by sputtering can be used as an oxygen supply source while also functioning as a barrier film for impurities such as hydrogen.

[0211] In addition, an insulating layer 128 serving as an interlayer film is preferably provided over the insulating layer 126. As with the insulating layer 122 and the like, the concentration of impurities such as water and hydrogen in the insulating layer 128 is preferably low.

[0212] like Fig. 9 As shown, the insulating layer 126_1 and the insulating layer 128_1 are provided with openings reaching the conductive layer 202_1 and the conductive layer 204_1, and the conductive layer 130_1 is provided in such a manner as to fill the openings. In addition, the insulating layer 123_1, the insulating layer 124_1, the insulating layer 126_1, and the insulating layer 128_1 are provided with openings reaching the conductive layer 206_1, the openings reaching the conductive layer 208_1, and the openings reaching the conductive layer 210_1, and the conductive layer 130_1 is provided in such a manner as to fill the openings. Here, the conductive layer 202_1 and the conductive layer 204_1 are equivalent to Fig. 10A and Fig. 10B The conductive layer 360, conductive layer 206_1, conductive layer 208_1 and conductive layer 210_1 are equivalent to Fig. 10A Conductive layer 342a or conductive layer 342b is shown.

[0213] like Fig. 10A As shown, the conductive layer 130 may have a two-layer structure of a conductive layer 130a and a conductive layer 130b. As the material of the conductive layer 130a and the conductive layer 130b, a single layer or a stacked layer of a conductive material such as a metal material, an alloy material, a metal nitride material or a metal oxide material may be used. It is preferred to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is particularly preferred. Alternatively, it is preferred to use a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be reduced. The conductive layer 130 may have a single-layer structure or a stacked structure of more than three layers.

[0214] Conductive layer 131, conductive layer 132, conductive layer 134, conductive layer 136, conductive layer 138, and conductive layer 140 are provided so as to have a region in contact with conductive layer 130_1. Region 108 and conductive layer 206_1 are electrically connected through conductive layer 130_1 and conductive layer 131. Furthermore, conductive layer 132 is electrically connected to conductive layer 202_1 through conductive layer 130_1. Conductive layer 134 is electrically connected to conductive layer 210_1 through conductive layer 130_1. Conductive layer 136 is electrically connected to conductive layer 204_1 through conductive layer 130_1. Conductive layer 138 is electrically connected to conductive layer 208_1 through conductive layer 130_1. Conductive layer 140 is electrically connected to region 110 through conductive layer 130_1.

[0215] The conductive layer 132 may be Figure 3 The conductive layer 136 may be a portion of the wiring 41_1 shown. Figure 3The conductive layer 138 may be a portion of the wiring 42_1 shown. Figure 3 The conductive layer 140 may be a portion of the wiring 44_1 shown. Figure 3 A portion of wiring 47 is shown.

[0216] As the conductive layers 131, 132, 134, 136, 138, and 140, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above elements (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film), etc. can be used. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide added with silicon oxide can be used.

[0217] exist Fig. 9 In the embodiment, the conductive layer 131, the conductive layer 132, the conductive layer 134, the conductive layer 136, the conductive layer 138, and the conductive layer 140 have a single-layer structure, but the present invention is not limited thereto and may have a stacked structure of two or more layers. For example, a conductor having high compactness with the conductor having a barrier property and the conductor having a high conductivity may be formed between the conductor having a barrier property and the conductor having a high conductivity.

[0218] An insulating layer 142 is provided over the insulating layer 128_1, the conductive layer 131, the conductive layer 132, the conductive layer 134, the conductive layer 136, the conductive layer 138, and the conductive layer 140. The insulating layer 142 can have the same structure as the insulating layer 112.

[0219] An insulating layer 144 is provided over the insulating layer 142. The insulating layer 144 can have the same structure as the insulating layer 114. Therefore, the insulating layer 144 can have a barrier property against hydrogen and the like, and degradation of characteristics of the OS transistor provided in the layer 30_2 can be suppressed.

[0220] The insulating layer 116_2 is provided on the insulating layer 144, and the transistor 12_2 and the transistor 13_2 are provided on the insulating layer 116_2. As described above, the transistor 12_2 and the transistor 13_2 can be used. Fig. 10A and Fig. 10B The transistor 300 is shown. Thus, the transistor 12_1, the transistor 13_1, the transistor 12_2, and the transistor 13_2 can have the same structure.

[0221] exist Fig. 9 In the embodiment, the conductive layer 202_2 and the conductive layer 204_2 are equivalent to Fig. 10A and Fig. 10BThe conductive layer 360, conductive layer 206_2, conductive layer 208_2 and conductive layer 210_2 are equivalent to Fig. 10A Conductive layer 342a or conductive layer 342b is shown.

[0222] Conductive layer 161, conductive layer 162, conductive layer 164, conductive layer 166, conductive layer 168, and conductive layer 170 are provided so as to have a region in contact with conductive layer 130_2. Region 108 and conductive layer 206_2 are electrically connected through conductive layer 130_1, conductive layer 131, conductive layer 130_2, and conductive layer 161. In addition, conductive layer 162 is electrically connected to conductive layer 202_2 through conductive layer 130_2. Conductive layer 164 is electrically connected to conductive layer 210_2 through conductive layer 130_2. Conductive layer 166 is electrically connected to conductive layer 204_2 through conductive layer 130_2. Conductive layer 168 is electrically connected to conductive layer 208_2 through conductive layer 130_2. Conductive layer 170 is electrically connected to region 110 through conductive layer 130_2, conductive layer 140, and conductive layer 130_1.

[0223] The conductive layer 162 may be Figure 3 The conductive layer 166 may be a portion of the wiring 41_2 shown. Figure 3 The conductive layer 168 may be a portion of the wiring 42_2 shown. Figure 3 The conductive layer 170 may be a portion of the wiring 44_2 shown. Figure 3 A portion of wiring 47 is shown.

[0224] Conductive layers 161 , 162 , 164 , 166 , 168 , and 170 may have the same structure as conductive layers 131 , 132 , 134 , 136 , 138 , and 140 .

[0225] An insulating layer 172 is provided over insulating layer 128_2, conductive layer 161, conductive layer 162, conductive layer 164, conductive layer 166, conductive layer 168, and conductive layer 170. Insulating layer 172 may have the same structure as insulating layer 112 and insulating layer 142. Figure 1 Description of a configuration example of a pixel in the imaging device 10 shown in FIG. 1 .

[0226] As described above, the holding circuit 32_1 disposed on the layer 30_1 and the holding circuit 32_2 disposed on the layer 30_2 may have the same structure. Fig. 9As shown, for example, conductive layer 202_1 may have an area overlapping with conductive layer 202_2, conductive layer 204_1 may have an area overlapping with conductive layer 204_2, conductive layer 206_1 may have an area overlapping with conductive layer 206_2, conductive layer 208_1 may have an area overlapping with conductive layer 208_2, and conductive layer 210_1 may have an area overlapping with conductive layer 210_2. In addition, conductive layer 130_1 may have an area overlapping with conductive layer 130_2. In addition, conductive layer 131 may have an area overlapping with conductive layer 161, conductive layer 132 may have an area overlapping with conductive layer 162, conductive layer 134 may have an area overlapping with conductive layer 164, conductive layer 136 may have an area overlapping with conductive layer 166, conductive layer 138 may have an area overlapping with conductive layer 168, and conductive layer 140 may have an area overlapping with conductive layer 170.

[0227] Therefore, even if a material shielding visible light is used as the conductive layer, the aperture ratio of the imaging device 10 can be suppressed from decreasing compared to the case of only one layer 30. Therefore, the imaging device of one embodiment of the present invention can acquire a plurality of imaging data at short time intervals and acquire imaging data corresponding to high-quality images.

[0228] In addition, the holding circuit 32_2 and the holding circuit 32_1 can be manufactured using the same mask. Therefore, the number of masks used when manufacturing the imaging device 10 can be suppressed from being greater than the number of masks used when there is only one layer 30. Thus, a significant increase in the manufacturing cost of the imaging device 10 can be suppressed compared to the case where there is only one layer 30, and a low-cost imaging device 10 can be realized.

[0229] <Pixel Structure Example 2>

[0230] Fig.11A is a diagram for explaining a specific structural example of pixels included in the imaging device 10, and is Fig. 9 Examples of variations of the structure shown. Fig.11A In the embodiment, layer 30 is arranged below layer 20. Thus, for example, Fig.11A The structure shown is used for Figure 7 The camera device 10 is shown.

[0231] exist Fig.11A In the pixel shown, an insulating layer 112 is disposed on the substrate 100, an insulating layer 114 is disposed on the insulating layer 112, and a layer 30 is disposed on the insulating layer 114. For example, the substrate 100 may be a substrate containing silicon, such as a single crystal silicon substrate.

[0232] In addition, an insulating layer 173 is disposed on the insulating layer 172. The insulating layer 173 may have Fig. 9The insulating layer 114 shown has the same structure.

[0233] The photoelectric conversion element 21 is provided on the insulating layer 173. The photoelectric conversion element 21 includes a conductive layer 176, a photoelectric conversion layer 182, and a conductive layer 184. The conductive layer 176 serves as one electrode of the photoelectric conversion element 21, and the conductive layer 184 serves as the other electrode of the photoelectric conversion element 21.

[0234] Insulating layer 173 and insulating layer 172 are provided with openings that reach conductive layer 161, and conductive layer 176 can be formed so as to fill the openings. Thus, one of the source and drain of transistor 12 is electrically connected to one electrode of photoelectric conversion element 21. For example, a conductive layer having the same structure as conductive layer 130 may be provided in the openings, and conductive layer 176 may be provided so as to have a region in contact with the conductive layer.

[0235] The conductive layer 178 is provided in the layer 20 in a manner separated from the conductive layer 176. For example, the conductive layer 178 and the conductive layer 176 can be formed using the same material and the same process. Figure 3 The conductive layer 184 is a portion of the wiring 47 shown. Furthermore, the conductive layer 184 may be provided so as to have a region in contact with the conductive layer 178. Thus, the other electrode of the photoelectric conversion element 21 may be electrically connected to the wiring 47. In addition, the conductive layer 178 and the conductive layer 184 may not be in direct contact but may be electrically connected via another conductive layer.

[0236] The photoelectric conversion layer 182 may include a selenium-based material. The photoelectric conversion element 21 using a selenium-based material has a high external quantum efficiency for visible light. In addition, since the light absorption coefficient of the selenium-based material is high, it has the advantage of being easy to form the photoelectric conversion layer 182 thinner. By using a selenium-based material for the photoelectric conversion element 21, a highly sensitive sensor can be formed whose amplification is increased due to avalanche multiplication. That is, by using a selenium-based material for the photoelectric conversion layer 182, sufficient photocurrent can be obtained even if the pixel area becomes smaller, and a highly sensitive camera device 10 can be realized. Therefore, it can be considered that the camera device 10 provided with a photoelectric conversion element 21 using a selenium-based material is suitable for imaging in a low-light environment.

[0237] As the selenium material, amorphous selenium or crystalline selenium can be used. Crystalline selenium can be formed, for example, by heat treatment after forming amorphous selenium. By making the crystal grain size of crystalline selenium smaller than the pixel pitch, the characteristic deviation between each pixel can be reduced. In addition, compared with amorphous selenium, crystalline selenium has a higher spectral sensitivity and light absorption coefficient to visible light.

[0238] The photoelectric conversion layer 182 may be a layer containing a compound of copper, indium, and selenium (CIS). Alternatively, the photoelectric conversion layer 182 may be a layer containing a compound of copper, indium, gallium, and selenium (CIGS). In a photoelectric conversion element using CIS and CIGS, avalanche multiplication can be utilized in the same manner as a single layer of selenium.

[0239] The conductive layer 184 preferably has light-transmitting properties. For example, the conductive layer 184 may be made of indium tin oxide, indium tin oxide containing silicon, indium oxide containing zinc, zinc oxide, zinc oxide containing gallium, zinc oxide containing aluminum, tin oxide, tin oxide containing fluorine, tin oxide containing antimony, graphene, or graphene oxide. The conductive layer 184 is not limited to a single layer, but may be a stack of films containing different materials.

[0240] Here, an organic compound may be used as the photoelectric conversion layer 182 . Fig. 11B 1 is a cross-sectional view showing a structural example of the photoelectric conversion element 21 when an organic compound is used as the photoelectric conversion layer 182 .

[0241] like Fig. 11B As shown, the hole transport layer 186, the active layer 180, and the electron transport layer 188 are sequentially stacked in the photoelectric conversion layer 182. At this time, the conductive layer 178 is used as the anode of the photoelectric conversion element 21, and the conductive layer 184 is used as the cathode of the photoelectric conversion element 21. In addition, when the conductive layer 178 is used as the cathode of the photoelectric conversion element 21 and the conductive layer 184 is used as the anode of the photoelectric conversion element 21, the stacking order is reversed.

[0242] The active layer 180 has a function of absorbing light irradiated to the photoelectric conversion element 21. The photoelectric conversion element 21 flows a current corresponding to the illuminance of the light absorbed by the active layer 180 due to the photoelectric effect. A plurality of organic materials may be appropriately combined in the active layer 180. For example, the active layer 180 may contain tetraphenyldibenzoindenepyrene (DBP) and fullerene.

[0243] The hole transport layer 186 has a function of transporting holes from the conductive layer 178 used as an anode to the active layer 180. The hole transport layer 186 includes a hole transport material. For example, the hole transport layer 186 may include molybdenum oxide. Note that as long as the hole transport property is higher than the electron transport property, a material other than the above may be used as the hole transport layer 186.

[0244] The electron transport layer 188 has a function of transporting electrons from the conductive layer 184 used as a cathode to the active layer 180. The electron transport layer 188 contains an electron transport material. The electron transport layer 188 may have a single layer structure or a stacked structure of two or more layers. For example, it may have a stacked structure of fullerene and bathocuproine (BCP). Note that as long as the material has a higher electron transport property than a hole transport property, materials other than the above may be used as the electron transport layer 188.

[0245] By using an organic compound as the photoelectric conversion layer 182 included in the photoelectric conversion element 21, it is possible to realize an inexpensive imaging device 10. In addition, the imaging device 10 can have flexibility.

[0246] <Pixel Structure Example 3>

[0247] Fig. 12A 1 is a perspective view showing an example of adding a coloring layer (color filter) or the like to a pixel included in the image pickup device 10. The perspective view also shows a cross section of a plurality of pixels. An insulating layer 380 is formed on the layer 20 forming the photoelectric conversion element 21. The insulating layer 380 can use a silicon oxide film having high light transmittance to visible light or the like. In addition, a structure of stacking a silicon nitride film can also be used as a passivation film. In addition, a structure of stacking a dielectric film of hafnium oxide or the like can also be used as an antireflection film.

[0248] A light shielding layer 381 may also be formed on the insulating layer 380. The light shielding layer 381 has a function of preventing mixing of light passing through the upper colored layer. A metal layer such as aluminum or tungsten may be used as the light shielding layer 381. In addition, the metal layer and a dielectric film having the function of an anti-reflection film may also be stacked.

[0249] An organic resin layer 382 used as a planarization film may be provided on the insulating layer 380 and the light shielding layer 381. In addition, a coloring layer 383 (a coloring layer 383a, a coloring layer 383b, and a coloring layer 383c) is formed in each pixel. For example, the coloring layers 383a, 383b, and 383c are made to have colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta), so that a color image can be obtained.

[0250] An insulating layer 386 or the like which is light-transmissive to visible light may be provided on the coloring layer 383 .

[0251] In addition, if Fig. 12B As shown, an optical conversion layer 385 may be used instead of the coloring layer 383. By adopting such a structure, an imaging device capable of obtaining images in various wavelength regions can be formed.

[0252] For example, when a filter that blocks light with a wavelength below the visible light is used as the optical conversion layer 385, an infrared camera device can be obtained. When a filter that blocks light with a wavelength below the near infrared light is used as the optical conversion layer 385, a far infrared camera device can be obtained. In addition, when a filter that blocks light with a wavelength above the visible light is used as the optical conversion layer 385, an ultraviolet camera device can be obtained.

[0253] In addition, a coloring layer corresponding to visible light and a filter corresponding to infrared light or ultraviolet light may be combined. By adopting this structure, a feature obtained by combining data of different wavelengths can be detected.

[0254] In addition, by using a scintillator for the optical conversion layer 385, an imaging device for obtaining an image that visualizes the radiation intensity, such as an X-ray imaging device, can be formed. When radiation such as X-rays that pass through the photographed object is incident on the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light due to the photoluminescence phenomenon. Image data is obtained by detecting this light with the photoelectric conversion element 21. In addition, the imaging device of this structure can also be used for radiation detectors, etc.

[0255] The scintillator contains a substance that absorbs the energy of radiation and emits visible light or ultraviolet light when the scintillator is irradiated with radiation such as X-rays or gamma rays. For example, materials such as Gd2O2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, CeF3, LiF, LiI, ZnO, etc. dispersed in resin or ceramics can be used.

[0256] In addition, in the photoelectric conversion element 21 using a selenium-based material, since radiation such as X-rays can be directly converted into electric charges, it is not necessary to use a scintillator.

[0257] In addition, if Fig. 12C As shown in FIG. 1 , a microlens array 384 may be provided on the coloring layer 383. Light transmitted through each lens of the microlens array 384 is irradiated to the photoelectric conversion element 21 via the coloring layer 383 provided thereunder. Fig. 12B The optical conversion layer 385 is shown with a microlens array 384 disposed thereon.

[0258] This embodiment mode can be combined with the description of other embodiment modes as appropriate.

[0259] (Implementation Method 2)

[0260] In this embodiment, a structural example of a transistor that can be used in an imaging device which is one embodiment of the present invention is described with reference to the drawings.

[0261] <Transistor Structure Example 1>

[0262] Reference Fig.13A , Fig. 13B and Fig. 13C A structural example of the transistor 510A is described. Fig.13A is a top view of transistor 510A. Fig. 13B is Fig.13A A cross-sectional view of the portion indicated by the dashed line L1-L2. Fig. 13C is Fig.13A A cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. Fig.13A In the top view, for the sake of clarity, part of the components are omitted and shown.

[0263] exist Fig.13A , Fig. 13B and Fig. 13C 5 shows a transistor 510A, and insulating layers 511, 512, 514, 516, 521, 522, 574, 580, 582, and 584, which are used as interlayer films. In addition, a conductive layer 546 (conductive layer 546a and conductive layer 546b) which is electrically connected to the transistor 510A and used as a contact plug is shown.

[0264] The transistor 510A includes: an insulating layer 524 used as a base insulating layer; a conductive layer 560 (conductive layer 560a and conductive layer 560b) used as a gate; an insulating layer 550 used as a gate insulating film; a metal oxide 530 (metal oxide 530a, metal oxide 530b and metal oxide 530c) including a region where a channel is formed; a conductive layer 542a used as one of a source and a drain; and a conductive layer 542b used as the other of a source and a drain.

[0265] 13, a metal oxide 530c, an insulating layer 550, and a conductive layer 560 are provided in an opening provided in the insulating layer 580 via an insulating layer 574. The metal oxide 530c, the insulating layer 550, and the conductive layer 560 are provided between the conductive layer 542a and the conductive layer 542b.

[0266] The insulating layer 511 and the insulating layer 512 serve as an interlayer film.

[0267] As the interlayer film, a single layer or a stack of insulating layers such as silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3) or (Ba, Sr)TiO3 (BST) can be used. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide can be added to these insulating layers. In addition, these insulating layers can also be nitrided. Silicon oxide, silicon oxynitride or silicon nitride can also be stacked on the above-mentioned insulating layer.

[0268] For example, the insulating layer 511 is preferably used as a barrier film for suppressing impurities such as water or hydrogen from entering the transistor 510A from the substrate side. Therefore, as the insulating layer 511, it is preferable to use an insulating material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, copper atoms (not allowing the above impurities to pass through easily). In addition, it is preferable to use an insulating material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (not allowing the above oxygen to pass through easily). In addition, for example, it is preferable to use aluminum oxide or silicon nitride as the insulating layer 511. By adopting this structure, it is possible to suppress impurities such as hydrogen and water from diffusing from the side closer to the substrate than the insulating layer 511 to the side of the transistor 510A.

[0269] For example, the dielectric constant of the insulating layer 512 is preferably lower than that of the insulating layer 511. By using a material having a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0270] In the transistor 510A, the conductive layer 560 is sometimes used as a gate.

[0271] The insulating layer 514 and the insulating layer 516 are used as an interlayer film similarly to the insulating layer 511 or the insulating layer 512. For example, the insulating layer 514 is preferably used as a barrier film for suppressing impurities such as water or hydrogen from entering the transistor 510A from the substrate side. By adopting this structure, impurities such as hydrogen and water can be suppressed from diffusing from the side closer to the substrate than the insulating layer 514 to the transistor 510A side. For example, the dielectric constant of the insulating layer 516 is preferably lower than that of the insulating layer 514. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0272] The insulating layer 522 preferably has a barrier property. When the insulating layer 522 has a barrier property, the insulating layer 522 serves as a layer for suppressing impurities such as hydrogen from entering the transistor 510A from the periphery of the transistor 510A.

[0273] As the insulating layer 522, for example, a single layer or a stack of insulating layers of so-called high-k materials such as aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium silicate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3) or (Ba, Sr)TiO3 (BST) are preferably used. When miniaturization and high integration of transistors are performed, problems such as leakage current sometimes occur due to the thin film of the gate insulating film. By using a high-k material as an insulating layer used as a gate insulating film, the gate potential when the transistor is operating can be reduced while maintaining the physical thickness.

[0274] The insulating layer 521 preferably has thermal stability. For example, since silicon oxide and silicon oxynitride have thermal stability, a high-k material is used as the insulating layer 521 and a material containing silicon oxide and / or silicon oxynitride is used as the insulating layer 522, thereby forming a stacked structure having thermal stability and a high relative dielectric constant.

[0275] The metal oxide 530 including a region used as a channel formation region includes a metal oxide 530a, a metal oxide 530b on the metal oxide 530a, and a metal oxide 530c on the metal oxide 530b. When the metal oxide 530a is provided below the metal oxide 530b, it is possible to prevent impurities from diffusing from a structure formed below the metal oxide 530a to the metal oxide 530b. When the metal oxide 530c is provided above the metal oxide 530b, it is possible to prevent impurities from diffusing from a structure formed above the metal oxide 530c to the metal oxide 530b. As the metal oxide 530, an oxide semiconductor of one of the above-mentioned metal oxides can be used.

[0276] The metal oxide 530c is preferably provided in the opening provided in the insulating layer 580 via the insulating layer 574. When the insulating layer 574 has a barrier property, diffusion of impurities from the insulating layer 580 into the metal oxide 530 can be suppressed.

[0277] One of the conductive layers 542 is used as a source electrode, and the other is used as a drain electrode.

[0278] Conductive layer 542a, conductive layer 542b can be made of a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum or tungsten, or an alloy containing these elements as main components. In particular, metal nitride films such as tantalum nitride are preferred because they have barrier properties against hydrogen and oxygen and have high oxidation resistance.

[0279] In addition, although a single-layer structure is shown in FIG. 13 , a stacked structure of two or more layers may be adopted. For example, a tantalum nitride film and a tungsten film are preferably stacked. Alternatively, a titanium film and an aluminum film may be stacked. Alternatively, a two-layer structure of an aluminum film stacked on a tungsten film, a two-layer structure of a copper film stacked on a copper-magnesium-aluminum alloy film, a two-layer structure of a copper film stacked on a titanium film, or a two-layer structure of a copper film stacked on a tungsten film may be adopted.

[0280] Alternatively, a three-layer structure may be used in which an aluminum film or a copper film is stacked on a titanium film or a titanium nitride film and a titanium film or a titanium nitride film is formed thereon, or an aluminum film or a copper film is stacked on a molybdenum film or a molybdenum nitride film and a molybdenum film or a molybdenum nitride film is formed thereon. Alternatively, a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0281] Alternatively, a barrier layer may be provided over the conductive layer 542. The barrier layer is preferably made of a substance that has a barrier property against oxygen or hydrogen. With this structure, oxidation of the conductive layer 542 can be suppressed when the insulating layer 574 is formed.

[0282] The barrier layer may be made of, for example, a metal oxide. In particular, it is preferable to use an insulating film having barrier properties to oxygen or hydrogen, such as aluminum oxide, hafnium oxide, or gallium oxide. Alternatively, silicon nitride formed by CVD may be used.

[0283] By including the barrier layer, the range of choices for the material of the conductive layer 542 can be expanded. For example, a material with low oxidation resistance and high conductivity, such as tungsten or aluminum, can be used for the conductive layer 542. In addition, for example, a conductive layer that is easy to deposit or process can be used.

[0284] The insulating layer 550 is used as a gate insulating film. The insulating layer 550 is preferably provided in the opening provided in the insulating layer 580 via the metal oxide 530 c and the insulating layer 574 .

[0285] When miniaturization and high integration of transistors are performed, leakage current and other problems may occur due to the thin film of the gate insulating film. In this case, the insulating layer 550 may also have a laminated structure. By making the insulating layer used as the gate insulating film have a laminated structure of a high-k material and a material with thermal stability, the gate potential of the transistor during operation can be reduced while maintaining the physical thickness. In addition, a laminated structure with thermal stability and a high relative dielectric constant can be achieved.

[0286] The conductive layer 560 used as a gate includes a conductive layer 560a and a conductive layer 560b on the conductive layer 560a. As the conductive layer 560a, a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms is preferably used. In addition, a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) is preferably used. In this specification, etc., "the function of suppressing the diffusion of impurities or oxygen" refers to the function of suppressing the diffusion of any one or all of the above impurities and the above oxygen.

[0287] When the conductive layer 560a has a function of suppressing diffusion of oxygen, the selectivity of the material of the conductive layer 560b can be improved. That is, by including the conductive layer 560a, even if an easily oxidizable material is used as the material constituting the conductive layer 560b, a decrease in conductivity due to oxidation of the conductive layer 560b can be suppressed.

[0288] As a conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used. In addition, as the conductive layer 560a, an oxide semiconductor that can be used for the metal oxide 530 can be used. In this case, by forming the conductive layer 560b by sputtering, the resistivity of the conductive layer 560a can be reduced to make it a conductive layer. The conductive layer can be called an OC (Oxide Conductor) electrode.

[0289] As the conductive layer 560b, a conductive material mainly composed of tungsten, copper or aluminum is preferably used. Since the conductive layer 560 is used as wiring, it is preferable to use a conductive layer with high conductivity. For example, a conductive material mainly composed of tungsten, copper or aluminum can be used. The conductive layer 560b can also have a laminated structure, for example, a laminated structure of titanium, titanium nitride and the above conductive materials can be used.

[0290] An insulating layer 574 is disposed between the insulating layer 580 and the transistor 510A. An insulating material having a function of suppressing diffusion of impurities such as water or hydrogen and oxygen is preferably used as the insulating layer 574. For example, aluminum oxide or hafnium oxide is preferably used. In addition, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon oxynitride, or silicon nitride can be used.

[0291] The imaging device of one embodiment of the present invention includes the insulating layer 574, which can prevent impurities such as water and hydrogen contained in the insulating layer 580 from diffusing into the metal oxide 530b through the metal oxide 530c and the insulating layer 550. In addition, oxidation of the conductive layer 560 by excess oxygen contained in the insulating layer 580 can be prevented.

[0292] The insulating layer 580 , the insulating layer 582 , and the insulating layer 584 serve as an interlayer film.

[0293] Similar to the insulating layer 514, the insulating layer 582 is preferably used as a block insulating film for preventing impurities such as water and hydrogen from entering the transistor 510A from the outside.

[0294] As with the insulating layer 516, the insulating layer 580 and the insulating layer 584 preferably have a lower dielectric constant than the insulating layer 582. By using a material having a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0295] In addition, the transistor 510A can also be electrically connected to other structures through plugs and wiring such as the conductive layer 546 embedded in the insulating layer 580, the insulating layer 582, and the insulating layer 584.

[0296] In addition, as the material of the conductive layer 546, a single layer or a stack of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials can be used. For example, a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity is preferably used. Alternatively, a low-resistance conductive material such as aluminum or copper is preferably used. By using a low-resistance conductive material, wiring resistance can be reduced.

[0297] For example, by using a stacked-layer structure of tantalum nitride or the like which is a conductive layer having a barrier property against hydrogen and oxygen and tungsten which has high conductivity as the conductive layer 546, diffusion of impurities from the outside can be suppressed while maintaining the conductivity of the wiring.

[0298] By using the above transistor as a transistor included in the imaging device of one embodiment of the present invention, the imaging device of one embodiment of the present invention can be an imaging device including a metal oxide and a transistor with a large on-state current. In addition, the imaging device of one embodiment of the present invention can be an imaging device including a metal oxide and a transistor with a small off-state current. In addition, the imaging device of one embodiment of the present invention can be an imaging device with small changes in electrical characteristics, stable electrical characteristics, and high reliability.

[0299] <Transistor Structure Example 2>

[0300] Reference Fig.14A , Fig. 14B and Fig. 14C A structural example of the transistor 510B is described. Fig.14A is a top view of transistor 510B. Fig. 14B is Fig.14A A cross-sectional view of the portion indicated by the dashed line L1-L2. Fig. 14C is Fig.14A A cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. Fig.14A In the top view, for the sake of clarity, part of the components are omitted and shown.

[0301] The transistor 510B is a modified example of the transistor 510A. Therefore, in order to avoid duplication of descriptions, the differences from the transistor 510A will be mainly described.

[0302] The transistor 510B includes a region where the conductive layer 542 (the conductive layer 542a and the conductive layer 542b) overlaps with the metal oxide 530c, the insulating layer 550, and the conductive layer 560. With this structure, a transistor with high on-state current can be provided. In addition, a transistor with high controllability can be provided.

[0303] The conductive layer 560 used as a gate includes a conductive layer 560a and a conductive layer 560b on the conductive layer 560a. As the conductive layer 560a, a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms is preferably used. In addition, a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) is preferably used.

[0304] When the conductive layer 560a has a function of suppressing diffusion of oxygen, the selectivity of the material of the conductive layer 560b can be improved. That is, by including the conductive layer 560a, oxidation of the conductive layer 560b and a decrease in conductivity can be suppressed.

[0305] In addition, it is preferable to provide an insulating layer 574 so as to cover the top surface and side surfaces of the conductive layer 560, the side surfaces of the insulating layer 550, and the side surfaces of the metal oxide 530c. As the insulating layer 574, it is preferable to use an insulating material having a function of suppressing the diffusion of impurities such as water or hydrogen and oxygen. For example, aluminum oxide or hafnium oxide is preferably used. In addition, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon oxynitride, or silicon nitride can be used.

[0306] By providing the insulating layer 574, oxidation of the conductive layer 560 can be suppressed. In addition, by including the insulating layer 574, diffusion of impurities such as water and hydrogen contained in the insulating layer 580 into the transistor 510B can be suppressed.

[0307] Alternatively, an insulating layer 576 (insulating layer 576a and insulating layer 576b) having a barrier property may be provided between the conductive layer 546 and the insulating layer 580. Providing the insulating layer 576 can prevent oxidation of the conductive layer 546 due to reaction of oxygen in the insulating layer 580 with the conductive layer 546.

[0308] In addition, by providing the insulating layer 576 having a barrier property, the range of materials for the conductive layer used for the plug or wiring can be expanded. For example, by using a metal material having a property of absorbing oxygen and having high conductivity as the conductive layer 546, a low-power camera device can be provided. Specifically, a material having low oxidation resistance and high conductivity such as tungsten or aluminum can be used. In addition, for example, a conductive layer that is easy to form or process can be used as the conductive layer 546.

[0309] <Transistor Structure Example 3>

[0310] Reference Fig.15A , Fig. 15B and Fig. 15C A structural example of the transistor 510C is described. Fig.15A is a top view of transistor 510C. Fig. 15B is Fig.15A A cross-sectional view of the portion indicated by the dashed line L1-L2. Fig. 15C is Fig.15A A cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. Fig.15A In the top view, part of the components are omitted for clarity.

[0311] The transistor 510C is a modified example of the transistor 510A. Therefore, in order to avoid duplication of descriptions, the differences from the transistor 510A will be mainly described.

[0312] The transistor 510C shown in FIG. 15 has a conductive layer 547a disposed between the conductive layer 542a and the metal oxide 530b, and a conductive layer 547b disposed between the conductive layer 542b and the metal oxide 530b. Here, the conductive layer 542a (conductive layer 542b) has a region extending beyond the top surface of the conductive layer 547a (conductive layer 547b) and the side surface on one side of the conductive layer 560 and in contact with the top surface of the metal oxide 530b. As the conductive layer 547, a conductive layer that can be used for the conductive layer 542 can be used. In addition, the thickness of the conductive layer 547 is preferably at least thicker than that of the conductive layer 542.

[0313] Since the transistor 510C shown in FIG15 has the above structure, the conductive layer 542 can be closer to the conductive layer 560 than the transistor 510A. Alternatively, the end of the conductive layer 542a and the end of the conductive layer 542b can overlap with the conductive layer 560. Thus, the substantial channel length of the transistor 510C can be reduced, and the on-state current and frequency characteristics can be improved.

[0314] In addition, the conductive layer 547a (conductive layer 547b) preferably overlaps the conductive layer 542a (conductive layer 542b). With this structure, when etching is performed to form an opening to fill the conductive layer 546a (conductive layer 546b), the conductive layer 547a (conductive layer 547b) is used as an etching stop layer to suppress overetching of the metal oxide 530b.

[0315] In the transistor 510C shown in FIG15 , an insulating layer 545 may be provided in contact with the insulating layer 544. The insulating layer 544 is preferably used as a blocking insulating film for suppressing impurities such as water or hydrogen and excess oxygen from entering the transistor 510C from the insulating layer 580 side. As the insulating layer 545, an insulating layer that can be used for the insulating layer 544 can be used. As the insulating layer 544, for example, a nitride insulating layer such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride, or silicon nitride oxide can be used.

[0316] <Transistor Structure Example 4>

[0317] Reference Fig.16A , Fig. 16B and Fig. 16C A structural example of the transistor 510D is described. Fig.16A is a top view of transistor 510D. Fig. 16B is Fig.16A A cross-sectional view of the portion indicated by the dashed line L1-L2. Fig. 16C is Fig.16A A cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. Fig.16A In the top view, part of the components are omitted for clarity.

[0318] The transistor 510D is a modified example of the above-described transistor, and thus, in order to avoid duplication of descriptions, the description will be mainly focused on the differences from the above-described transistor.

[0319] The transistor 510D includes an insulating layer 550 on the metal oxide 530c and a metal oxide 552 on the insulating layer 550. In addition, a conductive layer 560 is included on the metal oxide 552 and an insulating layer 570 is included on the conductive layer 560. In addition, an insulating layer 571 is included on the insulating layer 570.

[0320] The metal oxide 552 preferably has a function of suppressing oxygen diffusion. By providing the metal oxide 552 that suppresses oxygen diffusion between the insulating layer 550 and the conductive layer 560, oxygen diffusion to the conductive layer 560 is suppressed. In other words, a decrease in the amount of oxygen supplied to the metal oxide 530 can be suppressed. In addition, oxidation of the conductive layer 560 can be suppressed.

[0321] In addition, the metal oxide 552 may be used as a part of the gate. For example, an oxide semiconductor that can be used as the metal oxide 530 may be used as the metal oxide 552. In this case, by forming the conductive layer 560 by sputtering, the resistance value of the metal oxide 552 can be reduced to make it a conductive layer. This may be referred to as an OC (Oxide Conductor) electrode.

[0322] In addition, the metal oxide 552 is sometimes used as a part of the gate insulating film. Therefore, when silicon oxide or silicon oxynitride, which are materials with high thermal stability, are used for the insulating layer 550, it is preferable to use a metal oxide, which is a high-k material with a high relative dielectric constant, as the metal oxide 552. By adopting this stacked structure, the transistor 510D can be made into a transistor with thermal stability and a high relative dielectric constant. Therefore, the gate potential applied when the transistor is working can be reduced while maintaining the physical thickness. In addition, the equivalent oxide thickness (EOT) of the insulating layer used as a gate insulating film can be reduced.

[0323] Although the metal oxide 552 in the transistor 510D is shown as a single-layer structure, a stacked structure of two or more layers may be employed. For example, a metal oxide used as part of a gate electrode and a metal oxide used as part of a gate insulating film may be stacked.

[0324] By including the metal oxide 552 in the transistor 510D, when the metal oxide 552 is used as a gate, the on-state current of the transistor 510D can be increased without weakening the influence of the electric field from the conductive layer 560. In addition, when the metal oxide 552 is used as a gate insulating film, the distance between the conductive layer 560 and the metal oxide 530 is maintained by utilizing the physical thickness of the insulating layer 550 and the metal oxide 552. Therefore, the leakage current between the conductive layer 560 and the metal oxide 530 can be suppressed. Thus, by having the stacked-layer structure of the insulating layer 550 and the metal oxide 552 in the transistor 510D, the physical distance between the conductive layer 560 and the metal oxide 530 and the electric field strength applied from the conductive layer 560 to the metal oxide 530 can be easily adjusted.

[0325] Specifically, an oxide semiconductor that can be used for the metal oxide 530 can be used as the metal oxide 552 by reducing its resistance. Alternatively, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, and magnesium can be used.

[0326] In particular, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used as an insulating layer containing an oxide of one or both of aluminum and hafnium. In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is not easy to crystallize in the heat treatment of the subsequent process, so it is preferred. Note that the metal oxide 552 is not an essential component and can be appropriately designed according to the desired transistor characteristics.

[0327] An insulating material having a function of inhibiting the permeation of impurities such as water or hydrogen and oxygen is preferably used as the insulating layer 570. For example, aluminum oxide or hafnium oxide is preferably used. Thus, oxidation of the conductive layer 560 due to oxygen from above the insulating layer 570 can be prevented. In addition, impurities such as water or hydrogen can be inhibited from entering the metal oxide 530 from above the insulating layer 570 through the conductive layer 560 and the insulating layer 550.

[0328] The insulating layer 571 is used as a hard mask. By providing the insulating layer 571, the conductive layer 560 can be processed in such a way that the side surface of the conductive layer 560 is approximately perpendicular to the substrate surface. Specifically, the angle formed by the side surface of the conductive layer 560 and the substrate surface can be made greater than 75 degrees and less than 100 degrees, preferably greater than 80 degrees and less than 95 degrees.

[0329] Alternatively, the insulating layer 571 may also function as a barrier layer by using an insulating material having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen. In this case, the insulating layer 570 may not be provided.

[0330] By using the insulating layer 571 as a hard mask, the insulating layer 570, the conductive layer 560, the metal oxide 552, the insulating layer 550, and a portion of the metal oxide 530c are selectively removed, so that their side surfaces can be roughly aligned and a portion of the surface of the metal oxide 530b can be exposed.

[0331] The transistor 510D includes a region 531a and a region 531b in a portion of the surface of the exposed metal oxide 530b. One of the region 531a and the region 531b is used as a source region, and the other of the region 531a and the region 531b is used as a drain region.

[0332] For example, the regions 531a and 531b can be formed by introducing an impurity element such as phosphorus or boron into the surface of the exposed metal oxide 530b by ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment. Note that in this embodiment mode, "impurity element" refers to an element other than a main component element.

[0333] Alternatively, after a portion of the surface of the metal oxide 530 b is exposed, a metal film may be formed, and then heat treatment may be performed to diffuse elements included in the metal film into the metal oxide 530 b , thereby forming the regions 531 a and 531 b .

[0334] The resistivity of the region into which the impurity element is introduced in the metal oxide 530b decreases. Therefore, the region 531a and the region 531b are sometimes referred to as “impurity regions” or “low resistance regions”.

[0335] By using the insulating layer 571 and / or the conductive layer 560 as a mask, the region 531a and the region 531b can be formed in a self-aligned manner. Therefore, the region 531a and / or the region 531b do not overlap with the conductive layer 560, and the parasitic capacitance can be reduced. In addition, the bias region is not formed between the channel formation region and the source and drain region (region 531a or region 531b). By forming the region 531a and the region 531b in a self-aligned manner, an increase in on-state current, a decrease in threshold voltage, an increase in operating frequency, etc. can be achieved.

[0336] In addition, in order to further reduce the off-state current, a bias region may be provided between the channel formation region and the source / drain region. The bias region is a region with high resistivity and is a region where the above-mentioned impurity element is not introduced. The bias region can be formed by introducing the above-mentioned impurity element after forming the insulating layer 575. In this case, the insulating layer 575 is also used as a mask as in the case of the insulating layer 571. Therefore, the region of the metal oxide 530b overlapping with the insulating layer 575 is not introduced with the impurity element, thereby maintaining the resistivity of the region high.

[0337] The transistor 510D includes an insulating layer 575 on the side of the insulating layer 570, the conductive layer 560, the metal oxide 552, the insulating layer 550, and the metal oxide 530c. The insulating layer 575 is preferably an insulating layer having a low relative dielectric constant. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide with pores, or resin is preferably used. In particular, when silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide with pores is used for the insulating layer 575, it is preferred because an excess oxygen region can be easily formed in the insulating layer 575 in the subsequent process. In addition, silicon oxide and silicon oxynitride are thermally stable and therefore are preferred. In addition, the insulating layer 575 preferably has a function of diffusing oxygen.

[0338] The transistor 510D includes an insulating layer 574 over the insulating layer 575 and the metal oxide 530. The insulating layer 574 is preferably formed by a sputtering method. By using a sputtering method, an insulating layer with less impurities such as water and hydrogen can be formed. For example, aluminum oxide is preferably used as the insulating layer 574.

[0339] Oxide films formed by sputtering may extract hydrogen from the structure being formed. Therefore, when the insulating layer 574 is formed by sputtering, the insulating layer 574 extracts hydrogen and water from the metal oxide 530 and the insulating layer 575. Thus, the hydrogen concentration of the metal oxide 530 and the insulating layer 575 can be reduced.

[0340] <Transistor Structure Example 5>

[0341] Reference Fig.17A , Fig. 17B and Fig. 17C A structural example of the transistor 510E is described. Fig.17A is a top view of transistor 510E. Fig. 17B is Fig.17A A cross-sectional view of the portion indicated by the dashed line L1-L2. Fig. 17C is Fig.17A A cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. Fig.17A In the top view, part of the components are omitted for clarity.

[0342] The transistor 510E is a modified example of the above-described transistor. Therefore, in order to avoid duplication of descriptions, the differences from the above-described transistor will be mainly described.

[0343] The transistor 510E includes a region 531a and a region 531b in a portion of the surface of the exposed metal oxide 530b, but does not include a conductive layer 542. One of the region 531a and the region 531b is used as a source region, and the other is used as a drain region. In addition, an insulating layer 573 is included between the metal oxide 530b and the insulating layer 574.

[0344] The region 531 (region 531a and region 531b) shown in Fig. 17 is a region in which the following elements are added to the metal oxide 530b. The region 531 can be formed by using a dummy gate, for example.

[0345] Specifically, a dummy gate is provided on the metal oxide 530b, and the dummy gate is used as a mask to add an element that makes the metal oxide 530b low in resistance. That is, the element is added to the region of the metal oxide 530 that does not overlap with the dummy gate, thereby forming a region 531. As a method for adding the element, an ion implantation method in which the ionized source gas is mass-separated and added; an ion doping method in which the ionized source gas is not mass-separated and added; and a plasma immersion ion implantation method, etc. can be used.

[0346] In addition, as an element that reduces the resistance of the metal oxide 530, boron or phosphorus is typical. In addition, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, rare gases, etc. can also be used. Typical examples of rare gases include helium, neon, argon, krypton, and xenon. The concentration of the element can be measured by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry) or the like.

[0347] In particular, boron and phosphorus are preferred because they can be used in the production line of amorphous silicon or low-temperature polysilicon. Existing equipment can be used, thereby reducing equipment investment.

[0348] Next, an insulating film serving as an insulating layer 573 and an insulating film serving as an insulating layer 574 may be formed over the metal oxide 530b and the dummy gate. By providing a stack of the insulating film serving as the insulating layer 573 and the insulating film serving as the insulating layer 574, a region where the region 531 overlaps with the metal oxide 530c and the insulating layer 550 can be provided.

[0349] Specifically, an insulating film that becomes the insulating layer 580 is provided on the insulating film that becomes the insulating layer 574, and then the insulating film that becomes the insulating layer 580 is subjected to CMP (Chemical Mechanical Polishing) treatment to remove a portion of the insulating film that becomes the insulating layer 580, so that the dummy gate is exposed. Next, when removing the dummy gate, it is preferable to also remove a portion of the insulating layer 573 that is in contact with the dummy gate. As a result, the insulating layer 574 and the insulating layer 573 are exposed on the side of the opening portion provided in the insulating layer 580, and a portion of the region 531 provided in the metal oxide 530b is exposed on the bottom surface of the opening portion. Next, an oxide film that becomes the metal oxide 530c, an insulating film that becomes the insulating layer 550, and a conductive film that becomes the conductive layer 560 are sequentially formed in the opening portion, and then a portion of the oxide film that becomes the metal oxide 530c, the insulating film that becomes the insulating layer 550, and the conductive film that becomes the conductive layer 560 are removed by CMP treatment or the like until the insulating layer 580 is exposed, thereby forming the transistor shown in FIG. 17.

[0350] Note that the insulating layer 573 and the insulating layer 574 are not necessarily provided and may be appropriately designed depending on required transistor characteristics.

[0351] The transistor shown in FIG 17 can utilize existing devices and does not provide the conductive layer 542, thereby reducing costs.

[0352] This embodiment mode can be combined with the description of other embodiment modes as appropriate.

[0353] (Implementation method 3)

[0354] In this embodiment, an example of a package and a camera module that accommodate an image sensor chip is described with reference to the drawings. As the image sensor chip, the structure of an imaging device according to one embodiment of the present invention can be used.

[0355] Fig.18A1 FIG. 1 is a perspective view of the top surface of a package that contains an image sensor chip. Fig.18A3 The image sensor chip 650 is shown to be fixed to a packaging substrate 610 , a glass cover 620 , and an adhesive 630 that adheres them.

[0356] Fig.18A2 This is a three-dimensional view of the bottom side of the package. The bottom side of the package includes a BGA (Ball Grid Array) with solder balls as bumps 640. Note that it is not limited to BGA, and can also include LGA (Land Grid Array), PGA (Pin Grid Array), etc.

[0357] Fig.18A3 FIG. 6 is a perspective view of a package in which a portion of the glass cover 620 and the adhesive 630 are omitted. An electrode pad 660 is formed on the package substrate 610. The electrode pad 660 is connected to the package substrate 610 through a through hole. Fig.18A2 The bumps 640 are shown to be electrically connected. The electrode pads 660 are electrically connected to the image sensor chip 650 through the wires 670 .

[0358] in addition, Figure 18B1 The top side of the camera module is a perspective view of the image sensor chip housed in a lens-integrated package. Figure 18B3 The image sensor chip 651 is shown to be fixed to a package substrate 611 , a lens cover 621 , a lens 635 , and the like.

[0359] Figure 18B2 This is a perspective view of the bottom side of the camera module. The bottom and side surfaces of the package substrate 611 have a QFN (Quad Flat No-lead package) structure with a storage connection pad 641. Note that this structure is an example, and a QFP (Quad Flat Package) or the above-mentioned BGA can also be provided.

[0360] Figure 18B3This is a perspective view of the module in which a portion of the lens cover 621 and the lens 635 are omitted. The connection pad 641 is electrically connected to the electrode pad 661, and the electrode pad 661 is electrically connected to the image sensor chip 651 or the IC chip 690 through the lead 671. In addition, an IC chip 690 having functions such as a driving circuit and a signal conversion circuit of the camera device is provided between the package substrate 611 and the image sensor chip 651, and has a structure as a SiP (System in Package).

[0361] By housing the image sensor chip in a package of the above type, it can be easily mounted on a printed circuit board or the like, and thus the image sensor chip can be incorporated into various semiconductor devices and electronic devices.

[0362] This embodiment mode can be combined with the description of other embodiment modes as appropriate.

[0363] (Implementation 4)

[0364] In this embodiment, electronic equipment including an imaging device according to one embodiment of the present invention is described.

[0365] Fig.19A 1 is an external view of a camera 1000 equipped with a viewfinder 1100. The camera 1000 may be, for example, a digital camera. Fig.19A In the embodiment, the camera 1000 and the viewfinder 1100 are separate and detachable electronic devices, but a viewfinder having a display device may be built into the housing 1001 of the camera 1000 .

[0366] The camera 1000 includes a housing 1001 , a display portion 1002 , operation buttons 1003 , a shutter button 1004 , etc. In addition, the camera 1000 is equipped with a detachable lens 1006 .

[0367] Here, the camera 1000 has a structure in which the lens 1006 can be removed from the housing 1001 and replaced, but the lens 1006 and the housing 1001 may be formed integrally.

[0368] The camera 1000 can capture an image by pressing a shutter button 1004. In addition, the display portion 1002 is used as a touch panel, and the image can be captured by touching the display portion 1002.

[0369] The housing 1001 of the camera 1000 includes an embedder having electrodes, and can be connected to a flash device or the like in addition to the viewfinder 1100 .

[0370] The viewfinder 1100 includes a housing 1101 , a display portion 1102 , etc. The viewfinder 1100 may be an electronic viewfinder.

[0371] The housing 1101 includes an inserter that is fitted into the inserter of the camera 1000, and the viewfinder 1100 can be mounted on the camera 1000. In addition, the inserter includes electrodes, and the image or the like received from the camera 1000 by the electrodes can be displayed on the display unit 1102.

[0372] The imaging device of one embodiment of the present invention may be provided in the camera 1000. Thus, the camera 1000 can acquire imaging data corresponding to a high-resolution image at short time intervals. Therefore, the camera 1000 may be a high-speed camera.

[0373] Fig.19B This is an appearance diagram of the head mounted display 1200.

[0374] The head mounted display 1200 includes a mounting portion 1201 , a lens 1202 , a main body 1203 , a display portion 1204 , a cable 1205 , etc. In addition, a battery 1206 is built in the mounting portion 1201 .

[0375] Power is supplied from a battery 1206 to the main body 1203 via a cable 1205. The main body 1203 is provided with a wireless receiver and the like, and can display an image corresponding to received image data and the like on the display unit 1204. In addition, by capturing the movement of the user's eyeballs and eyelids with a camera provided in the main body 1203 and calculating the coordinates of the user's line of sight based on the data, the user's line of sight can be used as an input method.

[0376] In addition, a plurality of electrodes may be provided at the position of the mounting portion 1201 that is touched by the user. The main body 1203 may also have a function of recognizing the user's line of sight by detecting the current flowing through the electrodes according to the movement of the user's eyeballs. In addition, the main body 1203 may have a function of monitoring the user's pulse by detecting the current flowing through the electrodes. The mounting portion 1201 may have various sensors such as a temperature sensor, a pressure sensor, an acceleration sensor, and may also have a function of displaying the user's biological data on the display portion 1204. In addition, the main body 1203 may also detect the movement of the user's head, etc., and change the image displayed on the display portion 1204 in synchronization with the movement of the user's head, etc.

[0377] The camera provided in the main body 1203 and the sensor provided in the mounting portion 1201 may be provided with an imaging device of one embodiment of the present invention. Thus, the camera can obtain imaging data corresponding to a high-resolution image at short time intervals. Therefore, the camera may be a high-speed camera.

[0378] Fig.19C , Fig.19D and Fig.19E13 is an external view of a head mounted display 1300 . The head mounted display 1300 includes a housing 1301 , a display unit 1302 , a belt-shaped fixing tool 1304 , and a pair of lenses 1305 .

[0379] The user can see the display on the display unit 1302 through the lens 1305. Preferably, the display unit 1302 is arranged in a curved manner. By arranging the display unit 1302 in a curved manner, the user can experience a high sense of presence. Note that in this embodiment, a structure in which one display unit 1302 is provided is exemplified, but the present invention is not limited thereto. For example, a structure in which two display units 1302 are provided may also be adopted. In this case, when each display unit is arranged on one side of each eye of the user, a three-dimensional display using parallax or the like can be performed.

[0380] In addition, a camera may be provided in the head mounted display 1300. Thus, it is possible to capture external scenery. Therefore, the head mounted display 1300 can synthesize an image captured by the camera and a virtual image such as a computer graphics (CG). Therefore, the head mounted display 1300 can be used as an augmented reality (AR) device.

[0381] As the camera, an imaging device according to one embodiment of the present invention may be provided. Thus, the camera can obtain imaging data corresponding to a high-resolution image at short time intervals. Therefore, the camera may be a high-speed camera.

[0382] Fig. 20A 14 is an external view of a mobile phone 1400. The mobile phone 1400 includes a housing 1481, a display portion 1482, operation buttons 1483, an external connection interface 1484, a speaker 1485, a microphone 1486, a camera 1487, and the like. The mobile phone has a touch sensor on the display portion 1482. By touching the display portion 1482 with a finger or a stylus pen, various operations such as making a call or inputting text can be performed.

[0383] The camera 1487 may be a camera device according to one embodiment of the present invention. Thus, the camera 1487 can obtain image data corresponding to a high-resolution image at short intervals. Therefore, the camera 1487 may be a high-speed camera.

[0384] Fig. 20B 1 is an external view of the portable data terminal 1500. The portable data terminal 1500 includes a housing 1511, a display unit 1512, a speaker 1513, a camera 1519, etc. Information can be input and output through the touch panel function of the display unit 1512. In addition, text can be recognized from an image obtained by the camera 1519, and the text can be output as a voice using the speaker 1513.

[0385] As the camera 1519, an imaging device according to one embodiment of the present invention may be provided. Thus, the camera 1519 can obtain imaging data corresponding to a high-resolution image at short intervals. Therefore, the camera 1519 may be a high-speed camera.

[0386] Fig. 20C 16 is an external view of a surveillance camera 1600. The surveillance camera 1600 includes a bracket 1651, a camera unit 1652, a protective cover 1653, etc. The camera unit 1652 is provided with a rotating mechanism, etc., and can be installed on the ceiling to capture the surroundings. Note that "surveillance camera" is a general name and is not limited to its use. For example, a device that functions as a surveillance camera is called a video camera or a video camera.

[0387] As the camera unit 1652, an imaging device according to one embodiment of the present invention may be provided. Thus, the camera unit 1652 can obtain imaging data corresponding to a high-resolution image at short intervals. Therefore, the camera unit 1652 may be a high-speed camera.

[0388] Fig.20D 17 is an appearance diagram of a wristwatch-type information terminal 1700. The information terminal 1700 includes a display unit 1732, a housing and wristband 1733, and a camera 1739. The display unit 1732 includes a touch panel for operating the information terminal. The display unit 1732 and the housing and wristband 1733 are flexible and suitable for being worn on the body.

[0389] As the camera 1739, an imaging device according to one embodiment of the present invention may be provided. Thus, the camera 1739 can obtain imaging data corresponding to a high-resolution image at short intervals. Therefore, the camera 1739 may be a high-speed camera.

[0390] This embodiment mode can be combined with the description of other embodiment modes as appropriate.

[0391] [Explanation of symbols]

[0392] 10: imaging device, 12: transistor, 12_1: transistor, 12_2: transistor, 13: transistor, 13_1: transistor, 13_2: transistor, 14: transistor, 14_1: transistor, 15: transistor, 15_1: transistor, 15_2: transistor, 16: capacitor, 20: layer, 21: photoelectric conversion element, 30: layer, 30_i: layer, 30_n: layer, 30_1: layer, 30_2: layer, 31: imaging unit, 32: holding circuit, 32_i: holding circuit, 32_n: holding circuit, 32_1: holding circuit, 32_2: holding circuit, 33: gate driver circuit, 33_n: gate driver circuit, 33_1: gate driver circuit, 34: Source driver circuit, 34_n: source driver circuit, 34_1: source driver circuit, 35: AD conversion circuit, 35_n: AD conversion circuit, 35_1: AD conversion circuit, 35_2: AD conversion circuit, 36: demultiplexer circuit, 37: multiplexer circuit, 40: wiring, 40_1: wiring, 40_2: wiring, 41: wiring, 41_1: wiring, 41_2: wiring, 42: wiring, 42_1: wiring, 42_2: wiring, 43: wiring, 43_1: wiring, 43_2: wiring, 44: wiring, 44_1: wiring, 44_2: wiring, 45: wiring, 46: wiring, 47: wiring, 51: exposure operation, 52: holding operation, 53: reading operation , 100: substrate, 102: insulating layer, 104: region, 106: region, 108: region, 110: region, 112: insulating layer, 114: insulating layer, 116: insulating layer, 116_1: insulating layer, 116_2: insulating layer, 118: insulating layer, 120: insulating layer, 122: insulating layer, 123: insulating layer, 123_1: insulating layer, 124: insulating layer, 124_1: insulating layer, 126: insulating layer, 126_1: insulating layer, 128: insulating layer, 128_1: insulating layer, 128_2: insulating layer, 130: conductive layer, 130_1: conductive layer, 130_2: conductive layer, 130a: conductive layer, 130b: conductive layer, 131: conductive layer, 13 2: conductive layer, 134: conductive layer, 136: conductive layer, 138: conductive layer, 140: conductive layer, 142: insulating layer, 144: insulating layer, 161: conductive layer, 162: conductive layer, 164: conductive layer, 166: conductive layer, 168: conductive layer, 170: conductive layer, 172: insulating layer, 173: insulating layer, 176: conductive layer, 178: conductive layer, 180: active layer, 182: photoelectric conversion layer, 184: conductive layer, 186: hole transport layer, 188: electron transport layer, 202_1: conductive layer, 202_2: conductive layer, 204_1: conductive layer, 204_2: conductive layer, 206_1: conductive layer, 206_2: conductive layer, 208_1: conductive layer,208_2: conductive layer, 210_1: conductive layer, 210_2: conductive layer, 300: transistor, 324: insulator, 330: metal oxide, 330a: metal oxide, 330b: metal oxide, 330c: metal oxide, 342: conductive layer, 342a: conductive layer, 342b: conductive layer, 343: region, 343a: region, 343b: region, 350: insulating layer, 360: conductive layer, 360a: conductive layer, 360b: conductive layer, 380: insulating layer, 381: light shielding layer, 382: organic resin layer, 383: coloring layer, 383a: coloring layer, 383b: coloring layer, 383c: coloring layer, 384: microlens array, 385: optical conversion layer Change layer, 386: insulating layer, 510A: transistor, 510B: transistor, 510C: transistor, 510D: transistor, 510E: transistor, 511: insulating layer, 512: insulating layer, 514: insulating layer, 516: insulating layer, 521: insulating layer, 522: insulating layer, 524: insulating layer, 530: metal oxide, 530a: metal oxide, 530b: metal oxide, 530c: metal oxide, 531: region, 531a: region, 531b: region, 542: conductive layer, 542a: conductive layer, 542b: conductive layer, 544: insulating layer, 545: insulating layer, 546: conductive layer, 546a: conductive layer, 546b: conductive layer, 547: Conductive layer, 547a: conductive layer, 547b: conductive layer, 550: insulating layer, 552: metal oxide, 560: conductive layer, 560a: conductive layer, 560b: conductive layer, 570: insulating layer, 571: insulating layer, 573: insulating layer, 574: insulating layer, 575: insulating layer, 576: insulating layer, 576a: insulating layer, 576b: insulating layer, 580: insulating layer, 582: insulating layer, 584: insulating layer, 610: packaging substrate, 611: packaging substrate, 620: glass cover, 621: lens cover, 630: adhesive, 635: lens, 640: bump, 641: connection pad, 650: image sensor chip, 651: image sensor chip, 660: electrical 1: electrode pad, 661: electrode pad, 670: lead, 671: lead, 690: IC chip, 1000: camera, 1001: housing, 1002: display unit, 1003: operation button, 1004: shutter button, 1006: lens, 1100: viewfinder, 1101: housing, 1102: display unit, 1200: head mounted display, 1201: mounting portion, 1202: lens, 1203: main body, 1204: display unit, 1205: cable, 1206: battery, 1300: head mounted display, 1301: housing, 1302: display unit, 1304: fixing tool, 1305: lens, 1400: mobile phone, 1481: housing, 1482: display unit,1483: operation button, 1484: external connection port, 1485: speaker, 1486: microphone, 1487: camera, 1500: portable data terminal, 1511: housing, 1512: display unit, 1513: speaker, 1519: camera, 1600: surveillance camera, 1651: bracket, 1652: camera unit, 1653: protective cover, 1700: information terminal, 1732: display unit, 1733: housing and wristband, 1739: camera.

Claims

1. A camera device comprising a stack of a first layer, a second layer and a third layer, in, The first layer includes a photoelectric conversion element, The second layer includes a first circuit including a region overlapping with the photoelectric conversion element, The third layer includes a second circuit, the second circuit includes a region overlapping with the photoelectric conversion element, One electrode of the photoelectric conversion element is electrically connected to the first circuit, One electrode of the photoelectric conversion element is electrically connected to the second circuit, The first circuit has a function of holding first imaging data, the first imaging data being data corresponding to the illuminance of light irradiated to the photoelectric conversion element. The second circuit has a function of holding second imaging data, the second imaging data being data corresponding to the illuminance of light irradiated to the photoelectric conversion element. The second layer is provided with the first circuits having the same number of rows and columns as the photoelectric conversion elements, Furthermore, the second circuits are provided in the third layer in the same number of rows and columns as the photoelectric conversion elements.

2. The imaging device according to claim 1, wherein the first circuit comprises a first transmission transistor, The second circuit includes a second transfer transistor, one electrode of the photoelectric conversion element is electrically connected to one of a source and a drain of the first transfer transistor, And one electrode of the photoelectric conversion element is electrically connected to one of the source and the drain of the second transfer transistor.

3. The imaging device according to claim 2, wherein one of a source and a drain of the first transfer transistor has a region overlapping with one of a source and a drain of the second transfer transistor, the other of the source and the drain of the first transfer transistor has a region overlapping with the other of the source and the drain of the second transfer transistor, And the gate of the first transfer transistor has a region overlapping with the gate of the second transfer transistor.

4. The imaging device according to claim 2 or 3, wherein the first and second transfer transistors include metal oxide in a channel formation region, The metal oxide comprises elements M and Zn, And the element M is one or more of Al, Ga, Y and Sn.

5. The imaging device according to claim 1, The first circuit and the second circuit have the same structure.

6. The imaging device according to claim 1, wherein the second layer comprises a first AD conversion circuit, The third layer includes a second AD conversion circuit, And the first AD conversion circuit and the second AD conversion circuit have a region overlapping each other.

7. The imaging device according to claim 1, The first layer includes a multiplexer circuit and an AD conversion circuit. a first input terminal of the multiplexer circuit is electrically connected to the first circuit, a second input terminal of the multiplexer circuit is electrically connected to the second circuit, And the output terminal of the multiplexer circuit is electrically connected to the AD conversion circuit.

8. The imaging device according to claim 2 or 3, The first circuit includes the first transmission transistor, the first reset transistor, the first amplification transistor and the first selection transistor, the other of the source and the drain of the first transfer transistor is electrically connected to one of the source and the drain of the first reset transistor, One of the source and the drain of the first reset transistor is electrically connected to the gate of the first amplifying transistor, And one of the source and the drain of the first amplifying transistor is electrically connected to one of the source and the drain of the first selecting transistor.

9. The imaging device according to claim 8, wherein the first transfer transistor, the first reset transistor, the first amplification transistor, and the first selection transistor include metal oxide in a channel formation region, The metal oxide comprises elements M and Zn, And the element M is one or more of Al, Ga, Y and Sn.

10. The imaging device according to claim 9, The second circuit includes the second transmission transistor, the second reset transistor, the second amplification transistor and the second selection transistor, the other of the source and the drain of the second transfer transistor is electrically connected to one of the source and the drain of the second reset transistor, One of the source and the drain of the second reset transistor is electrically connected to the gate of the second amplifying transistor, And one of the source and the drain of the second amplifying transistor is electrically connected to one of the source and the drain of the second selecting transistor.

11. The imaging device according to claim 10, wherein the second transfer transistor, the second reset transistor, the second amplifying transistor, and the second selection transistor include metal oxide in a channel formation region, The metal oxide comprises elements M and Zn, And the element M is one or more of Al, Ga, Y and Sn.

12. The imaging device according to claim 1, The period during which the imaging device acquires the first imaging data is different from the period during which the imaging device acquires the second imaging data.

13. An electronic device, comprising: The camera device according to claim 1; as well as Display device.

14. A method for operating an image pickup device, the image pickup device comprising a stack of a first layer having a photoelectric conversion element, a second layer having a first circuit and a first AD conversion circuit, and a third layer having a second circuit and a second AD conversion circuit, in, During a first period, first imaging data is acquired and held in the first circuit, the first imaging data being data corresponding to the illuminance of light irradiating the photoelectric conversion element, During a second period, second imaging data is acquired and held in the second circuit, the second imaging data being data corresponding to the illuminance of light irradiating the photoelectric conversion element, reading out the first imaging data held by the first circuit and the second imaging data held by the second circuit during a third period, Furthermore, during the third period, the first AD conversion circuit converts the first imaging data, which is analog data, into digital data, and the second AD conversion circuit converts the second imaging data, which is analog data, into digital data.

15. A method for operating an image pickup device, the image pickup device comprising a stack of a photoelectric conversion element, a first circuit, a second circuit, and an AD conversion circuit, in, During a first period, first imaging data is acquired and held in the first circuit, the first imaging data being data corresponding to the illuminance of light irradiating the photoelectric conversion element, During a second period, second imaging data is acquired and held in the second circuit, the second imaging data being data corresponding to the illuminance of light irradiating the photoelectric conversion element, reading out the first imaging data held by the first circuit during a third period, During the third period, the AD conversion circuit converts the first imaging data, which is analog data, into digital data. reading out the second imaging data held by the second circuit during a fourth period, Furthermore, during the fourth period, the AD conversion circuit converts the second imaging data, which is analog data, into digital data.

16. The operating method of the camera device according to claim 14 or 15, wherein the first camera data is obtained in a global shutter manner during the first period, And during the second period, the second imaging data is acquired using a global shutter method.

Images