A computing device and an operating method thereof

Abstract

The present invention provides a computing device and an operation method thereof, wherein the device comprises a data module and a computing module, wherein the data module operates on data, including reading or writing data from a memory and inputting computing data to the computing module, and the computing module is used to perform relevant operations on the data according to instructions. The present invention improves the execution performance of tasks involving a large number of vector calculations, and has the advantages of concise instruction structure, flexible and efficient data operations, etc.

Description

Technical Field

[0001] The present invention belongs to the field of computers, and specifically relates to a computing device and an operating method thereof, which are used to efficiently and flexibly perform operations on data of the same scale or different scales according to instructions. The present invention well solves the problem that more and more algorithms currently contain a large amount of operations on data of the same scale or different scales, reduces the limitation of the scale of the computing unit, and improves the flexibility and effectiveness of vector operations. Background Art

[0002] With the advent of the big data era, applications related to vector operations are also increasing, the amount of data involved in the operation is increasing, the data specifications and dimensions are expanding, and the operation forms are gradually increasing. On the one hand, the scale of the operation unit is difficult to expand significantly with the substantial increase in the amount of data, which puts forward requirements on how to regulate the operation data during the operation; on the other hand, these operations are no longer limited to data of the same specifications, but a large part of the operations are performed on data of different specifications or dimensions, which puts forward higher requirements on the flexibility of the operation device.

[0003] In the prior art, a known solution for performing vector operations is to use a general-purpose processor (CPU) or a graphics processing unit (GPU). However, this method is either less efficient when performing vector operations because its structure is more suitable for scalar operations; or because its on-chip cache is too small, it cannot meet the requirements of efficiently completing large-scale vector operations. In another prior art, a specially customized vector operation device is used to perform vector calculations, that is, a customized storage unit and processing unit are used to perform vector operations. However, the existing dedicated vector operation devices are limited by register stacks and can only support vector operations of the same length, which lacks flexibility.

[0004] In addition, the instruction set corresponding to the above device can only perform operations on data of the same length, and is limited by the size of the memory and the size of the operation unit. For data of different lengths and data that does not meet the size of the operation unit, one way is to use multiple instructions to call the data in sequence, and the other way is to use loop instructions to call repeatedly. This not only makes the structure of the instruction set complex, the instruction queue lengthy, and the execution efficiency low, but also has many runtime restrictions and poor flexibility, and cannot provide convenience for large-scale vector operations. Summary of the invention

[0005] 1. Technical issues to be resolved

[0006] The purpose of the present invention is to provide a computing device and an operating method thereof, which are used to efficiently and flexibly perform operations on data of the same scale or different scales according to instructions, solve the current problem that more and more algorithms contain a large amount of operations on data of the same scale or different scales, and reduce the scale of the computing unit.

[0007] (II) Technical solution

[0008] The present invention provides a computing device, the device comprising an instruction module, a data module and a computing module, wherein:

[0009] The instruction module is used to cache instructions and provide instructions to the data module and the operation module;

[0010] The data module is used to provide operation data to the operation module according to the instructions in the instruction module;

[0011] The operation module is used to perform operations according to the instructions in the instruction module and the operation data provided by the data module.

[0012] Furthermore, the instruction module includes an instruction cache unit, an instruction processing unit, a dependency processing unit, and a storage queue unit, wherein:

[0013] The instruction cache unit is used to store instructions to be executed, the instruction processing unit is used to obtain instructions from the instruction cache unit and process the instructions, and the dependency processing unit is used to determine whether the instruction accesses the same data as the previous instruction being executed:

[0014] If yes, the dependency processing unit stores the instruction in the storage queue unit, and provides the instruction to the computing module after the previous instruction being executed is completed;

[0015] Otherwise, the instruction is directly provided to the operation module.

[0016] Furthermore, the instruction processing unit includes:

[0017] The instruction fetch part is used to fetch instructions from the instruction cache unit;

[0018] A decoding part, used to decode the fetched instructions;

[0019] The instruction queue part is used to sequentially store the decoded instructions.

[0020] Furthermore, the data module includes a data I / O unit and a data temporary storage unit, wherein the data I / O unit is used to directly read the operation data from the memory, and the data temporary storage unit is used to store the operation data and provide the operation data to the operation module after adjusting the operation data.

[0021] Furthermore, the data temporary storage unit is used to adjust the operation data and provide it to the operation module, including:

[0022] When the lengths of the two operation data involved in the operation are both less than or equal to the operation scale of the operation module, the data temporary storage unit directly provides the two operation data to the operation module;

[0023] When the lengths of two operation data involved in the operation are both greater than the operation scale of the operation module, each operation data is split into a plurality of sub-operation data whose lengths are less than or equal to the operation scale, and the sub-operation data are provided to the operation module in multiple times;

[0024] When one of the two operation data involved in the operation has a length greater than the operation scale of the operation module, and the other operation data has a length less than or equal to the operation scale of the operation module, the operation data with a length greater than the operation scale is split into multiple sub-operation data with lengths less than or equal to the operation scale, and the multiple sub-operation data and the operation data with a length less than or equal to the operation scale are provided to the operation module in multiple times.

[0025] Furthermore, the operation data is a vector, and the operation module is used to perform vector logical operations or vector arithmetic operations.

[0026] The present invention also provides an operating method of a computing device, the method comprising:

[0027] S1, cache instructions in the instruction module;

[0028] S2, providing the instruction in the instruction module to the data module, and the data module provides operation data to the operation module according to the instruction;

[0029] S3, providing the instruction in the instruction module to the operation module, and the operation module performs operation according to the instruction and the operation data provided by the operation data module.

[0030] Further, the instruction module includes an instruction cache unit, an instruction processing unit, a dependency processing unit, and a storage queue unit, and the step S1 includes:

[0031] S11, storing instructions to be executed in an instruction cache unit;

[0032] S12, the instruction processing unit obtains the instruction from the instruction cache unit and processes the instruction;

[0033] S13, the dependency processing unit determines whether the instruction accesses the same data as the previous instruction being executed. If so, the dependency processing unit stores the instruction in the storage queue unit, and provides the instruction to the operation module after the previous instruction being executed is completed. Otherwise, the instruction is directly provided to the operation module.

[0034] Further, the instruction processing unit includes an instruction fetching part, a decoding part and an instruction queue part, wherein step S12 includes:

[0035] S121, the instruction fetching part fetches instructions from the instruction cache unit;

[0036] S122, the decoding part decodes the acquired instruction;

[0037] S123, the instruction queue part stores the decoded instructions in sequence.

[0038] Further, the data module includes a data I / O unit and a data temporary storage unit, wherein step S2 includes:

[0039] S21, the data I / O unit directly reads the operation data from the memory and stores it in the data temporary storage unit;

[0040] S22, the data temporary storage unit adjusts the stored operation data and provides it to the operation module.

[0041] Further, step S22 includes:

[0042] When the lengths of the two operation data involved in the operation are both less than or equal to the operation scale of the operation module, the data temporary storage unit directly provides the two operation data to the operation module;

[0043] When the lengths of two operation data involved in the operation are both greater than the operation scale of the operation module, each operation data is split into a plurality of sub-operation data whose lengths are less than or equal to the operation scale, and the sub-operation data are provided to the operation module in multiple times;

[0044] When one of the two operation data involved in the operation has a length greater than the operation scale of the operation module, and the other operation data has a length less than or equal to the operation scale of the operation module, the operation data with a length greater than the operation scale is split into multiple sub-operation data with lengths less than or equal to the operation scale, and the multiple sub-operation data and the operation data with a length less than or equal to the operation scale are provided to the operation module in multiple times.

[0045] Furthermore, the operation data is a vector, and the operation module is used to perform vector logical operations or vector arithmetic operations.

[0046] (III) Beneficial effects

[0047] The computing device and the operation method thereof provided by the present invention can read the computing data from the memory and temporarily store it in the data temporary storage unit when only one instruction is sent. The data temporary storage unit adjusts the computing data according to the length of the computing data and provides it to the computing module, thereby supporting the computing of data of different lengths and reducing the scale of the computing unit. In addition, the present invention adopts a dependency processing unit to solve the correlation problem in data storage, thereby improving the execution performance of a large number of computing tasks. Moreover, the instructions adopted by the present invention have a streamlined format, so that the instruction set structure is simple, easy to use, and supports flexible data length and computing scale.

[0048] The present invention can be applied to the following (including but not limited to) scenarios: various electronic products such as data processing, robots, computers, printers, scanners, telephones, tablet computers, smart terminals, mobile phones, driving recorders, navigators, sensors, cameras, cloud servers, cameras, camcorders, projectors, watches, headphones, mobile storage, wearable devices, etc.; various means of transportation such as airplanes, ships, and vehicles; various household appliances such as televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, range hoods, etc.; and various medical equipment including magnetic resonance imaging, B-ultrasound, electrocardiographs, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 It is a schematic diagram of the structure of the computing device provided by the present invention.

[0050] Figure 2 It is a structural diagram of the instruction module in the present invention.

[0051] Figure 3 It is a structural diagram of the data module in the present invention.

[0052] Figure 4 It is a structural schematic diagram of the operation module in the present invention.

[0053] Figure 5 It is a flow chart of a method for supporting instructions for operating data of different lengths in the present invention.

[0054] Figure 6 It is a schematic diagram of the operation relationship of cyclically reading shorter vectors for operation when operation vectors of different lengths are operated according to an embodiment of the present invention. DETAILED DESCRIPTION

[0055] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0056] Figure 1 is a schematic diagram of the structure of the computing device provided by the present invention, such as Figure 1 As shown, the device includes an instruction module 10, a data module 20 and an operation module 30. The instruction module 10 is used to cache instructions and provide instructions to the data module 20 and the operation module 30. The instructions in the instruction module 10 control the direction of the data flow of the data module 20, and the data of the data module 20 will affect the processing of the dependency relationship in the instruction module 10. At the same time, the instructions in the instruction module 10 control the specific operation of the operation module 30. Whether the operation of the operation module 30 is completed will control whether the instruction module 10 reads new instructions; the data module 20 provides specific operation data for the operation module 30, and the operation module 30 will send the operation result back to the data module 20 for storage.

[0057] Figure 2 Schematic diagram of the instruction module of the device provided by the present invention. Figure 2 As shown, the instruction module 10 includes an instruction cache unit 11, an instruction processing unit 12, a dependency processing unit 13 and a storage queue unit 14. Among them, the instruction processing unit 12 is divided into three parts: an instruction fetching part 121, a decoding part 122 and an instruction queue part 123. The instruction cache unit 11 is used to cache the instruction during the instruction execution process. When an instruction is executed, if the instruction is also the earliest instruction among the uncommitted instructions in the instruction cache unit 11, the instruction will be submitted. Once submitted, the change of the device state caused by the operation performed by the instruction cannot be undone. The instruction fetching part 121 is used to fetch the next instruction to be executed from the instruction cache unit 11 and pass the instruction to the decoding part 122; the decoding part 122 is used to decode the instruction and pass the decoded instruction to the instruction queue 123; the instruction queue part 123 is used to sequentially store the decoded instructions. The dependency processing unit 13 is used to process the data dependency that may exist between the current instruction and the previous instruction. For example, when accessing data from the data module 20, the previous and next instructions may access data in the same storage space. If the previous instruction is not executed completely, and the data is operated, it will affect the consistency of the data, thereby causing the correctness of the operation result. Therefore, if the current instruction is detected by the dependency processing unit 13 to have a data dependency with the previous instruction, the instruction must wait in the storage queue unit 14 until the dependency is eliminated, wherein the storage queue unit 14 is an ordered queue, and instructions that have a data dependency with the previous instruction are stored in the queue until the dependency is eliminated.

[0058] Figure 3 It is a schematic diagram of the structure of the data module in the present invention. Figure 3As shown, the data module 20 is composed of two parts, namely, a data I / O unit 21 and a data temporary storage unit 22. The data I / O unit 21 is used to interact with the memory, that is, it can directly read data from the memory or directly write data into the memory. The data temporary storage unit 22 is composed of a high-speed scratchpad memory (ScratchpadMemory), wherein the memory can be implemented by various different storage devices (SRAM, eDRAM, DRAM, memristor, 3D-DRAM or non-volatile storage, etc.). The data temporary storage unit 22 can store operation data of different sizes, such as vector data of various sizes. The data I / O unit 21 reads out the necessary operation data according to the instruction and temporarily stores it in the data temporary storage unit 22. Due to the use of a high-speed scratchpad memory, operation data of different lengths can be stored. At the same time, during the operation process, the data temporary storage unit 22 can adjust the operation data according to the scale of the operation module 30 and the length of the operation data, and provide it to the operation module 30.

[0059] Specifically, when the lengths of the two operation data involved in the operation are both less than or equal to the operation scale of the operation module, the data temporary storage unit 22 directly provides the two operation data to the operation module 30. For example, the operation scale of the operation module 30 is to process two groups of vectors at one time, each group of vectors includes 4 elements, such as (A1, A2, A3, A4) and (B1, B2, B3, B4) is the operation scale of the operation module 30; the two operation data are vectors with less than 4 elements, such as (A1, A2, A3) and (B1, B2), at this time, (A1, A2, A3) and (B1, B2) can be directly provided to the operation module 30 for operation.

[0060] When the lengths of the two operation data involved in the operation are both greater than the operation scale of the operation module, the data temporary storage unit 22 splits each operation data into multiple sub-operation data whose lengths are less than or equal to the operation scale, and provides the sub-operation data to the operation module in multiple times. For example, the operation scale of the operation module 30 is the operation scale that can process two groups of vector operations at one time, where each group of vectors includes 4 elements, such as (A1, A2, A3, A4) and (B1, B2, B3, B4) The operation between is the operation scale of the operation module 30; two operation data are both greater than the operation scale, such as (A1, A2, A3, A4, A5) and (B1, B2, B3, B4, B5), at this time, (A1, A2, In the above example, the operation data larger than the operation scale are split into two segments, and the sub-operation data of the corresponding segment are provided each time. When the number of segments of two operation data is inconsistent, for example, the first operation data is split into 3 segments, represented by D1, D2, and D3, and the second operation data is split into 2 segments, represented by d1 and d2, then the first operation data D1, D2, and D3 are provided to the operation unit 3 times, and the second operation data d1 and d2 need to be provided cyclically for these 3 times, that is, D1 and d1 are provided for the first time, D2 and d2 are provided for the second time, and D3 and d1 are provided for the third time. For another example, the first operation data is split into 5 segments, represented by D1, D2, D3, D4, and D5, and the second operation data is split into 3 segments, represented by d1, d2, and d3, then the operation data are provided to the operation unit 5 times, that is, D1 and d1 are provided for the first time, D2 and d2 are provided for the second time, D3 and d3 are provided for the third time, D4 ​​and d1 are provided for the fourth time, and D5 and d2 are provided for the fifth time.

[0061] When one of the two operation data involved in the operation is longer than the operation scale of the operation module, and the other is less than or equal to the operation scale of the operation module, the operation data with a length greater than the operation scale is split into a plurality of sub-operation data with lengths less than or equal to the operation scale, and the plurality of sub-operation data and the operation data with a length less than or equal to the operation scale are provided to the operation module in multiple times. For example, the length of the first operation data is greater than the operation scale, and is split into three segments D1, D2, and D3. The second operation data is less than or equal to the operation scale and does not need to be split, which is represented by d. Then the first and second operation data are provided to the operation unit in three times, that is, D1 and d are provided for the first time, D2 and d are provided for the second time, and D3 and d are provided for the third time.

[0062] In general, the adjustment of the operation data by the data temporary storage unit 22 means that when the length of the operation data is not greater than the operation scale of the operation unit, the data to be operated can be directly sent to the operation module 30 through the memory; otherwise, for each operation, the data that meets the operation scale of the operation module 30 is sent to the operation module 30, and after the operation is completed or the batch of data enters the next level of pipeline, the memory sends a new batch of data that meets the operation scale of the operation module 30 to the operation module 30 for operation. In addition, when the lengths of two data to be operated are the same, they are directly or split into pieces and sent to the operation module 30 for operation; otherwise, the data with a larger length is segmented and read in sequence, and the data with a smaller length is segmented and read cyclically until the operation is completed.

[0063] Figure 4 Schematic diagram of the structure of the computing module of the device provided by the present invention. Figure 4 As shown, the operation module is composed of several different operation components, such as vector addition component, vector subtraction component, vector logical AND component, vector dot product component, etc. There are several of each component. Using these operation components, the operation module can support a variety of vector operations.

[0064] Figure 5 1 is a flowchart of a method for supporting instructions of different lengths of operation data in the present invention. The process of executing the instruction includes:

[0065] S1, the instruction fetching part 121 in the instruction processing unit 12 fetches a vector operation instruction from the instruction cache unit 11, and sends the instruction to the decoding part 122 in the instruction processing unit.

[0066] S2, the decoding part 122 decodes the instruction and splits the instruction into an operation code and various operation domains according to the self-defined instruction rules. The self-defined instruction rules adopted here are that the instruction includes an operation code and at least one operation domain, the operation code defines the type of vector operation, the operation domain stores the data value to be operated, the address of data storage, the length of the data or the address of the operation result storage, etc. The meaning of the specific operation domain varies according to the different operation codes. Then, the operation instruction is sent to the instruction queue part 123.

[0067] S3, in the instruction queue part 123, the data to be operated is obtained according to the operation code and operation domain of the instruction, and sent to the dependency processing unit 13 to analyze and judge the data dependency.

[0068] S4, in the dependency processing unit 14, analyze whether the instruction has a data dependency relationship with the previous instruction that has not yet been executed. If there is no dependency relationship, there is no need to wait, otherwise the instruction is stored in the storage queue unit and waits until it no longer has a data dependency relationship with the previous instruction that has not yet been executed. The instruction is sent to the operation module 30.

[0069] S5, when the instruction is sent to the operation module 30 for calculation, the data temporary storage unit 22 in the data module 20 adjusts the data according to the length of the data and the scale of the operation module 30, that is, when the vector length is not greater than the operation scale of the operation module 30, the vector to be calculated can be directly sent to the operation module 30; otherwise, for each calculation, the data that meets the operation scale of the operation module 30 is sent to the operation module 30, and after the calculation is completed, a new batch of data that meets the operation scale is sent to the operation module 30 for calculation until the calculation is completed. When the lengths of the two vectors to be calculated are the same, they are directly sent to the operation module for calculation; otherwise, the vector with a larger length is read in sequence, and the vector with a smaller length is read in a loop until the calculation is completed. If the vector to be calculated needs to be adjusted according to the scale of the operation module and the length needs to be adjusted at the same time, it is ensured that the vector with a larger length is read in sequence, and the vector with a smaller length is read in a loop, and the data that meets the operation scale is read in sequence.

[0070] S6, after the operation is completed, the result is written back to the specified address in the data temporary storage unit 22, and the instruction in the instruction cache unit 11 is submitted.

[0071] In order to make the process more clear, a specific embodiment is provided below, and the process is further described in detail with reference to the accompanying drawings.

[0072] Embodiment 1

[0073] This embodiment describes the specific process of using a computing device to perform vector AND operations. First, the vector AND operation instruction format in this embodiment is:

[0074]

[0075] Assume that each register address can store 16-bit data, and the operation unit contains 4 inter-and operations, each of which can perform inter-and operations on 16-bit data at the same time. Take the operation instruction VAV 00001 01000 01001 0100010001 as an example. This instruction indicates that vector 0 and vector 1 perform VAV operations, that is, inter-vector and operations. Specifically, the process of inter-vector and operations includes:

[0076] S1, the instruction fetch part 121 in the instruction processing unit 11 fetches a vector operation instruction, namely VAV 00001 01000 01001 01000 10001, from the instruction cache unit 11, and sends the instruction to the decoding part 122 in the instruction processing unit 12.

[0077] S2, the decoding part 122 decodes the instruction and obtains the instruction operation code VAV, which indicates to perform an AND operation between vectors. There are five operation domains, which respectively represent the starting address and length of the vector vin0 to be operated, the starting address and length of the vector vin1, and the storage address of the operation result. The operation instruction is sent to the instruction queue part 123.

[0078] S3, in the instruction queue part 123, the data to be operated is obtained according to the operation code and operation domain of the instruction. The instruction operation code is VAV, that is, the vector and logic operation is performed, and the data address and data length to be operated are obtained from the operation domains 1, 2, 3, and 4, that is, the starting address of vector vin0 is 00001, the length of vector vin0 is 01000, the starting address of vector vin1 is 01001, and the length of vector vin1 is 01000. That is, vector vin0 starts from address 00001 and reads data with a length of 8 addresses, that is, data with addresses 00001 to 01000; vector vin1 starts from address 01001 and similarly reads data with a length of 8 addresses. Then, it is sent to the dependency processing unit 13 to analyze and judge the data dependency.

[0079] S4, in the dependency processing unit 123, analyze whether the instruction has a data dependency relationship with the previous instruction that has not yet been executed. If there is no dependency relationship, there is no need to wait, otherwise the instruction is stored in the storage queue unit 14 and waits until it no longer has a data dependency relationship with the previous instruction that has not been executed. The instruction is sent to the operation module 30.

[0080] S5, the data I / O unit 21 in the data module 20 obtains data from the external memory in advance, and stores the obtained data in the data temporary storage unit 22. When the instruction is sent to the operation module 30 for operation, the data temporary storage unit 22 finds the corresponding data according to the data address indicated by the instruction and provides it to the operation module 30. Before providing, the data temporary storage unit 22 adjusts the data according to the length of the data and the operation scale of the operation module 30. Here, the operation module 30 can only process the AND operation of 4 groups of 16-bit vectors at a time, so the data sent to the operation module 30 for the first time is the data of the first 4 address lengths pointed to by vin0 and the data of the first 4 address lengths pointed to by vin1, that is, the data with addresses 00001~00100 and 01001~01100 are operated. After the operation is completed, the data with the last 4 address lengths of vin0 and vin1 are loaded for operation, that is, the data with addresses 00101~01000 and 01101~10000 are operated.

[0081] S6, after the operation is completed, the result is written back to the designated address 10001 in the data temporary storage unit 22, and the vector and logic instruction in the instruction cache unit is submitted at the same time.

[0082] Embodiment 2

[0083] This embodiment describes the specific process of using a computing device to perform a vector addition operation. First, in this embodiment, the vector addition operation instruction format is defined as:

[0084]

[0085] Assume that each address of the register can store 16-bit data, and the operation unit contains 4 adders, each of which can perform 16-bit data addition operations at the same time. Take VA 00001 01000 01001 00010 10001 as an example. This instruction indicates that vector 0 and vector 1 perform VA operation, that is, vector addition operation. The process of the operation device executing the vector addition instruction includes:

[0086] S1, the instruction fetching part 121 in the instruction processing unit 12 fetches a vector operation instruction, namely VA 00001 01000 01001 00010 10001, from the instruction cache unit 11, and sends the instruction to the decoding part 12 in the instruction processing unit.

[0087] S2, the decoding part 12 decodes the instruction and obtains the instruction operation code VA, which indicates the execution of vector addition operation. There are five operation domains, which respectively represent the starting address and length of the vector vin0 to be operated, the starting address and length of the vector vin1, and the storage address of the operation result. The operation instruction is sent to the instruction queue part 123.

[0088] S3, in the instruction queue part 123, the data to be operated is obtained according to the operation code and operation domain of the instruction. The instruction operation code is VA, that is, the vector addition operation is performed, and the data address and data length to be operated are obtained from the operation domains 1, 2, 3, and 4, that is, the starting address of vector vin0 is 00001, the length of vector vin0 is 01000, the starting address of vector vin1 is 01001, and the length of vector vin1 is 00010. That is, vector vin0 starts from address 00001 and reads data with a length of 8 addresses, that is, data with addresses 00001 to 01000; vector vin1 starts from address 01001 and reads data with a length of 2 addresses. Then, it is sent to the dependency processing unit 13 to analyze and judge the data dependency.

[0089] S4, in the dependency processing unit 13, analyze whether the instruction has a data dependency with the previous instruction that has not yet been executed. If there is no dependency, there is no need to wait, otherwise the instruction is stored in the storage queue unit and waits until it no longer has a data dependency with the previous instruction that has not yet been executed. The instruction is sent to the operation unit.

[0090] S5, after the dependency relationship no longer exists, the vector addition instruction is sent to the operation module 30. The operation module 30 takes out the required vector from the data temporary storage unit 22 according to the address and length of the required data, and then completes the addition operation in the operation unit. Here, because the operation module 30 can only process the addition operation of 4 groups of 16-bit vectors at a time, all data cannot be sent to the operation unit for operation at one time, but needs to be performed in multiple times. Because the lengths of vin0 and vin1 are different, and the length of vin1 is shorter, the data of vin1 needs to be read cyclically during the operation. Figure 6As shown, the data sent to the operation module 30 for the first time are the data of the first 4 address lengths pointed to by vin0 and the data of the 2 address lengths pointed to by vin1, that is, the data sent are the data of addresses 00001~00100 and 01001~01010, wherein the corresponding relationship of the data to be operated is: the data at address 00001 is added to the data at address 01001, the data at address 00010 is added to the data at address 01010, the data at address 00011 is added to the data at address 01001, and the data at address 00100 is added to the data at address 01010. After the operation is completed, the data sent to the operation module 30 for the second time is the data of the last 4 address lengths pointed to by vin0 and the data of the 2 address lengths pointed to by vin1, that is, the data at addresses 00101~01000 and 01001~01010 are added. The corresponding relationship during the operation is that the data at address 00101 is added to the data at address 01001, the data at address 00110 is added to the data at address 01010, the data at address 00111 is added to the data at address 01001, and the data at address 01000 is added to the data at address 01010.

[0091] S6, after the operation is completed, the result is written back to the designated address 10001 in the data temporary storage unit 22, and the vector addition instruction in the instruction cache unit 11 is submitted at the same time.

[0092] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A computing device, characterized in that: The computing device comprises: a data module, used to acquire and store operation data, and adjust the operation data according to the length of the operation data and the scale of the operation module to obtain adjusted operation data, so that the adjusted operation data conforms to the scale of the operation module; and A calculation module, used for performing calculations according to the adjusted calculation data provided by the data module; Wherein, the operation data includes first data and second data; The data module is used for, when the length of the first data and the length of the second data are both greater than the operation scale of the operation module, splitting the first data and the second data into a plurality of first sub-operation data and a plurality of second sub-operation data, respectively, and providing the first sub-operation data and the second sub-operation data to the operation module for operation in batches; the length of the first sub-operation data and the length of the second sub-operation data are both less than or equal to the operation scale of the operation module; or The data module is used to split the first data into multiple first sub-operation data when the length of the first data is greater than the operation scale of the operation module and the length of the second data is less than the operation scale of the operation module, and provide the first sub-operation data and the second data to the operation module for operation in multiple times; the length of the first sub-operation data is less than or equal to the operation scale of the operation module.

2. The computing device according to claim 1, wherein: The data module includes: A data I / O unit, used to read operation data from the memory or write the operation data into the memory; The data temporary storage unit is used to store the data read by the data I / O unit, and adjust the data according to the length of the operation data and the scale of the operation module to obtain adjusted data.

3. The computing device according to claim 2, wherein: The operation data includes first data and second data; When the length of the first data and the length of the second data are both less than or equal to the operation scale of the operation module, the data temporary storage unit is used to directly provide the first data and the second data as adjusted operation data to the operation module for operation.

4. The computing device according to claim 2, wherein: When the number of the first sub-operation data is greater than the number of the second sub-operation data, the data temporary storage unit is used to provide the plurality of the first sub-operation data to the operation module in sequence, and cyclically provide the plurality of the second sub-operation data to the operation module until the operation is completed; When the quantity of the first sub-operation data is equal to the quantity of the second sub-operation data, the data temporary storage unit is used to provide the first sub-operation data and the second sub-operation data to the operation module in sequence.

5. The computing device according to any one of claims 2 to 4, characterized in that: The data temporary storage unit is composed of a high-speed temporary storage memory, and the data temporary storage unit can store operation data of different lengths.

6. The computing device according to claim 5, characterized in that: The computing device further comprises an instruction module, which is used to cache instructions and provide instructions to the data module and the computing module; Wherein, the instruction module includes: An instruction cache unit, used to store instructions to be executed; An instruction processing unit, used for obtaining instructions from the instruction cache unit and processing the instructions; The dependency processing unit and the storage queue unit are used to determine whether the instruction and the previous instruction being executed access the same data: if so, the dependency processing unit stores the instruction in the storage queue unit, and provides the instruction to the operation module after the previous instruction being executed is completed; otherwise, the instruction is directly provided to the operation module; Wherein, the instruction processing unit includes: An instruction fetching part, used for fetching instructions from the instruction cache unit; A decoding part, used to decode the fetched instructions; The instruction queue part is used to sequentially store the decoded instructions.

7. The computing device according to claim 1, wherein: The operation data is a vector, and the operation module is used to perform vector logic operations or vector arithmetic operations according to instructions.

8. The computing device according to claim 7, characterized in that: The instruction includes an operation code and an operation field, wherein the operation field includes a starting storage address of the first data, a length of the first data, a starting storage address of the second data, and a length of the second data; When the instruction is sent to the operation module for preparation for operation, the data module obtains the first data according to the starting storage address of the first data of the instruction and the length of the first data, and obtains the second data according to the starting storage address of the second data and the length of the second data. 9 . The computing device according to claim 7 , wherein the instructions include vector AND instructions and vector addition instructions.

10. The computing device according to claim 1, wherein: The operation module includes at least one of an addition component, a subtraction component, a logical AND component and a dot product component.

11. An electronic device, characterized in that: A computing device comprising any one of claims 1-10.

12. A data computing method, characterized in that: The method comprises: The data module acquires and stores the operation data, and adjusts the operation data according to the length of the operation data and the scale of the operation module to obtain the adjusted operation data, so that the adjusted operation data conforms to the scale of the operation module; The operation module performs operation according to the adjusted operation data provided by the data module; The operation data includes first data and second data; the data module adjusts the operation data according to the length of the operation data and the scale of the operation module, including: When the length of the first data and the length of the second data are both greater than the operation scale of the operation module, the first data and the second data are split into a plurality of first sub-operation data and a plurality of second sub-operation data, and the first sub-operation data and the second sub-operation data are provided to the operation module for operation in batches; the length of the first sub-operation data and the length of the second sub-operation data are both less than or equal to the operation scale of the operation module; When the length of the first data is greater than the operation scale of the operation module and the length of the second data is less than the operation scale of the operation module, the data module splits the first data into multiple first sub-operation data, and provides the first sub-operation data and the second data to the operation module for operation in multiple times; the length of the first sub-operation data is less than or equal to the operation scale of the operation module.

13. The method according to claim 12, characterized in that The data includes first data and second data; the data module adjusts the operation data according to the length of the operation data and the scale of the operation module, including: When the length of the first data and the length of the second data are both less than or equal to the operation scale of the operation module, the first data and the second data are directly used as adjusted operation data and provided to the operation module for operation.

14. The method according to claim 12, characterized in that When the number of the first sub-operation data is greater than the number of the second sub-operation data, the data module provides a plurality of the first sub-operation data to the operation module in sequence, and cyclically provides a plurality of the second sub-operation data to the operation module until the operation is completed; When the quantity of the first sub-operation data is equal to the quantity of the second sub-operation data, the data temporary storage unit sequentially provides the first sub-operation data and the second sub-operation data to the operation module.

15. The method according to any one of claims 12 to 14, characterized in that: The method further comprises: The instruction module caches instructions and provides instructions to the data module and the operation module; The instruction module caches instructions and provides instructions to the data module and the operation module, including: Storing instructions to be executed in an instruction cache unit; The instruction processing unit obtains the instruction from the instruction cache unit and processes the instruction; The dependency processing unit determines whether the instruction accesses the same data as the previously executed instruction. If so, the dependency processing unit stores the instruction in the storage queue unit and provides the instruction to the operation module after the previously executed instruction is completed. Otherwise, the instruction is directly provided to the operation module.

16. The method according to claim 15, characterized in that The operation data is a vector, and the instructions include vector AND instructions and vector addition instructions; the operation module is used to perform vector logic operations or vector arithmetic operations according to the instructions; The instruction includes an operation code and an operation field, and the operation field includes a starting storage address of the first data, a length of the first data, a starting storage address of the second data, and a length of the second data; When the instruction is sent to the operation module for preparation for operation, the data module obtains the first data according to the starting storage address of the first data of the instruction and the length of the first data, and obtains the second data according to the starting storage address of the second data and the length of the second data.

Images