A packaging structure and packaging method for high voltage power semiconductor chip

Abstract

The present invention provides a packaging structure and a packaging method for a high-voltage power semiconductor chip. The packaging structure for the high-voltage power semiconductor chip comprises a substrate; a high-voltage power semiconductor chip located on a portion of a collector conductive layer and electrically connected to the collector conductive layer, wherein an emitter of the high-voltage power semiconductor chip is electrically connected to the emitter conductive layer; a collector lead-out terminal located on the collector conductive layer and electrically connected to the collector conductive layer; an emitter lead-out terminal located on the emitter conductive layer and electrically connected to the emitter conductive layer; the collector lead-out terminal comprises a first section, the emitter lead-out terminal comprises a second section arranged opposite to the first section, the first section is recessed toward the emitter lead-out terminal, and / or the second section is recessed toward the collector lead-out terminal; and a first insulating filling layer between the first section and the second section. The packaging structure has a relatively small parasitic inductance and is therefore suitable for packaging high-voltage power semiconductor chips.

Description

Technical Field

[0001] The present invention relates to the field of power semiconductor device packaging, and in particular to a packaging structure and a packaging method for a high-voltage power semiconductor chip. Background Art

[0002] In order to meet the large-scale development and utilization of renewable energy, the traditional power grid is developing towards the direction of smart grid represented by the widespread application of power electronics technology. Power electronic devices play an irreplaceable role in various fields such as the construction of strong smart grid of State Grid Corporation of China, FACTS high-voltage transmission, and access to new energy. This undoubtedly puts forward higher requirements for high-voltage, large-capacity, high-frequency, and high-temperature resistant power electronic devices. At present, most of the high-power power electronic devices in the power system use silicon-based power electronic devices to achieve the control and conversion of electric energy. Since silicon-based power electronic devices are subject to the limitations of the physical properties of the material itself, such as voltage resistance and operating temperature, in order to fundamentally improve the reliability and stability of high-power power electronic equipment, reduce the overall loss of the system, and improve the control and conversion efficiency of energy, it is necessary to research and develop new power electronic devices with higher voltage resistance, lower power consumption, and high temperature resistance. Silicon Carbide (SiC)-based devices are one of the most mature and widely used third-generation semiconductor power electronic devices so far. They can break the physical limits of traditional silicon-based devices and have the advantages of high voltage level, large current capacity, low loss, and fast heat dissipation. They can be widely used in new power electronic equipment such as solid-state transformers and solid-state circuit breakers, as well as traditional FACTS and DC transmission equipment. They will have an important impact on the economic and safe operation of power systems and realize the innovation of power grid technology.

[0003] The application switching frequency of traditional silicon-based power semiconductor chips is less than 40kHZ, while the application switching frequency of silicon carbide-based power semiconductor chips is greater than 100kHz, that is, the application switching frequency of silicon carbide-based power semiconductor chips is much greater than that of traditional silicon-based power semiconductor chips. Currently, there are few packaging structures for high-voltage silicon carbide-based devices. High-voltage silicon carbide-based devices require low parasitic inductance (less than 10nH), and the parasitic inductance of the packaging structure used for traditional silicon-based power semiconductor chips is extremely high. Excessive parasitic inductance will produce very high voltage spikes during the device switching process, thereby affecting the switching frequency. Therefore, the packaging structure of traditional silicon-based power semiconductor chips is not suitable for high-voltage power semiconductor chip packaging. Summary of the invention

[0004] The technical problem to be solved by the present invention is to overcome the defect of high parasitic inductance of the packaging structure of the power semiconductor chip in the prior art.

[0005] In order to solve the above technical problems, the present invention provides a packaging structure of a high-voltage power semiconductor chip, comprising:

[0006] A substrate, wherein a separate emitter conductive layer and a collector conductive layer are disposed on the surface of the substrate;

[0007] a high-voltage power semiconductor chip located on part of the collector conductive layer and electrically connected to the collector conductive layer, wherein the high-voltage power semiconductor chip has an emitter on a side opposite to the substrate, and the emitter is electrically connected to the emitter conductive layer;

[0008] A collector lead-out terminal, the collector lead-out terminal is located on the collector conductive layer and is electrically connected to the collector conductive layer;

[0009] An emitter lead-out terminal, the emitter lead-out terminal is located on the emitter conductive layer and is electrically connected to the emitter conductive layer;

[0010] The collector lead terminal includes a first segment, the emitter lead terminal includes a second segment arranged opposite to the first segment, the first segment is recessed toward the emitter lead terminal, and / or the second segment is recessed toward the collector lead terminal;

[0011] A first insulating filling layer is located between the first section and the second section.

[0012] Optionally, the collector conductive layer and the emitter conductive layer are arranged opposite to each other, and the high-voltage power semiconductor chip is located between the collector lead-out terminal and the emitter lead-out terminal.

[0013] Optionally, the packaging structure of the high-voltage power semiconductor chip further includes:

[0014] Bottom plate; the substrate is located on a portion of the bottom plate;

[0015] Insulating frame; the insulating frame comprises: a frame body with a hollow structure, the frame body is located on the bottom plate around the substrate; a frame cover mounted on the frame body, the frame cover having a collector opening and an emitter opening penetrating the frame cover;

[0016] The collector lead terminal is located in the frame body and extends outside the collector opening, the emitter lead terminal is located in the frame body and extends outside the emitter opening, and the first section area and the second section area are located inside the frame body;

[0017] The frame cover includes a frame cover body and an insulating filling layer connected to the frame cover body, the insulating filling layer is located between the collector opening and the emitter opening, and the insulating filling layer includes a first insulating filling layer extending toward the bottom plate relative to the frame cover body.

[0018] Optionally, the first section is located between the top and bottom of the collector lead terminal, and the second section is located between the top and bottom of the emitter lead terminal; the distance between the top of the collector lead terminal and the top of the emitter lead terminal is greater than the distance between the first section and the second section;

[0019] The insulating filling layer further comprises a second insulating filling layer connected to the frame cover body, the second insulating filling layer is located on a side of the first insulating filling layer facing away from the bottom plate and connected to the first insulating filling layer;

[0020] The area between the top of the collector lead terminal and the top of the first section is the third section, and the area between the top of the emitter lead terminal and the top of the second section is the fourth section;

[0021] The second insulating filling layer is located between the third section area and the fourth section area.

[0022] Optionally, the second insulating filling layer is a reinforcing rib structure.

[0023] Optionally, a first connecting piece is provided at a top of the collector lead terminal away from the substrate; a second connecting piece is provided at a top of the emitter lead terminal away from the substrate;

[0024] The insulating frame also includes: fillers respectively located in the collector opening and the emitter opening, and the fillers are mounted on the frame body; the first connecting piece and the second connecting piece are located on a side of the filler facing away from the substrate and in contact with an upper surface of the filler.

[0025] Optionally, the first connecting piece has a first hole passing through the first connecting piece; the second connecting piece has a second hole passing through the second connecting piece; the filling piece has a third hole passing through the filling piece, the third hole of the filling piece located below the first connecting piece is connected to the first hole, and the third hole of the filling piece located below the second connecting piece is connected to the second hole.

[0026] Optionally, the height of the collector lead terminal is 38mm-40mm; the height of the emitter lead terminal is 38mm-40mm.

[0027] Optionally, the first section occupies 5 mm to 6 mm of the height of the collector lead terminal; and the second section occupies 17 mm to 18 mm of the height of the emitter lead terminal.

[0028] Optionally, the packaging structure of the high-voltage power semiconductor chip further includes a packaging glue layer, and the packaging glue is located in the accommodating cavity formed by the base plate, the frame body and the frame cover and covers the high-voltage power semiconductor chip.

[0029] Optionally, the encapsulation adhesive layer includes a silicone gel layer and an epoxy adhesive layer located on a surface of the silicone gel layer facing away from the substrate, wherein a top surface of the silicone gel layer is flush with a top of the first section or the second section.

[0030] The present invention also provides a packaging method for a high-voltage power semiconductor chip, comprising the following steps:

[0031] Providing a substrate, a high-voltage power semiconductor chip, a collector lead terminal and an emitter lead terminal, wherein a separate emitter conductive layer and a collector conductive layer are arranged on the surface of the substrate, and the high-voltage power semiconductor chip has an emitter on a side opposite to the substrate;

[0032] The high-voltage power semiconductor chip is arranged on a portion of the collector conductive layer, the high-voltage power semiconductor chip is electrically connected to the collector conductive layer, and the emitter is electrically connected to the emitter conductive layer;

[0033] The collector lead-out terminal is arranged on the collector conductive layer, the collector lead-out terminal is electrically connected to the collector conductive layer, and the collector lead-out terminal includes a first section;

[0034] An emitter lead-out terminal is arranged on the emitter conductive layer, the emitter lead-out terminal is electrically connected to the emitter conductive layer, the emitter lead-out terminal comprises a second segment area arranged opposite to the first segment area, the first segment area is recessed toward the emitter lead-out terminal, and / or the second segment area is recessed toward the collector lead-out terminal;

[0035] A first insulating filling layer is disposed between the first section and the second section.

[0036] Optionally, the packaging method of the high-voltage power semiconductor chip further includes:

[0037] A bottom plate and an insulating frame are provided, wherein the insulating frame comprises: a frame body with a hollow structure and a frame cover, wherein the frame cover has a collector opening and an emitter opening penetrating the frame cover, wherein the frame cover comprises the frame cover body and the insulating filling layer connected to the frame cover body, wherein the insulating filling layer is located between the collector opening and the emitter opening, and wherein the insulating filling layer comprises a first insulating filling layer;

[0038] Before the collector lead terminal is disposed on the collector conductive layer, and before the emitter lead terminal is disposed on the emitter conductive layer, the substrate is fixedly connected to a portion of the bottom plate;

[0039] After the collector lead terminal is disposed on the collector conductive layer, and after the emitter lead terminal is disposed on the emitter conductive layer, the frame body is fixedly connected to the bottom plate around the substrate;

[0040] The frame cover is overlapped on the edge of the frame body, the collector lead terminal extends outward from the collector opening, and the emitter lead terminal extends outward from the emitter opening. In the process of overlapping the frame cover on the edge of the frame body, a first insulating filling layer is arranged between the first section area and the second section area.

[0041] Optionally, the first section is located between the top and bottom of the collector lead terminal, the second section is located between the top and bottom of the emitter lead terminal, the area between the top of the collector lead terminal and the top of the first section is the third section, and the area between the top of the emitter lead terminal and the top of the second section is the fourth section; the distance between the top of the collector lead terminal and the top of the emitter lead terminal is greater than the distance between the first section and the second section;

[0042] The insulating filling layer also includes a second insulating filling layer, and the frame body, the second insulating filling layer and the first insulating filling layer are connected in sequence; in the process of overlapping the frame cover on the edge of the frame body, the second insulating filling layer is filled between the third section and the fourth section.

[0043] Optionally, a first connecting piece is provided at a top of the collector lead terminal away from the substrate; a second connecting piece is provided at a top of the emitter lead terminal away from the substrate; and the insulating frame further includes a filling piece;

[0044] After overlapping the frame cover on the upper edge of the frame body, the method further includes: arranging the filling piece at the collector opening and the emitter opening respectively, and the first connecting piece and the second connecting piece are located on the side of the filling piece facing away from the substrate and in contact with the upper surface of the filling piece.

[0045] Optionally, after the frame body is fixedly connected to the bottom plate around the substrate, the method further includes: forming a silicone gel layer into the frame body, wherein the top surface of the silicone gel layer is flush with the top of the first section or the second section;

[0046] After the frame cover is overlapped on the edge of the frame body, the method further includes a step of forming an epoxy glue layer on the silicone gel layer.

[0047] The technical solution of the present invention has the following advantages:

[0048] 1. The packaging structure of a high-voltage power semiconductor chip provided by the present invention is that the high-voltage power semiconductor chip is arranged on the collector conductive layer of the substrate and is electrically connected to the collector conductive layer, the emitter is electrically connected to the emitter conductive layer, the collector lead terminal is arranged on the collector conductive layer and is electrically connected to the collector conductive layer, and the emitter lead terminal is arranged on the emitter conductive layer and is electrically connected to the emitter conductive layer, so that the collector lead terminal, the collector, the emitter and the emitter lead terminal are electrically connected, and the current applied to the collector lead terminal and the emitter lead terminal can form a loop to perform a single chip reliability screening test; at the same time, since the first section of the collector lead terminal is recessed toward the emitter lead terminal, and the second section of the emitter lead terminal arranged opposite to the first section is recessed toward the collector lead terminal, the effective area enclosed by the above-mentioned loop is reduced, thereby reducing the parasitic inductance. At the same time, a first insulating filling layer is arranged between the first section and the second section to separate the collector lead terminal from the emitter lead terminal, thereby increasing the creepage distance and thus enhancing the insulation strength, so as to avoid the discharge of the above two conductive terminals under the influence of the applied high voltage current, causing adverse effects on device performance or even device damage. Therefore, the first insulating filling layer is arranged so that the first section is recessed toward the emitter lead terminal and the second section of the emitter lead terminal is recessed toward the collector lead terminal, which provides a basis for being suitable for high-voltage power semiconductor chip packaging.

[0049] 2. In the packaging structure of the high-voltage power semiconductor chip provided by the present invention, the collector conductive layer and the emitter conductive layer are arranged opposite to each other, and the high-voltage power semiconductor chip is located between the collector lead terminal and the emitter lead terminal. The distance from the collector lead terminal and the emitter lead terminal to the high-voltage power semiconductor chip can be set to be smaller, thereby further reducing the effective area of ​​the loop surrounded by the collector lead terminal, the collector, the emitter and the emitter lead terminal, thereby further reducing the parasitic inductance.

[0050] 3. The packaging structure of the high-voltage power semiconductor chip provided by the present invention, the base plate and the insulating frame form an accommodating inner cavity, and the high-voltage power semiconductor chip is placed in the accommodating inner cavity, so that the high-voltage power semiconductor chip is isolated from the outside world during the test process, thereby avoiding the adverse effects of the external environment on the test results, thereby ensuring the accuracy of the test results; at the same time, the insulating frame includes a frame body with a hollow structure and a frame cover mounted on the frame body, and the separate structure facilitates the assembly of the packaging structure.

[0051] 4. The packaging structure of the high-voltage power semiconductor chip provided by the present invention increases the insulation strength between the collector lead terminal and the emitter lead terminal by limiting the distance between the top of the collector lead terminal to the top of the emitter lead terminal to be greater than the distance between the first section and the second section, and arranges a second insulating filling layer between the third section and the fourth section, so as to avoid the discharge of the above two conductive terminals under the influence of the applied high voltage, causing adverse effects on device performance or even device damage; at the same time, the provision of the second insulating filling layer reduces the effective area of ​​the loop formed by the collector lead terminal, the collector, the emitter and the emitter lead terminal, thereby reducing parasitic inductance.

[0052] 5. The packaging structure of the high-voltage power semiconductor chip provided by the present invention, the collector lead terminal is provided with a first connecting piece at the top away from the substrate, the emitter lead terminal is provided with a second connecting piece at the top away from the substrate, the first connecting piece and the second connecting piece are used to connect with the test device during the chip reliability screening test to apply voltage to the high-voltage power semiconductor chip; by arranging the filling piece in the collector opening and the emitter opening, and the first connecting piece and the second connecting piece are located on the side of the filling piece facing away from the substrate and in contact with the upper surface of the filling piece, the collector lead terminal and the emitter lead terminal are firmly fixed between the frame cover and the filling piece, thereby improving the stability of the collector lead terminal and the emitter lead terminal.

[0053] 6. The packaging structure of the high-voltage power semiconductor chip provided by the present invention comprises: the first connecting piece having a first hole penetrating the first connecting piece, the second connecting piece having a second hole penetrating the second connecting piece, the first hole and the second hole being used to connect with the connecting screws in the test device during the chip reliability screening test; the filling piece having a third hole penetrating the filling piece, the provision of the third hole improves the stability of the connection between the connecting screws of the test end and the first hole and the second hole respectively, avoids the collector lead terminal and the emitter lead terminal from falling off from the substrate due to excessive force during connection, and ensures the normal progress of the test.

[0054] 7. The packaging structure of the high-voltage power semiconductor chip provided by the present invention, by arranging the packaging glue layer in the accommodating cavity formed by the base plate and the insulating frame, not only improves the insulation strength of the packaging structure, but also avoids discharge inside the chip under the influence of the applied high-voltage current, which causes adverse effects on device performance or even device damage, and also improves the stability of the packaging structure.

[0055] 8. In the packaging structure of a high-voltage power semiconductor chip provided by the present invention, the top surface of the silicone gel layer is flush with the top of the first section or the second section. Since the silicone gel layer is soft in texture and deforms slightly when the temperature changes, damage to the packaging structure caused by a large deformation of the packaging glue layer due to a large temperature difference before and after the test is avoided. The top surface of the epoxy glue layer is flush with the top surface of the third section or the fourth section. Since the epoxy glue is hard in texture and can isolate water vapor, it not only provides certain support for the packaging structure and improves the strength of the packaging structure, but also avoids damage to the semiconductor chip by water vapor in the environment, thereby ensuring the performance and life of the high-voltage power semiconductor chip.

[0056] 9. The packaging method of a high-voltage power semiconductor chip provided by the present invention is to arrange the high-voltage power semiconductor chip on the collector conductive layer of the substrate and electrically connect it to the collector conductive layer, the emitter is electrically connected to the emitter conductive layer, and the collector lead terminal is arranged on the collector conductive layer and electrically connected to the collector conductive layer, and the emitter lead terminal is arranged on the emitter conductive layer and electrically connected to the emitter conductive layer, so that the collector lead terminal, the collector, the emitter and the emitter lead terminal are electrically connected, and the current applied to the collector lead terminal and the emitter lead terminal can form a loop to perform a single chip reliability screening test; at the same time, since the first section of the collector lead terminal is recessed toward the emitter lead terminal, and the second section of the emitter lead terminal opposite to the first section is recessed toward the collector lead terminal, the effective area enclosed by the above-mentioned loop is reduced, thereby reducing the parasitic inductance. At the same time, a first insulating filling layer is arranged between the first section and the second section to separate the collector lead terminal from the emitter lead terminal, thereby increasing the creepage distance and thus enhancing the insulation strength, so as to avoid the discharge of the above two conductive terminals under the influence of the applied high voltage current, causing adverse effects on device performance or even device damage. Therefore, the first insulating filling layer is arranged so that the first section is recessed toward the emitter lead terminal and the second section of the emitter lead terminal is recessed toward the collector lead terminal, which provides a basis for being suitable for high-voltage power semiconductor chip packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0058] Figure 1 A schematic structural diagram of a packaging structure of a high-voltage power semiconductor chip provided in an embodiment of the present invention;

[0059] Figure 2 for Figure 1 A schematic diagram of the packaging structure of a high-voltage power semiconductor chip and a structure of a base plate and an insulating frame;

[0060] Figure 3 For the corresponding Figure 2 The structural diagram of the middle frame body;

[0061] Figure 4 For the corresponding Figure 2 A schematic diagram of the structure of the middle frame cover;

[0062] Figure 5 For the corresponding Figure 2 A schematic diagram of the structure of the filling piece;

[0063] Figure 6 A schematic diagram of a process for packaging a high-voltage power semiconductor chip provided in an embodiment of the present invention;

[0064] Figures 7 to 12 A schematic diagram of the structure of a packaging process of a high-voltage power semiconductor chip packaging method provided by an embodiment of the present invention;

[0065] Fig.13 For the corresponding Figure 2 An exploded view of the insulating frame in the packaging structure of medium and high voltage power semiconductor chips;

[0066] Reference numerals:

[0067] 1-bottom plate; 2-substrate; 21-emitter conductive layer; 22-collector conductive layer; 23-gate conductive layer; 24-auxiliary emitter conductive layer; 3-high-voltage power semiconductor chip; 4-collector lead terminal; 41-first connecting piece; 42-first hole; 43-first section; 44-third section; 5-emitter lead terminal; 51-second connecting piece; 52-second hole; 53-second section; 54-fourth section; 6-gate lead terminal; 7-auxiliary emitter Pole lead terminal; 8-insulating frame; 81-frame body; 811-second reinforcing rib structure; 82-frame cover body; 821-collector opening; 822-emitter opening; 823-gate opening; 824-auxiliary emitter opening; 825-first insulating filling layer; 826-second insulating filling layer; 827 third reinforcing rib structure; 828-isolation structure; 829-groove; 83-filling piece; 831-third hole; 832-protruding structure; 9-bonding wire. DETAILED DESCRIPTION

[0068] The technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings.

[0069] This embodiment provides a packaging structure for a high-voltage power semiconductor chip. Figure 1 ,include:

[0070] A substrate 2, wherein a separate emitter conductive layer 21 and a collector conductive layer 22 are provided on the surface of the substrate;

[0071] A high-voltage power semiconductor chip 3 located on part of the collector conductive layer 22 and electrically connected to the collector conductive layer 22, wherein the high-voltage power semiconductor chip 3 has an emitter on a side opposite to the substrate 2, and the emitter is electrically connected to the emitter conductive layer 21;

[0072] A collector lead terminal 4, the collector lead terminal is located on the collector conductive layer 22 and is electrically connected to the collector conductive layer 22;

[0073] an emitter lead-out terminal 5, the emitter lead-out terminal being located on the emitter conductive layer 21 and being electrically connected to the emitter conductive layer 21;

[0074] The collector lead terminal 4 includes a first section 43, the emitter lead terminal 5 includes a second section 53 arranged opposite to the first section, the first section 43 is recessed toward the emitter lead terminal 5, and / or the second section 53 is recessed toward the collector lead terminal 4;

[0075] A first insulating filling layer (not shown in the figure) is located between the first section 43 and the second section 53 .

[0076] The packaging structure of the above-mentioned high-voltage power semiconductor chip is achieved by arranging the high-voltage power semiconductor chip on the collector conductive layer of the substrate and electrically connecting it to the collector conductive layer, the emitter is electrically connected to the emitter conductive layer, and the collector lead terminal is arranged on the collector conductive layer and electrically connected to the collector conductive layer, and the emitter lead terminal is arranged on the emitter conductive layer and electrically connected to the emitter conductive layer, so that the collector lead terminal, the collector, the emitter and the emitter lead terminal are electrically connected, and the current applied to the collector lead terminal and the emitter lead terminal can form a loop to perform a single chip reliability screening test; at the same time, since the first section of the collector lead terminal is recessed toward the emitter lead terminal, and the second section of the emitter lead terminal arranged opposite to the first section is recessed toward the collector lead terminal, the effective area enclosed by the above-mentioned loop is reduced, thereby reducing the parasitic inductance. At the same time, a first insulating filling layer is arranged between the first section and the second section to separate the collector lead terminal from the emitter lead terminal, thereby increasing the creepage distance and thus enhancing the insulation strength, so as to avoid the discharge of the above two conductive terminals under the influence of the applied high voltage current, causing adverse effects on device performance or even device damage. Therefore, the first insulating filling layer is arranged so that the first section is recessed toward the emitter lead terminal and the second section of the emitter lead terminal is recessed toward the collector lead terminal, which provides a basis for being suitable for high-voltage power semiconductor chip packaging.

[0077] In this embodiment, the high-voltage power semiconductor chip 3 includes an emitter and a collector, and the emitter and the collector are arranged on opposite surfaces of the high-voltage power semiconductor chip 3, the collector is connected to the collector conductive layer 22 by a nanomaterial sintering process, and the emitter is connected to the emitter conductive layer 21 by a bonding wire 9. The bonding wire 9 includes but is not limited to aluminum wire, copper wire, and aluminum-clad copper wire. The collector lead terminal 4 is welded to the collector conductive layer 22; the emitter lead terminal 5 is welded to the emitter conductive layer 21. The substrate 2 can be a ceramic substrate, and the emitter conductive layer 21 and the collector conductive layer 22 are metal layers on the surface of the ceramic substrate; specifically, the ceramic substrate can be DBC (ceramic copper-clad substrate) or DBA (ceramic aluminum-clad substrate), and the material of the metal layer can be copper or aluminum. The material of the first insulating filling layer 825 can be silicone gel or epoxy. The high-voltage power semiconductor chip 3 may be an insulated gate bipolar transistor (IGBT), a fast recovery diode (FRD), or a metal-oxide-semiconductor field-effect transistor (MOSFET) chip.

[0078] Furthermore, the side of the high-voltage power semiconductor chip 3 away from the substrate 2 and above the bonding wire 9 are coated with an insulating solid material, which can enhance the strength of the bonding wire 9 and the bonding point, prevent the bonding wire 9 from being disconnected or the bonding point from falling off, and also prevent the local discharge phenomenon from damaging the high-voltage power semiconductor chip 3 during the test. The insulating solid material includes but is not limited to polyimide.

[0079] In this embodiment, if Figure 1 As shown, the collector conductive layer 22 is arranged opposite to the emitter conductive layer 21, and the high-voltage power semiconductor chip 3 is located between the collector lead terminal 4 and the emitter lead terminal 5, so that the distance from the collector lead terminal and the emitter lead terminal to the high-voltage power semiconductor chip can be set smaller, further reducing the effective area of ​​the loop surrounded by the collector lead terminal, the collector, the emitter and the emitter lead terminal, thereby further reducing the parasitic inductance.

[0080] like Figure 2 As shown, in this embodiment, the packaging structure of the high-voltage power semiconductor chip further includes:

[0081] Bottom plate 1, the substrate is located on part of the bottom plate 1;

[0082] The insulating frame 8 comprises: a frame body 81 of a hollow structure, the frame body 81 being located on the bottom plate 1 around the substrate 2; a frame cover mounted on the frame body 81, the frame cover having a collector opening 821 and an emitter opening 822 penetrating the frame cover; the frame body 81 may further comprise a second reinforcing rib structure 811 to enhance the strength of the frame body 81 and enhance the stability of the packaging structure; the structure of the frame is as follows Figure 3 As shown, the structure of the frame cover is as follows Figure 4 As shown;

[0083] The collector lead terminal 4 is located in the frame body 81 and extends to the outside of the collector opening 821, the emitter lead terminal 5 is located in the frame body 81 and extends to the outside of the emitter opening 822, and the first section 43 and the second section 53 are located inside the frame body 81;

[0084] The frame cover includes the frame cover body 82 and the insulating filling layer connected to the frame cover body 82 , the insulating filling layer is located between the collector opening 821 and the emitter opening 822 , and the insulating filling layer includes a first insulating filling layer 825 , which extends toward the base plate 1 relative to the frame cover body 82 .

[0085] In the above-mentioned packaging structure of the high-voltage power semiconductor chip, the base plate and the insulating frame form an accommodating inner cavity. By placing the high-voltage power semiconductor chip in the accommodating inner cavity, the high-voltage power semiconductor chip is isolated from the outside world during the test process, thereby avoiding the adverse effects of the external environment on the test results, thereby ensuring the accuracy of the test results; at the same time, the insulating frame includes a frame body with a hollow structure and a frame cover mounted on the frame body, and the separate structure facilitates the assembly of the packaging structure.

[0086] Specifically, the base plate 1 can be a heat sink to dissipate the heat generated during the test to prevent heat accumulation from adversely affecting the performance of the high-voltage power semiconductor chip 3; the heat sink includes but is not limited to AlSiC ceramic plates, copper, aluminum metal plates, and tungsten-copper alloy plates; the substrate 2 is welded to the base plate 1 by welding material, and the welding material is a high-temperature welding sheet with a melting point greater than 250°C, and the material of the high-temperature welding sheet includes but is not limited to PbSnAg; the material of the insulating frame is polybutylene terephthalate (PBT), polyphthalamide (PPA) or polyphenylene sulfide (PPS); the frame body 81 and the substrate 2 are bonded by silicone.

[0087] Furthermore, if Figure 1As shown, the first section 43 is located between the top and bottom of the collector lead-out terminal 4, and the second section 53 is located between the top and bottom of the emitter lead-out terminal 5; the distance between the top of the collector lead-out terminal 4 and the top of the emitter lead-out terminal 5 is greater than the distance between the first section 43 and the second section 53; the insulating filling layer also includes a second insulating filling layer 826 connected to the frame cover body 82, and the second insulating filling layer 826 is located on the side of the first insulating filling layer 825 facing away from the base plate 1 and is connected to the first insulating filling layer 825; the area between the top of the collector lead-out terminal 4 and the top of the first section 43 is the third section 44, and the area between the top of the emitter lead-out terminal 5 and the top of the second section 53 is the fourth section 54; the second insulating filling layer 826 is located between the third section 44 and the fourth section 54. By limiting the distance between the top of the collector lead terminal and the top of the emitter lead terminal to be greater than the distance between the first section and the second section, and providing a second insulating filling layer between the third section and the fourth section, the insulation strength between the collector lead terminal and the emitter lead terminal is increased to prevent the two conductive terminals from discharging under the influence of the applied high voltage current, causing adverse effects on device performance or even device damage; at the same time, the provision of the second insulating filling layer reduces the effective area of ​​the loop formed by the collector lead terminal, the collector, the emitter and the emitter lead terminal, thereby reducing parasitic inductance.

[0088] Specifically, the second insulating filling layer is a first reinforcing rib structure, which is beneficial to enhancing the strength of the packaging structure and increasing the life of the packaging structure.

[0089] In an embodiment, Figure 1 As shown, the collector lead terminal 4 is provided with a first connecting piece 41 at the top away from the substrate 2; the emitter lead terminal 5 is provided with a second connecting piece 51 at the top away from the substrate 2, and the first connecting piece 41 and the second connecting piece 51 are used to connect with the test device during the chip reliability screening test to apply voltage to the high-voltage power semiconductor chip 3. Figure 2 As shown, the insulating frame 8 further includes: a filler 83 located in the collector opening 821 and the emitter opening 822, respectively, and the filler 83 is mounted on the frame body 81; the first connecting piece 41 and the second connecting piece 51 are located on the side of the filler 83 facing away from the substrate 2 and in contact with the upper surface of the filler 83. The structure of the filler 83 is as shown in FIG. Figure 5 The arrangement of the filling piece enables the collector lead-out terminal and the emitter lead-out terminal to be firmly fixed between the frame cover and the filling piece, thereby improving the stability of the collector lead-out terminal and the emitter lead-out terminal.

[0090] Specifically, Figure 4-Figure 5 As shown, the collector opening 821 and the emitter opening 822 extend to the side of the frame cover body 82 respectively. The frame cover body 82 is divided into a first part, a second part and an insulating filling layer, and the first part is connected to the second part through the insulating filling layer. The upper and lower edges of the first part and the second part are provided with grooves 829, and the upper and lower surfaces of the filler 83 protrude from the two opposite sides to form a protruding structure 832, and the protruding structure 832 is adapted to the groove 829, so that the filler 83 can be inserted into the collector opening 821 and the emitter opening 822 from the side of the frame cover body 82 along the groove 829. Fig.13 It is an exploded view of the insulating frame 8.

[0091] Furthermore, if Figure 1 As shown, the first connecting piece 41 has a first hole 42 that passes through the first connecting piece 41; the second connecting piece 51 has a second hole 52 that passes through the second connecting piece 51, and the first hole 42 and the second hole 52 are used to connect with the connecting screws in the test device during the chip reliability screening test; Figure 5 As shown, the filler 83 has a third hole 831 penetrating the filler 83, the third hole 831 of the filler 83 located below the first connection piece 41 is connected to the first hole 42, and the third hole 831 of the filler 83 located below the second connection piece 51 is connected to the second hole 52. The provision of the third hole improves the stability of the connection screws of the test end connected to the first hole and the second hole respectively, avoids the collector lead terminal and the emitter lead terminal from falling off from the substrate due to excessive force during connection, and ensures the normal conduct of the test.

[0092] Furthermore, the height of the collector lead terminal 4 is 38mm-40mm; the height of the emitter lead terminal 5 is 38mm-40mm. By limiting the height of the collector lead terminal and the emitter lead terminal, the effective area of ​​the loop formed by the collector lead terminal, the high-voltage power semiconductor chip and the emitter lead terminal can be controlled while ensuring the normal test of the package structure, thereby controlling the size of the parasitic inductance. The first section 43 occupies 5mm to 6mm of the height of the collector lead terminal 4; the second section 53 occupies 17mm to 18mm of the height of the collector lead terminal 4. By limiting the height of the collector lead terminal occupied by the first section and the height of the collector lead terminal occupied by the second section, the effective area of ​​the loop formed by the collector lead terminal, the high-voltage power semiconductor chip and the emitter lead terminal can be further controlled while ensuring the normal test of the package structure, thereby further controlling the size of the parasitic inductance.

[0093] In this embodiment, the packaging structure of the high-voltage power semiconductor chip further includes a packaging glue layer, and the packaging glue is located in the accommodating inner cavity formed by the bottom plate 1, the frame body 81 and the frame cover and covers the high-voltage power semiconductor chip. By arranging the packaging glue layer in the accommodating inner cavity formed by the bottom plate 1 and the insulating frame 8, not only the insulation strength of the packaging structure is improved, the discharge inside the chip is prevented from being caused by the applied high-voltage current, which may adversely affect the device performance or even damage the device, but also the stability of the packaging structure is improved.

[0094] The encapsulation adhesive layer includes a silicone gel layer and an epoxy adhesive layer located on the surface of the silicone gel layer facing away from the substrate, wherein the top surface of the silicone gel layer is flush with the top of the first section 43 or the second section 53. Specifically, the top surface of the silicone gel layer is flush with the bottom of the third section 44 or the fourth section 54, and the top surface of the epoxy adhesive layer is flush with the top surface of the third section 44 or the fourth section 54. The top surface of the silicone gel layer is flush with the top of the first section or the second section. Since the silicone gel layer is soft, the deformation degree is small when the temperature changes, which avoids the large deformation of the encapsulation adhesive layer due to the large temperature difference before and after the test, thereby avoiding damage to the encapsulation structure; the top surface of the epoxy adhesive layer is flush with the top surface of the third section or the fourth section. Since the epoxy adhesive is hard and can isolate water vapor, it not only plays a certain supporting role in the encapsulation structure and improves the strength of the encapsulation structure, but also avoids the damage of the semiconductor chip to the semiconductor chip by water vapor in the environment, thereby ensuring the performance and life of the high-voltage power semiconductor chip.

[0095] In this embodiment, if Figure 1 As shown, the substrate 2 may further include a gate conductive layer 23 and an auxiliary emitter conductive layer 24, the gate conductive layer 23 and the auxiliary emitter conductive layer 24 being metal layers on the surface of the ceramic substrate different from the gate conductive layer 23 and the auxiliary emitter conductive layer 24; Figure 2 As shown, the frame cover body 82 also includes a gate opening 823 and an auxiliary emitter opening 824, and the side of the high-voltage power semiconductor chip 3 where the emitter is set also includes a gate and an auxiliary electrode, the gate is electrically connected to the gate conductive layer 23 through a bonding wire 9, and the auxiliary electrode is electrically connected to the auxiliary electrode conductive layer through a bonding wire 9; Figure 1As shown, the packaging structure of the high-voltage power semiconductor chip also includes a gate lead-out terminal 6 and an auxiliary emitter lead-out terminal 75, wherein the gate lead-out terminal 6 is located on the gate conductive layer 23 and is electrically connected to the gate conductive layer 23, and the auxiliary emitter lead-out terminal 75 is located on the auxiliary emitter conductive layer 24 and is electrically connected to the auxiliary emitter conductive layer 24; specifically, the gate lead-out terminal 6 is welded to the gate conductive layer 23, and the auxiliary emitter lead-out terminal 75 is welded to the auxiliary emitter conductive layer 24. The gate lead-out terminal 6 extends from the gate opening 823 to the outside, and the auxiliary electrode lead-out terminal extends from the auxiliary electrode opening to the outside. The packaging structure of the high-voltage power semiconductor chip described above is suitable for various tests of high-voltage power semiconductor chips by setting the gate lead-out terminal and the auxiliary emitter lead-out terminal, and has greater flexibility.

[0096] On this basis, the frame cover also includes a third reinforcing rib structure 827, which is connected to the second insulating filling part and is located between the connecting line between the collector opening 821 and the emitter opening 822 and the connecting line between the gate opening 823 and the auxiliary electrode opening, so as to improve the insulation strength and avoid the discharge phenomenon caused by excessive voltage when at least one of the gate lead-out terminal and the auxiliary emitter lead-out terminal is tested by applying voltage simultaneously with at least one of the collector lead-out terminal and the emitter lead-out terminal; the frame cover also includes an isolation structure 828, which is connected to the side of the third reinforcing rib away from the frame cover body 82, so as to improve the insulation strength and further avoid the discharge phenomenon caused by excessive voltage when at least one of the gate lead-out terminal and the auxiliary emitter lead-out terminal is tested by applying voltage simultaneously with at least one of the collector lead-out terminal and the emitter lead-out terminal.

[0097] This embodiment also provides a packaging method for a high-voltage power semiconductor chip, see Figure 6 , including the following steps:

[0098] S1, providing a substrate 2, a high-voltage power semiconductor chip 3, a collector lead terminal 4 and an emitter lead terminal 5, wherein a separate emitter conductive layer 21 and a collector conductive layer 22 are provided on the surface of the substrate 2, and the high-voltage power semiconductor chip 3 has an emitter on a side opposite to the substrate 2;

[0099] S2, disposing the high-voltage power semiconductor chip 3 on part of the collector conductive layer 22, the high-voltage power semiconductor chip 3 is electrically connected to the collector conductive layer 22, and the emitter is electrically connected to the emitter conductive layer 21;

[0100] S3, disposing the collector lead terminal 4 on the collector conductive layer 22, the collector lead terminal 4 is electrically connected to the collector conductive layer 22, and the collector lead terminal 4 includes a first section 43;

[0101] S4, disposing an emitter lead-out terminal 5 on the emitter conductive layer 21, the emitter lead-out terminal 5 being electrically connected to the emitter conductive layer 21, the emitter lead-out terminal 5 comprising a second segment 53 disposed opposite to the first segment, the first segment 43 being recessed toward the emitter lead-out terminal 5, and / or the second segment 53 being recessed toward the collector lead-out terminal 4;

[0102] S5. Dispose a first insulating filling layer 825 between the first section 43 and the second section 53 .

[0103] The packaging method of the above-mentioned high-voltage power semiconductor chip is provided by arranging the high-voltage power semiconductor chip on the collector conductive layer of the substrate and electrically connecting it to the collector conductive layer, the emitter and the emitter conductive layer, and the collector lead terminal is arranged on the collector conductive layer and electrically connected to the collector conductive layer, and the emitter lead terminal is arranged on the emitter conductive layer and electrically connected to the emitter conductive layer, so that the collector lead terminal, the collector, the emitter and the emitter lead terminal are electrically connected, and the current applied to the collector lead terminal and the emitter lead terminal can form a loop to perform a single chip reliability screening test; at the same time, since the first section area of ​​the collector lead terminal is recessed toward the emitter lead terminal, and the second section area of ​​the emitter lead terminal arranged opposite to the first section area is recessed toward the collector lead terminal, the effective area enclosed by the above-mentioned loop is reduced, thereby reducing the parasitic inductance. At the same time, a first insulating filling layer is arranged between the first section and the second section to separate the collector lead terminal from the emitter lead terminal, thereby increasing the creepage distance and thus enhancing the insulation strength, so as to avoid the discharge of the above two conductive terminals under the influence of the applied high voltage current, causing adverse effects on device performance or even device damage. Therefore, the first insulating filling layer is arranged so that the first section is recessed toward the emitter lead terminal and the second section of the emitter lead terminal is recessed toward the collector lead terminal, which provides a basis for being suitable for high-voltage power semiconductor chip packaging.

[0104] The technical solution of the present invention is described clearly and completely below in conjunction with the accompanying drawings.

[0105] In step S1, a substrate 2, a high-voltage power semiconductor chip 3, a collector lead terminal 4 and an emitter lead terminal 5 are provided. The surface of the substrate 2 is provided with a discrete emitter conductive layer 21 and a collector conductive layer 22, and the high-voltage power semiconductor chip 3 has an emitter on the side opposite to the substrate 2.

[0106] Specifically, the high-voltage power semiconductor chip 3 includes an emitter and a collector, and the emitter and the collector are arranged on opposite surfaces of the high-voltage power semiconductor chip 3. The substrate 2 can be a ceramic substrate, and the emitter conductive layer 21 and the collector conductive layer 22 are metal layers on the surface of the ceramic substrate. The ceramic substrate can be a DBC (ceramic copper-clad substrate) or a DBA (ceramic aluminum-clad substrate), and the material of the metal layer can be copper or aluminum. The high-voltage power semiconductor chip 3 can be an insulated gate bipolar transistor (IGBT), a fast recovery diode (FRD), or a metal-oxide-semiconductor field-effect transistor (MOSFET) chip.

[0107] See also Figure 7 In step S2 , the high-voltage power semiconductor chip 3 is disposed on a portion of the collector conductive layer 22 , the high-voltage power semiconductor chip 3 is electrically connected to the collector conductive layer 22 , and the emitter is electrically connected to the emitter conductive layer 21 .

[0108] Specifically, the collector of the high-voltage power semiconductor chip 3 is connected to the collector conductive layer 22 through a nanomaterial sintering process, and the two oppositely disposed surfaces of the high-voltage power semiconductor chip 3 are plated using vacuum ion sputtering technology, and the coating composition is metal silver or copper to improve the sintering quality. The emitter is connected to the emitter conductive layer 21 through a bonding wire 9, and the bonding wire 9 includes but is not limited to aluminum wire, copper wire, and aluminum-clad copper wire.

[0109] Furthermore, the collector conductive layer 22 is arranged opposite to the emitter conductive layer 21, and the high-voltage power semiconductor chip 3 is located between the collector lead terminal 4 and the emitter lead terminal 5, so that the distance from the collector lead terminal and the emitter lead terminal to the high-voltage power semiconductor chip can be set to be smaller, thereby further reducing the effective area of ​​the loop formed by the collector lead terminal, the collector, the emitter and the emitter lead terminal, thereby further reducing the parasitic inductance.

[0110] After the collector of the high-voltage power semiconductor chip 3 is electrically connected to the collector conductive layer 22 and the emitter is electrically connected to the emitter conductive layer 21, the following steps are further included:

[0111] An insulating curing material is applied to the side of the high-voltage power semiconductor chip 3 away from the substrate 2 and above the bonding wire 9, and then cured in a high-temperature vacuum. The insulating curing material can enhance the strength of the bonding wire 9 and the bonding point, prevent the bonding wire 9 from being disconnected or the bonding point from falling off, and also prevent the local discharge phenomenon from damaging the high-voltage power semiconductor chip 3 during the test. The insulating curing material includes, but is not limited to, polyimide.

[0112] See also Figure 8 After the collector of the high-voltage power semiconductor chip 3 is electrically connected to the collector conductive layer 22 and the emitter is electrically connected to the emitter conductive layer 21 , the following steps are also included: providing a base plate 1 and fixing the substrate 2 on the base plate 1 .

[0113] Specifically, the substrate 2 is welded to the bottom plate 1 by welding material, and the welding material is a high-temperature welding sheet with a melting point greater than 250°C, and the material of the high-temperature welding sheet includes but is not limited to PbSnAg. The bottom plate 1 can be a heat sink to dissipate the heat generated during the test to prevent heat accumulation from adversely affecting the performance of the high-voltage power semiconductor chip 3; the heat sink includes but is not limited to AlSiC ceramic plate, copper, aluminum metal plate, tungsten copper alloy plate;

[0114] It should be understood that the order of the steps of coating the insulating curing material and curing it at high temperature and the step of fixing and connecting the substrate to the bottom plate is not limited here.

[0115] See also Fig. 9 In step S3, the collector lead terminal 4 is disposed on the collector conductive layer 22, the collector lead terminal 4 is electrically connected to the collector conductive layer 22, and the collector lead terminal 4 includes a first section 43. Specifically, the collector lead terminal 4 is welded to the collector conductive layer 22.

[0116] In step S4, the emitter lead-out terminal 5 is arranged on the emitter conductive layer 21, the emitter lead-out terminal 5 is electrically connected to the emitter conductive layer 21, the emitter lead-out terminal 5 includes a second section 53 arranged opposite to the first section, the first section 43 is recessed toward the emitter lead-out terminal 5, and / or the second section 53 is recessed toward the collector lead-out terminal 4; specifically, the emitter lead-out terminal 5 is welded to the emitter conductive layer 21.

[0117] See also Fig.10After the collector lead terminal is disposed on the collector conductive layer, and after the emitter lead terminal is disposed on the emitter conductive layer, the following steps are also included:

[0118] An insulating frame 8 is provided, the insulating frame comprising: a frame body 81 of a hollow structure and a frame cover, the frame cover having a collector opening 821 and an emitter opening 822 penetrating the frame cover, the frame cover comprising the frame cover body 82 and the insulating filling layer connected to the frame cover body 82, the insulating filling layer being located between the collector opening 821 and the emitter opening 822, and the insulating filling layer comprising a first insulating filling layer 825. The structure of the frame is as follows Figure 3 As shown, the structure of the frame cover is as follows Figure 4 As shown; the frame body 81 is fixedly connected to the bottom plate 1 around the substrate 2.

[0119] Specifically, the frame body 81 is bonded to the substrate 2 by silicone. The material of the insulating frame is polybutylene terephthalate (PBT), polyphthalamide (PPA) or polyphenylene sulfide (PPS).

[0120] After the frame body 81 is fixedly connected to the bottom plate 1 around the substrate 2, a step of forming a silicone gel layer in the frame body 81 is also included, wherein the top surface of the silicone gel layer is flush with the top of the first section or the second section, and is flush with the bottom of the third section 44 or the fourth section 54. The silicone gel layer is formed by vacuum-injecting silicone gel into the collector opening 821 or the emitter opening 822 in steps and curing.

[0121] See also Fig.11 In step S5 , a first insulating filling layer 825 is disposed between the first section 43 and the second section 53 .

[0122] Specifically, the frame cover is overlapped on the edge of the frame body 81, the collector lead terminal 4 extends to the outside from the collector opening 821, and the emitter lead terminal 5 extends to the outside from the emitter opening 822. In the process of overlapping the frame cover on the edge of the frame body, the first insulating filling layer 825 is arranged between the first section area 43 and the second section area 53.

[0123] After the frame cover is overlapped on the edge of the frame body 81, the step of forming an epoxy glue layer on the silicone gel layer is also included, and the top surface of the epoxy glue layer is flush with the top surface of the third section 44 or the fourth section 54. The epoxy glue layer is formed by injecting epoxy glue into the collector opening 821 or the emitter opening 822.

[0124] It is important to understand that Figure 1 As shown, the first section 43 is located between the top and bottom of the collector lead-out terminal 4, and the second section 53 is located between the top and bottom of the emitter lead-out terminal 5; the area between the top of the collector lead-out terminal 4 and the top of the first section 43 is the third section 44, and the area between the top of the emitter lead-out terminal 5 and the top of the second section 53 is the fourth section 54; the distance between the top of the collector lead-out terminal 4 and the top of the emitter lead-out terminal 5 is greater than the distance between the first section 43 and the second section 53; the insulating filling layer also includes a second insulating filling layer 826, and the frame body 81, the second insulating filling layer 826 and the first insulating filling layer 825 are connected in sequence; in the process of overlapping the frame cover on the edge of the frame body 81, the second insulating filling layer 826 is filled between the third section 44 and the fourth section 54. By limiting the distance between the top of the collector lead terminal and the top of the emitter lead terminal to be greater than the distance between the first section and the second section, and providing a second insulating filling layer between the third section and the fourth section, the insulation strength between the collector lead terminal and the emitter lead terminal is increased to prevent the two conductive terminals from discharging under the influence of the applied high voltage, causing adverse effects on device performance or even device damage; at the same time, the provision of the second insulating filling layer reduces the effective area of ​​the loop formed by the collector lead terminal, collector, emitter and emitter lead terminal, thereby reducing parasitic inductance. Specifically, the second insulating filling layer is a reinforcing rib structure. The reinforcing rib structure is conducive to enhancing the strength of the packaging structure and increasing the life of the packaging structure.

[0125] The collector lead terminal 4 is provided with a first connecting piece 41 at the top away from the substrate 2; the emitter lead terminal 5 is provided with a second connecting piece 51 at the top away from the substrate 2; the insulating frame 8 also includes a filling member 83, the structure of the filling member 83 is as follows Figure 5 As shown;

[0126] See also Fig.12 After the frame cover is overlapped on the upper edge of the frame body 81, the step of respectively setting the filler 83 at the collector opening 821 and the emitter opening 822 is also included, and the first connecting piece 41 and the second connecting piece 51 are located on the side of the filler 83 facing away from the substrate 2 and in contact with the upper surface of the filler 83. The setting of the filler 83 allows the collector lead terminal 4 and the emitter lead terminal 5 to be firmly fixed between the frame cover and the filler 83, thereby improving the stability of the collector lead terminal 4 and the emitter lead terminal 5.

[0127] Specifically, Figure 4As shown, the collector opening 821 and the emitter opening 822 extend to the side of the frame cover body 82 respectively. The frame cover body 82 is divided into a first part, a second part and an insulating filling layer, and the first part is connected to the second part through the insulating filling layer. The upper and lower edges of the first part and the second part are provided with grooves 829, and the upper and lower surfaces of the filler 83 protrude from the two opposite sides to form a protruding structure 832, and the protruding structure 832 is adapted to the groove 829, so that the filler 83 can be inserted into the collector opening 821 and the emitter opening 822 from the side of the frame cover body 82 along the groove 829.

[0128] The first connecting piece 41 has a first hole 42 that passes through the first connecting piece 41; the second connecting piece 51 has a second hole 52 that passes through the second connecting piece 51, and the first hole 42 and the second hole 52 are used to connect with the connecting screws in the test device during the chip reliability screening test; the filling piece 83 has a third hole 831 that passes through the filling piece 83, and in the process of setting the filling piece 83 at the collector opening 821 and the emitter opening 822, the third hole 831 of the filling piece 83 located below the first connecting piece 41 needs to be connected with the first hole 42, and the third hole 831 of the filling piece 83 located below the second connecting piece 51 needs to be connected with the second hole 52. The setting of the third hole 831 improves the stability of the connection of the connecting screws of the test end with the first hole 42 and the second hole 52, respectively, and avoids the collector lead terminal 4 and the emitter lead terminal 5 from falling off from the substrate 2 due to excessive force during connection, thereby ensuring the normal progress of the test.

[0129] It should be understood that the substrate 2 may also include a gate conductive layer 23 and an auxiliary emitter conductive layer 24, which are metal layers on the surface of the ceramic substrate that are different from the gate conductive layer 23 and the auxiliary emitter conductive layer 24, and the side of the high-voltage power semiconductor chip 3 on which the emitter is set also includes a gate and an auxiliary electrode, and the frame cover body 82 also includes a gate opening 823 and an auxiliary emitter opening 824, and the packaging structure of the high-voltage power semiconductor chip also includes a gate lead terminal 6 and an auxiliary emitter lead terminal 75.

[0130] Therefore, step S2 also includes the following steps: the gate is electrically connected to the gate conductive layer 23 via a bonding wire 9, and the auxiliary electrode is electrically connected to the auxiliary electrode conductive layer via a bonding wire 9;

[0131] In step S3 or step S4, the following steps are also included: the gate lead-out terminal 6 is located on the gate conductive layer 23 and is electrically connected to the gate conductive layer 23, the auxiliary emitter lead-out terminal 75 is located on the auxiliary emitter conductive layer 24 and is electrically connected to the auxiliary emitter conductive layer 24. Specifically, the gate lead-out terminal 6 is welded to the gate conductive layer 23, and the auxiliary emitter lead-out terminal 75 is welded to the auxiliary emitter conductive layer 24.

[0132] In step S5 , in the process of overlapping the frame cover on the edge of the frame body, the gate lead terminal 6 extends outward from the gate opening 823 , and the auxiliary electrode lead terminal extends outward from the auxiliary electrode opening.

[0133] On this basis, the frame cover further includes a third reinforcing rib structure 827 and an isolation structure 828, wherein the third reinforcing rib structure 827 is connected to the second insulating filling portion, and the isolation structure 828 is connected to the side of the third reinforcing rib away from the frame cover body 82. In step S5, in the process of overlapping the frame cover on the edge of the frame body, the isolation structure 828 is arranged between the area formed by the collector lead terminal 4 and the emitter lead terminal 5 and the area formed by the gate lead terminal 6 and the auxiliary emitter lead terminal 75. The isolation structure can be an insulating plate material, and its material is the same as that of the insulating frame body.

[0134] In the packaging process of high-voltage power semiconductor chips, the above-mentioned packaging method can be used as follows: first connect the substrate and the bottom plate together, then set the collector lead terminal on the collector conductive layer, and set the emitter lead terminal on the emitter conductive layer; or first set the collector lead terminal on the collector conductive layer, set the emitter lead terminal on the emitter conductive layer, and then connect the substrate and the bottom plate together.

[0135] It should be understood that the effective loop area described in the present application refers to the area that affects the increase or decrease of parasitic inductance, specifically refers to the area with weak insulation strength in the loop surrounded by the collector lead terminal, the collector, the emitter and the emitter lead terminal. Specifically, the size of the effective loop area is the loop area surrounded by the collector lead terminal, the collector, the emitter and the emitter lead terminal minus the cross-sectional area of ​​the first insulating filling layer on the surface, or the size of the effective loop area is the loop area surrounded by the collector lead terminal, the collector, the emitter and the emitter lead terminal minus the cross-sectional area of ​​the first insulating filling layer and the second insulating filling layer on the surface.

[0136] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. A packaging structure of a high-voltage power semiconductor chip, characterized in that: include: A substrate, wherein a separate emitter conductive layer and a collector conductive layer are disposed on the surface of the substrate; a high-voltage power semiconductor chip located on part of the collector conductive layer and electrically connected to the collector conductive layer, wherein the high-voltage power semiconductor chip has an emitter on a side opposite to the substrate, and the emitter is electrically connected to the emitter conductive layer; the collector conductive layer and the emitter conductive layer are arranged opposite to each other, and the high-voltage power semiconductor chip is located between the collector lead terminal and the emitter lead terminal; A collector lead-out terminal, the collector lead-out terminal is located on the collector conductive layer and is electrically connected to the collector conductive layer; An emitter lead-out terminal, the emitter lead-out terminal is located on the emitter conductive layer and is electrically connected to the emitter conductive layer; The collector lead terminal includes a first segment, the emitter lead terminal includes a second segment arranged opposite to the first segment, the first segment is recessed toward the emitter lead terminal, and / or the second segment is recessed toward the collector lead terminal; A first insulating filling layer, the first insulating filling layer is located between the first section and the second section; The packaging structure of the high-voltage power semiconductor chip also includes: Bottom plate; the substrate is located on a portion of the bottom plate; Insulating frame; the insulating frame comprises: a frame body with a hollow structure, the frame body is located on the bottom plate around the substrate; a frame cover mounted on the frame body, the frame cover having a collector opening and an emitter opening penetrating the frame cover; The collector lead terminal is located in the frame body and extends outside the collector opening, the emitter lead terminal is located in the frame body and extends outside the emitter opening, and the first section area and the second section area are located inside the frame body; The frame cover includes a frame cover body and an insulating filling layer connected to the frame cover body, the insulating filling layer is located between the collector opening and the emitter opening, and the insulating filling layer includes a first insulating filling layer extending toward the bottom plate relative to the frame cover body.

2. The packaging structure of the high-voltage power semiconductor chip according to claim 1, characterized in that: The first section is located between the top and bottom of the collector lead terminal, and the second section is located between the top and bottom of the emitter lead terminal; the distance between the top of the collector lead terminal and the top of the emitter lead terminal is greater than the distance between the first section and the second section; The insulating filling layer further comprises a second insulating filling layer connected to the frame cover body, the second insulating filling layer is located on a side of the first insulating filling layer facing away from the bottom plate and connected to the first insulating filling layer; The area between the top of the collector lead terminal and the top of the first section is the third section, and the area between the top of the emitter lead terminal and the top of the second section is the fourth section; The second insulating filling layer is located between the third section area and the fourth section area.

3. The packaging structure of the high-voltage power semiconductor chip according to claim 2, characterized in that: The second insulating filling layer is a reinforcing rib structure.

4. The packaging structure of a high-voltage power semiconductor chip according to claim 1, characterized in that: A first connecting piece is provided at the top of the collector lead terminal away from the substrate; a second connecting piece is provided at the top of the emitter lead terminal away from the substrate; The insulating frame also includes: fillers respectively located in the collector opening and the emitter opening, and the fillers are mounted on the frame body; the first connecting piece and the second connecting piece are located on a side of the filler facing away from the substrate and in contact with an upper surface of the filler.

5. The packaging structure of the high-voltage power semiconductor chip according to claim 4, characterized in that: The first connecting sheet has a first hole penetrating through the first connecting sheet; The second connecting sheet has a second hole penetrating through the second connecting sheet; The filling piece has a third hole therein and passes through the filling piece. The third hole of the filling piece below the first connecting piece is connected to the first hole, and the third hole of the filling piece below the second connecting piece is connected to the second hole.

6. The packaging structure of a high-voltage power semiconductor chip according to claim 1, characterized in that: The height of the collector lead terminal is 38mm-40mm; the height of the emitter lead terminal is 38mm-40mm.

7. The packaging structure of a high-voltage power semiconductor chip according to claim 1 or 6, characterized in that: The first section area occupies 5 mm to 6 mm of the height of the collector lead terminal; the second section area occupies 17 mm to 18 mm of the height of the emitter lead terminal.

8. The packaging structure of a high-voltage power semiconductor chip according to claim 1, characterized in that: It also includes a packaging glue layer, which is located in the accommodating cavity formed by the bottom plate, the frame body and the frame cover and covers the high-voltage power semiconductor chip.

9. The packaging structure of the high-voltage power semiconductor chip according to claim 8, characterized in that: The packaging adhesive layer includes a silicone gel layer and an epoxy adhesive layer located on a surface of the silicone gel layer facing away from the substrate, wherein the top surface of the silicone gel layer is flush with the top of the first section or the second section.

10. A packaging method for a high-voltage power semiconductor chip, used for preparing the packaging structure of the high-voltage power semiconductor chip according to any one of claims 1 to 9, characterized in that: The following steps are involved: Providing a substrate, a high-voltage power semiconductor chip, a collector lead terminal and an emitter lead terminal, wherein a separate emitter conductive layer and a collector conductive layer are arranged on the surface of the substrate, and the high-voltage power semiconductor chip has an emitter on a side opposite to the substrate; The high-voltage power semiconductor chip is arranged on a portion of the collector conductive layer, the high-voltage power semiconductor chip is electrically connected to the collector conductive layer, and the emitter is electrically connected to the emitter conductive layer; The collector lead-out terminal is arranged on the collector conductive layer, the collector lead-out terminal is electrically connected to the collector conductive layer, and the collector lead-out terminal includes a first section; An emitter lead-out terminal is arranged on the emitter conductive layer, the emitter lead-out terminal is electrically connected to the emitter conductive layer, the emitter lead-out terminal comprises a second segment area arranged opposite to the first segment area, the first segment area is recessed toward the emitter lead-out terminal, and / or the second segment area is recessed toward the collector lead-out terminal; Disposing a first insulating filling layer between the first section and the second section; The packaging method of the high-voltage power semiconductor chip further includes: A bottom plate and an insulating frame are provided, wherein the insulating frame comprises: a frame body with a hollow structure and a frame cover, wherein the frame cover has a collector opening and an emitter opening penetrating the frame cover, wherein the frame cover comprises the frame cover body and the insulating filling layer connected to the frame cover body, wherein the insulating filling layer is located between the collector opening and the emitter opening, and wherein the insulating filling layer comprises a first insulating filling layer; Before the collector lead terminal is disposed on the collector conductive layer, and before the emitter lead terminal is disposed on the emitter conductive layer, the substrate is fixedly connected to a portion of the bottom plate; After the collector lead terminal is disposed on the collector conductive layer, and after the emitter lead terminal is disposed on the emitter conductive layer, the frame body is fixedly connected to the bottom plate around the substrate; The frame cover is overlapped on the edge of the frame body, the collector lead terminal extends outward from the collector opening, and the emitter lead terminal extends outward from the emitter opening. In the process of overlapping the frame cover on the edge of the frame body, a first insulating filling layer is arranged between the first section area and the second section area.

11. The packaging method of a high-voltage power semiconductor chip according to claim 10, characterized in that: The first section is located between the top and bottom of the collector lead terminal, the second section is located between the top and bottom of the emitter lead terminal, the area between the top of the collector lead terminal and the top of the first section is the third section, and the area between the top of the emitter lead terminal and the top of the second section is the fourth section; the distance between the top of the collector lead terminal and the top of the emitter lead terminal is greater than the distance between the first section and the second section; The insulating filling layer also includes a second insulating filling layer, and the frame body, the second insulating filling layer and the first insulating filling layer are connected in sequence; in the process of overlapping the frame cover on the edge of the frame body, the second insulating filling layer is filled between the third section and the fourth section.

12. The packaging method of a high-voltage power semiconductor chip according to claim 10 or 11, characterized in that: A first connecting piece is provided at the top of the collector lead terminal away from the substrate; a second connecting piece is provided at the top of the emitter lead terminal away from the substrate; and the insulating frame further includes a filling piece; After overlapping the frame cover on the upper edge of the frame body, the method further includes: arranging the filling piece at the collector opening and the emitter opening respectively, and the first connecting piece and the second connecting piece are located on the side of the filling piece facing away from the substrate and in contact with the upper surface of the filling piece.

13. The packaging method of a high-voltage power semiconductor chip according to claim 10, characterized in that: After the frame body is fixedly connected to the bottom plate around the substrate, the method further includes: forming a silicone gel layer into the frame body, wherein the top surface of the silicone gel layer is flush with the top of the first section or the second section; After the frame cover is overlapped on the edge of the frame body, the method further includes a step of forming an epoxy glue layer on the silicone gel layer.

Images