Output drive circuit with electrostatic protection function

Abstract

An output drive circuit comprises: an output drive module, comprising a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube, and an output end; the source of the first PMOS tube is connected to a power line VDD, and the drain is connected to the drain of the first NMOS tube; the source of the second PMOS tube is connected to the power line VDD, and the drain is connected to the drain of the second NMOS tube; the source of the first NMOS tube and the source of the second NMOS tube are both connected to a ground line VSS; the output end is connected to the drains of the first PMOS tube and the first NMOS tube, and is also connected to the drains of the second PMOS tube and the second NMOS tube; a first potential control module and a second potential control module, the first potential control module is connected to the gate of the first PMOS tube and the gate of the second PMOS tube, and is used to make the gate of the first PMOS tube and the gate of the second PMOS tube have the same potential in an ESD state; the second potential control module is connected to the gate of the first NMOS tube and the gate of the second NMOS tube, and is used to make the gate of the first NMOS tube and the gate of the second NMOS tube have the same potential in an ESD state.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to an output drive circuit with an electrostatic protection circuit. Background Art

[0002] Semiconductor integrated circuits must have electrostatic discharge (ESD) protection circuits to ensure the reliability of the integrated circuits. In order to save chip area, the NMOS and PMOS in the output drive circuit of the semiconductor integrated circuit have dual functions. On the one hand, they are used as the output drive level of the circuit, and on the other hand, they can also be used as ESD protection circuits when ESD occurs.

[0003] In the prior art, the output drive circuit using gate coupling technology is subjected to electrostatic discharge test. Although the electrostatic voltage on the output end will couple some voltage to the gate of the NMOS tube through the parasitic capacitance between the gate and the drain, so as to cause the NMOS transistor to conduct to discharge the ESD current, the existing circuit structure will cause the problem of uneven conduction between different NMOSs, thereby affecting the ESD tolerance of the output drive stage.

[0004] Therefore, it is necessary to further improve the electrostatic protection capability of the overall output drive circuit. Summary of the invention

[0005] The technical problem to be solved by the present invention is to improve the ESD tolerance of the output drive circuit.

[0006] In order to solve the above problems, the technical solution of the present invention provides an output drive circuit with an electrostatic protection function, including: an output drive module, including a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube, and an output end; the source of the first PMOS tube is connected to the power line VDD, and the drain is connected to the drain of the first NMOS tube; the source of the second PMOS tube is connected to the power line VDD, and the drain is connected to the drain of the second NMOS tube; the source of the first NMOS tube and the source of the second NMOS tube are both connected to the ground line VSS; the output end is connected to the first PMOS tube and the first NMOS tube. The drain of the OS tube is also connected to the drain of the second PMOS tube and the second NMOS tube; a first potential control module and a second potential control module, the first potential control module is connected to the gate of the first PMOS tube and the gate of the second PMOS tube, and is used to make the gate of the first PMOS tube and the gate of the second PMOS tube have the same potential in the ESD state; the second potential control module is connected to the gate of the first NMOS tube and the gate of the second NMOS tube, and is used to make the gate of the first NMOS tube and the gate of the second NMOS tube have the same potential in the ESD state.

[0007] Optionally, the first potential control module includes a first control voltage terminal and a third control PMOS tube; the gate of the third control PMOS tube is connected to the first control voltage terminal, the source is connected to the power line VDD, and the drain is connected to the gate of the second PMOS transistor.

[0008] Optionally, the first potential control module includes: a first control NMOS tube, a second control NMOS tube and a first control voltage terminal; the drain of the first control NMOS tube is connected to the gate of the first PMOS tube, the source is connected to the ground line VSS, and the gate is connected to the first control voltage terminal; the drain of the second control NMOS tube is connected to the gate of the second PMOS tube, the source is connected to the ground line VSS, and the gate is connected to the first control voltage terminal.

[0009] Optionally, when a negative ESD voltage is applied to the output end, the voltage at the first control voltage terminal controls the first control NMOS tube and the second control NMOS tube to be turned on, and the third control PMOS tube to be turned off; when the voltage at the first control voltage terminal is in normal working state, the voltage at the first control voltage terminal controls the first control NMOS tube and the second control NMOS tube to be turned off, and the third control PMOS tube to be turned on.

[0010] Optionally, the first potential control module also includes a first control voltage output unit, which includes a first capacitor and a first voltage divider device, one end of the first capacitor is connected to the power line VDD, the first voltage divider device is connected between the other end of the first capacitor and the ground line VSS, and the connection end between the first voltage divider device and the first capacitor serves as the first control voltage end.

[0011] Optionally, the first voltage-dividing device is a first resistor or a first voltage-dividing NMOS tube, the gate of the first voltage-dividing NMOS tube is connected to the power line VDD, the drain is connected to the first capacitor, and the source is connected to the ground line VSS.

[0012] Optionally, the second potential control module includes a second control voltage terminal and a third control NMOS tube; the gate of the third control NMOS tube is connected to the second control voltage terminal, the drain is connected to the gate of the second NMOS tube, and the source is connected to the ground line VSS.

[0013] Optionally, the second potential control module also includes: a first control PMOS tube, a second control PMOS tube and a second control voltage terminal; the drain of the first control PMOS tube is connected to the gate of the first NMOS tube, the source is connected to the power line VDD, and the gate is connected to the second control voltage terminal; the drain of the second control PMOS tube is connected to the gate of the second NMOS tube, the source is connected to the power line VDD, and the gate is connected to the second control voltage terminal.

[0014] Optionally, when a positive ESD voltage is applied to the output end, the voltage at the second control voltage terminal controls the first control PMOS tube and the second control PMOS tube to be turned on, and the third control NMOS transistor to be turned off; when the voltage at the second control voltage terminal is in normal working state, the voltage at the first control PMOS tube and the second control PMOS tube to be turned off, and the third control NMOS tube to be turned on.

[0015] Optionally, the second potential control module also includes a second control voltage output unit, which includes a second capacitor and a second voltage divider device, one end of the second capacitor is connected to the ground line VSS, the second voltage divider device is connected between the other end of the second capacitor and the power line VDD, and the connection end between the second voltage divider device and the second capacitor serves as the second control voltage end.

[0016] Optionally, the second voltage-dividing device is a second resistor or a second voltage-dividing PMOS tube, the gate of the second voltage-dividing PMOS tube is connected to the ground line VSS, the source is connected to the power line VDD, and the drain is connected to the second capacitor.

[0017] Optionally, the gate of the first PMOS tube is connected to the first output end of the pre-driving circuit; the gate of the first NMOS tube is connected to the second output end of the pre-driving circuit.

[0018] In the ESD state, each transistor in the output drive unit of the output drive circuit of the present invention can be evenly turned on to evenly discharge the ESD current, thereby improving the ESD tolerance of the output drive circuit, thereby effectively improving the electrostatic discharge (ESD) protection capability of the overall output drive stage. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a structural schematic diagram of an output drive circuit according to a specific embodiment of the present invention;

[0020] Figure 2 This is a schematic diagram of the connection structure of a first voltage-dividing NMOS tube according to a specific embodiment of the present invention;

[0021] Figure 3 A schematic diagram of the connection structure of a second voltage-dividing PMOS tube according to a specific embodiment of the present invention;

[0022] Figure 4 It is a schematic structural diagram of an output drive circuit according to a specific embodiment of the present invention. DETAILED DESCRIPTION

[0023] The specific implementation of the output drive circuit with electrostatic protection function provided by the present invention is described in detail below with reference to the accompanying drawings.

[0024] Please refer to Figure 1 , is a schematic diagram of the structure of an output drive circuit according to a specific embodiment of the present invention.

[0025] The output driving circuit includes an output driving module, and the output driving module includes a first PMOS transistor Mp1, a second PMOS transistor Mp2, a first NMOS transistor Mn1, a second NMOS transistor Mn2, and an output terminal 101.

[0026] The source of the first PMOS transistor Mp1 is connected to the power line VDD, and the drain is connected to the drain of the first NMOS transistor Mn1.

[0027] The source of the second PMOS transistor Mp2 is connected to the power line VDD, and the drain is connected to the drain of the second NMOS transistor Mn2.

[0028] The source of the first NMOS transistor Mn1 and the source of the second NMOS transistor Mn2 are both connected to the ground line VSS.

[0029] The output end 101 is connected between the drains of the first PMOS transistor Mp1 and the first NMOS transistor Mn1, and is also connected between the drains of the second PMOS transistor Mp2 and the second NMOS transistor Mn2.

[0030] The output driving circuit further includes a first potential control module 110 and a second potential control module 120 .

[0031] The first potential control module 110 is connected to the gate of the first PMOS tube Mp1 and the gate of the second PMOS tube Mp2, and is used to make the gate of the first PMOS tube Mp1, the gate of the second PMOS tube Mp2 and the gate of the first control PMOS tube Mp3 have the same potential in the ESD state, so that the first PMOS tube and the second PMOS tube of the output driving unit can be evenly turned on to discharge the ESD current in the ESD state. The ESD state is when the output terminal 101 is applied with an ESD voltage.

[0032] The second potential control module 120 is connected to the gate of the first NMOS tube Mn1 and the gate of the second NMOS tube Mn2, and is used to make the gate of the first NMOS tube Mn1 and the gate of the second NMOS tube Mn2 have the same potential in the ESD state, so that the first NMOS tube Mn1 and the second PMOS tube Mn2 of the output driving unit can be evenly turned on to discharge the ESD current in the ESD state.

[0033] The gate 4 of the first PMOS transistor Mp1 is connected to the first output terminal of the pre-driving circuit; the gate 1 of the first NMOS transistor Mn1 is connected to the second output terminal of the pre-driving circuit. In this specific implementation, the first output terminal of the pre-driving circuit is connected to the gate 4 through the first inverter Inv1, and the second output terminal of the pre-driving circuit is connected to the gate 1 through the second inverter Inv2.

[0034] When the output drive circuit is in the ESD state, each transistor in the output drive unit can be evenly turned on to evenly discharge the ESD current, thereby improving the ESD tolerance of the output drive circuit, thereby effectively improving the electrostatic discharge (ESD) protection capability of the overall output drive stage.

[0035] exist Figure 1 In the specific implementation shown, the first potential control module 110 includes: a first control NMOS tube Mdn1, a second control NMOS tube Mdn2, a third control PMOS tube Mdp3 and a first control voltage terminal Q1; the drain of the first control NMOS tube Mdn1 is connected to the gate of the first PMOS tube Mp1, the source is connected to the ground line VSS, and the gate is connected to the first control voltage terminal Q1; the drain of the second control NMOS tube Mdn2 is connected to the gate of the second PMOS tube Mp2, the source is connected to the ground line VSS, and the gate is connected to the first control voltage terminal Q1; the gate of the third control PMOS tube Mdp3 is connected to the first control voltage terminal Q1, the source is connected to the power line VDD, and the drain is connected to the gate of the second PMOS transistor Mp2.

[0036] The second potential control module 120 includes: a first control PMOS tube Mdp1, a second control PMOS tube Mdp2, a third control NMOS tube Mdn3 and a second control voltage terminal Q2; the drain of the first control PMOS tube Mdp1 is connected to the gate of the first NMOS tube Mn1, the source is connected to the power line VDD, and the gate is connected to the second control voltage terminal Q2; the drain of the second control PMOS tube Mdp2 is connected to the gate of the second NMOS tube, the source is connected to the power line VDD, and the gate is connected to the second control voltage terminal Q2; the gate of the third control NMOS tube Mdn3 is connected to the second control voltage terminal Q2, the drain is connected to the gate of the second NMOS tube Mn2, and the source is connected to the ground line VSS.

[0037] When a positive ESD voltage is applied to the output terminal 101, the power line VDD can be charged through the parasitic diodes Dp1 and Dp2, causing the voltage of the power line VDD to increase. At this time, the voltage of the second control voltage terminal Q2 is controlled to be low, and the positive ESD voltage on the output terminal 101 is coupled to the gate 2 of Mn2 through the parasitic capacitance of Mn2, so that the voltage at the gate 2 is high, thereby causing the Mdn3 to be disconnected. At this time, since Q2 is connected to the gates of Mdp1 and Mdp2 and is low voltage, Mdp1 and Mdp2 are turned on; the gate 2 of Mn2 is connected to VDD through the turned-on Mdp2, and the gate 1 of Mn1 is connected to VDD through the turned-on Mdp1, so that both Mn2 and Mn1 are turned on, and since the gate 1 and gate 2 are both connected to VDD and have the same potential, Mn2 and Mn1 have the same conduction state. The positive ESD voltage at the output terminal 101 is uniformly discharged to VDD through Mn1 and Mn2 , thereby improving the ESD tolerance of the circuit.

[0038] When a positive ESD voltage is applied to the output terminal 101, the gates 4 and 3 of Mp1 and Mp2 are coupled with a high voltage through the parasitic capacitance of Mp1 and Mp2, and Mp1 and Mp2 are turned off, and the ESD voltage is not discharged.

[0039] The output terminal 101 is in a normal working state without ESD voltage, and controls the voltage of the second control voltage terminal Q2 to be in a high voltage state, so that the first control PMOS tube Mdp1 and the second control PMOS tube Mdp2 are turned off, and the third control NMOS tube Mdn3 is turned on, so that the gate voltages of the first NMOS tube Mn1 and the second NMOS tube Mn2 are not affected by the first control PMOS tube Mdp1 and the second control PMOS tube Mdp2. Specifically, the gate 1 of Mn1 is floating, and the gate 2 of Mn2 is connected to VSS.

[0040] When a negative ESD voltage is applied to the output terminal 101, the voltage of the power line VDD can be reduced through the parasitic diodes Dp1 and Dp2. The first control voltage terminal Q1 is controlled to be a high voltage, and the negative ESD voltage on the output terminal 101 is coupled to the gate 3 of Mp2 through the parasitic capacitance of Mp2, so that the voltage at the gate 3 is low, so that the Mdp3 is disconnected. At this time, since Q1 is connected to the gates of Mdn1 and Mdn2 and is a high voltage, it can control Mdp1, Mdn1 and Mdn2 to be turned on. The gate 4 of Mp1 is connected to VSS through Mdn, and the gate 3 of Mp2 is connected to VSS through Mdn2, so that Mp1 and Mp2 are both turned on, and the negative ESD voltage of the output terminal 101 is discharged to VSS by Mp1 and Mp2. Furthermore, since the gate 4 and the gate 3 are both connected to VSS and have the same potential, Mp1 and Mp2 have the same conduction state, and therefore have a uniform discharge capability for the ESD voltage, thereby improving the ESD tolerance capability.

[0041] When a negative ESD voltage is applied to the output terminal 101, the gates 1 and 2 of Mn1 and Mn2 are coupled with a negative voltage through the parasitic capacitance of Mn1 and Mn2, and Mn1 and Mn2 are turned off, and the ESD voltage is not discharged.

[0042] The voltage of the first control voltage terminal Q1 is a low voltage under normal working conditions, and the first control NMOS tube Mdn1 and the second control NMOS tube Mdn2 are controlled to be turned off, and the third control PMOS tube Mdp3 is turned on, so that the gate voltages of the first PMOS tube Mp1 and the second PMOS tube Mp2 are not affected by the first control NMOS tube Mdn1 and the second control NMOS tube Mdn2. Specifically, the gate 4 of Mp1 is floating, and the gate 3 of Mp2 is connected to VDD.

[0043] In this specific implementation, the first potential control module 110 also includes a first control voltage output unit, which includes a first capacitor C1 and a first resistor R1, one end of the first capacitor C1 is connected to the power line VDD, the first resistor R1 is connected between the other end of the first capacitor C1 and the ground line VSS, and the connection end between the first resistor R1 and the first capacitor C1 serves as a first control voltage end Q1.

[0044] When a negative ESD state is applied to the output terminal 101, the Q1 is grounded through the first resistor R1, and the negative ESD voltage drops the voltage of the power line VDD through the parasitic diodes Dp1 and Dp2. Since the first capacitor C1 is connected between VDD and the Q1, due to the capacitive reactance effect, Q1 still maintains a high voltage for a period of time, thereby controlling the Mp2 and Mp1 to be turned on and discharging the negative ESD voltage.

[0045] In other specific implementations, the first control voltage output unit may also adopt other circuit forms to achieve voltage control of the first control voltage terminal Q1.

[0046] Under normal working conditions, the gate of Mdp3 is grounded to VSS through R1, Mdp3 is turned on, and the gate 3 of Mp2 is connected to VDD, so that Mp2 is turned off. At this time, the gates of Mdn1 and Mdn2 are both grounded through R1 and are in the off state. The gate 4 of the first PMOS tube Mp1 is in a floating state, which does not affect the normal circuit operation.

[0047] The first resistor R1 may also be replaced by other voltage-dividing devices. For example, the first resistor R1 may also be replaced by a first voltage-dividing NMOS tube with a certain on-resistance. Figure 2 At this time, the gate of the first voltage-dividing NMOS tube MR2 is connected to the power line VDD, the drain is connected to the first capacitor C1, and the source is connected to the ground line VSS.

[0048] The second potential control module 120 also includes a second control voltage output unit, which includes a second capacitor C2 and a second resistor R2, one end of the second capacitor C2 is connected to the ground line VSS, the second resistor R2 is connected between the other end of the second capacitor C2 and the power line VDD, and the connection end between the second resistor R2 and the second capacitor C2 serves as a second control voltage end Q2.

[0049] When a positive ESD state is applied to the output terminal 101, Q2 is connected to VDD through the second resistor R2, and the positive ESD voltage is coupled through the parasitic diodes Dp1 and Dp2, so that the voltage of the power line VDD rises. Since a second capacitor C2 is connected between VDD and Q2, Q2 still maintains a low voltage for a period of time due to the capacitive reactance effect, thereby controlling Mn2 and Mn1 to be turned on and discharging the positive EDS voltage.

[0050] In other specific implementations, the second control voltage output unit may also adopt other circuit forms to achieve voltage control of the second control voltage terminal Q2.

[0051] Under normal working conditions, the gate of Mdn3 is connected to VDD through R2, Mdn3 is turned on, and the gate 2 of Mn2 is connected to VSS, so that Mn2 is turned off. At this time, the gates of Mdp1 and Mdp2 are both connected to VDD through R2 and are in the off state. The gate 1 of the first NMOS tube Mn1 is in a floating state, which does not affect the normal circuit operation.

[0052] The second resistor R2 can also be replaced by other voltage-dividing devices, for example, a second voltage-dividing PMOS transistor MR2 with a certain on-resistance (see Figure 3 ), the gate of the second voltage-dividing PMOS tube MR2 is connected to the ground line VSS, the source is connected to the ground line VDD, and the drain is connected to the second capacitor C2.

[0053] The first capacitor C1, the second resistor R1, the second capacitor C2 and the second resistor R2 are all adjustable devices, which are convenient for adjusting the potential at Q1 and Q2. Those skilled in the art need to adjust the size of C1 and R1 as well as C2 and R2 according to actual needs, so that Q1 and Q2 have a suitable potential in the ESD state to achieve the above-mentioned ESD voltage discharge.

[0054] Please refer to Figure 4 , is a schematic diagram of the structure of an output drive circuit according to another specific embodiment of the present invention.

[0055] and Figure 1 In contrast, in this specific implementation, the first potential control module 210 of the output drive circuit includes a first control voltage terminal Q1, and the voltage control of the Q1 terminal can also be achieved by a first control unit including a first resistor R1 and a first capacitor C1. When a negative ESD voltage is applied, the Q1 voltage is high, so that Mdp3 is disconnected, the gate 3 of Mp2 is in a floating state, and at this time the gate 4 of Mp1 is also in a floating state, and the potentials of the gates 3 and 4 are the same or almost the same, so that the conduction states of the Mp1 and Mp2 are the same or slightly different, and basically the uniform discharge of the negative ESD voltage can be achieved.

[0056] The second potential control module 220 of the output drive circuit includes a second control voltage terminal Q2, and the voltage control of the Q2 terminal can also be realized by a second control unit including a second resistor R2 and a second capacitor C2. When a positive ESD voltage is applied, the voltage of Q1 is low, so that Mdn3 is disconnected, the gate 2 of Mn2 is in a floating state, and at this time, the gate 1 of Mn1 is also in a floating state, and the potentials of the gate 2 and the gate 1 are the same or almost the same, so that the conduction states of the Mn1 and Mn2 are the same or slightly different, and basically the uniform discharge of the positive ESD voltage can be realized.

[0057] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. An output drive circuit with electrostatic protection function, characterized in that: include: An output driving module, comprising a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube, and an output end; a source of the first PMOS tube is connected to a power line VDD, and a drain is connected to a drain of the first NMOS tube; a source of the second PMOS tube is connected to a power line VDD, and a drain is connected to a drain of the second NMOS tube; a source of the first NMOS tube and a source of the second NMOS tube are both connected to a ground line VSS; the output end is connected to the drains of the first PMOS tube and the first NMOS tube, and is also connected to the drains of the second PMOS tube and the second NMOS tube; a first potential control module and a second potential control module, wherein the first potential control module is connected to the gate of the first PMOS tube and the gate of the second PMOS tube, and is used to make the gate of the first PMOS tube and the gate of the second PMOS tube have the same potential in an ESD state; and the second potential control module is connected to the gate of the first NMOS tube and the gate of the second NMOS tube, and is used to make the gate of the first NMOS tube and the gate of the second NMOS tube have the same potential in an ESD state; The first potential control module includes a first control voltage terminal and a third control PMOS transistor; the gate of the third control PMOS transistor is connected to the first control voltage terminal, the source is connected to the power line VDD, and the drain is connected to the gate of the second PMOS transistor; The first potential control module further includes: a first control NMOS tube and a second control NMOS tube; The drain of the first control NMOS tube is connected to the gate of the first PMOS tube, the source is connected to the ground line VSS, and the gate is connected to the first control voltage terminal; the drain of the second control NMOS tube is connected to the gate of the second PMOS tube, the source is connected to the ground line VSS, and the gate is connected to the first control voltage terminal; The first potential control module also includes a first control voltage output unit, which includes a first capacitor and a first voltage divider device, one end of the first capacitor is connected to the power line VDD, the first voltage divider device is connected between the other end of the first capacitor and the ground line VSS, and the connection end between the first voltage divider device and the first capacitor serves as a first control voltage end.

2. The output drive circuit according to claim 1, characterized in that: When a negative ESD voltage is applied to the output end, the voltage of the first control voltage terminal controls the first control NMOS tube and the second control NMOS tube to be turned on, and the third control PMOS tube to be turned off; when the voltage of the first control voltage terminal is in a normal working state, the first control NMOS tube and the second control NMOS tube are controlled to be turned off, and the third control PMOS tube is turned on.

3. The output drive circuit according to claim 1, characterized in that: The first voltage-dividing device is a first resistor or a first voltage-dividing NMOS tube. The gate of the first voltage-dividing NMOS tube is connected to the power line VDD, the drain is connected to the first capacitor, and the source is connected to the ground line VSS.

4. The output drive circuit according to claim 1, characterized in that: The second potential control module includes a second control voltage terminal and a third control NMOS tube; the gate of the third control NMOS tube is connected to the second control voltage terminal, the drain is connected to the gate of the second NMOS tube, and the source is connected to the ground line VSS; The second potential control module also includes a second control voltage output unit, which includes a second capacitor and a second voltage divider. One end of the second capacitor is connected to the ground line VSS, and the second voltage divider is connected between the other end of the second capacitor and the power line VDD. The connection end between the second voltage divider and the second capacitor serves as a second control voltage end.

5. The output drive circuit according to claim 4, characterized in that: The second potential control module also includes: a first control PMOS tube and a second control PMOS tube; the drain of the first control PMOS tube is connected to the gate of the first NMOS tube, the source is connected to the power line VDD, and the gate is connected to the second control voltage terminal; the drain of the second control PMOS tube is connected to the gate of the second NMOS tube, the source is connected to the power line VDD, and the gate is connected to the second control voltage terminal.

6. The output drive circuit according to claim 5, characterized in that: When a positive ESD voltage is applied to the output end, the voltage at the second control voltage end controls the first control PMOS tube and the second control PMOS tube to be turned on, and the third control NMOS transistor to be turned off; when the voltage at the second control voltage end is in a normal working state, the voltage at the first control PMOS tube and the second control PMOS tube to be turned off, and the third control NMOS tube to be turned on.

7. The output drive circuit according to claim 4, characterized in that: The second voltage-dividing device is a second resistor or a second voltage-dividing PMOS tube, the gate of the second voltage-dividing PMOS tube is connected to the ground line VSS, the source is connected to the power line VDD, and the drain is connected to the second capacitor.

8. The output drive circuit according to claim 1, characterized in that: The gate of the first PMOS tube is connected to the first output end of the pre-driving circuit; the gate of the first NMOS tube is connected to the second output end of the pre-driving circuit.

9. An output drive circuit with electrostatic protection function, characterized in that: include: An output driving module, comprising a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube, and an output end; a source of the first PMOS tube is connected to a power line VDD, and a drain is connected to a drain of the first NMOS tube; a source of the second PMOS tube is connected to a power line VDD, and a drain is connected to a drain of the second NMOS tube; a source of the first NMOS tube and a source of the second NMOS tube are both connected to a ground line VSS; the output end is connected to the drains of the first PMOS tube and the first NMOS tube, and is also connected to the drains of the second PMOS tube and the second NMOS tube; a first potential control module and a second potential control module, wherein the first potential control module is connected to the gate of the first PMOS tube and the gate of the second PMOS tube, and is used to make the gate of the first PMOS tube and the gate of the second PMOS tube have the same potential in an ESD state; and the second potential control module is connected to the gate of the first NMOS tube and the gate of the second NMOS tube, and is used to make the gate of the first NMOS tube and the gate of the second NMOS tube have the same potential in an ESD state; The second potential control module includes a second control voltage terminal and a third control NMOS tube; the gate of the third control NMOS tube is connected to the second control voltage terminal, the drain is connected to the gate of the second NMOS tube, and the source is connected to the ground line VSS; The second potential control module further includes: a first control PMOS tube and a second control PMOS tube; the drain of the first control PMOS tube is connected to the gate of the first NMOS tube, the source is connected to the power line VDD, and the gate is connected to the second control voltage terminal; the drain of the second control PMOS tube is connected to the gate of the second NMOS tube, the source is connected to the power line VDD, and the gate is connected to the second control voltage terminal; The second potential control module also includes a second control voltage output unit, which includes a second capacitor and a second voltage divider. One end of the second capacitor is connected to the ground line VSS, and the second voltage divider is connected between the other end of the second capacitor and the power line VDD. The connection end between the second voltage divider and the second capacitor serves as a second control voltage end.

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