MOSFET device and preparation method thereof

Abstract

The present invention discloses a MOSFET device and a preparation method, and relates to the field of semiconductor power devices. It is used to solve the problems of poor reliability and weak peripheral withstand voltage of the existing MOSFET. It includes: an active area groove, a peripheral groove, a first conductive type drift layer, a first conductive type body region and a second conductive type source region; the active area groove and the peripheral groove are arranged on the first conductive type drift layer; the second conductive type source region is arranged between the active area grooves and between the active area grooves and the peripheral grooves, and the bottom of the second conductive type source region is in contact with the upper surface of the first conductive type body region; the thickness of the SAC oxide layer in the peripheral groove is greater than the thickness of the gate oxide layer.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor power devices, and more specifically to a MOSFET device and a preparation method thereof. Background Art

[0002] In order to form a source on the lower-doped first conductive type drift layer on the surface of the silicon wafer, the traditional power device MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) uses a traditional injection voltage divider ring terminal design method, that is, the terminal area uses a PN junction for voltage resistance, and there is no thick dielectric layer in the terminal area. Therefore, a source light mask is required to shield the terminal area to prevent the source from being injected into the terminal area and destroying the PN junction voltage resistance structure.

[0003] In the prior art, each additional layer of mask increases the cost by about 15%. Therefore, when preparing the prior art MOSFET device, a mask plate needs to be prepared when the source electrode is injected, which has the problems of high manufacturing cost and complicated process. Summary of the invention

[0004] The embodiment of the present invention provides a MOSFET device and a preparation method thereof, which are used to solve the problems of high manufacturing cost and complicated process in the preparation of existing MOSFET devices due to the need to prepare a mask plate during source electrode injection.

[0005] The embodiment of the present invention provides a MOSFET device, an active area trench, a peripheral trench, a first conductivity type drift layer, a first conductivity type body region, and a second conductivity type source region;

[0006] The active area trench and the peripheral trench are arranged on the first conductive type drift layer;

[0007] The second conductive type source region is arranged between the active area trenches and between the active area trenches and the peripheral trenches, and the bottom of the second conductive type source region is in contact with the upper surface of the first conductive type body region;

[0008] The thickness of the SAC oxide layer in the peripheral trench is greater than the thickness of the gate oxide layer.

[0009] Preferably, it also includes a polysilicon layer;

[0010] The polysilicon layer is arranged in both the active area groove and the peripheral groove. The upper surface of the polysilicon layer located in the active area groove has the same height as the upper surface of the gate oxide layer located on both sides of the active area groove, and the upper surface of the polysilicon layer located in the peripheral groove has the same height as the upper surface of the gate oxide layer located on both sides of the peripheral groove.

[0011] Preferably, it also includes a cut-off ring region trench, a source region metal layer, a peripheral cut-off region metal layer and a gate region metal layer;

[0012] The cut-off ring area groove is adjacent to the peripheral groove;

[0013] The source region metal layer contacts the first conductive type body regions located between the active region trenches and between the active region trenches and the peripheral trenches respectively through the contact hole metal layer;

[0014] The gate region metal layer contacts the polysilicon layer through the contact hole metal layer;

[0015] The peripheral stop region metal layer is in contact with the first conductive type body region located at one side of the stop ring region trench and the polysilicon layer located in the peripheral trench respectively through the contact hole metal layer.

[0016] Preferably, the width of the peripheral trench is greater than the width of the active area trench;

[0017] The depth of the peripheral trench is greater than the depth of the active area trench;

[0018] The spacing between the peripheral trenches is equal to the spacing between the active area trenches.

[0019] Preferably, the width of the peripheral trench is 1.5 times the width of the active area trench;

[0020] The depth of the peripheral trench is 0.2 microns greater than the depth of the active area trench;

[0021] The peripheral trench includes a gate trench and a peripheral voltage-sustaining region trench.

[0022] An embodiment of the present invention provides a method for preparing a MOSFET device, comprising:

[0023] An active area trench and a peripheral trench are formed in the first conductive type drift layer by an etching method; the width of the peripheral trench is greater than the width of the active area trench, and the depth of the peripheral trench is greater than the depth of the active area trench;

[0024] forming a SAC oxide layer and a gate oxide layer on the first conductive type drift layer, in the active area trench and in the peripheral trench, wherein the thickness of the SAC oxide layer in the peripheral trench is greater than the thickness of the gate oxide layer;

[0025] forming a polysilicon layer and a polysilicon annealed oxide layer on the gate oxide layer by precipitation, etching and thermal oxidation processes;

[0026] Forming a first conductive type body region and a second conductive type source region between the active area trenches and between the active area and the peripheral trenches by ion implantation, wherein the second conductive type source region is located between the active area trenches and between the active area trenches and the peripheral trenches;

[0027] A contact hole metal layer is formed on the first conductive type body region and the polysilicon layer, and a gate region metal layer and a source region metal layer are sequentially formed through the contact hole.

[0028] Preferably, after forming the SAC oxide layer on the first conductive type drift layer, in the active area trench and in the peripheral trench, the method further comprises:

[0029] Performing photolithography to remove the active area trench and the SAC oxide layer on the upper surface of the active area trench by using a SAC mask;

[0030] The gate oxide layer is formed on the first conductivity type drift layer, in the active area trench and in the peripheral trench by a thermal oxidation method.

[0031] Preferably, the forming of the first conductivity type body region and the second conductivity type source region between the active area trenches and between the active area and the peripheral trenches by ion implantation specifically includes:

[0032] Forming the first conductive type body region between the active area trenches and between the active area trenches and the peripheral trenches by a first ion implantation;

[0033] The SAC oxide layer and the gate oxide layer are used as masks between the peripheral trenches, and second conductivity type source regions are formed on the first conductivity type body regions between the active area trenches and between the active area trenches and the peripheral trenches by a second ion implantation.

[0034] Preferably, the step of forming a contact hole metal layer on the first conductive type body region and the polysilicon layer, and sequentially forming a gate region metal layer and a source region metal layer through the contact hole specifically includes:

[0035] A silicon dioxide layer is formed on the peripheral trench and the active trench by a deposition process, and a contact hole metal layer is formed on the silicon dioxide layer by a photolithography process. Through the contact hole metal layer, the first conductive type body region located between the active area trenches, the first conductive type body region located between the active area trenches and the peripheral trenches, and the polysilicon layer located in the peripheral trenches are contacted in sequence to form a gate area metal layer and a source area metal layer.

[0036] Preferably, the width of the peripheral trench is 1.5 times the width of the active area trench;

[0037] The depth of the peripheral trench is 0.2 microns greater than the depth of the active area trench;

[0038] The peripheral trenches include gate trenches and peripheral voltage-sustaining region trenches;

[0039] The method also includes forming a stop ring outside the peripheral trench.

[0040] An embodiment of the present invention provides a MOSFET device, comprising: an active area trench, a peripheral trench, a first conductivity type drift layer, a first conductivity type body region and a second conductivity type source region; the active area trench and the peripheral trench are arranged on the first conductivity type drift layer; the second conductivity type source region is arranged between the active area trenches and between the active area trenches and the peripheral trenches, and the bottom of the second conductivity type source region is in contact with the upper surface of the first conductivity type body region; the thickness of the SAC oxide layer in the peripheral trench is greater than the thickness of the gate oxide layer. The terminal voltage divider ring of the MOSFET device is different from the traditional injection voltage divider ring. It uses a groove as a voltage divider, which can avoid the influence of the thermal process on the terminal injection ring, and is easier to control in terms of manufacturing process; and the thickness of the SAC oxide layer on the peripheral groove is greater than the thickness of the gate oxide layer on the active area groove, which can effectively prevent the device from breaking down at the bottom of the groove and improve the voltage resistance characteristics of the device; because the SAC oxide layer and the gate oxide layer retained in the terminal area have sufficient thickness, during the second ion implantation, the SAC oxide layer and the gate oxide layer can be used as a photolithography mask between the peripheral grooves, and only the second conductive type source area is formed between the active areas, and this method simplifies the process. At the same time, the MOSFET device solves the existing problems of high manufacturing and production costs and complex processes due to the need to prepare a mask plate during source electrode injection, and solves the problems of poor reliability and weak peripheral voltage resistance of MOSFET. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0042] Figure 1 A schematic diagram of a MOSFET device structure provided by an embodiment of the present invention;

[0043] Figure 2A schematic diagram of a MOSFET device preparation process provided by an embodiment of the present invention;

[0044] Figure 3A A schematic diagram of preparing a first conductivity type drift layer provided in an embodiment of the present invention;

[0045] Figure 3B A schematic diagram of the preparation of active area trenches, peripheral trenches and stop ring area trenches provided in an embodiment of the present invention;

[0046] Figure 3C A schematic diagram of preparing a SAC oxide layer provided in an embodiment of the present invention;

[0047] Figure 3D A schematic diagram of a SAC oxide layer without an active region and a cutoff ring provided in an embodiment of the present invention;

[0048] Figure 3E A schematic diagram of preparing a gate oxide layer on a first conductivity type drift layer, in an active area trench and in a peripheral trench provided in an embodiment of the present invention;

[0049] Figure 3F A schematic diagram of preparing a polysilicon layer provided in an embodiment of the present invention;

[0050] Figure 3G A schematic diagram of preparing a polysilicon annealing oxide layer provided in an embodiment of the present invention;

[0051] Figure 3H A schematic diagram of preparing a first conductivity type body region provided in an embodiment of the present invention;

[0052] Fig. 3I A schematic diagram of preparing a second conductivity type source region provided in an embodiment of the present invention;

[0053] Figure 3J A schematic diagram of preparing a silicon dioxide layer provided in an embodiment of the present invention;

[0054] Figure 3K A schematic diagram of preparing a metal layer for a contact hole provided in an embodiment of the present invention;

[0055] Figure 3L A schematic diagram of preparing a metal layer provided in an embodiment of the present invention.

[0056] Among them, the first conductive type substrate layer ~1, the first conductive type drift layer ~2, the active area trench ~3, the gate trench ~4, the peripheral voltage-resistant area trench ~5, the cut-off ring area trench ~6, the SAC oxide layer ~7, the gate oxide layer ~8, the polysilicon layer ~9, the polysilicon annealed oxide layer ~10, the first conductive type body region ~11, the second conductive type source region ~12, the silicon dioxide layer ~13, the contact hole ~14, the contact hole metal layer ~15, the source region metal layer ~17, the gate region metal layer ~18, the peripheral cut-off region metal layer ~19, the drain region metal layer ~20, and the peripheral trench ~45. DETAILED DESCRIPTION

[0057] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0058] Figure 1 An exemplary schematic diagram of a MOSFET device structure provided by an embodiment of the present invention is shown. Figure 1 As shown, the MOSFET device mainly includes an active area trench 3 , a peripheral trench 45 , a first conductive type drift layer 2 , a first conductive type body region 11 and a second conductive type source region 12 .

[0059] like Figure 1 As shown, the active area trench 3, the peripheral trench 45 and the stop ring area trench 6 are all arranged on the first conductive type drift layer 2, wherein the active area trench 3 and the stop ring area trench 6 are respectively arranged on both sides of the peripheral trench 45. In the embodiment of the present invention, in order to optimize the electric field distribution in the active area and the peripheral boundary area, preferably, on the one hand, the depth of the peripheral trench 45 is greater than the depth of the active area trench 3; on the other hand, the width of the peripheral trench 45 is also greater than the width of the active area trench 3.

[0060] Furthermore, in order to prevent the device from being broken down at the bottom of the trench, that is, to improve the voltage resistance characteristics of the device, preferably, the thickness of the SAC (Sacrificial) oxide layer 7 in the peripheral trench 45 is greater than the thickness of the gate oxide layer 8 in the active area trench 3.

[0061] In practical applications, the peripheral groove 45 includes a gate groove 4 and a peripheral voltage-resistant region groove 5, wherein the gate groove 4 is located between the active region groove 3 and the peripheral voltage-resistant region groove 5, and correspondingly, the peripheral voltage-resistant region groove 5 is located between the gate groove 4 and the cut-off ring region groove 6. It should be noted that the number of the gate groove 4 and the peripheral voltage-resistant region groove 5 included in the peripheral groove 45 includes multiple, and the spacing between the multiple peripheral grooves 45 is equal. In order to improve the electric field distribution in the peripheral area so that the peripheral voltage resistance of the device is higher than the voltage resistance of the active area, preferably, the spacing between the multiple peripheral grooves 45 and the active region groove 3 is also equal. Furthermore, the gate groove 4 and the peripheral voltage-resistant region groove 5 have the same width, and the gate groove 4 and the peripheral voltage-resistant region groove 5 also have the same groove depth.

[0062] like Figure 1 As shown, a layer of polysilicon layer 9 is deposited in the active area trench 3, the gate trench 4, the peripheral voltage-sustaining area trench 5 and the cut-off ring area trench 6. Since a layer of gate oxide layer 8 is grown in the active area trench 3 by a thermal oxidation process, and a layer of SAC oxide layer 7 and gate oxide layer 8 are deposited in the gate trench 4, the cut-off ring area trench 6 and the peripheral voltage-sustaining area trench 5, and the thickness of the SAC oxide layer 7 is greater than the thickness of the gate oxide layer 8, the polysilicon layer 9 deposited on the active area trench 3, the gate trench 4, the peripheral voltage-sustaining area trench 5 and the cut-off ring area trench 6 has different heights. Specifically, as shown in FIG. Figure 1 As shown, the upper surface of the polysilicon layer 9 in the active area trench 3 has the same height as the upper surface of the gate oxide layer 8 on both sides of the active area trench, while the upper surface of the polysilicon layer 9 in the gate trench 4, the cut-off ring area trench 6 and the peripheral voltage-sustaining area trench 5 has the same height as the upper surface of the gate oxide layer 8 on the SAC oxide layer 7. That is, the upper surface of the gate oxide layer 8 on both sides of the active area trench is on the same horizontal line as the upper surface of the polysilicon layer 9 in the active area trench 3, while the upper surface of the gate oxide layer 8 on both sides of the gate trench 4, the cut-off ring area trench 6 and the peripheral voltage-sustaining area trench 5 on the SAC oxide layer 7 is on the same horizontal line as the upper surface of the polysilicon layer 9 in the gate trench 4, the cut-off ring area trench 6 and the peripheral voltage-sustaining area trench 5.

[0063] Since there are multiple active area trenches 3, a first conductive type body region 11 is included between the multiple active area trenches 3. Further, one side of the cut-off ring area trench 6 also includes the first conductive type body region 11. Further, the area adjacent to the active area trench 3 and the gate trench 4 also includes the first conductive type body region 11, while the first conductive type body region 11 is not arranged between the cut-off ring area trench 6 and the peripheral voltage-resistant area trench 5, and only the first conductive type body region 11 is included on the other side of the cut-off ring area trench 6.

[0064] Furthermore, a second conductive type source region 12 is also included in the first conductive type body region 11. Specifically, a second conductive type source region 12 is arranged on the first conductive type body region 11 located between the active area trenches 3; a second conductive type source region 12 is also arranged on the first conductive type body region 11 located in the area adjacent to the source area trench 3 and the gate trench 4; and a second conductive type source region 12 is also arranged on the first conductive type body region 11 located on one side of the cutoff ring area trench 6.

[0065] like Figure 1 As shown, a contact hole 14 is provided on the first conductive type body region 11 and the second conductive type source region 12 located between the active area trench 3. After metal is provided in the contact hole 14, the contact hole 14 forms a contact hole metal layer 15. The first conductive type body region 11 located between the active area trench 3 and the gate trench 4 is provided with a contact hole metal layer 15, and the above two contact hole metal layers 15 are in contact with the active area metal layer; the first conductive type body region 11 and the second conductive type source region 12 located on one side of the stop ring area trench 6 are provided with a contact hole metal layer 15, and the polysilicon layer 9 in the stop ring area trench 6 is provided with a contact hole metal layer 15, and the above two contact hole metal layers 15 are in contact with the peripheral stop area metal layer 19; the polysilicon layer 9 located in the gate trench 4 is provided with a contact hole metal layer 15, and the contact hole metal layer 15 is in contact with the gate area metal layer 18. It should be noted that in the embodiment of the present invention, in order to ensure that the dynamic characteristics of the gate area are better than those of other MOSFET devices, it is similar to the charge balance principle of the split-gate MOSFET device. Preferably, the contact hole metal layer 15 in contact with the gate metal layer is surrounded by grooves on both sides, that is, the polysilicon layer 9 in contact with the contact hole metal layer 15 has multiple polysilicon layers 9 on both sides, and the above-mentioned polysilicon layers 9 all refer to polysilicon layers 9 arranged in the grooves.

[0066] In an embodiment of the present invention, in order to optimize the electric field distribution in the peripheral boundary area of ​​the active area, preferably, the width of the gate trench 4 and the peripheral voltage-resistant area trench 5 is 1.5 times the width of the active area trench 3, and the depth of the gate trench 4 and the peripheral voltage-resistant area trench 5 is 0.2 microns greater than the depth of the active area trench 3.

[0067] In the embodiment of the present invention, the first conductivity type is N-type, and the second conductivity type is P-type; or the first conductivity type is P-type, and the second conductivity type is N-type.

[0068] In order to more clearly introduce the MOSFET device provided by the embodiment of the present invention, a method for preparing the MOSFET device is introduced below.

[0069] Figure 2 A schematic diagram of a MOSFET device preparation process provided by an embodiment of the present invention; Figure 3AA schematic diagram of preparing a first conductivity type drift layer provided in an embodiment of the present invention; Figure 3B A schematic diagram of the preparation of active area trenches, peripheral trenches and stop ring area trenches provided in an embodiment of the present invention; Figure 3C A schematic diagram of preparing a SAC oxide layer provided in an embodiment of the present invention; Figure 3D A schematic diagram of a SAC oxide layer without an active region and a cutoff ring provided in an embodiment of the present invention; Figure 3E A schematic diagram of preparing a gate oxide layer on a first conductivity type drift layer, in an active area trench and in a peripheral trench provided in an embodiment of the present invention; Figure 3F A schematic diagram of preparing a polysilicon layer provided in an embodiment of the present invention; Figure 3G A schematic diagram of preparing a polysilicon annealing oxide layer provided in an embodiment of the present invention; Figure 3H A schematic diagram of preparing a first conductivity type body region provided in an embodiment of the present invention; Fig. 3I A schematic diagram of preparing a second conductivity type source region provided in an embodiment of the present invention; Figure 3J A schematic diagram of preparing a silicon dioxide layer provided in an embodiment of the present invention; Figure 3K A schematic diagram of preparing a metal layer for a contact hole provided in an embodiment of the present invention; Figure 3L A schematic diagram of preparing a metal layer provided in an embodiment of the present invention.

[0070] The following Figure 2 The preparation method provided is schematically shown in FIG. Figure 3A to Figure 3L The preparation schematic diagram provided is used to introduce the preparation method of MOSFET devices in detail. Specifically, Figure 2 As shown, the method mainly includes the following steps:

[0071] Step 101, forming an active area trench and a peripheral trench in a first conductive type drift layer by an etching method; the width of the peripheral trench is greater than the width of the active area trench, and the depth of the peripheral trench is greater than the depth of the active area trench;

[0072] Step 102, forming a SAC oxide layer and a gate oxide layer on the first conductive type drift layer, in the active area trench and in the peripheral trench, and the thickness of the SAC oxide layer in the peripheral trench is greater than the thickness of the gate oxide layer;

[0073] Step 103, forming a polysilicon layer and a polysilicon annealed oxide layer on the gate oxide layer by precipitation, etching and thermal oxidation processes;

[0074] Step 104, forming a first conductivity type body region and a second conductivity type source region between the active area trenches and between the active area and the peripheral trenches by ion implantation, wherein the second conductivity type source region is located between the active area trenches and between the active area trenches and the peripheral trenches;

[0075] Step 105 , forming a contact hole metal layer on the first conductive type body region and the polysilicon layer, and sequentially forming a gate region metal layer and a source region metal layer through the contact hole.

[0076] Specifically, Figure 3A As shown, an N-type heavily doped semiconductor first conductivity type substrate layer 1 is first provided, and then an N-type lightly doped first conductivity type drift layer 2 is grown on the N-type heavily doped semiconductor first conductivity type substrate layer 1 .

[0077] In step 101, if Figure 3B As shown, the active area trench 3, the peripheral trench 45 and the stop ring area trench 6 are sequentially formed in the first conductive type drift layer 2 by etching. It should be noted that the peripheral trench 45 includes the gate trench 4 and the peripheral voltage-sustaining area trench 5.

[0078] In the embodiment of the present invention, in order to optimize the electric field distribution in the active area and the peripheral boundary area, preferably, on the one hand, the depth of the peripheral trench 45 is greater than the depth of the active area trench 3; on the other hand, the width of the peripheral trench 45 is also greater than the width of the active area trench 3. Further, in order to improve the electric field distribution in the peripheral area so that the device periphery withstand voltage is higher than the withstand voltage capability of the active area, preferably, the spacing between the plurality of peripheral trenches 45 and the active area trench 3 is also equal.

[0079] In step 102, if Figure 3C As shown, a sacrificial oxide layer is grown on the upper surface of the first conductive type drift layer 2 and inside the active area trench 3, the gate trench 4, the peripheral voltage-resistant area trench 5 and the cut-off ring area trench 6 by a thermal oxidation process, and then an oxide layer is deposited by a chemical vapor deposition process to form a SAC oxide layer 7.

[0080] Furthermore, if Figure 3D As shown, photolithography is performed by using a SAC mask to remove the SAC oxide layer 7 on the upper surface of the first conductive type drift layer 2 in the active area trench 3 and on both sides of the active area trench 3, and remove the SAC oxide layer 7 on the upper surface of the first conductive type drift layer 2 on one side of the cut-off ring area trench 6. It should be noted that the first conductive type drift layer 2 on one side of the cut-off ring area trench 6 represents the side that is not adjacent to the peripheral voltage-sustaining area trench 5.

[0081] Furthermore, if Figure 3EAs shown, a gate oxide layer 8 is grown by thermal oxidation process on the upper surface of the first conductive type drift layer 2, in the active area trench 3, in the gate trench 4, in the peripheral voltage-sustaining area trench 5, and in the cut-off ring area trench 6. In the embodiment of the present invention, in order to prevent the device from being broken down at the bottom of the trench, that is, to improve the voltage-sustaining characteristics of the device, preferably, the thickness of the SAC oxide layer 7 in the gate trench 4 and the peripheral voltage-sustaining area trench 5 is greater than the thickness of the gate oxide layer 8 in the active area trench 3.

[0082] In step 103, if Figure 3F As shown, a layer of N-type heavily doped polysilicon layer 9 is deposited on the upper surface of the gate oxide layer 8 by a deposition process, that is, while the polysilicon layer 9 is formed in the active area trench 3, the gate trench 4, the peripheral voltage-resistant area trench 5 and the cut-off ring area trench 6, a layer of heavily doped polysilicon layer 9 is also deposited on the gate oxide layer 8 on both sides of the active area trench 3, the gate trench 4, the peripheral voltage-resistant area trench 5 and the cut-off ring area trench 6. Further, the layer of heavily doped polysilicon layer 9 deposited on the gate oxide layer 8 on both sides of the active area trench 3, the gate trench 4, the peripheral voltage-resistant area trench 5 and the cut-off ring area trench 6 is etched away by an etch-back process.

[0083] like Figure 3G As shown, annealing is performed through a thermal oxidation process to activate the doped elements inside the polysilicon layer 9, and a polysilicon annealed oxide layer 10 is grown on the upper surface of the gate oxide layer 8.

[0084] In step 104, if Figure 3H As shown, a first conductivity type body region 11 is formed in the first conductivity type drift layer 2 by the first implantation method. It should be noted that the first conductivity type body region 11 is located between the active area trenches 3, between the active area trenches 3 and the gate trenches 4, and on one side of the cut-off ring area trench 6. That is, when the first ion implantation is performed, the SAC oxide layer 7 and the gate oxide layer 8 are used as a mask between the peripheral trenches 45, thereby blocking the first ion implantation between the peripheral trenches 45.

[0085] It should be noted that, during the first injection, the upper surface of the SAC oxide layer 7 is blocked by photolithography, while the upper surface of the active area gate oxide layer 8 is exposed. Therefore, through this injection, a first conductive type body region 11 is formed between the active area trenches 3, between the active area trenches 3 and the gate trenches 4, and on one side of the cutoff ring area trench 6.

[0086] like Fig. 3IAs shown, a second conductive type source region 12 is formed in the first conductive type body region 11 between the active region trenches 3, a second conductive type source region 12 is formed in the first conductive type body region 11 between the active region trenches 3 and the gate trenches 4, and a second conductive type source region 12 is formed in the first conductive type body region 11 on one side of the cut-off ring region trench 6. It should be noted that in the embodiment of the present invention, the SAC oxide layer 7 and the gate oxide layer 8 located on the peripheral trench 45 can be used as a photoresist mask for the second conductive type source region 12. Therefore, when performing the second ion implantation, a photoresist mask is not prepared on the peripheral trench 45. Further, since a photoresist mask is not prepared on the peripheral trench 45, a second conductive type source region 12 is also formed in the first conductive type body region 11 between the source region trench 3 and the gate trench 4.

[0087] In step 105, if Figure 3J As shown, an isolation silicon dioxide layer 13 is deposited on the surface of the polysilicon annealed oxide layer 10 by a deposition process. Figure 3K As shown, a contact hole 14 is formed on the silicon dioxide layer 13 by an etching method, and then a metal is filled into the contact hole 14 by a filling method to form a contact hole metal layer 15. Specifically, a contact hole metal layer 15 is formed on the first conductive type body region 11 and the second conductive type source region 12 located between the active area trenches 3, and a contact hole metal layer 15 is formed on the first conductive type body region 11 located between the active area trenches 3 and the gate trenches 4; a contact hole metal layer 15 is formed on the first conductive type body region 11 and the second conductive type source region 12 located on one side of the stop ring area trench 6, and a contact hole metal layer 15 is formed on the polysilicon layer 9 in the stop ring area trench 6; and a contact hole metal layer 15 is formed on the polysilicon layer 9 located in the gate trench 4.

[0088] A metal layer is sputtered on the surface of the silicon dioxide layer 13 by a sputtering process, and a source region metal layer 17, a gate region metal layer 18 and a peripheral cut-off region metal layer 19 are defined by a photolithography and etching process. After the wafer is thinned by a grinding process, a drain region metal layer 20 is formed by a metal evaporation process. Figure 3LAs shown, the contact hole metal layer 15 on the first conductive type body region 11 and the second conductive type source region 12 between the active region trench 3 and the contact hole metal layer 15 on the first conductive type body region 11 between the active region trench 3 and the gate trench 4 are both in contact with the active region metal layer; the contact hole metal layer 15 on the first conductive type body region 11 and the second conductive type source region 12 on one side of the stop ring region trench 6 and the contact hole metal layer 15 of the polysilicon layer 9 in the stop ring region trench 6 are both in contact with the peripheral stop region metal layer 19; the contact hole metal layer 15 of the polysilicon layer 9 in the gate trench 4 is in contact with the gate region metal layer 18. The drain region metal layer 20 is in contact with the lower surface of the first conductive type substrate layer 1.

[0089] In summary, an embodiment of the present invention provides a MOSFET device, comprising: an active area trench, a peripheral trench, a first conductive type drift layer, a first conductive type body region and a second conductive type source region; the active area trench and the peripheral trench are arranged on the first conductive type drift layer; the second conductive type source region is arranged between the active area trenches and between the active area trenches and the peripheral trenches, and the bottom of the second conductive type source region is in contact with the upper surface of the first conductive type body region; the thickness of the SAC oxide layer in the peripheral trench is greater than the thickness of the gate oxide layer. The terminal voltage divider ring of the MOSFET device is different from the traditional injection voltage divider ring. It uses a groove as a voltage divider, which can avoid the influence of the thermal process on the terminal injection ring, and is easier to control in terms of manufacturing process; and the thickness of the SAC oxide layer on the peripheral groove is greater than the thickness of the gate oxide layer on the active area groove, which can effectively prevent the device from breaking down at the bottom of the groove and improve the voltage resistance characteristics of the device; because the SAC oxide layer and the gate oxide layer retained in the terminal area have sufficient thickness, during the second ion implantation, the SAC oxide layer and the gate oxide layer can be used as a photolithography mask between the peripheral grooves, and only the second conductive type source area is formed between the active areas, and this method simplifies the process. At the same time, the MOSFET device solves the existing problems of high manufacturing and production costs and complex processes due to the need to prepare a mask plate during source electrode injection, and solves the problems of poor reliability and weak peripheral voltage resistance of MOSFET.

[0090] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0091] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A method for preparing a MOSFET device, characterized in that: The MOSFET device comprises: an active area trench, a peripheral trench, a first conductive type drift layer, a second conductive type body region and a first conductive type source region; The active area trench and the peripheral trench are arranged on the first conductive type drift layer; The first conductive type source region is arranged between the active area trenches and between the active area trenches and the peripheral trenches, and the bottom of the first conductive type source region is in contact with the upper surface of the second conductive type body region; The thickness of the SAC oxide layer in the peripheral trench is greater than the thickness of the gate oxide layer; The preparation of the MOSFET device comprises the following steps: An active area trench and a peripheral trench are formed in the first conductive type drift layer by an etching method; the width of the peripheral trench is greater than the width of the active area trench, and the depth of the peripheral trench is greater than the depth of the active area trench; forming a SAC oxide layer and a gate oxide layer on the first conductive type drift layer, in the active area trench and in the peripheral trench, wherein the thickness of the SAC oxide layer in the peripheral trench is greater than the thickness of the gate oxide layer; forming a polysilicon layer and a polysilicon annealed oxide layer on the gate oxide layer by precipitation, etching and thermal oxidation processes; Using the SAC oxide layer and the gate oxide layer as masks between the peripheral trenches, forming the second conductive type body region between the active area trenches and between the active area trenches and the peripheral trenches by a first ion implantation; Using the SAC oxide layer and the gate oxide layer as masks between the peripheral trenches, forming a first conductivity type source region on the second conductivity type body region between the active area trenches and between the active area trenches and the peripheral trenches by a second ion implantation; A contact hole metal layer is formed on the second conductive type body region and the polysilicon layer, and a gate region metal layer and a source region metal layer are sequentially formed through the contact hole.

2. The device preparation method according to claim 1, characterized in that: Also including a polysilicon layer; The polysilicon layer is arranged in both the active area groove and the peripheral groove. The upper surface of the polysilicon layer located in the active area groove has the same height as the upper surface of the gate oxide layer located on both sides of the active area groove, and the upper surface of the polysilicon layer located in the peripheral groove has the same height as the upper surface of the gate oxide layer located on both sides of the peripheral groove.

3. The device preparation method according to claim 2, characterized in that: It also includes a cut-off ring region trench, a source region metal layer, a peripheral cut-off region metal layer and a gate region metal layer; The cut-off ring area groove is adjacent to the peripheral groove; The source region metal layer contacts the second conductive type body regions located between the active region trenches and between the active region trenches and the peripheral trenches respectively through the contact hole metal layer; The gate region metal layer contacts the polysilicon layer through the contact hole metal layer; The peripheral stop region metal layer contacts the second conductive type body region located at one side of the stop ring region trench and the polysilicon layer located in the peripheral trench respectively through the contact hole metal layer.

4. The device preparation method according to claim 3, characterized in that: The width of the peripheral trench is greater than the width of the active area trench; The depth of the peripheral trench is greater than the depth of the active area trench; The spacing between the peripheral trenches is equal to the spacing between the active area trenches.

5. The device preparation method according to claim 4, characterized in that: The width of the peripheral trench is 1.5 times the width of the active area trench; The depth of the peripheral trench is 0.2 microns greater than the depth of the active area trench; The peripheral trench includes a gate trench and a peripheral voltage-sustaining region trench.

6. The device preparation method according to claim 1, characterized in that: After forming the SAC oxide layer on the first conductive type drift layer, in the active area trench and in the peripheral trench, the method further includes: Performing photolithography to remove the active area trench and the SAC oxide layer on the upper surface of the active area trench by using a SAC mask; The gate oxide layer is generated on the first conductive type drift layer, in the active area trench and in the peripheral trench by a thermal oxidation method.

7. The device preparation method according to claim 1, characterized in that: The step of forming a contact hole metal layer on the second conductive type body region and the polysilicon layer, and sequentially forming a gate region metal layer and a source region metal layer through the contact hole specifically includes: A silicon dioxide layer is formed on the peripheral trench and the active trench by a deposition process, and a contact hole metal layer is formed on the silicon dioxide layer by a photolithography process. Through the contact hole metal layer, the second conductive type body region located between the active area trenches, the second conductive type body region located between the active area trenches and the peripheral trenches, and the polysilicon layer located in the peripheral trenches are contacted in sequence to form a gate area metal layer and a source area metal layer.

8. The device preparation method according to any one of claims 1 to 7, characterized in that: The width of the peripheral trench is 1.5 times the width of the active area trench; The depth of the peripheral trench is 0.2 microns greater than the depth of the active area trench; The peripheral trenches include gate trenches and peripheral voltage-sustaining region trenches; The method also includes forming a stop ring outside the peripheral trench.

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