Semiconductor structure

Abstract

The present invention provides a semiconductor structure, comprising: a substrate; a gate disposed on the substrate; a source disposed in the substrate and located on one side of the gate; a drain disposed in the substrate and located on the other side of the gate; and a gate extension disposed on the substrate and located between the gate and the drain, wherein the doping type of the gate is opposite to the doping type of the gate extension. The special semiconductor structure design of the present invention can effectively reduce the power loss of the switching device, greatly increase the switching frequency and achieve high-efficiency electric power conversion.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure, and more particularly to a semiconductor structure capable of reducing drain-to-gate capacitance. Background Art

[0002] In many semiconductor structures, a field plate structure disposed between the gate and the drain is often used as an important device to disperse the electric field strength in the drain region (drift region) to avoid excessive concentration of the electric field near the drain region (drift region) causing device damage. However, when this field plate structure forms an electrical connection with its adjacent gate, this field plate structure will also contribute a considerable degree of drain-to-gate capacitance.

[0003] Generally speaking, for high-speed switching devices that are expected to achieve high-efficiency power conversion, it is necessary to minimize power loss during operation in order to maintain high-speed conversion between devices. However, when the switch is turned on and a large current flows, if the transistor adjacent to the load (phase) has the above-mentioned drain-gate capacitance, the transistor will have an undesirable current flowing through it due to the coupling effect, resulting in power loss of the switching device.

[0004] Currently, there are several methods to reduce the drain-gate capacitance, such as changing the field plate structure to be electrically connected to the source, or increasing the thickness of the oxide layer under the field plate or the gate, or implanting dopants on the substrate surface under the gate that are opposite to the doping type of the drain region (drift region), etc. However, the above methods still have many disadvantages, such as an increase in resistance.

[0005] Therefore, it is highly anticipated to develop a semiconductor structure that can effectively disperse the electric field strength in the drain region (drift region) and simultaneously reduce the drain-to-gate capacitance. Summary of the invention

[0006] According to an embodiment of the present invention, a semiconductor structure is provided, comprising: a substrate; a gate disposed on the substrate; a source disposed in the substrate and located on one side of the gate; a drain disposed in the substrate and located on the other side of the gate; and a gate extension disposed on the substrate and located between the gate and the drain, wherein the doping type of the gate is opposite to the doping type of the gate extension.

[0007] In some embodiments, the substrate is a P-type substrate or an N-type substrate. In some embodiments, when the substrate is a P-type substrate, the doping type of the gate is N-type, the doping type of the source is N-type, the doping type of the drain is N-type, and the doping type of the gate extension is P-type. In some embodiments, when the substrate is an N-type substrate, the doping type of the gate is P-type, the doping type of the source is P-type, the doping type of the drain is P-type, and the doping type of the gate extension is N-type. In some embodiments, the gate and the gate extension are polysilicon doped with P-type dopants or N-type dopants.

[0008] In some embodiments, the gate is in substantial contact with the gate extension. In some embodiments, the gate is substantially separated from the gate extension.

[0009] In some embodiments, when the gate is in substantial contact with the gate extension, the semiconductor structure of the present invention further includes a metal field plate disposed on the substrate between the gate extension and the drain. In some embodiments, the semiconductor structure of the present invention further includes an oxide layer disposed on the substrate below the metal field plate. In some embodiments, the metal field plate is electrically connected to the gate and the gate extension. In some embodiments, the metal field plate is electrically connected to the source. In some embodiments, the ratio of the width of the gate extension to the width of the gate is between 0.3 and 1.2. In some embodiments, the sum of the width of the gate extension and the width of the gate is a constant.

[0010] In some embodiments, when the gate is substantially separated from the gate extension, the gate is electrically connected to the gate extension. In some embodiments, the gate extension is electrically connected to the source.

[0011] The present invention forms two regions of opposite doping types in the polysilicon gate of the MOS transistor through an implantation process (for example, the region of the gate adjacent to the drain (defined as the gate extension in the present invention) is P-type doped, and the region of the gate away from the drain (defined as the gate in the present invention) is N-type doped). Due to the effect of capacitor series connection, the drain-to-gate capacitance is improved, and as the ratio of the width of the gate extension to the width of the gate gradually increases, the proportion of the drain-to-gate capacitance decreases more significantly. At this time, the gate extension also has the function of a field plate, which can effectively disperse the electric field strength of the drain region (drift region) to avoid damage to the device in a high-voltage operating environment. In addition, the above two regions of opposite doping types can also be made into two separated structures. On the one hand, the gate extension can have the function of a field plate, and on the other hand, the overall effect of reducing the drain-to-gate capacitance can be achieved. The present invention has low cost and can be simply manufactured without changing the existing MOS process rules. Due to the decrease of drain-gate capacitance, the undesired current flow caused by the coupling effect of the transistor is avoided. The special semiconductor structure design of the present invention can effectively reduce the power loss of the switching device, greatly increase the switching frequency and achieve high-efficiency power conversion. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0013] Figure 1 is a cross-sectional schematic diagram showing a semiconductor structure according to an embodiment of the present invention;

[0014] Figure 2 is a cross-sectional schematic diagram showing a semiconductor structure according to an embodiment of the present invention;

[0015] Figure 3 is a cross-sectional schematic diagram showing a semiconductor structure according to an embodiment of the present invention;

[0016] Figure 4 is a cross-sectional schematic diagram showing a semiconductor structure according to an embodiment of the present invention;

[0017] Figure 5 is a cross-sectional schematic diagram showing a semiconductor structure according to an embodiment of the present invention;

[0018] Figure 6 is a cross-sectional schematic diagram showing a semiconductor structure according to an embodiment of the present invention; and

[0019] Figure 7 The figure is a cross-sectional schematic diagram showing a semiconductor structure according to an embodiment of the present invention.

[0020] Reference numerals:

[0021] 10 Semiconductor structure

[0022] 12 substrate

[0023] 14 Gate

[0024] 16 Source

[0025] 18 Drain

[0026] 20 Gate extension

[0027] 22 Drain drift region

[0028] 24 metal field plates

[0029] 26 Oxide layer

[0030] 28, 30, 32, 34 metal layers

[0031] B E Gate extension boundary

[0032] W E Width of gate extension

[0033] W G Gate width

[0034] W T The sum of the width of the gate extension and the width of the gate DETAILED DESCRIPTION

[0035] To make the purpose, technical solution and advantages of the embodiments of the present invention more clear, the embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings. Here, the exemplary embodiments of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention.

[0036] See also Figure 1 According to one embodiment of the present invention, a semiconductor structure 10 is provided. Figure 1 is a schematic cross-sectional view of the semiconductor structure 10 .

[0037] like Figure 1As shown, the semiconductor structure 10 includes a substrate 12, a gate 14, a source 16, a drain 18, a gate extending portion 20, and a drain drift region 22. The gate 14 is disposed on the substrate 12. The source 16 is disposed in the substrate 12 and is located on one side of the gate 14. The drain 18 is disposed in the substrate 12 and is located on the other side of the gate 14. The gate extending portion 20 is disposed on the substrate 12 and is located between the gate 14 and the drain 18. The drain drift region 22 is located in the substrate 12 and surrounds the drain 18. It is worth noting that the doping type of the gate 14 is opposite to the doping type of the gate extending portion 20, for example, when the doping type of the gate 14 is N-type, the doping type of the gate extending portion 20 is P-type, or, when the doping type of the gate 14 is P-type, the doping type of the gate extending portion 20 is N-type. Since the doping type of the gate 14 is opposite to the doping type of the gate extension 20 , a depletion region (not shown) is naturally formed between the gate 14 and the gate extension 20 .

[0038] In some embodiments, the substrate 12 is a P-type semiconductor substrate or an N-type semiconductor substrate. In some embodiments, when the substrate 12 is a P-type semiconductor substrate, the doping type of the gate 14 is N-type, the doping type of the source 16 is N-type, the doping type of the drain 18 is N-type, and the doping type of the gate extension 20 is P-type. In some embodiments, when the substrate 12 is an N-type semiconductor substrate, the doping type of the gate 14 is P-type, the doping type of the source 16 is P-type, the doping type of the drain 18 is P-type, and the doping type of the gate extension 20 is N-type. In some embodiments, the gate 14 and the gate extension 20 are polysilicon doped with P-type dopants or N-type dopants.

[0039] exist Figure 1 In some embodiments, the gate 14 is in substantial contact with the gate extension 20, for example, the gate 14 is in substantial contact with the gate extension 20 in a lateral direction (ie, the sidewall of the gate 14 is in substantial contact with the sidewall of the gate extension 20). E The width W of the gate 14 G The ratio of W is approximately between 0.3 and 1.2. For example, the width W of the gate extension 20 is E The gate 14 has a width W of about 0.15 microns. G is about 0.5 microns (the ratio of the two is about 0.3), or the width W of the gate extension 20 is about 0.5 microns (the ratio of the two is about 0.3). E The gate 14 has a width W of about 0.25 micrometers. G is about 0.4 microns (the ratio of the two is about 0.625), or the width W of the gate extension 20 is about 0.4 microns (the ratio of the two is about 0.625). EThe gate 14 has a width W of about 0.35 microns. G is about 0.3 microns (the ratio of the two is about 1.17). In some embodiments, the width W of the gate extension 20 is E The width W of the gate 14 G The ratio of can also be in other appropriate ranges, and is not limited thereto. In some embodiments, the boundary B between the gate extension 20 and the gate 14 is E Preferably, the gate extension 20 does not exceed the range of the drain drift region 22 (ie, the gate extension 20 only overlaps with the drain drift region 22 in the substrate 12 ). In some embodiments, in the semiconductor structure 10 , the width W of the gate extension 20 is E The width W of the gate 14 G The total W T is a certain value, for example, when the width W of the gate extension 20 is E The width W of the gate 14 G When the ratio of is within the range of 0.3-1.2, the width W of the gate extension 20 is E The width W of the gate 14 G The total W T The width W of the gate extension 20 is about 0.65 micrometers (for example, E The gate 14 has a width W of about 0.15 microns. G The width W of the gate extension 20 is about 0.5 micrometers, or E The gate 14 has a width W of about 0.25 micrometers. G The width W of the gate extension 20 is about 0.4 micrometers, or E The gate 14 has a width W of about 0.35 microns. G In some embodiments, according to different product requirements, the width W of the gate extension 20 is E The width W of the gate 14 G The total W T Other suitable sizes may also be included, but are not limited to these.

[0040] exist Figure 1 In the embodiment, the semiconductor structure 10 further includes a metal field plate 24 disposed on the substrate 12 and located between the gate extension 20 and the drain 18. Figure 1 As shown, the semiconductor structure 10 further includes an oxide layer 26 disposed on the substrate 12 and below the metal field plate 24. Figure 1In the embodiment, the metal field plate 24 and the oxide layer 26 thereunder cover a portion of the gate extension 20, and the metal field plate 24 is electrically connected to the gate 14 and the gate extension 20 through the metal layer 28. Since the metal field plate 24 is electrically connected to the gate extension 20, in this embodiment, the gate extension 20 can also be regarded as another portion of the metal field plate. According to some embodiments, the method for manufacturing the gate 14 and the gate extension 20 that are in substantial contact with each other is as follows. For example, first, a patterned polysilicon layer is formed on the substrate 12. Then, an N-type implantation process is performed on the area of ​​the patterned polysilicon layer where the gate 14 is predetermined to be formed, and a P-type implantation process is performed on the area of ​​the patterned polysilicon layer where the gate extension 20 is predetermined to be formed. Alternatively, a P-type implantation process is performed on the area of ​​the patterned polysilicon layer where the gate 14 is predetermined to be formed, and an N-type implantation process is performed on the area of ​​the patterned polysilicon layer where the gate extension 20 is predetermined to be formed. At this point, the manufacturing of the gate 14 and the gate extension 20 that have opposite doping types and are in substantial contact with each other is completed.

[0041] See also Figure 2 According to one embodiment of the present invention, a semiconductor structure 10 is provided. Figure 2 is a schematic cross-sectional view of the semiconductor structure 10 .

[0042] like Figure 2 As shown, the semiconductor structure 10 includes a substrate 12, a gate 14, a source 16, a drain 18, a gate extending portion 20, and a drain drift region 22. The gate 14 is disposed on the substrate 12. The source 16 is disposed in the substrate 12 and is located on one side of the gate 14. The drain 18 is disposed in the substrate 12 and is located on the other side of the gate 14. The gate extending portion 20 is disposed on the substrate 12 and is located between the gate 14 and the drain 18. The drain drift region 22 is located in the substrate 12 and surrounds the drain 18. It is worth noting that the doping type of the gate 14 is opposite to the doping type of the gate extending portion 20, for example, when the doping type of the gate 14 is N-type, the doping type of the gate extending portion 20 is P-type, or, when the doping type of the gate 14 is P-type, the doping type of the gate extending portion 20 is N-type. Since the doping type of the gate 14 is opposite to the doping type of the gate extension 20 , a depletion region (not shown) is naturally formed between the gate 14 and the gate extension 20 .

[0043] In some embodiments, the substrate 12 is a P-type semiconductor substrate or an N-type semiconductor substrate. In some embodiments, when the substrate 12 is a P-type semiconductor substrate, the doping type of the gate 14 is N-type, the doping type of the source 16 is N-type, the doping type of the drain 18 is N-type, and the doping type of the gate extension 20 is P-type. In some embodiments, when the substrate 12 is an N-type semiconductor substrate, the doping type of the gate 14 is P-type, the doping type of the source 16 is P-type, the doping type of the drain 18 is P-type, and the doping type of the gate extension 20 is N-type. In some embodiments, the gate 14 and the gate extension 20 are polysilicon doped with P-type dopants or N-type dopants.

[0044] exist Figure 2 In some embodiments, the gate 14 is in substantial contact with the gate extension 20, for example, the gate 14 is in substantial contact with the gate extension 20 in a lateral direction (ie, the sidewall of the gate 14 is in substantial contact with the sidewall of the gate extension 20). E The width W of the gate 14 G The ratio of W is approximately between 0.3 and 1.2. For example, the width W of the gate extension 20 is E The gate 14 has a width W of about 0.15 microns. G is about 0.5 microns (the ratio of the two is about 0.3), or the width W of the gate extension 20 is about 0.5 microns (the ratio of the two is about 0.3). E The gate 14 has a width W of about 0.25 micrometers. G is about 0.4 microns (the ratio of the two is about 0.625), or the width W of the gate extension 20 is about 0.4 microns (the ratio of the two is about 0.625). E The gate 14 has a width W of about 0.35 microns. G is about 0.3 microns (the ratio of the two is about 1.17). In some embodiments, the width W of the gate extension 20 is E The width W of the gate 14 G The ratio of can also be in other appropriate ranges, and is not limited thereto. In some embodiments, the boundary B between the gate extension 20 and the gate 14 is E Preferably, the gate extension 20 does not exceed the range of the drain drift region 22 (ie, the gate extension 20 only overlaps with the drain drift region 22 in the substrate 12 ). In some embodiments, in the semiconductor structure 10 , the width W of the gate extension 20 is E The width W of the gate 14 G The total W T is a certain value, for example, when the width W of the gate extension 20 is E The width W of the gate 14 G When the ratio of is within the range of 0.3-1.2, the width W of the gate extension 20 is E The width W of the gate 14 GThe total W T The width W of the gate extension 20 is about 0.65 micrometers (for example, E The gate 14 has a width W of about 0.15 microns. G The width W of the gate extension 20 is about 0.5 micrometers, or E The gate 14 has a width W of about 0.25 micrometers. G The width W of the gate extension 20 is about 0.4 micrometers, or E The gate 14 has a width W of about 0.35 microns. G In some embodiments, according to different product requirements, the width W of the gate extension 20 is E The width W of the gate 14 G The total W T Other suitable sizes may also be included, but are not limited to these.

[0045] exist Figure 2 In the embodiment, the semiconductor structure 10 further includes a metal field plate 24 disposed on the substrate 12 and located between the gate extension 20 and the drain 18. Figure 2 As shown, the semiconductor structure 10 further includes an oxide layer 26 disposed on the substrate 12 and below the metal field plate 24. Figure 2 In the embodiment, the metal field plate 24 and the oxide layer 26 thereunder cover a portion of the gate extension 20, and the metal field plate 24 is electrically connected to the source 16 through the metal layer 30. According to some embodiments, the method for manufacturing the gate 14 and the gate extension 20 that are substantially in contact with each other is as follows, for example, first, a patterned polysilicon layer is formed on the substrate 12, and then, an N-type implantation process is performed on a region of the patterned polysilicon layer where the gate 14 is to be formed, and a P-type implantation process is performed on a region of the patterned polysilicon layer where the gate extension 20 is to be formed, or, a P-type implantation process is performed on a region of the patterned polysilicon layer where the gate 14 is to be formed, and an N-type implantation process is performed on a region of the patterned polysilicon layer where the gate extension 20 is to be formed, so that the manufacturing of the gate 14 and the gate extension 20 that have opposite doping types and are substantially in contact with each other is completed.

[0046] See also Figure 3 According to one embodiment of the present invention, a semiconductor structure 10 is provided. Figure 3 is a schematic cross-sectional view of the semiconductor structure 10 .

[0047] like Figure 3As shown, the semiconductor structure 10 includes a substrate 12, a gate 14, a source 16, a drain 18, a gate extending portion 20, and a drain drift region 22. The gate 14 is disposed on the substrate 12. The source 16 is disposed in the substrate 12 and is located on one side of the gate 14. The drain 18 is disposed in the substrate 12 and is located on the other side of the gate 14. The gate extending portion 20 is disposed on the substrate 12 and is located between the gate 14 and the drain 18. The drain drift region 22 is located in the substrate 12 and surrounds the drain 18. It is worth noting that the doping type of the gate 14 is opposite to the doping type of the gate extending portion 20, for example, when the doping type of the gate 14 is N-type, the doping type of the gate extending portion 20 is P-type, or, when the doping type of the gate 14 is P-type, the doping type of the gate extending portion 20 is N-type. Since the doping type of the gate 14 is opposite to the doping type of the gate extension 20 , a depletion region (not shown) is naturally formed between the gate 14 and the gate extension 20 .

[0048] In some embodiments, the substrate 12 is a P-type semiconductor substrate or an N-type semiconductor substrate. In some embodiments, when the substrate 12 is a P-type semiconductor substrate, the doping type of the gate 14 is N-type, the doping type of the source 16 is N-type, the doping type of the drain 18 is N-type, and the doping type of the gate extension 20 is P-type. In some embodiments, when the substrate 12 is an N-type semiconductor substrate, the doping type of the gate 14 is P-type, the doping type of the source 16 is P-type, the doping type of the drain 18 is P-type, and the doping type of the gate extension 20 is N-type. In some embodiments, the gate 14 and the gate extension 20 are polysilicon doped with P-type dopants or N-type dopants.

[0049] exist Figure 3 In the embodiment, the gate 14 is in substantial contact with the gate extension 20, for example, the gate 14 is in substantial contact with the gate extension 20 in a lateral direction (i.e., the sidewall of the gate 14 is in substantial contact with the sidewall of the gate extension 20). In the present embodiment, the width W of the gate extension 20 (P-type doping) is E The width W of the gate 14 (N-type doping) G The ratio of is about 0.3. At this time, the width W of the gate extension 20 is E The gate 14 has a width W of about 0.15 microns. G In some embodiments, the width W of the gate extension 20 is about 0.5 micrometers. E The width W of the gate 14 G The ratio of can also be in other appropriate ranges, and is not limited thereto. In some embodiments, the boundary B between the gate extension 20 and the gate 14 is EPreferably, the gate extension 20 does not exceed the range of the drain drift region 22 (ie, the gate extension 20 only overlaps with the drain drift region 22 in the substrate 12 ). In some embodiments, in the semiconductor structure 10 , the width W of the gate extension 20 is E The width W of the gate 14 G The total W T is a certain value. In this embodiment, when the width W of the gate extension 20 is E The width W of the gate 14 G When the ratio is 0.3, the width W of the gate extension 20 E The width W of the gate 14 G The total W T is about 0.65 micrometers (ie, the width W of the gate extension 20 E The gate 14 has a width W of about 0.15 microns. G In some embodiments, according to different product requirements, the width W of the gate extension 20 is E The width W of the gate 14 G The total W T Other suitable dimensions may also be included, but are not limited thereto. In the present embodiment, the gate extension 20 may be considered as a metal field plate. If the semiconductor structure of the present embodiment is used to perform device operation, various operating conditions (e.g., threshold voltage (Vth), linear region drain current (Idlin), saturation region drain current (Idsat), static breakdown voltage (BVoff)) and drain-to-gate capacitance (Cgd) are listed in Table 1.

[0050] According to some embodiments, the method for manufacturing the gate 14 and the gate extension 20 that are in substantial contact with each other is as follows. For example, first, a patterned polysilicon layer is formed on the substrate 12. Then, an N-type implantation process is performed on the area (approximately 0.5 microns wide) in the patterned polysilicon layer where the gate 14 is predetermined to be formed, and a P-type implantation process is performed on the area (approximately 0.15 microns wide) in the patterned polysilicon layer where the gate extension 20 is predetermined to be formed (as in the present embodiment). Alternatively, a P-type implantation process is performed on the area (approximately 0.5 microns wide) in the patterned polysilicon layer where the gate 14 is predetermined to be formed, and an N-type implantation process is performed on the area (approximately 0.15 microns wide) in the patterned polysilicon layer where the gate extension 20 is predetermined to be formed. At this point, the manufacturing of the gate 14 and the gate extension 20 that have opposite doping types and are in substantial contact with each other is completed.

[0051] See also Figure 4 According to one embodiment of the present invention, a semiconductor structure 10 is provided. Figure 4 is a schematic cross-sectional view of the semiconductor structure 10 .

[0052] like Figure 4 As shown, the semiconductor structure 10 includes a substrate 12, a gate 14, a source 16, a drain 18, a gate extending portion 20, and a drain drift region 22. The gate 14 is disposed on the substrate 12. The source 16 is disposed in the substrate 12 and is located on one side of the gate 14. The drain 18 is disposed in the substrate 12 and is located on the other side of the gate 14. The gate extending portion 20 is disposed on the substrate 12 and is located between the gate 14 and the drain 18. The drain drift region 22 is located in the substrate 12 and surrounds the drain 18. It is worth noting that the doping type of the gate 14 is opposite to the doping type of the gate extending portion 20, for example, when the doping type of the gate 14 is N-type, the doping type of the gate extending portion 20 is P-type, or, when the doping type of the gate 14 is P-type, the doping type of the gate extending portion 20 is N-type. Since the doping type of the gate 14 is opposite to the doping type of the gate extension 20 , a depletion region (not shown) is naturally formed between the gate 14 and the gate extension 20 .

[0053] In some embodiments, the substrate 12 is a P-type semiconductor substrate or an N-type semiconductor substrate. In some embodiments, when the substrate 12 is a P-type semiconductor substrate, the doping type of the gate 14 is N-type, the doping type of the source 16 is N-type, the doping type of the drain 18 is N-type, and the doping type of the gate extension 20 is P-type. In some embodiments, when the substrate 12 is an N-type semiconductor substrate, the doping type of the gate 14 is P-type, the doping type of the source 16 is P-type, the doping type of the drain 18 is P-type, and the doping type of the gate extension 20 is N-type. In some embodiments, the gate 14 and the gate extension 20 are polysilicon doped with P-type dopants or N-type dopants.

[0054] exist Figure 4 In the embodiment, the gate 14 is in substantial contact with the gate extension 20, for example, the gate 14 is in substantial contact with the gate extension 20 in a lateral direction (i.e., the sidewall of the gate 14 is in substantial contact with the sidewall of the gate extension 20). In the present embodiment, the width W of the gate extension 20 (P-type doping) is E The width W of the gate 14 (N-type doping) G The ratio of is about 0.625. At this time, the width W of the gate extension 20 is E The gate 14 has a width W of about 0.25 micrometers. G In some embodiments, the width W of the gate extension 20 is about 0.4 microns. E The width W of the gate 14G The ratio of can also be in other appropriate ranges, and is not limited thereto. In some embodiments, the boundary B between the gate extension 20 and the gate 14 is E Preferably, the gate extension 20 does not exceed the range of the drain drift region 22 (ie, the gate extension 20 only overlaps with the drain drift region 22 in the substrate 12 ). In some embodiments, in the semiconductor structure 10 , the width W of the gate extension 20 is E The width W of the gate 14 G The total W T is a certain value. In this embodiment, when the width W of the gate extension 20 is E The width W of the gate 14 G When the ratio is 0.625, the width W of the gate extension 20 E The width W of the gate 14 G The total W T is about 0.65 micrometers (ie, the width W of the gate extension 20 E The gate 14 has a width W of about 0.25 micrometers. G In some embodiments, according to different product requirements, the width W of the gate extension 20 is E The width W of the gate 14 G The total W T Other suitable dimensions may also be included, but are not limited thereto. In the present embodiment, the gate extension 20 may be considered as a metal field plate. If the semiconductor structure of the present embodiment is used to perform device operation, various operating conditions (e.g., threshold voltage (Vth), linear region drain current (Idlin), saturation region drain current (Idsat), static breakdown voltage (BVoff)) and drain-to-gate capacitance (Cgd) are listed in Table 1.

[0055] According to some embodiments, the method for manufacturing the gate 14 and the gate extension 20 that are in substantial contact with each other is as follows. For example, first, a patterned polysilicon layer is formed on the substrate 12. Then, an N-type implantation process is performed on the area (approximately 0.4 microns wide) in the patterned polysilicon layer where the gate 14 is predetermined to be formed, and a P-type implantation process is performed on the area (approximately 0.25 microns wide) in the patterned polysilicon layer where the gate extension 20 is predetermined to be formed (as in the present embodiment). Alternatively, a P-type implantation process is performed on the area (approximately 0.4 microns wide) in the patterned polysilicon layer where the gate 14 is predetermined to be formed, and an N-type implantation process is performed on the area (approximately 0.25 microns wide) in the patterned polysilicon layer where the gate extension 20 is predetermined to be formed. At this point, the manufacturing of the gate 14 and the gate extension 20 that have opposite doping types and are in substantial contact with each other is completed.

[0056] See also Figure 5 According to one embodiment of the present invention, a semiconductor structure 10 is provided. Figure 5 is a schematic cross-sectional view of the semiconductor structure 10 .

[0057] like Figure 5 As shown, the semiconductor structure 10 includes a substrate 12, a gate 14, a source 16, a drain 18, a gate extending portion 20, and a drain drift region 22. The gate 14 is disposed on the substrate 12. The source 16 is disposed in the substrate 12 and is located on one side of the gate 14. The drain 18 is disposed in the substrate 12 and is located on the other side of the gate 14. The gate extending portion 20 is disposed on the substrate 12 and is located between the gate 14 and the drain 18. The drain drift region 22 is located in the substrate 12 and surrounds the drain 18. It is worth noting that the doping type of the gate 14 is opposite to the doping type of the gate extending portion 20, for example, when the doping type of the gate 14 is N-type, the doping type of the gate extending portion 20 is P-type, or, when the doping type of the gate 14 is P-type, the doping type of the gate extending portion 20 is N-type. Since the doping type of the gate 14 is opposite to the doping type of the gate extension 20 , a depletion region (not shown) is naturally formed between the gate 14 and the gate extension 20 .

[0058] In some embodiments, the substrate 12 is a P-type semiconductor substrate or an N-type semiconductor substrate. In some embodiments, when the substrate 12 is a P-type semiconductor substrate, the doping type of the gate 14 is N-type, the doping type of the source 16 is N-type, the doping type of the drain 18 is N-type, and the doping type of the gate extension 20 is P-type. In some embodiments, when the substrate 12 is an N-type semiconductor substrate, the doping type of the gate 14 is P-type, the doping type of the source 16 is P-type, the doping type of the drain 18 is P-type, and the doping type of the gate extension 20 is N-type. In some embodiments, the gate 14 and the gate extension 20 are polysilicon doped with P-type dopants or N-type dopants.

[0059] exist Figure 5 In the embodiment, the gate 14 is in substantial contact with the gate extension 20, for example, the gate 14 is in substantial contact with the gate extension 20 in a lateral direction (i.e., the sidewall of the gate 14 is in substantial contact with the sidewall of the gate extension 20). In the present embodiment, the width W of the gate extension 20 (P-type doping) is E The width W of the gate 14 (N-type doping) G The ratio of is about 1.17. At this time, the width W of the gate extension 20 is E The gate 14 has a width W of about 0.35 microns.G In some embodiments, the width W of the gate extension 20 is about 0.3 microns. E The width W of the gate 14 G The ratio of can also be in other appropriate ranges, and is not limited thereto. In some embodiments, the boundary B between the gate extension 20 and the gate 14 is E Preferably, the gate extension 20 does not exceed the range of the drain drift region 22 (ie, the gate extension 20 only overlaps with the drain drift region 22 in the substrate 12 ). In some embodiments, in the semiconductor structure 10 , the width W of the gate extension 20 is E The width W of the gate 14 G The total W T is a certain value. In this embodiment, when the width W of the gate extension 20 is E The width W of the gate 14 G When the ratio is 1.17, the width W of the gate extension 20 E The width W of the gate 14 G The total W T is about 0.65 micrometers (ie, the width W of the gate extension 20 E The gate 14 has a width W of about 0.35 microns. G In some embodiments, according to different product requirements, the width W of the gate extension 20 is E The width W of the gate 14 G The total W T Other suitable dimensions may also be included, but are not limited thereto. In the present embodiment, the gate extension 20 may be considered as a metal field plate. If the semiconductor structure of the present embodiment is used to perform device operation, various operating conditions (e.g., threshold voltage (Vth), linear region drain current (Idlin), saturation region drain current (Idsat), static breakdown voltage (BVoff)) and drain-to-gate capacitance (Cgd) are listed in Table 1.

[0060] According to some embodiments, the method for manufacturing the gate 14 and the gate extension 20 that are in substantial contact with each other is as follows. For example, first, a patterned polysilicon layer is formed on the substrate 12. Then, an N-type implantation process is performed on the area (approximately 0.3 microns wide) in the patterned polysilicon layer where the gate 14 is predetermined to be formed, and a P-type implantation process is performed on the area (approximately 0.35 microns wide) in the patterned polysilicon layer where the gate extension 20 is predetermined to be formed (as in the present embodiment). Alternatively, a P-type implantation process is performed on the area (approximately 0.3 microns wide) in the patterned polysilicon layer where the gate 14 is predetermined to be formed, and an N-type implantation process is performed on the area (approximately 0.35 microns wide) in the patterned polysilicon layer where the gate extension 20 is predetermined to be formed. At this point, the manufacturing of the gate 14 and the gate extension 20 that have opposite doping types and are in substantial contact with each other is completed.

[0061] Table 1

[0062]

[0063] As can be seen from Table 1, under the same operating conditions, as the ratio of the width of the gate extension to the width of the gate gradually increases, the drain-to-gate capacitance is significantly reduced due to the effect of capacitor series connection. For example, when Vds=0V, the ratio of the width of the gate extension to the width of the gate is 0.3, the drain-to-gate capacitance of the semiconductor structure of the present invention is reduced by about 50.2% compared with the drain-to-gate capacitance of the semiconductor structure in which the polysilicon is not doped with P-type. When the ratio of the width of the gate extension to the width of the gate is 0.625, the drain-to-gate capacitance of the semiconductor structure of the present invention is reduced by about 78.2% compared with the drain-to-gate capacitance of the semiconductor structure in which the polysilicon is not doped with P-type. When the ratio of the width of the gate extension to the width of the gate is 1.17, the drain-to-gate capacitance of the semiconductor structure of the present invention is reduced by about 1.2%. The drain-gate capacitance of the semiconductor structure is reduced by about 81% compared with the drain-gate capacitance of the semiconductor structure in which the polysilicon is not doped with P-type. When Vds=1.8V and the ratio of the width of the gate extension to the width of the gate is 0.3, the drain-gate capacitance of the semiconductor structure of the present invention is reduced by about 12.5% ​​compared with the drain-gate capacitance of the semiconductor structure in which the polysilicon is not doped with P-type. When the ratio of the width of the gate extension to the width of the gate is 0.625, the drain-gate capacitance of the semiconductor structure of the present invention is reduced by about 15.4% compared with the drain-gate capacitance of the semiconductor structure in which the polysilicon is not doped with P-type. When the ratio of the width of the gate extension to the width of the gate is 1.17, the drain-gate capacitance of the semiconductor structure of the present invention is reduced by about 16.3% compared with the drain-gate capacitance of the semiconductor structure in which the polysilicon is not doped with P-type.

[0064] See also Figure 6According to one embodiment of the present invention, a semiconductor structure 10 is provided. Figure 6 is a schematic cross-sectional view of the semiconductor structure 10 .

[0065] like Figure 6 As shown, the semiconductor structure 10 includes a substrate 12, a gate 14, a source 16, a drain 18, a gate extending portion 20, and a drain drift region 22. The gate 14 is disposed on the substrate 12. The source 16 is disposed in the substrate 12 and is located on one side of the gate 14. The drain 18 is disposed in the substrate 12 and is located on the other side of the gate 14. The gate extending portion 20 is disposed on the substrate 12 and is located between the gate 14 and the drain 18. The drain drift region 22 is located in the substrate 12 and surrounds the drain 18. It is worth noting that the doping type of the gate 14 is opposite to the doping type of the gate extending portion 20, for example, when the doping type of the gate 14 is N-type, the doping type of the gate extending portion 20 is P-type, or, when the doping type of the gate 14 is P-type, the doping type of the gate extending portion 20 is N-type.

[0066] In some embodiments, the substrate 12 is a P-type semiconductor substrate or an N-type semiconductor substrate. In some embodiments, when the substrate 12 is a P-type semiconductor substrate, the doping type of the gate 14 is N-type, the doping type of the source 16 is N-type, the doping type of the drain 18 is N-type, and the doping type of the gate extension 20 is P-type. In some embodiments, when the substrate 12 is an N-type semiconductor substrate, the doping type of the gate 14 is P-type, the doping type of the source 16 is P-type, the doping type of the drain 18 is P-type, and the doping type of the gate extension 20 is N-type. In some embodiments, the gate 14 and the gate extension 20 are polysilicon doped with P-type dopants or N-type dopants.

[0067] exist Figure 6 In the embodiment, the gate 14 is substantially separated from the gate extension 20 , for example, the gate 14 is substantially separated from the gate extension 20 in a laterally direction (ie, the sidewall of the gate 14 is substantially separated from the sidewall of the gate extension 20 and does not contact).

[0068] exist Figure 6In the embodiment, the gate extension 20 is electrically connected to the gate 14 through the metal layer 32. In the present embodiment, the gate extension 20 can be regarded as a metal field plate. According to some embodiments, the method for manufacturing the gate 14 and the gate extension 20 which are substantially separated from each other is as follows. For example, first, a patterned polysilicon layer including two separation parts is formed on the substrate 12. Then, an N-type implantation process is performed on the separation part of the patterned polysilicon layer where the gate 14 is to be formed, and a P-type implantation process is performed on the separation part of the patterned polysilicon layer where the gate extension 20 is to be formed. Alternatively, a P-type implantation process is performed on the separation part of the patterned polysilicon layer where the gate 14 is to be formed, and an N-type implantation process is performed on the separation part of the patterned polysilicon layer where the gate extension 20 is to be formed. Thus, the gate 14 and the gate extension 20 which have opposite doping types and are substantially separated from each other are manufactured.

[0069] See also Figure 7 According to one embodiment of the present invention, a semiconductor structure 10 is provided. Figure 7 is a schematic cross-sectional view of the semiconductor structure 10 .

[0070] like Figure 7 As shown, the semiconductor structure 10 includes a substrate 12, a gate 14, a source 16, a drain 18, a gate extending portion 20, and a drain drift region 22. The gate 14 is disposed on the substrate 12. The source 16 is disposed in the substrate 12 and is located on one side of the gate 14. The drain 18 is disposed in the substrate 12 and is located on the other side of the gate 14. The gate extending portion 20 is disposed on the substrate 12 and is located between the gate 14 and the drain 18. The drain drift region 22 is located in the substrate 12 and surrounds the drain 18. It is worth noting that the doping type of the gate 14 is opposite to the doping type of the gate extending portion 20, for example, when the doping type of the gate 14 is N-type, the doping type of the gate extending portion 20 is P-type, or, when the doping type of the gate 14 is P-type, the doping type of the gate extending portion 20 is N-type.

[0071] In some embodiments, the substrate 12 is a P-type semiconductor substrate or an N-type semiconductor substrate. In some embodiments, when the substrate 12 is a P-type semiconductor substrate, the doping type of the gate 14 is N-type, the doping type of the source 16 is N-type, the doping type of the drain 18 is N-type, and the doping type of the gate extension 20 is P-type. In some embodiments, when the substrate 12 is an N-type semiconductor substrate, the doping type of the gate 14 is P-type, the doping type of the source 16 is P-type, the doping type of the drain 18 is P-type, and the doping type of the gate extension 20 is N-type. In some embodiments, the gate 14 and the gate extension 20 are polysilicon doped with P-type dopants or N-type dopants.

[0072] exist Figure 7 In the embodiment, the gate 14 is substantially separated from the gate extension 20 , for example, the gate 14 is substantially separated from the gate extension 20 in a laterally direction (ie, the sidewall of the gate 14 is substantially separated from the sidewall of the gate extension 20 and does not contact).

[0073] exist Figure 7 In the embodiment, the gate extension 20 is electrically connected to the source 16 through the metal layer 34. In the present embodiment, the gate extension 20 can be regarded as a metal field plate. According to some embodiments, the method for manufacturing the gate 14 and the gate extension 20 which are substantially separated from each other is as follows. For example, first, a patterned polysilicon layer including two separation parts is formed on the substrate 12. Then, an N-type implantation process is performed on the separation part of the patterned polysilicon layer where the gate 14 is to be formed, and a P-type implantation process is performed on the separation part of the patterned polysilicon layer where the gate extension 20 is to be formed. Alternatively, a P-type implantation process is performed on the separation part of the patterned polysilicon layer where the gate 14 is to be formed, and an N-type implantation process is performed on the separation part of the patterned polysilicon layer where the gate extension 20 is to be formed. Thus, the gate 14 and the gate extension 20 which have opposite doping types and are substantially separated from each other are manufactured.

[0074] The present invention forms two regions of opposite doping types in the polysilicon gate of the MOS transistor through an implantation process (for example, the region of the gate adjacent to the drain (defined as the gate extension in the present invention) is P-type doped, and the region of the gate away from the drain (defined as the gate in the present invention) is N-type doped). Due to the effect of capacitor series connection, the drain-to-gate capacitance is improved, and as the ratio of the width of the gate extension to the width of the gate gradually increases, the proportion of the drain-to-gate capacitance decreases more significantly. At this time, the gate extension also has the function of a field plate, which can effectively disperse the electric field strength of the drain region (drift region) to avoid damage to the device in a high-voltage operating environment. In addition, the above two regions of opposite doping types can also be made into two separated structures. On the one hand, the gate extension can have the function of a field plate, and on the other hand, the overall effect of reducing the drain-to-gate capacitance can be achieved. The present invention has low cost and can be simply manufactured without changing the existing MOS process rules. Due to the decrease of drain-gate capacitance, the undesired current flow caused by the coupling effect of the transistor is avoided. The special semiconductor structure design of the present invention can effectively reduce the power loss of the switching device, greatly increase the switching frequency and achieve high-efficiency power conversion.

[0075] The features of the above embodiments are helpful for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and change other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and can be changed, replaced, or modified without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure, characterized in that: include: a substrate; a gate disposed on the substrate; A source electrode is disposed in the substrate and is located on one side of the gate electrode; a drain electrode disposed in the substrate and located on the other side of the gate electrode; and a gate extension disposed on the substrate and between the gate and the drain, wherein the gate has a doping type opposite to that of the gate extension, and the gate is in substantial contact with the gate extension; and A metal field plate is disposed on the substrate and is located between the gate extension and the drain, wherein the gate extension has a first width and the gate has a second width, and when the ratio of the first width to the second width increases, the drain-gate capacitance value of the semiconductor structure decreases.

2. The semiconductor structure according to claim 1, wherein: The substrate is a P-type or N-type substrate.

3. The semiconductor structure according to claim 2, wherein: When the substrate is a P-type substrate, the gate is doped with an N-type, the source is doped with an N-type, the drain is doped with an N-type, and the gate extension is doped with a P-type.

4. The semiconductor structure according to claim 2, characterized in that When the substrate is an N-type substrate, the doping type of the gate is P-type, the doping type of the source is P-type, the doping type of the drain is P-type, and the doping type of the gate extension is N-type.

5. The semiconductor structure according to claim 1, wherein: It also includes an oxide layer, which is disposed on the substrate and below the metal field plate.

6. The semiconductor structure according to claim 1, wherein: The metal field plate is electrically connected to the gate and the gate extension.

7. The semiconductor structure according to claim 1, wherein: The metal field plate is electrically connected to the source.

8. The semiconductor structure according to claim 1, wherein: The ratio of the width of the gate extension to the width of the gate is between 0.3 and 1.

2.

9. The semiconductor structure according to claim 8, characterized in that The sum of the width of the gate extension portion and the width of the gate is a constant.

10. The semiconductor structure according to claim 1, wherein: The gate and the gate extension are made of polysilicon.

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