A method for verifying chip information

Abstract

Provided is a method for chip information verification, providing an integrated circuit wafer, which includes multiple chips under test; obtaining identification chip information of the chips under test; comparing the background chip information and identification chip information of the same chip under test to confirm whether the two match; if they do not match, finding the cause of the mismatch, correcting the cause of the mismatch after finding the cause, and returning to obtain the identification chip information of each chip under test; if they match, recording the test data and test results of the chip under test. The method of the present invention uses chip information real-time comparison and verification without affecting the test efficiency, and finds chip information errors and finds out the causes of the errors at the first time, avoiding retesting caused by late discovery or unqualified chips flowing into the next link, avoiding irreparable losses; under the premise that the test time remains unchanged, real-time verification records whether the chip information of the chip under test is correct, and improves the traceability of the chip information of the chip under test.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor testing, and in particular to a chip information verification method. Background Art

[0002] During the testing process of integrated circuit wafers, the test data and test results of all the tested chips are usually saved, and the chip information of each tested chip on each integrated circuit wafer needs to correspond to its specific test data and test results one by one. Therefore, during the test, the batch number, chip number and position coordinates of the tested chip recognized by the optical character recognition (OCR) are often read back from the integrated circuit probe station (Prober) through the general-purpose interface bus (GPIB), and the information is recorded, and then the detailed test data and test results corresponding to these tested chips are saved.

[0003] However, OCR recognition may be abnormal, resulting in an incorrect batch number of the chip under test; or GPIB communication may be abnormal, resulting in an incorrect position coordinate of the chip under test, which will result in incorrect information recorded by the chip under test, making it impossible for these information errors to correspond one-to-one with the actual test data, and also making it impossible for these information errors to correspond one-to-one with the actual test results. If these problems are not discovered in time, the chips under test with unqualified test results will flow into the next link, making these chips under test impossible to trace. Summary of the invention

[0004] The purpose of the present invention is to provide a chip information verification method to solve the problem in the prior art that a chip under test with incorrect information recording flows into the next link, or that information errors are discovered late, resulting in retesting.

[0005] In order to solve the above problem, the present invention provides a chip information verification method, comprising the following steps:

[0006] Step S1: providing an integrated circuit wafer, wherein the integrated circuit wafer comprises a plurality of chips under test, the chips under test undergo a plurality of test items, and each of the chips under test comprises background chip information;

[0007] Step S2: Obtaining identification chip information of each chip under test;

[0008] Step S3: comparing the background chip information and the identification chip information of the same chip under test to confirm whether the background chip information and the identification chip information of the chip under test match;

[0009] Step S4: If the background chip information and identification chip information of the chip under test do not match, find the cause of the mismatch, correct the cause of the mismatch after finding the cause, and return to step S2; or, if the background chip information and identification chip information of the chip under test match, record the test data and test results of the chip under test.

[0010] Optionally, the background chip information of each chip under test is binary data.

[0011] Furthermore, the batch number, chip number, location coordinates, wafer fabrication plant code, and test plant code of each of the tested chips are first converted into ASCII code and then translated into binary to obtain the background chip information.

[0012] Optionally, step S2 includes:

[0013] Read back the identification chip information of each chip under test by optical character recognition from the integrated circuit probe station through the universal interface bus;

[0014] The identification chip information is recorded, and the test results and test data of each of the tested chips are correspondingly saved.

[0015] Furthermore, the identification chip information includes the batch number, chip number and location coordinates, wafer foundry code, test factory code and other information of the chip under test.

[0016] Furthermore, the test data specifically includes test data in formats such as rawdata, stdf, and txt.

[0017] Furthermore, the test data includes at least one screening identifier.

[0018] Furthermore, the test data includes HardBin and SoftBin.

[0019] Optionally, when the background chip information and the identification chip information of the chip under test do not match, the chip information of the chip under test in the integrated circuit wafer is recorded incorrectly.

[0020] Furthermore, when the background chip information and the identification chip information of the chip under test do not match, the batch number of the chip under test is wrong; or, the communication of the universal interface bus interface is wrong; or, the position coordinate setting of the chip under test is wrong.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] The present invention provides a method for chip information verification, comprising the following steps: Step S1: providing an integrated circuit wafer, wherein the integrated circuit wafer comprises a plurality of chips to be tested, the chips to be tested undergo a plurality of test items, and each of the chips to be tested comprises background chip information; Step S2: obtaining identification chip information of each of the chips to be tested; Step S3: comparing the background chip information and identification chip information of the same chip to be tested to confirm whether the background chip information and identification chip information of the chip to be tested match; Step S4: if the background chip information and identification chip information of the chip to be tested do not match, finding the cause of the mismatch, correcting the cause of the mismatch after finding the cause, and returning to Step S2; or, if the background chip information and identification chip information of the chip to be tested match, recording the test data and test results of the chip to be tested. The method of the present invention utilizes chip information for real-time comparison and verification without affecting the test efficiency, and discovers chip information errors and finds out the causes of the errors at the first time, thereby avoiding the need for retesting due to late discovery of chip information errors in the tested chip or directly flowing into the next link with unqualified test results, thereby avoiding irreparable losses; and under the premise of unchanged test time, real-time verification records whether the chip information of the tested chip is correct, thereby improving the traceability of the chip information of the tested chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1a A schematic diagram of a survey map with incorrect location coordinates;

[0024] Figure 1b A schematic diagram of a correct survey map for a location coordinate setting;

[0025] Figure 2 A schematic flow chart of a chip information verification method according to an embodiment of the present invention;

[0026] Figure 3 A chip test map of an integrated circuit wafer according to an embodiment of the present invention.

[0027] Description of reference numerals:

[0028] 1-Integrated circuit wafer; 10-Chip under test. DETAILED DESCRIPTION

[0029] As described in the background technology, if the chip under test is tested in parallel through multiple stations, then before the test starts, it is necessary to arrange the positions on the probe card according to the requirements and set the position coordinates. For example, the test setting schemes for the position arrangement of 16 chips under test include 2*8 arrangement, 8*2 arrangement, 4*4 arrangement, etc. When setting the position coordinates, a setting error occurs, for example, the 2*8 arrangement is set to the 8*2 arrangement, and the actual result of the chip under test cannot correspond to the test result of the chip under test one by one. Figure 1a A schematic diagram of a survey map with incorrect location coordinate settings. Figure 1b Schematic diagram of the correct survey map for a location coordinate setting. Figure 1a and Figure 1b As shown, the correct map has a relatively uniform circle of unqualified chips on the outermost circle (i.e., a circle of black chips on the edge of the integrated circuit wafer), while the map with incorrect position coordinate settings has shifted as a whole, resulting in an additional circle of unqualified chips on the left edge (i.e., an additional circle of black chips on the left edge of the integrated circuit wafer). This map error due to incorrect position coordinate settings is generally not easy to detect. Only experienced engineers will find it when checking the map after the test is completed. After the discovery, the only solution is to retest the entire wafer. Those that cannot be discovered will flow into the next link, making these chips impossible to trace.

[0030] However, in the prior art, it is impossible to completely avoid the various problems caused by information errors in the tested chip. It may cause a waste of testing time due to retesting after discovery. It may also directly cause the tested chip with unqualified test results to flow into the next link due to misplaced information records, resulting in irreparable errors.

[0031] The core idea of ​​the present invention is to provide a chip information verification method, which can verify in real time whether the chip information of the tested chip is correct under the premise that the test time of the integrated circuit wafer remains unchanged, thereby improving the traceability of the chip information.

[0032] A chip information verification method of the present invention will be described in further detail below. The present invention will be described in more detail below with reference to the accompanying drawings, in which preferred embodiments of the present invention are shown. It should be understood that those skilled in the art can modify the present invention described herein and still achieve the beneficial effects of the present invention. Therefore, the following description should be understood as being widely known to those skilled in the art and not as a limitation of the present invention.

[0033] For the sake of clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not described in detail because they would clutter the invention with unnecessary detail. It should be recognized that in the development of any actual embodiment, a large number of implementation details must be made to achieve the developer's specific goals, such as changing from one embodiment to another according to the limitations of the relevant system or the relevant business. In addition, it should be recognized that such development work may be complex and time-consuming, but it is just a routine task for those skilled in the art.

[0034] In order to make the purpose and features of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are further described below in conjunction with the accompanying drawings. It should be noted that the accompanying drawings are all in a very simplified form and use inaccurate ratios, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0035] Figure 2 FIG. 1 is a flow chart of a chip information verification method of this embodiment. Figure 2 As shown, this embodiment provides a chip information verification method, which is a chip information verification method for an integrated circuit wafer during a test process.

[0036] The method comprises the following steps:

[0037] Step S1: providing an integrated circuit wafer, wherein the integrated circuit wafer comprises a plurality of chips under test, the chips under test undergo a plurality of test items, and each of the chips under test comprises background chip information;

[0038] Step S2: Obtaining identification chip information of each chip under test;

[0039] Step S3: comparing the background chip information and the identification chip information of the same chip under test to confirm whether the background chip information and the identification chip information of the chip under test match;

[0040] Step S4: if the background chip information of the chip under test does not match the identification chip information, find the cause of the mismatch, correct the cause of the mismatch after finding the cause, and return to step S2; or,

[0041] If the background chip information and the identification chip information of the chip under test match, the test data and test results of the chip under test are recorded.

[0042] Combine the following Figure 2-3 A chip information verification method provided by an embodiment of the present invention is introduced in detail.

[0043] First, step S1 is performed to provide an integrated circuit wafer 1, wherein the integrated circuit wafer 1 includes a plurality of chips under test 10, the chips under test 10 undergo a plurality of test items, and each of the chips under test 10 includes background chip information.

[0044] The batch number, chip number, location coordinates, wafer factory code, test factory code and other information of each chip under test 10 are first converted into ASCII code, then translated into binary data, and the binary data is used to generate the background chip information of each chip under test 10, thereby generating a background chip information database of all chips under test 10 in the integrated circuit wafer 1. The multiple test items are, for example, all test items of the chip under test 10.

[0045] Figure 3 This is a chip test map of the integrated circuit wafer of this embodiment. Figure 3 As shown, in this embodiment, the integrated circuit wafer 1 has a total of 615 chips under test 10, each of the chips under test 10 may include information such as batch number, chip number, position coordinates, wafer factory code, and test factory code. As an example, the batch number of each chip under test 10 is 7ECA23; the chip number is 1#~25#; the position coordinates include an X-coordinate position and a Y-coordinate position, the coordinate range of the X-coordinate position is 1~28, and the coordinate range of the Y-coordinate position is 1~25. The chip under test 10 is tested by a double-station test, the two stations are arranged up and down, and the coordinates of the first chip under test 10 are (X=9, Y=2). According to the optimal walking method designed for the chip under test 10 during the test, the test coordinates of the chip under test 10 are calculated to be (9, 2), (10, 2), (11, 1), (11, 2), (12, 1), (12, 2) ... (17, 1), (17, 2), (18, 2), (19, 2), (22, 4), (21, 3), (21, 4), (20, 3), (20, 4) ... The wafer plant code is, for example, SC, and the test plant code is, for example, TC. Based on the above information, a program is written to convert the batch number, chip number, numbers, letters and symbols in the position coordinates into ASCII codes, and then translate them into binary data to generate background chip information for each chip under test 10, thereby generating a background chip information database for all chips under test 10 in the integrated circuit wafer 1, wherein the background chip information database includes the chip information of each chip under test 10 in the integrated circuit wafer 1.

[0046] As shown in the following table, each row of binary data represents the background chip information of a chip under test, and the first 48 bits of binary data in each row represent the batch number of the chip under test, the 48th to 56th bits of binary data represent the chip number of the chip under test, the 57th to 72nd bits of binary data represent the position coordinates of the chip under test, the 73rd to 88th bits of binary data represent the wafer factory code of the chip under test, and the 89th to 104th bits of binary data represent the test factory code of the chip under test. This table is the background chip information database of all chips under test in the integrated circuit wafer 1 of this embodiment.

[0047]

[0048] Then, step S2 is performed to obtain the identification chip information of each chip under test.

[0049] Specifically,

[0050] First, the optical character recognition (OCR) identification chip information of each chip under test is read back from an integrated circuit probe station (Prober) through a general-purpose interface bus (GPIB).

[0051] The chip identification information includes the batch number, chip number, location coordinates, wafer foundry code, test factory code and other information of the chip under test.

[0052] Next, record the identification chip information, and save the test results and test data of each chip under test accordingly. The test data specifically includes test data in the formats of rawdata, stdf, txt, etc. The test data includes at least one screening identifier, such as HardBin and SoftBin. The HardBin is used to identify the position where the chip under test falls into the corresponding test item. The SoftBin also identifies the screening of the chip under test, which is a further subdivision after the HardBin classification, and it is only stored in the table as a structure for customers to view. The result includes the relevant description of the test item. The test results include pass and fail.

[0053] like Figure 3 As shown, the black tested chips 10 in the integrated circuit wafer are chips that fail the test items, and the white tested chips 10 not shown in the integrated circuit wafer are chips that pass the test items.

[0054] Then, step S3 is performed to compare the background chip information and the identification chip information of the same chip under test 10 to confirm whether the background chip information and the identification chip information of the chip under test match. Specifically, the identification chip information of each chip under test 10 is compared with the corresponding background chip information to confirm whether the background chip information and the identification chip information of the chip under test match.

[0055] Then execute step S4: if the background chip information and the identification chip information of the chip under test do not match, find the cause of the mismatch, correct the cause of the mismatch after finding the cause, and return to step S2; or, if the background chip information and the identification chip information match, record the test data and test results of the chip under test.

[0056] Specifically,

[0057] When the identification chip information of each of the tested chips 10 matches the corresponding background chip information (that is, the identification chip information of each of the tested chips 10 is consistent with the corresponding background chip information), it means that the chip information record of each of the tested chips 10 in the integrated circuit wafer 1 is correct, and therefore, the chip information verification test is completed.

[0058] When the identification chip information of each of the tested chips 10 does not match the corresponding background chip information (the identification chip information of each of the tested chips 10 is inconsistent with the corresponding background chip information), it means that the chip information of the tested chip 10 is recorded incorrectly (for example, the batch number of the tested chip 10 is wrong, or the GPIB communication is wrong, or the position coordinate setting is wrong, etc.), and the test needs to be temporarily stopped to check and find the cause of the error. After finding the cause of the error, it is corrected in time, and after correcting the error, it returns to step S2 to re-acquire the identification chip information of each of the tested chips, and compare the background chip information and identification chip information of the same tested chip to confirm whether the background chip information and the identification chip information of the tested chip match. If the background chip information and the identification chip information match, the test is terminated; if the background chip information and the identification chip information do not match, continue to check and find the cause of the error. After finding the cause of the error, it is corrected in time, and after correcting the error, it returns to step S2 until the background chip information and the identification chip information match, record the test data and test results of the tested chip, and the chip information verification test is terminated. The method of this embodiment utilizes real-time chip information comparison and verification without affecting the test efficiency, and discovers chip information errors and finds out the causes of the errors as soon as possible, thereby avoiding the need for retesting due to late discovery of chip information errors in the tested chip or chips with unqualified test results directly flowing into the next link, thereby avoiding irreparable losses; and under the premise that the test time remains unchanged, real-time verification records whether the chip information of the tested chip is correct, thereby improving the traceability of the chip information of the tested chip.

[0059] In summary, the present invention provides a method for chip information verification, comprising the following steps: Step S1: providing an integrated circuit wafer, the integrated circuit wafer comprising multiple chips under test, the chips under test undergoing multiple test items, and each of the chips under test comprising background chip information; Step S2: obtaining identification chip information of each of the chips under test; Step S3: comparing the background chip information and identification chip information of the same chip under test to confirm whether the background chip information and identification chip information of the chip under test match; Step S4: if the background chip information and identification chip information of the chip under test do not match, finding the cause of the mismatch, correcting the cause of the mismatch after finding the cause, and returning to Step S2; or, if the background chip information and identification chip information of the chip under test match, recording the test data and test results of the chip under test. The method of the present invention utilizes chip information for real-time comparison and verification without affecting the test efficiency, and discovers chip information errors and finds out the causes of the errors at the first time, thereby avoiding the need for retesting due to late discovery of chip information errors in the tested chip or directly flowing into the next link with unqualified test results, thereby avoiding irreparable losses; and under the premise of unchanged test time, real-time verification records whether the chip information of the tested chip is correct, thereby improving the traceability of the chip information of the tested chip.

[0060] In addition, it should be noted that, unless otherwise specified or indicated, the description of the terms "first" and "second" in the specification is only used to distinguish the various components, elements, steps, etc. in the specification, rather than to represent the logical relationship or sequential relationship between the various components, elements, steps, etc. It is understandable that, although the present invention has been disclosed as above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified to equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of protection of the technical solution of the present invention.

Claims

1. A chip information verification method, characterized in that: The following steps are involved: Step S1: providing an integrated circuit wafer, wherein the integrated circuit wafer comprises a plurality of chips under test, the chips under test undergo a plurality of test items, and each of the chips under test comprises background chip information; Step S2: Obtaining identification chip information of each chip under test; Step S3: comparing the background chip information and the identification chip information of the same chip under test to confirm whether the background chip information and the identification chip information of the chip under test match; Step S4: If the background chip information and the identification chip information of the chip under test do not match, find the cause of the mismatch, correct the cause of the mismatch after finding it, and return to step S2 for real-time comparison and verification, and find out the chip information error and the cause of the error as soon as possible, so as to avoid the need for retesting or the chip with unqualified test results directly flowing into the next link due to the late discovery of the chip information error of the chip under test; or, if the background chip information and the identification chip information of the chip under test match, record the test data and test results of the chip under test.

2. The method according to claim 1, characterized in that The background chip information of each chip under test is binary data.

3. The method according to claim 2, characterized in that The batch number, chip number, location coordinates, wafer fabrication plant code, and test plant code of each chip under test are first converted into ASCII code and then translated into binary code to obtain the background chip information.

4. The method according to claim 1, characterized in that Step S2 includes: Read back the identification chip information of each chip under test by optical character recognition from the integrated circuit probe station through a universal interface bus; The identification chip information is recorded, and the test results and test data of each of the tested chips are correspondingly saved.

5. The method according to claim 4, characterized in that The identification chip information includes the batch number, chip number and location coordinates, wafer foundry code and test factory code of the chip under test.

6. The method according to claim 4, characterized in that The test data specifically includes test data in rawdata, stdf, and txt formats.

7. The method according to claim 4, characterized in that The test data includes at least one screening identifier.

8. The method according to claim 7, characterized in that The test data includes HardBin and SoftBin.

9. The method according to claim 8, characterized in that When the background chip information and the identification chip information of the chip under test do not match, the chip information of the chip under test in the integrated circuit wafer is recorded incorrectly.

10. The method according to claim 9, characterized in that When the background chip information and identification chip information of the chip under test do not match, the batch number of the chip under test is wrong; or, the communication of the universal interface bus interface is wrong; or, the position coordinate setting of the chip under test is wrong.

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