System and method for analyzing semiconductor devices

Abstract

The present application discloses a system and method for analyzing semiconductor devices. The system for analyzing semiconductor devices includes an etching module, an analysis module, and a calculation module. The etching module can repeatedly etch the entire surface of a wafer at the same etching rate to expose the next surface of the wafer at the next depth where an object to be analyzed exists. The analysis module can obtain two-dimensional structural information from each repeatedly etched surface of the wafer. The calculation device is used to continuously stack the repeatedly obtained two-dimensional structural information to generate a three-dimensional image.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Application No. 10-2019-0088824 filed on July 23, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments may generally relate to systems and methods for analyzing semiconductor devices, and more particularly, to systems and methods for analyzing structures of semiconductor devices. Background Art

[0004] The current technology used in the manufacture of semiconductor devices can produce highly integrated three-dimensional structures with dimensions on the order of tens of nanometers. Patterns with such three-dimensional structures may have various defects in the deep part of the pattern. Using current semiconductor inspection equipment to obtain two-dimensional information may not be able to find these defects in the deep part of the pattern. Summary of the invention

[0005] In an example embodiment of the present disclosure, a system for analyzing a semiconductor device includes an etching module for repeatedly etching the entire surface of a wafer at the same etching rate to expose a next surface of the wafer at a next depth where an object to be analyzed exists. The system also includes an analysis module for repeatedly obtaining two-dimensional structural information from each repeatedly etched surface of the wafer. The system also includes a computing device for continuously stacking the repeatedly obtained two-dimensional structural information to generate a three-dimensional image.

[0006] In example embodiments, the etching module includes at least one of a milling device for irradiating an entire surface of the wafer with an ion beam, a chemical mechanical polishing (CMP) device, a dry etching device, and a wet etching device.

[0007] The analysis module may include an analysis device, an inspection device, and a calibration device configured to obtain two-dimensional information using light, an electron beam, and an X-ray. For example, the analysis module may include at least one of a scanning electron microscope (SEM), a photoelectron emission microscope (PEEM), an X-ray photoelectron spectrometer (XPS), an energy dispersive X-ray analyzer (EDX), and an optical metrology / inspection tool.

[0008] The repeatedly obtained two-dimensional structural information includes a two-dimensional image, and the computing device may include a controller for classifying the two-dimensional image according to the etching depth and the two-dimensional coordinates (X, Y), so as to generate a three-dimensional image by continuously stacking the two-dimensional images based on the etching depth and the two-dimensional coordinates. The computing device may also include a memory for storing the classified two-dimensional images.

[0009] In an example embodiment of the present disclosure, a method for analyzing a semiconductor device includes: repeatedly etching the entire surface of a wafer to a target depth at the same etching rate to expose the next surface of the wafer. The method also includes repeatedly obtaining two-dimensional structural information from each repeatedly etched surface of the wafer. The method also includes continuously stacking the repeatedly obtained two-dimensional structural information to generate a three-dimensional image.

[0010] In an example embodiment, obtaining the two-dimensional structural information includes obtaining two-dimensional physical information of the wafer and obtaining two-dimensional electrical information of the wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and another aspect, features and advantages of the presently disclosed subject matter will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a block diagram illustrating a system for analyzing a semiconductor device according to an example embodiment;

[0013] Figure 2 is a cross-sectional view showing an etching module according to an example embodiment;

[0014] Figure 3 is a block diagram illustrating a computing module according to an example embodiment;

[0015] Figure 4 is a flowchart illustrating the operation of a system for analyzing a semiconductor device according to an example embodiment;

[0016] Figure 5 is a cross-sectional view showing an etched surface of a wafer according to example embodiments;

[0017] Figure 6 It is shown Figure 5 a view of a two-dimensional image of an etched surface of a wafer in FIG.

[0018] Figure 7 It is shown from Figure 6 A view of a three-dimensional image generated from a two-dimensional image in;

[0019] Figure 8 is a block diagram illustrating an analysis module according to an example embodiment;

[0020] Fig. 9 and Fig.10 It is shown that the use Figure 8 a view of a method for analyzing a semiconductor device using an analysis module in the semiconductor device; and

[0021] Fig.11 is a block diagram illustrating a system for analyzing a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0022] Various embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The accompanying drawings are schematic diagrams of various embodiments (and intermediate structures). As such, variations in the illustrated configurations and shapes, for example due to manufacturing techniques and / or tolerances, can be expected. Therefore, the described embodiments should not be interpreted as being limited to the specific configurations and shapes shown herein, but may include deviations in configurations and shapes that do not depart from the spirit and scope of the present invention as defined by the appended claims.

[0023] The present invention is described herein with reference to cross-sections and / or plan views of ideal embodiments of the present invention. However, the embodiments of the present invention should not be construed as limitations on the inventive concept. Although some embodiments of the present invention will be shown and described, it will be appreciated by those of ordinary skill in the art that changes may be made to these embodiments without departing from the principles and spirit of the present invention.

[0024] Figure 1 is a block diagram illustrating a system 100 for analyzing a semiconductor device according to example embodiments.

[0025] refer to Figure 1 , the system 100 for analyzing a semiconductor device may include a two-dimensional information inspection apparatus 110, a calculation apparatus 150, and a cleaning module 180. The two-dimensional information inspection apparatus 110 may include an etching module 120 and an analysis module 130.

[0026] The etching module 120 can etch the entire surface of the wafer to a uniform thickness (depth) at the same etching rate, that is, the etching target thickness (etching target depth). The same etching rate means that different areas of the wafer surface are etched substantially the same distance during the same duration. For example, the etching module 120 may include an ion beam milling device, a chemical mechanical polishing (CMP) device, a dry etching device, or a wet etching device using ion beam etching, which is configured to etch the entire surface of a wafer of about 300 mm in size. The ion beam milling device can remove the layer on the entire surface of the wafer by ion beam radiation in a sputtering manner. The ion beam milling device can uniformly irradiate the entire surface of the wafer with an ion beam, thereby removing the entire surface of the wafer with a uniform thickness. The CMP device can use a polishing pad to remove the entire surface of the wafer with a uniform thickness.

[0027] The etching target thickness (etching target depth) may be set according to the inspection position of the wafer. For example, the etching target thickness may be no greater than about 10 nm in consideration of etching depth resolution.

[0028] In an example embodiment, the etching module 120 may etch each layer on the wafer to a uniform target depth (thickness) at the same etching rate. For example, the etching rate of each layer on the wafer may be about 1. When the etching module 120 includes an ion beam milling device, the milling device may include at least one ion beam source to remove each layer on the wafer at the same etching rate.

[0029] The analysis module 130 can obtain two-dimensional structural information of the etched surface of the wafer etched by the etching module 120. For example, the analysis module 130 can obtain a two-dimensional image of the etched surface of the wafer from the ions and electrons emitted by the wafer w. The analysis module 130 may include an analysis device, an inspection device, and a calibration device configured to obtain two-dimensional information using light, an electron beam, and an X-ray. For example, the analysis module 130 may include at least one of a scanning electron microscope (SEM) device, a photoelectron emission microscope (PEEM) device, an X-ray photoelectron spectrometer (XPS) device, an energy dispersive X-ray analysis (EDX) device, and an optical metrology / inspection tool. In addition, the analysis module 130 may include a mass spectrometer and / or an optical emission spectroscopy (OES) device. The mass spectrometer and / or the OES device can measure the amount of byproducts generated during the etching of the wafer w. The mass spectrometer and / or the OES device can provide the amount of byproducts to the computing device 150. The computing device 150 can control the target depth of the etching module 120. The computing device 150 can analyze the properties of the byproducts.

[0030] Figure 2 is a diagram showing a method according to an example embodiment Figure 1 sectional view of the etching module 120.

[0031] refer to Figure 2 For one embodiment, the etching module 120 may include a milling device using an ion beam. Hereinafter, such an embodiment is described, and the reference numeral 120 of the etching module refers to the milling device.

[0032] The milling device 120 may include a stage 111 configured to support a wafer w. The wafer w may include a semiconductor substrate 101 and a circuit layer 102 including a plurality of materials on the semiconductor substrate 101.

[0033] The milling device 120 may include an ion radiator 115 (also referred to as an ion accelerator) configured to accelerate ions to irradiate the entire surface of the wafer w with an ion beam BEAM. The ion radiator 115 may be arranged above the stage 111. The diameter of the ion radiator 115 may be greater than the diameter of the wafer W. The ion radiator 115 may irradiate with an ion beam BEAM to uniformly etch the entire surface of the wafer w (i.e., the surface of the circuit layer 102) in a direction substantially perpendicular to the surface of the semiconductor substrate 101 with a uniform thickness. The ion beam BEAM may be incident on the surface of the wafer w in various directions.

[0034] In an example embodiment, the milling device 120 may focus a focused ion beam (FIB) on the surface of the wafer w using a FIB device, or irradiate a cluster ion beam (CIB) on the surface of the wafer w using a CIB device. The ion beam generated by the FIB method or the CIB method may be irradiated to the entire surface of the wafer w to etch the entire surface of the circuit layer 102 with a uniform thickness.

[0035] For example, the milling device 120 may use Ar ions as etching ions.

[0036] When the milling device 120 uses a FIB or a CIB, the etching ions may include a metal source having a low melting point and low reactivity. The metal source may include Al, As, Au, Be, Bi, Cs, Cu, Ga, Ge, Fe, In, Li, Ni, Pb, Pd, Pr, Pt, Zn, etc. For example, the milling device 120 may heat a solid Ga source to generate Ga + The milling device 120 may include an ion gun configured to accelerate Ga + Ion acceleration and radiation Ga + Ions. For example, the ion gun may generate an ion beam having an acceleration voltage of about 30 keV or higher. When the ion beam generated by the milling device 120 irradiates the surface of the wafer w, ions and electrons may be emitted from the surface of the wafer w. The milling speed of the ion beam and the depth resolution of the ion beam may be controlled by the current of the ion beam and the incident angle of the ion beam to the surface of the wafer w.

[0037] When the etching module 120 includes a FIB device or a CIB device, the analysis module 130 may be disposed in the etching module 120. The analysis module 130 may be positioned above the wafer w to detect ions and electrons emitted from the wafer w. The SEM device 130 may obtain a two-dimensional image of the wafer w from the ions and electrons emitted from the wafer w.

[0038] refer to Figure 1, the computing device 150 may continuously stack the two-dimensional (image) information obtained from the analysis module 130 to obtain a three-dimensional image.

[0039] Figure 3 is a diagram showing a method according to an example embodiment Figure 1 A block diagram of a computing device 150 is shown.

[0040] refer to Figure 3 , the computing device 150 may include a controller 152 , a memory 154 , an input / output unit 156 , and an interface unit 158 ​​.

[0041] The controller 152 may calculate various process monitoring data based on the two-dimensional image I obtained from the analysis module 130. The calculation of the controller 152 may be driven according to an algorithm designed to calculate the process monitoring data. The controller 152 may continuously stack the two-dimensional images obtained from the analysis module 130 to generate a three-dimensional image.

[0042] The memory 154 may include a non-volatile storage medium. For example, the memory 154 may include a hard disk and / or a memory of a non-volatile semiconductor device, such as a flash memory, a phase change memory, a magnetic memory, etc. The memory 154 may store the two-dimensional image obtained from the analysis module 130 and the image data (such as parameters and three-dimensional images) processed by the computing device 150.

[0043] The input / output unit 156 may include a keyboard, a keypad, and / or a display device.

[0044] The image data obtained from the two-dimensional information inspection device 110 can be transmitted to the computing device 150 through the interface unit 158. The data processed by the computing device 150 can be transmitted to the inspection device 110 or other external devices, such as a data server or an agent policy center (APC) server, through the interface unit 158. The interface unit 158 ​​may include a wired communication device, a wireless communication device, and / or a universal serial bus (USB) port. The controller 152, the memory 154, the input / output unit 156, and the interface unit 158 ​​can be coupled to each other via a data bus.

[0045] refer to Figure 1 The cleaning module 180 may clean the etched surface of the wafer w etched to a uniform depth. The cleaning module 180 may include a wet cleaning device or a dry cleaning device.

[0046] Figure 4 is a flowchart illustrating the operation of a system for analyzing a semiconductor device according to an example embodiment, Figure 5 is a cross-sectional view showing an etched surface of a wafer according to example embodiments, Figure 6 It is shown Figure 5a view of a two-dimensional image of the etched surface of the wafer, and Figure 7 It is shown from Figure 6 A view of a three-dimensional image generated from a two-dimensional image in FIG. In example embodiments, the etching module 120 may include a milling device. The wafer w may include a plurality of contact plugs CT1, CT2, and CT3 (CT1-CT3).

[0047] refer to Figure 4 and Figure 5 , the wafer w may be loaded into the two-dimensional information inspection device 110. In operation S1, the etching module 120 may use an ion beam to uniformly irradiate the entire surface of the wafer w and etch the entire surface of the wafer w to a target depth. For example, the ion beam may be initially irradiated to an initial target depth. Figure 5 The surface A-A' of the wafer w in the ion beam is shown in FIG. Therefore, the surface of the wafer w can be sputtered and etched to a uniform depth by the ion beam. When the wafer w is etched by the ion beam, the mass spectrometer or OES in the analysis module 130 can measure the amount of by-products. The etching depth of the wafer w can be determined and thus controlled based on the amount of by-products.

[0048] In operation S2, the analysis module 130 may measure electrons emitted from the surface of the wafer w to obtain a two-dimensional image of the etched surface of the wafer w. After ion beam milling, the analysis module 130 such as SEM, EDX or PEEM may generate a two-dimensional image of the etched surface of the wafer w.

[0049] Using ions, the wafer w is repeatedly moved down to a target depth of Figure 5 The next surface BB' in the wafer w is etched to obtain a two-dimensional image of the etched surface BB' of the wafer w, and then the ion beam is used to repeat the etching of the wafer w down to the target depth. Figure 5 The next surface CC' in the wafer w is etched, and a two-dimensional image of the etched surface CC' surface of the wafer w is obtained. This cycle of etching to a target depth and then obtaining a two-dimensional image can be performed repeatedly. Figure 5 In addition, the surface of the wafer w may be cleaned to obtain a two-dimensional image, and then the surface of the wafer w may be etched again.

[0050] Under ideal conditions, the two-dimensional image of the surface A-A', the two-dimensional image of the surface B-B', and the two-dimensional image of the surface CC' may be substantially the same as each other. However, in reality, in a highly integrated three-dimensional device, the size and shape of the contact plugs CT1-CT3 may be uneven and / or a void v may be generated in the contact plugs CT1-CT3. The void v and / or shape error may be detected in the two-dimensional image according to the detection point. Further, the shape of the three-dimensional pattern of a highly integrated semiconductor device may be unpredictable.

[0051] In an exemplary embodiment, reference Figure 6 , in operation S3, the controller 152 of the computing device 150 may continuously stack two-dimensional information (such as a two-dimensional image obtained by the analysis module 130) to obtain three-dimensional image data. The controller 152 may classify the two-dimensional information measured by the analysis module 130 along the XY direction according to the etching depth. The controller 152 may provide the classified two-dimensional information to the memory 154. In particular, the controller 152 may classify the two-dimensional image of the entire surface of the wafer w into two-dimensional coordinates (X, Y). The controller 152 may provide the two-dimensional coordinates (X, Y) to the memory 154. In addition, the controller 152 may classify the two-dimensional information in order according to the etching depth. The controller 152 may provide the classified two-dimensional information to the memory 154 in order according to the etching depth. Although not in Figure 3 Although not shown in FIG. 1 , an additional noise filter for filtering noise in the two-dimensional image may also be arranged in the controller 152 .

[0052] The controller 152 may align the XY coordinates of the two-dimensional images and sort them by target depth to stack the two-dimensional images, thereby obtaining a three-dimensional image. A detailed shape of a three-dimensional structure on the wafer w may be predicted based on a fault image of the wafer w.

[0053] For example, Figure 6 The size of the image of the third contact plug CT3 on the surface BB' in the embodiment may be smaller than the size of the image of the third contact plug CT3 on the surface A-A' or CC', and Figure 6 The image of the third contact plug CT3 on the surface BB' in FIG. 1 may deviate from the image of the third contact plug CT3 on the surface A-A' or CC'. Figure 7 In the three-dimensional image of the third contact plug CT3 in FIG. 1 , the third contact plug CT3 is shown to have different diameters. Therefore, the computing device 150 can detect shape failure, that is, a physical defect in the third contact plug CT3. The computing device 150 can calculate the size of the third contact plug CT3, the distance between the contact plugs CT1-CT3, the resistance of the contact plugs CT1-CT3, and the expected process parameters.

[0054] For example, Figure 6 As shown, when the cross-sectional image of the second contact plug CT2 on the surface CC' may have a ring shape, it can be noted that a void may be generated at the surface CC' of the second contact plug CT2. In addition, a portion of the three-dimensional image corresponding to the void may have a different color or transparency from other portions of the three-dimensional image. The controller 152 of the computing device 150 may rotate and deform (expand and reduce) the outline of the three-dimensional image. Therefore, shape destruction and internal destruction of the three-dimensional image can be easily detected.

[0055] The controller 152 of the computing device 150 may store a two-dimensional image of the wafer w according to the etching depth and the two-dimensional coordinates (X, Y). Therefore, when the input / output unit 156 inputs the etching depth and the two-dimensional coordinates (X, Y) of the region of interest (ROI), the controller 152 may rotate and / or deform the image of the ROI. The controller 152 may output the image of the ROI to provide the output image to the user.

[0056] Figure 8 is a block diagram illustrating an analysis module 130 according to an example embodiment, and Fig. 9 and Fig.10 It is shown that the use Figure 8 FIG. 1 is a diagram of a method for analyzing a semiconductor device by using an analysis module 130 in FIG.

[0057] refer to Figure 8 , the analysis module 130 may include a first analysis unit 135a and a second analysis unit 135b. For example, the first analysis unit 135a may include a SEM device configured to detect a physical image of the etched surface. The second analysis unit 135b may include an EDX device or a PEEM device configured to display electrical properties of the etched surface. The second analysis unit 135b, such as a PEEM device, may graphically represent electrical properties such as concentration distribution of particles.

[0058] In the following, reference Fig. 9 and Fig.10 Detailed description and instructions for use Figure 8 A method for inspecting semiconductor devices using an analysis module in a semiconductor device.

[0059] Synthetic wafers can be prepared <w0>. Synthetic wafer <w0>A semiconductor substrate 10 having a MOS transistor may be included. The MOS transistor may include a gate structure, a source 20s, and a drain 20d on the semiconductor substrate 10. The gate structure may include a gate insulating layer 12, a gate 15, and a hard mask layer 17 stacked in sequence. The gate structure may further include a spacer 19 on the sidewalls of the gate insulating layer 12, the gate 15, and the hard mask layer 17. The source 20s and the drain 20d may be formed in the semiconductor substrate 10 on both sides of the gate structure. Synthesized Wafer <w0>An insulating interlayer 22 may be further included, the insulating interlayer 22 being configured to cover the MOS transistor and contacts 25a, 25b, and 25c. The contacts 25a, 25b, and 25c may be formed in the insulating interlayer 22. The contacts 25a, 25b, and 25c may contact the gate 15, the source 20s, and the drain 20d, respectively.

[0060] The first analysis unit 135a can measure the synthesized wafer <w0>Since the first analyzing unit 135a can detect a physical image, the image 10 can show the insulating interlayer 22 and the contacts 25a, 25b, and 25c. Physical information such as the shapes and positions of the contacts 25a, 25b, and 25c can be recognized from the image 10.

[0061] The etching module 120 may etch the wafer w to a first target depth da to expose the first surface aa' of the wafer w. For example, the first target depth da may be <w0>The first analyzing unit 135a may measure the physical image Ia of the exposed first surface a-a' of the wafer w. The physical image Ia of the first surface a-a' of the wafer w may show the shapes and positions of the hard mask layer 17, the contacts 25a, 25b and 25c, and the insulating interlayer 22 having different properties.

[0062] The etching module 120 may then etch the wafer w to a second target depth db to expose the second surface bb' of the wafer w. For example, the second target depth db may allow the gate 15 to be exposed. The first analysis unit 135a may measure a physical image Ib of the exposed second surface bb' of the wafer w. The physical image Ib of the second surface bb' of the wafer w may show the shapes and positions of the spacer 19, the gate 15, the insulating interlayer 22, and the contacts 25a, 25b, and 25c having different properties.

[0063] The etching module 120 may then etch the wafer w to a third target depth dc to expose the third surface c-c' of the wafer w. For example, the third target depth dc may allow the surface of the semiconductor substrate 10 to be exposed. The first analysis unit 135a and the second analysis unit 135b may measure a two-dimensional physical image Ic and an electrical image IEc of the exposed third surface c-c' of the wafer w. The two-dimensional physical image Ic measured by the first analysis unit 135a may display the shapes and positions of the semiconductor substrate 10, the source 20s, and the drain 20d having different properties. The two-dimensional electrical image IEc measured by the second analysis unit 135b may display the positions of the source 20s and the drain 20d and the concentration distribution of impurities. As shown in the two-dimensional electrical image IEc, it may be noted that, according to the Gaussian distribution, the impurity concentration in the source 20s and the drain 20d may decrease toward the edge portion.

[0064] Then the etching module 120 can etch the wafer w to a fourth target depth dd to expose the fourth surface d-d' of the wafer w. For example, the fourth target depth dd can allow the bottom surface of the source 20s and the bottom surface of the drain 20d to be exposed. The first analysis unit 135a and the second analysis unit 135b can measure the two-dimensional physical image Id and the electrical image IEd of the exposed fourth surface d-d' of the wafer w. The two-dimensional physical image Id measured by the first analysis unit 135a can show the shape and position of the drain 20d, the semiconductor substrate 10, and the source 20s with different properties. Because the source 20s and the drain 20d can be impurity regions, according to the Gaussian distribution, the doping concentration of the source 20s and the drain 20d can gradually decrease toward the lower part of the source 20s and the drain 20d. In addition, the width of the source 20s and the drain 20d can also gradually decrease toward the lower part of the source 20s and the drain 20d. Therefore, the width of the source 20s and the drain 20d exposed through the fourth surface d-d' of the wafer w can be narrower than the width of the source 20s and the drain 20d exposed through the third surface cc' of the wafer w. The two-dimensional electrical image IEd measured by the second analysis unit 135b can show the concentration distribution of the source 20s and the drain 20ds. As shown in the two-dimensional electrical image IEd, it can be noted that the impurity concentration in the source 20s and the drain 20d at the fourth surface d-d' of the wafer w can be lower than the impurity concentration in the source 20s and the drain 20d at the third surface cc' of the wafer w.

[0065] The controller 152 of the computing device 150 may collect the two-dimensional images I0, Ia, Ib, Ic, Id, IEc, and IEd obtained from the analysis module 130. Fig.10 As shown, the controller 152 can continuously stack the two-dimensional images to generate a three-dimensional image b corresponding to the actual structure a. Further, the two-dimensional physical images I0, Ia, Ib, Ic and Id obtained by the first analysis unit 135a and the two-dimensional electrical images IEc and IEd are synthesized with each other to obtain the shape, position and electrical characteristic distribution of the elements in the actual structure in the three-dimensional image. Therefore, shape damage and internal damage of the three-dimensional semiconductor device can be easily detected from the three-dimensional image.

[0066] Fig.11 is a block diagram illustrating a system 100 a for analyzing a semiconductor device according to example embodiments.

[0067] refer to Fig.11 The etching module 120, the analysis module 130, the computing device 150 and the cleaning module 180 in the system 100a may be configured as a cluster. The wafer w may be on standby at a load lock.

[0068] Therefore, the clustered etching module 120, analysis module 130, computing device 150, and cleaning module may be systematized to improve inspection efficiency.

[0069] According to example embodiments, a system for inspecting semiconductor devices can etch the entire surface of a wafer to a uniform depth at the same etching rate. A two-dimensional image of the etched surface can be acquired. The system can continuously stack the two-dimensional images to generate a three-dimensional image. Therefore, the system can easily detect three-dimensional damage in a highly integrated three-dimensional device from a three-dimensional image of the device obtained by collecting the two-dimensional images.

[0070] The above embodiments of the present teaching are intended to illustrate rather than limit the present teaching. Various alternatives and equivalents are possible. The present teaching is not limited to the embodiments described herein. The present teaching is also not limited to any particular type of semiconductor device. In view of the present disclosure, other additions, reductions or modifications may be implemented, and they are intended to fall within the scope of the appended claims.

Claims

1. A system for analyzing a semiconductor device, the system comprising: an etching module for repeatedly etching the entire surface of the wafer at the same etching rate to expose a next surface of the wafer at a next depth where an object to be analyzed exists; An analysis module, which is used to obtain two-dimensional structural information from each repeatedly etched surface of the wafer; as well as A computing device for continuously stacking the repeatedly acquired two-dimensional structural information to generate a three-dimensional image, wherein: The analysis module comprises: A first analysis unit, which is used to obtain a physical image of the etched surface of the wafer; and A second analysis unit is used to obtain an electrical image of the etched surface of the wafer.

2. The system of claim 1, wherein the etching module comprises at least one of the following: a milling device for irradiating the entire surface of the wafer with an ion beam; Chemical mechanical polishing (CMP) equipment; Dry etching equipment; and Wet etching equipment.

3. The system of claim 2, wherein: The milling apparatus includes an ion accelerator for accelerating ions into the entire surface of the wafer to remove material.

4. The system of claim 1, wherein: The analysis module includes at least one of the following: Scanning electron microscope SEM device; Photoelectron emission microscopy PEEM device; Energy dispersive X-ray analysis EDX device; X-ray photoelectron spectrometer XPS device; as well as Optical metrology / inspection tools.

5. The system of claim 4, wherein: The first analysis unit includes a scanning electron microscope (SEM) device.

6. The system of claim 4, wherein: The second analysis unit includes at least one of a photoelectron emission microscope (PEEM) device and an energy dispersive X-ray analysis (EDX) device.

7. The system of claim 1, wherein: The etching module comprises: a stage for supporting the wafer; and An ion accelerator is used to accelerate ions into the entire surface of the wafer to etch the circuit layer on the wafer.

8. The system of claim 7, wherein: The width of the ion accelerator is greater than the width of the wafer so that the accelerated ions are vertically incident on the entire surface of the wafer.

9. The system of claim 1, wherein: The repeatedly acquired two-dimensional structural information comprises a two-dimensional image, and wherein the calculation device comprises: a controller for classifying the two-dimensional images according to the etching depth and the two-dimensional coordinates (X, Y) to continuously stack the two-dimensional images based on the etching depth and the two-dimensional coordinates to generate the three-dimensional image; and The memory is used to store the classified two-dimensional images.

10. The system of claim 1, further comprising a cleaning module for cleaning an etched surface of the wafer.

11. The system of claim 10, further comprising a load lock, wherein the wafer is held at the load lock, wherein: The etching module, the analysis module, and the cleaning module are each connected to the load lock and are interconnected with each other through the load lock.

12. The system of claim 1, wherein: The analysis module includes at least one of the following: Mass spectrometer; and An optical emission spectrometer OES device is used to analyze by-products generated during the process of etching the wafer.

13. A method for analyzing a semiconductor device, the method comprising: Repeatedly etching the entire surface of the wafer to a target depth at the same etching rate to expose the next surface of the wafer; repeatedly obtaining two-dimensional structural information from each repeatedly etched surface of the wafer; as well as Continuously stacking the repeatedly acquired two-dimensional structural information to generate a three-dimensional image, The step of obtaining the two-dimensional structure information includes: obtaining two-dimensional physical information of the wafer; and Two-dimensional electrical information of the wafer is obtained.

14. The method of claim 13: in, The two-dimensional structural information repeatedly obtained includes a two-dimensional image; Wherein, repeatedly obtaining the two-dimensional structure information comprises: classifying the two-dimensional image according to the target depth and the two-dimensional coordinates (X, Y); and Wherein, continuously stacking the repeatedly acquired two-dimensional structure information includes: continuously stacking the two-dimensional images based on the target depth and the two-dimensional coordinates.

15. The method of claim 13, further comprising analyzing byproducts generated during etching of the wafer.

16. The method of claim 15, wherein the amount of the byproduct is analyzed to control the target depth.

17. The method of claim 13, further comprising: The etched surface of the wafer is cleaned between repeated etchings of the surface of the wafer, and the two-dimensional structural information is obtained.

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