Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same, wherein the method comprises: providing a substrate, wherein the substrate surface has a first dielectric layer; forming a first opening in the first dielectric layer, and the bottom of the first opening exposes a portion of the substrate surface; forming an initial first plug in the first opening; etching back the initial first plug to form a groove in the first dielectric layer and a first plug at the bottom of the groove; forming a second plug in the groove, and the material of the first plug is different from that of the second plug; forming a second dielectric layer on the second plug and the surface of the first dielectric layer; etching a portion of the second dielectric layer to form a second opening in the second dielectric layer, and the bottom of the second opening exposes the top surface of the second plug; forming a third plug in the second opening, and the bottom of the third plug contacts the surface of the second plug. The semiconductor structure formed by the method has good performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the rapid development of integrated circuit manufacturing technology, the size of semiconductor devices in integrated circuits has been continuously reduced, so that the operating speed of the entire integrated circuit can be effectively improved. As the size requirements of components become smaller and smaller, the size of the corresponding conductive structure is also getting smaller and smaller.

[0003] The method for forming the conductive structure is as follows: providing a semiconductor substrate; forming a first dielectric layer on the semiconductor substrate, wherein the first dielectric layer has a first opening; forming a first plug in the first opening; after forming the first plug, forming a second dielectric layer on the surface of the first plug and the surface of the first dielectric layer; forming a second opening in the second dielectric layer; after forming the second opening, forming a second plug in the second opening. The first plug and the second plug constitute a conductive structure. In order to reduce the resistance of the conductive structure with an increasingly reduced size, the conductive structure is formed by using a material with a relatively low resistivity.

[0004] However, the performance of semiconductor devices formed by the prior art needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0006] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the surface of the substrate has a first dielectric layer; forming a first opening in the first dielectric layer, and the bottom of the first opening exposes a portion of the substrate surface; forming an initial first plug in the first opening; etching back the initial first plug to form a groove and a first plug located at the bottom of the groove in the first dielectric layer; forming a second plug in the groove, and the material of the first plug is different from that of the second plug; forming a second dielectric layer between the second plug and the surface of the first dielectric layer; etching a portion of the second dielectric layer to form a second opening in the second dielectric layer, and the bottom of the second opening exposes the top surface of the second plug; forming a third plug in the second opening, and the bottom of the third plug is in contact with the surface of the second plug.

[0007] Optionally, the method further includes: after forming the first opening and before forming the initial first plug, forming an initial barrier layer on the side wall surface and the bottom surface of the first opening and the surface of the first dielectric layer.

[0008] Optionally, the method for forming the initial first plug includes: forming a first conductive material film in the first opening and on the surface of the initial barrier layer; planarizing the first conductive material film until the surface of the first dielectric layer is exposed, and forming an initial first plug in the first opening.

[0009] Optionally, the method further includes: after forming the groove and before forming the second plug, removing the initial barrier layer exposed on the sidewall of the groove, and forming a barrier layer on the bottom of the first opening and a portion of the sidewall surface.

[0010] Optionally, the process for removing the barrier layer exposed by the groove sidewall is a wet etching process; the parameters of the wet etching process include: the etching solution used includes diluted ammonia water and diluted hydrogen peroxide, the temperature is 20 degrees Celsius to 100 degrees Celsius, and the etching time is 60 seconds to 240 seconds.

[0011] Optionally, the depth of the groove ranges from 1 nanometer to 5 nanometers.

[0012] Optionally, the process of back-etching the initial first plug is a wet etching process; the parameters of the wet etching process include: the parameters of the wet etching process include: the etching solution used includes a diluted hydrofluoric acid solution, the temperature is 20 degrees Celsius to 100 degrees Celsius, and the etching time is 60 seconds to 240 seconds.

[0013] Optionally, the method for forming the second plug includes: forming a second conductive material film in the groove and on the surface of the first dielectric layer; planarizing the second conductive material film until the surface of the first dielectric layer is exposed, and forming the second plug in the groove.

[0014] Optionally, the second conductive material film includes: a first conductive film located on the sidewall surface and the bottom surface of the groove, and a second conductive film located on the surface of the first conductive film and the first dielectric layer.

[0015] Optionally, the process for forming the first conductive film includes: a selective chemical vapor deposition process; and the process for forming the second conductive film includes: a chemical vapor deposition process.

[0016] Optionally, the material of the first plug includes: cobalt or ruthenium.

[0017] Optionally, a material of the second plug includes: one or more combinations of titanium, nickel, copper, tungsten, aluminum, silver and tantalum.

[0018] Optionally, the method for forming the first opening includes: forming a first patterned layer on the surface of the first dielectric layer, the first patterned layer exposing a portion of the surface of the first dielectric layer; using the first patterned layer as a mask, etching the first dielectric layer until the substrate surface is exposed, thereby forming the first opening in the first dielectric layer.

[0019] Optionally, the method for forming the second opening includes: forming a second patterned layer on the surface of the second dielectric layer, the second patterned layer exposing a portion of the surface of the second dielectric layer; using the second patterned layer as a mask, etching the second dielectric layer until the top surface of the second plug is exposed, forming a second opening in the second dielectric layer, and the bottom of the second opening exposes the top surface of the second plug.

[0020] Optionally, the method for forming the third plug includes: forming a third conductive material film in the second opening and on the surface of the second dielectric layer; planarizing the third conductive material film until the surface of the second dielectric layer is exposed, and forming the third plug in the second opening.

[0021] Optionally, the third conductive material film includes: a third conductive film located on the bottom surface and side wall surface of the second opening, and a fourth conductive film located on the surface of the third conductive film and the surface of the second dielectric layer.

[0022] Optionally, the process of forming the third conductive film includes: a selective chemical vapor deposition process; the process of forming the fourth conductive film includes: a chemical vapor deposition process.

[0023] Optionally, a material of the third plug includes: one or more combinations of titanium, nickel, copper, tungsten, aluminum, silver and tantalum.

[0024] Correspondingly, an embodiment of the present invention also provides a semiconductor structure formed by any of the above methods, comprising: a substrate, a first dielectric layer on the surface of the substrate; a first opening located in the first dielectric layer, and the bottom of the first opening exposes the surface of the substrate; a groove located in the first opening and a first plug located at the bottom of the groove, and the top surface of the groove is exposed on the surface of the first dielectric layer; a second plug located in the groove, and the material of the second plug is different from that of the first plug; a second dielectric layer located on the surface of the second plug and the first dielectric layer, and a second opening located in the second dielectric layer; a third plug located in the second opening, and the bottom of the third plug is in contact with the surface of the second plug.

[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0026] In the method for forming a semiconductor structure provided by the technical solution of the present invention, a groove and a first plug are formed in the first dielectric layer by etching back the initial first plug, and the first plug is exposed at the bottom of the groove, so that the second plug formed in the groove is located on the surface of the first plug. Subsequently, a portion of the second dielectric layer is removed by etching, and in the process of forming a second opening in the second dielectric layer, the process of etching a portion of the second dielectric layer will cause etching damage to the surface of the second plug. Since the second plug and the first plug are made of different materials, the process of etching a portion of the second dielectric layer causes less etching damage to the surface of the second plug, which can avoid etching damage to the surface of the first plug, so that the performance of the formed semiconductor structure is better.

[0027] Furthermore, the initial barrier layer exposed by the sidewall of the groove is removed, and a barrier layer is formed at the bottom of the first opening and a portion of the sidewall surface, so that the resistance of the second plug formed in the groove is reduced. At the same time, the barrier layer located at the bottom of the first opening and a portion of the sidewall surface can reduce the diffusion of ions in the first plug into the first dielectric layer, resulting in an impact on the first dielectric layer, thereby improving the performance of the formed semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1 to 5 It is a schematic structural diagram of each step of a method for forming a semiconductor structure;

[0029] Figures 6 to 17 It is a schematic cross-sectional structure diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0030] As described in the background art, semiconductor structures have poor performance.

[0031] The following is a detailed description of the reasons for the poor performance of the semiconductor structure with reference to the accompanying drawings. Figures 1 to 5 The present invention is a structural schematic diagram of each step of a semiconductor structure forming method.

[0032] Please refer to Figure 1 , providing a substrate 100, wherein the surface of the substrate 100 has a first dielectric layer 110 and a first opening 120 located in the first dielectric layer 110, and the bottom of the first opening 120 exposes a portion of the surface of the substrate 100.

[0033] Please refer to Figure 2 A first barrier layer 121 is formed on the sidewalls and bottom surface of the first opening 120 and the surface of the first dielectric layer 110 .

[0034] Please refer to Figure 3 , a first plug 130 is formed in the first opening 120 , and the first barrier layer 121 is located between the first dielectric layer 110 and the first plug 130 .

[0035] Please refer to Figure 4 A second dielectric layer 140 is formed on the surface of the first dielectric layer 110 , and a second opening 150 is formed in the second dielectric layer 140 , and the bottom of the second opening 150 exposes the top surface of the first plug 130 .

[0036] Please refer to Figure 5 A second barrier layer 161 and a second plug 160 located on the surface of the second barrier layer 161 are formed on the sidewall surface and the bottom surface of the second opening 150 , and the second plug 160 fills the second opening 150 .

[0037] In the above method, since the resistivity of cobalt is relatively small, the material of the first plug 130 is cobalt, so that the resistance of the formed first plug 130 is reduced, which is beneficial to improving the performance of the formed semiconductor structure.

[0038] However, the method for forming the second opening 150 includes: forming a patterned layer (not shown in the figure) on the surface of the second dielectric layer 140, and the patterned layer exposes part of the surface of the second dielectric layer 140; using the patterned layer as a mask, etching the second dielectric layer 140 until the top surface of the first plug 130 is exposed to form the second opening 150. Since the cobalt material itself is fragile and easily corroded by the outside, the process of etching the second dielectric layer 150 is likely to cause significant etching damage to the surface of the first plug 130, resulting in defects on the surface of the first plug 130. At the same time, after the second opening 150 is formed, a wet etching process is also performed on the sidewalls and bottom surfaces of the second opening 150 to remove the byproducts remaining in the second opening 150. The wet etching process further causes etching damage to the surface of the first plug 130, resulting in further aggravation of the defects on the surface of the first plug 130. Thirdly, since the surface of the first plug 130 exposed at the bottom of the second opening 150 is easy to react with the outside world, after forming the second opening 150 and before forming the second plug 160, the surface of the first plug 130 is pre-cleaned to remove impurities on the surface of the first plug 130. The pre-cleaning process will cause certain etching damage to the surface of the first plug 130, causing the defects on the surface of the first plug 130 to be further aggravated.

[0039] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, providing a substrate, wherein the substrate surface has a first dielectric layer; forming a first opening in the first dielectric layer, and the bottom of the first opening exposes the substrate surface; forming an initial first plug in the first opening; etching back the initial first plug to form a groove and a first plug at the bottom of the groove in the first dielectric layer; after forming the first plug, forming a second plug in the groove, and the material of the first plug is different from that of the second plug; forming a second dielectric layer on the second plug and the surface of the first dielectric layer; etching part of the second dielectric layer to form a second opening in the second dielectric layer, and the bottom of the second opening exposes the top surface of the second plug; forming a third plug in the second opening, and the bottom of the third plug contacts the surface of the second plug. The semiconductor structure formed by the method has good performance.

[0040] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0041] Figures 6 to 17 It is a cross-sectional schematic diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention.

[0042] Please refer to Figure 6 , providing a substrate 200, wherein the surface of the substrate 200 has a first dielectric layer 210.

[0043] In this embodiment, the base 200 includes a substrate (not shown in the figure) and a device layer (not shown in the figure) located on the surface of the substrate. The device layer may include a device structure, for example, a PMOS transistor and an NMOS transistor. The device layer may also include an interconnection structure electrically connected to the device structure, and an insulating layer surrounding the device structure and the interconnection structure.

[0044] The material of the substrate 200 is a semiconductor material. In this embodiment, the material of the substrate 200 is silicon. In other embodiments, the material of the first substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of III-V group elements, silicon on insulator (SOI) or germanium on insulator. Among them, the multi-element semiconductor material composed of III-V group elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0045] The first dielectric layer 210 is used to provide support for the subsequent formation of a first opening and a first plug located in the first opening.

[0046] The material of the first dielectric layer 210 includes one or more of silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbonitride oxide, and silicon nitride oxide. In this embodiment, the material of the first dielectric layer 210 is silicon oxide.

[0047] Please refer to Figure 7 , a first opening 220 is formed in the first dielectric layer 210 , and a portion of the surface of the substrate 200 is exposed at the bottom of the first opening 220 .

[0048] The first opening 220 is used to be subsequently filled with a conductive material to form an initial first plug.

[0049] The method for forming the first opening 220 includes: forming a first patterned layer (not shown in the figure) on the surface of the first dielectric layer 210, wherein the first patterned layer exposes a portion of the surface of the first dielectric layer 210; using the first patterned layer as a mask, etching the first dielectric layer 210 until the surface of the substrate 200 is exposed to form the first opening 220.

[0050] The process of etching the first dielectric layer 210 includes: one of a dry etching process and a wet etching process, or a combination of the two.

[0051] Please refer to Figure 8 After forming the first opening 220 , an initial barrier layer 230 is formed on the sidewall surface and the bottom surface of the first opening 200 and the surface of the first dielectric layer 210 .

[0052] The initial barrier layer 230 is used for subsequently forming a barrier layer.

[0053] The material of the initial barrier layer 230 includes titanium nitride or tantalum nitride. Accordingly, the material of the barrier layer formed subsequently includes titanium nitride or tantalum nitride.

[0054] In this embodiment, the material of the initial barrier layer 230 is titanium nitride.

[0055] In other embodiments, the initial barrier layer may not be formed.

[0056] Please refer to Fig. 9 After forming the initial barrier layer 230 , an initial first plug 240 is formed in the first opening 220 .

[0057] The method for forming the initial first plug 240 includes: forming a first conductive material film (not shown) in the first opening 220 and on the surface of the initial barrier layer 230 ; planarizing the first conductive material film until the surface of the first dielectric layer 210 is exposed, and forming the initial first plug 240 in the first opening 220 .

[0058] The material of the first conductive material film includes: cobalt or ruthenium. In this embodiment, the material of the first conductive material film is cobalt.

[0059] Since the resistivity of the cobalt material is relatively low, the initial first plug 240 formed of the cobalt material is beneficial to reducing the resistance, so that the formed semiconductor structure has better performance.

[0060] Please refer to Fig.10 , the initial first plug 240 is etched back to form a groove 241 and a first plug 242 located at the bottom of the groove 241 in the first dielectric layer 220 .

[0061] The groove 241 is used to be filled with a conductive material to form a second plug.

[0062] The depth of the groove 241 ranges from 1 nanometer to 5 nanometers.

[0063] The significance of selecting the depth range is that: if the depth is less than 1 nanometer, the thickness of the second plug formed subsequently is too thin, which is not conducive to avoiding etching damage to the surface of the second plug caused by the subsequent etching process, and thus cannot effectively avoid etching damage to the surface of the first plug 242 located at the bottom of the second plug, resulting in poor performance of the formed semiconductor structure; if the depth is greater than 5 nanometers, the thickness of the second plug formed subsequently is too thick. Since the resistivity of the second plug material is greater than the resistivity of the first plug 242 material, a second plug with too thick thickness is not conducive to reducing resistance, resulting in poor performance of the formed semiconductor structure.

[0064] The process of etching back the initial first plug is a wet etching process; the parameters of the wet etching process include: the etching solution used includes a diluted hydrofluoric acid solution, the temperature is 20 degrees Celsius to 100 degrees Celsius, and the etching time is 60 seconds to 240 seconds.

[0065] Please refer to Fig.11 After forming the groove 241 , the initial barrier layer 230 exposed on the sidewall of the groove 241 is removed, and a barrier layer 231 is formed on the bottom and part of the sidewall surface of the first opening 220 .

[0066] The process for removing the barrier layer 230 exposed by the sidewall of the groove 241 is a wet etching process; the parameters of the wet etching process include: the etching solution used includes diluted ammonia water and diluted hydrogen peroxide, the temperature is 20 degrees Celsius to 100 degrees Celsius, and the etching time is 60 seconds to 240 seconds.

[0067] The initial barrier layer 230 exposed on the sidewall of the groove 241 is removed, and a barrier layer 231 is formed at the bottom of the first opening 220 and a portion of the sidewall surface, so that the resistance of the second plug subsequently formed in the groove 241 is reduced. At the same time, the barrier layer 231 located at the bottom of the first opening 220 and a portion of the sidewall surface can reduce the diffusion of ions in the first plug 242 into the first dielectric layer 210, resulting in an impact on the first dielectric layer 210, thereby improving the performance of the formed semiconductor structure.

[0068] Next, a second plug is formed in the groove, and the material of the first plug is different from the material of the second plug. For the specific process of forming the second plug, please refer to Figures 12 to 14 .

[0069] Please refer to Fig.12 A first conductive film 250 is formed on the side wall surface and the bottom surface of the groove 241 .

[0070] The material of the first conductive film 250 includes: one or more combinations of titanium, nickel, copper, tungsten, aluminum, silver and tantalum. In this embodiment, the material of the first conductive film 250 is tungsten.

[0071] The process of forming the first conductive film 250 includes: a selective chemical vapor deposition process.

[0072] Since the first plug 242 and the first dielectric layer 210 are made of different materials and have different surface properties, the selective chemical deposition process can realize the formation of the first conductive film 250 on the surface of the first plug 242 at the bottom of the groove 241, while it is not easy to form the first conductive film on the surface of the first dielectric layer 210, which is beneficial to avoid the deposited material from closing prematurely at the top of the groove 241, thereby avoiding the formation of voids in the formed first conductive film 250, so that the performance of the formed semiconductor structure is better.

[0073] Please refer to Fig.13 , a second conductive film 260 is formed on the surfaces of the first conductive film 250 and the first dielectric layer 210 .

[0074] The material of the second conductive film 260 includes one or more combinations of titanium, nickel, copper, tungsten, aluminum, silver and tantalum.

[0075] In this embodiment, the material of the second conductive film 260 is tungsten.

[0076] The process of forming the second conductive film includes: a chemical vapor deposition process.

[0077] It should be noted that the first conductive film 250 and the second conductive film 260 constitute a second conductive material film 270, and the second conductive material film 270 is located in the groove 241 ( Fig.11) inside and on the surface of the first dielectric layer 210.

[0078] Please refer to Fig.14 , planarizing the second conductive material film 270 until the surface of the first dielectric layer 210 is exposed, and forming a second plug 271 in the groove 241 .

[0079] The second plug 271 is formed by planarizing the second conductive material film. Therefore, the material of the second plug includes one or more combinations of titanium, nickel, copper, tungsten, aluminum, silver and tantalum.

[0080] In this embodiment, the material of the second plug is the same as the material of the subsequently formed third plug, and the material of the second plug is tungsten.

[0081] At present, the material is often used to form plug structures. The process is relatively mature, easy to operate, and easy to be compatible with subsequent processes.

[0082] The second plug 271 and the subsequent third plug are made of the same material, which is conducive to achieving process compatibility.

[0083] By etching back the initial first plug 240, a groove 241 and a first plug 242 are formed in the first dielectric layer 210, and the first plug 242 is exposed at the bottom of the groove 241, so that the second plug 271 formed in the groove 241 is located on the surface of the first plug 242. In the subsequent process of removing part of the second dielectric layer by etching, in the process of forming a second opening in the second dielectric layer, the process of etching part of the second dielectric layer will cause etching damage to the surface of the second plug 271. Since the second plug 271 and the first plug 242 are made of different materials, the process of etching part of the second dielectric layer causes less etching damage to the surface of the second plug 271, and can avoid etching damage to the surface of the first plug 242, so that the performance of the formed semiconductor structure is better.

[0084] Please refer to Fig.15 , a second dielectric layer 280 is formed on the surfaces of the second plug 271 and the first dielectric layer 210 .

[0085] The second dielectric layer 280 is used to provide support for the subsequent formation of a second opening and a third plug located in the second opening.

[0086] The material of the second dielectric layer 280 includes one or more of silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbonitride oxide, and silicon nitride oxide.

[0087] In this embodiment, the material of the second dielectric layer 280 is silicon oxide.

[0088] In this embodiment, the method further includes: after forming the second plug 271 and before forming the second dielectric layer 280, forming an etch stop layer (not shown in the figure) on the surface of the first dielectric layer 210, the etch stop layer being located between the first dielectric layer 210 and the second dielectric layer 280. The etch stop layer is used as a stop layer for subsequent etching to form the second opening.

[0089] Please refer to Fig.16 , a portion of the second dielectric layer 280 is etched to form a second opening 290 in the second dielectric layer 280 , and the bottom of the second opening 290 exposes the top surface of the second plug 271 .

[0090] The second opening 280 is used to be subsequently filled with a conductive material to form a third plug.

[0091] The method for forming the second opening 290 includes: forming a second patterned layer (not shown in the figure) on the surface of the second dielectric layer 280, wherein the second patterned layer exposes a portion of the surface of the second dielectric layer 280; using the second patterned layer as a mask, etching the second dielectric layer 280 until the top surface of the second plug 271 is exposed, and forming a second opening 290 in the second dielectric layer 280, wherein the bottom of the second opening 290 exposes the top surface of the second plug 271.

[0092] Please refer to Fig.17 A third plug 291 is formed in the second opening 290 , and the bottom of the third plug 291 contacts the surface of the second plug 271 .

[0093] The method for forming the third plug 291 includes: forming a third conductive material film (not shown) in the second opening 290 and on the surface of the second dielectric layer 280 ; planarizing the third conductive material film until the surface of the second dielectric layer 280 is exposed, and forming the third plug 291 in the second opening 290 .

[0094] The third conductive material film includes: a third conductive film (not shown in the figure) located on the bottom surface and sidewall surface of the second opening 290, and a fourth conductive film (not shown in the figure) located on the surface of the third conductive film and the surface of the second dielectric layer.

[0095] The material of the third conductive film includes: one or more combinations of titanium, nickel, copper, tungsten, aluminum, silver and tantalum. In this embodiment, the material of the third conductive film is tungsten.

[0096] The material of the fourth conductive film includes: one or more combinations of titanium, nickel, copper, tungsten, aluminum, silver and tantalum. In this embodiment, the material of the fourth conductive film is tungsten.

[0097] The process of forming the third conductive film includes: a selective chemical vapor deposition process; the process of forming the fourth conductive film includes: a chemical vapor deposition process.

[0098] The third plug 291 is formed by planarizing the third conductive material film. Therefore, the material of the third plug includes one or more combinations of titanium, nickel, copper, tungsten, aluminum, silver and tantalum.

[0099] In this embodiment, the material of the third plug 291 is tungsten. The existing process of using tungsten as a filling material for forming a plug structure is relatively mature, so the third plug 291 is easy to be compatible with subsequent processes.

[0100] Since the second plug 271 and the second dielectric layer 280 are made of different materials and have different surface properties, the selective chemical deposition process can realize that while the third conductive film is formed on the surface of the second plug 271 at the bottom of the second opening 290, it is not easy to form the third conductive film on the surface of the second dielectric layer 280, which is beneficial to avoid the deposited material from closing prematurely at the top of the second opening 290, thereby avoiding the formation of voids in the formed third conductive film, so that the performance of the formed semiconductor structure is better.

[0101] Accordingly, the embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to Fig.17 , comprising: a substrate 200, wherein the surface of the substrate 200 has a first dielectric layer 210; a first opening 220 located in the first dielectric layer 210, wherein the bottom of the first opening 220 exposes the surface of the substrate 200; a groove 241 ( Fig.11 ) and a first plug 242 located at the bottom of the groove 241, and the surface of the first dielectric layer 220 exposes the top surface of the groove 241; a second plug 271 located in the groove 241, and the material of the second plug 271 is different from that of the first plug 242; a second dielectric layer 280 located on the surface of the second plug 271 and the first dielectric layer 210, and a second opening 290 located in the second dielectric layer 280; a third plug 291 located in the second opening 290, and the bottom of the third plug 291 is in contact with the surface of the second plug 271.

[0102] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein a first dielectric layer is provided on a surface of the substrate; forming a first opening in the first dielectric layer, wherein a bottom of the first opening exposes a portion of the substrate surface; forming an initial first plug in the first opening; Etching back the initial first plug to form a groove and a first plug located at the bottom of the groove in the first dielectric layer; forming a second plug in the groove, wherein the material of the first plug is different from the material of the second plug; forming a second dielectric layer on the surface of the second plug and the first dielectric layer; Etching a portion of the second dielectric layer to form a second opening in the second dielectric layer, wherein the bottom of the second opening exposes the top surface of the second plug; forming a third plug in the second opening, with the bottom of the third plug in contact with the surface of the second plug; The resistivity of the second plug material is greater than that of the first plug material; the process of etching part of the second dielectric layer causes less etching damage to the surface of the second plug, thereby avoiding the process of etching part of the second dielectric layer causing damage to the surface of the first plug.

2. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: After forming the first opening and before forming the initial first plug, an initial barrier layer is formed on the sidewall surface and the bottom surface of the first opening and the surface of the first dielectric layer.

3. The method for forming a semiconductor structure according to claim 2, wherein: The method for forming the initial first plug includes: forming a first conductive material film in the first opening and on the surface of the initial barrier layer; planarizing the first conductive material film until the surface of the first dielectric layer is exposed, and forming an initial first plug in the first opening.

4. The method for forming a semiconductor structure according to claim 2, wherein: Also includes: After forming the groove and before forming the second plug, the initial barrier layer exposed on the sidewall of the groove is removed, and a barrier layer is formed on the bottom of the first opening and a portion of the sidewall surface.

5. The method for forming a semiconductor structure according to claim 4, wherein: The process for removing the barrier layer exposed by the groove sidewall is a wet etching process; the parameters of the wet etching process include: the etching solution used includes diluted ammonia water and diluted hydrogen peroxide, the temperature is 20 degrees Celsius to 100 degrees Celsius, and the etching time is 60 seconds to 240 seconds.

6. The method for forming a semiconductor structure according to claim 1, wherein: The depth of the groove ranges from 1 nanometer to 5 nanometers.

7. The method for forming a semiconductor structure according to claim 1, wherein: The process of etching back the initial first plug is a wet etching process; the parameters of the wet etching process include: the etching solution used includes a diluted hydrofluoric acid solution, the temperature is 20 degrees Celsius to 100 degrees Celsius, and the etching time is 60 seconds to 240 seconds.

8. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the second plug includes: forming a second conductive material film in the groove and on the surface of the first dielectric layer; planarizing the second conductive material film until the surface of the first dielectric layer is exposed, and forming a second plug in the groove.

9. The method for forming a semiconductor structure according to claim 8, wherein: The second conductive material film includes: a first conductive film located on the sidewall surface and the bottom surface of the groove, and a second conductive film located on the surface of the first conductive film and the first dielectric layer.

10. The method for forming a semiconductor structure according to claim 9, wherein: The process of forming the first conductive film includes: a selective chemical vapor deposition process; the process of forming the second conductive film includes: a chemical vapor deposition process.

11. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first plug includes: cobalt or ruthenium.

12. The method for forming a semiconductor structure according to claim 1, wherein: The material of the second plug includes: one or more combinations of titanium, nickel, copper, tungsten, aluminum, silver and tantalum.

13. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the first opening includes: forming a first patterned layer on the surface of the first dielectric layer, wherein the first patterned layer exposes a portion of the surface of the first dielectric layer; using the first patterned layer as a mask, etching the first dielectric layer until the substrate surface is exposed, thereby forming the first opening in the first dielectric layer.

14. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the second opening includes: forming a second patterned layer on the surface of the second dielectric layer, the second patterned layer exposing a portion of the surface of the second dielectric layer; using the second patterned layer as a mask, etching the second dielectric layer until the top surface of the second plug is exposed, forming a second opening in the second dielectric layer, and the bottom of the second opening exposes the top surface of the second plug.

15. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the third plug includes: forming a third conductive material film in the second opening and on the surface of the second dielectric layer; planarizing the third conductive material film until the surface of the second dielectric layer is exposed, and forming the third plug in the second opening.

16. The method for forming a semiconductor structure according to claim 15, wherein: The third conductive material film includes: a third conductive film located on the bottom surface and side wall surface of the second opening, and a fourth conductive film located on the surface of the third conductive film and the surface of the second dielectric layer.

17. The method for forming a semiconductor structure according to claim 16, wherein: The process of forming the third conductive film includes: a selective chemical vapor deposition process; the process of forming the fourth conductive film includes: a chemical vapor deposition process.

18. The method for forming a semiconductor structure according to claim 1, wherein: The material of the third plug includes: one or more combinations of titanium, nickel, copper, tungsten, aluminum, silver, and tantalum.

19. A semiconductor structure formed by the method according to any one of claims 1 to 18, characterized in that: include: A substrate, wherein a first dielectric layer is provided on a surface of the substrate; A first opening is located in the first dielectric layer, and the bottom of the first opening exposes the substrate surface; A groove located in the first opening and a first plug located at the bottom of the groove, and a first dielectric layer surface exposing a top surface of the groove; a second plug located in the groove, wherein the material of the second plug is different from the material of the first plug; a second dielectric layer located on the second plug and the surface of the first dielectric layer, and a second opening located in the second dielectric layer; A third plug is located in the second opening, and the third plug bottom is in contact with the second plug surface.

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