A power factor correction control circuit and a driving power supply

Abstract

The present invention discloses a power factor correction control circuit and a driving power supply. The circuit includes a grid input Vin, a rectifier bridge DB1, a capacitor C1, a capacitor C2, a switching transistor S1, a switching transistor S2, a switching transistor S3, a diode D1, an inductor L1, a resistor R1, a transformer T1, a first output rectifying circuit, an output capacitor Co, a power factor correction control circuit and a resonant control driving circuit. Beneficial effects: The present invention can prevent overstress of circuit devices and achieve the power factor correction function; the power factor correction control circuit and the driving power supply of the present invention have a simple circuit and convenient control. Compared with a two-stage circuit, the circuit cost is lower. Compared with a passive charge pump PFC, it can well balance the bus capacitance voltage and the power factor and can be applicable to a wide range of input and output load ranges.

Description

Technical Field

[0001] The present invention relates to the technical field of circuits and driving power supplies, and more particularly, to a power factor correction control circuit and a driving power supply. Background Art

[0002] In the field of power supplies, driving power supplies with high power density, high efficiency and low cost are more competitive. Usually, a resonant circuit is selected for a driving power supply to achieve the purpose of high power density and high efficiency. The resonant circuit can achieve zero-voltage turn-on of two or more switching tubes on the primary side and zero-current turn-off of the secondary rectifier diode, which can reduce the switching loss of the power supply and improve the efficiency and power density of the power converter. At the same time, in order to improve the power factor, an active PFC power factor correction circuit is often added in the front stage of the resonant circuit, but this will lead to a complex circuit and high cost.

[0003] Therefore, the prior art uses a charge pump circuit to replace the PFC (Power Factor Correction) circuit, so that a single-stage resonant circuit meets the power factor requirements. However, the resonant circuit with a charge pump has the following problems: when the circuit is under the working condition that the amplitude of the input voltage varies within a certain range, when the amplitude of the input voltage increases and the energy required by the resonant main circuit remains unchanged, the voltage on the bus capacitor will increase accordingly; or, when the output power of the resonant main circuit varies within a certain range (that is, the power required by the resonant main circuit varies within a certain range), when the output power decreases and the input voltage remains unchanged, the voltage on the bus capacitor will increase accordingly. If the voltage on the bus capacitor is at a relatively high amplitude level, the related devices of the subsequent resonant main circuit need to bear a relatively high voltage stress. Therefore, when designing the circuit, these devices of the resonant main circuit need to be selected according to the highest amplitude of the bus capacitor voltage for the withstand voltage performance. Devices with high withstand voltage performance are relatively expensive. For a circuit that works at a low amplitude of the bus capacitor voltage for a long time and occasionally works at a high amplitude of the bus capacitor voltage, it is too wasteful to choose devices with high withstand voltage performance but must choose them, otherwise the devices will be damaged due to the withstand voltage problem at the high amplitude of the bus capacitor voltage.

[0004] At the same time, the charge pump PFC, as a passive measure, is difficult to achieve ideal power factor correction in a wide input and load range, and the power factor and harmonic effects are not ideal.

[0005] In view of this, how to stably limit the voltage of the bus capacitor to a certain voltage value, avoid the voltage stress on the devices due to too high bus capacitor voltage, and achieve better power factor correction in a wide input and load range has become a technical problem that needs to be solved urgently by those skilled in the art.

[0006] In view of the problems in the related art, no effective solution has been proposed yet. Summary of the Invention

[0007] In view of the problems in the related art, the present invention provides a power factor correction control circuit and a driving power supply to overcome the above-mentioned technical problems existing in the existing related art.

[0008] For this purpose, the specific technical solution adopted by the present invention is as follows:

[0009] According to one aspect of the present invention, a power factor correction control circuit is provided. The power factor correction control circuit includes a grid input Vin, a rectifier bridge DB1, a capacitor C1, a capacitor C2, a switching transistor S1, a switching transistor S2, a switching transistor S3, a diode D1, an inductor L1, a resistor R1, a transformer T1, a first output rectifying circuit, an output capacitor Co, a power factor correction control circuit, and a resonant control driving circuit; the grid input Vin is connected to the first end and the third end of the rectifier bridge DB1, the second end of the rectifier bridge DB1 is sequentially connected to the positive electrode of the capacitor C1 and the first end of the switching transistor S1, the second end of the switching transistor S1 is sequentially connected to one end of the resistor R1 and the first end of the switching transistor S2, the other end of the resistor R1 is connected to one end of the inductor L1, the other end of the inductor L1 is connected to the first input terminal of the transformer T1, the second input terminal of the transformer T1 is connected to one end of the capacitor C2, the output terminal of the transformer T1 is connected in parallel with the first output rectifying circuit, the first output rectifying circuit is connected in parallel with the output capacitor Co, the other end of the capacitor C2 is sequentially connected to the first end of the switching transistor S3, the negative electrode of the diode D1, and the fourth end of the rectifier bridge DB1, the positive electrode of the diode D1 is sequentially connected to the negative electrode of the capacitor C1, the second end of the switching transistor S3, and the second end of the switching transistor S2 and grounded, the power factor correction control circuit is connected to the third end of the switching transistor S3, the first end of the resonant control driving circuit is connected to the third end of the switching transistor S1, and the second end of the resonant control driving circuit is connected to the third end of the switching transistor S2;

[0010] Among them, the power factor correction control circuit controls the conduction time of the switching transistor S3, which can limit and stabilize the voltage of the capacitor C1; when the current of the inductor L1 flows in the positive half cycle, by controlling the conduction time of the switching transistor S3, the magnitude of the current flowing through the rectifier bridge DB1 and the input grid Vin to the capacitor C1 can be controlled. The longer the conduction time of the switching transistor S3, the smaller the current charging the capacitor C1. On the contrary, the shorter the conduction time of the switching transistor S3, the larger the current charging the capacitor C1; when the conduction time of the switching transistor S3 is at a certain value, the charging and discharging currents of the capacitor C1 are equal, and the voltage of the capacitor C1 is in a steady state;

[0011] The power factor correction control circuit controls and modulates the conduction time and conduction duty cycle of the switching transistor S3 according to the input grid voltage, so that the average value of the current flowing through the rectifier bridge DB1 and the grid tracks the input grid voltage in the power frequency cycle, thereby realizing the power factor correction function;

[0012] The power factor correction control circuit samples the Vir signal, the Vin_rec signal of the full-wave rectified voltage obtained from the grid Vin, and the bus capacitor voltage Vbus, and adopts a dual-loop control method of an outer voltage loop and an inner loop average current control to realize the limitation and stable control of the bus voltage C1 and the power factor correction function of the grid.

[0013] Further, the capacitor C1 is a polarized capacitor.

[0014] Further, the capacitor Co is a polarized capacitor.

[0015] Further, the resonant control drive circuit obtains the desired output voltage Vo and current Io through feedback control; the power factor correction control circuit stabilizes the voltage of the capacitor C1 through feedback control to realize the power factor correction function.

[0016] Further, when the current of the inductor L1 flows from right to left in the negative half cycle, the diode D1 conducts and the rectifier bridge DB1 is cut off, and the current does not pass through the input grid Vin.

[0017] Further, when the current of the inductor L1 flows from left to right in the positive half cycle, if the switching transistor S3 conducts, the rectifier bridge DB1 is cut off, and the current does not pass through the input grid Vin.

[0018] Further, when the current of the inductor L1 flows from left to right in the positive half cycle, if the switching transistor S3 is turned off, the rectifier bridge DB1 conducts, and the current passes through the input grid Vin.

[0019] Further, the resonant control drive circuit provides energy to the output capacitor and the load through a transformer and a first output rectifier circuit.

[0020] Further, the resonant control drive circuit adopts frequency feedback control of the output voltage and output current, and its control method is similar to that of a general series resonance and series-parallel resonance circuit, symmetrically and complementarily driving the switching transistors S1 and S2, and obtaining the set output voltage Vo and output current Io through frequency control.

[0021] According to another aspect of the present invention, a drive power supply is provided, and the drive power supply is composed of the above-mentioned power factor correction control circuit.

[0022] The beneficial effects of the present invention are as follows:

[0023] The power factor correction control circuit and the driving power supply of the present invention limit and stabilize the voltage of the bus capacitor C1 by controlling the conduction time of the active switch tube S3, preventing overstress of circuit devices. At the same time, the input grid current is sampled, and a dual-loop average current control method is adopted. By controlling the conduction time of the active switch tube S3, the input current tracks the input grid voltage, realizing the power factor correction function. The power factor correction control circuit and the driving power supply of the present invention have a simple circuit and convenient control. Compared with two-stage circuits, the circuit cost is lower. Compared with passive charge pump PFCs, it can well balance the bus capacitance voltage and the power factor and can be applied to a wide range of input and output load ranges. Brief Description of the Drawings

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0025] Figure 1 is a schematic diagram of Embodiment 1;

[0026] Figure 2 is the voltage waveform diagram of Embodiment 1;

[0027] Figure 3 is Figure 1 a partial schematic diagram of;

[0028] Figure 4 is a schematic diagram of Embodiment 2;

[0029] Figure 5 is the voltage waveform diagram of Embodiment 2;

[0030] Figure 6 is Figure 4 the schematic diagram of the power factor correction control circuit in;

[0031] Figure 7 is Figure 6 the voltage waveform diagram of. Detailed Embodiments

[0032] To further illustrate the embodiments, the present invention provides drawings, which are part of the disclosure of the present invention. They are mainly used to illustrate the embodiments and can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. With reference to these contents, those of ordinary skill in the art should be able to understand other possible implementation manners and the advantages of the present invention. The components in the drawings are not drawn to scale, and similar component symbols are usually used to represent similar components.

[0033] According to an embodiment of the present invention, a power factor correction control circuit and a driving power supply are provided.

[0034] Embodiment 1

[0035] The present invention will be further described in conjunction with the accompanying drawings and specific embodiments. As Figures 1-3 shown, the power factor correction control circuit according to an embodiment of the present invention includes a grid input Vin, a rectifier bridge DB1, a capacitor C1, a capacitor C2, a switching transistor S1, a switching transistor S2, a switching transistor S3, a diode D1, an inductor L1, a resistor R1, a transformer T1, a first output rectifying circuit, an output capacitor Co, a power factor correction control circuit, and a resonant control driving circuit; the grid input Vin is connected to the first end and the third end of the rectifier bridge DB1, the second end of the rectifier bridge DB1 is sequentially connected to the positive electrode of the capacitor C1 and the first end of the switching transistor S1, the second end of the switching transistor S1 is sequentially connected to one end of the resistor R1 and the first end of the switching transistor S2, the other end of the resistor R1 is connected to one end of the inductor L1, the other end of the inductor L1 is connected to the first input terminal of the transformer T1, the second input terminal of the transformer T1 is connected to one end of the capacitor C2, the output terminal of the transformer T1 is connected in parallel with the first output rectifying circuit, the first output rectifying circuit is connected in parallel with the output capacitor Co, the other end of the capacitor C2 is sequentially connected to the first end of the switching transistor S3, the negative electrode of the diode D1, and the fourth end of the rectifier bridge DB1, the positive electrode of the diode D1 is sequentially connected to the negative electrode of the capacitor C1, the second end of the switching transistor S3, and the second end of the switching transistor S2 and grounded, the power factor correction control circuit is connected to the third end of the switching transistor S3, the first end of the resonant control driving circuit is connected to the third end of the switching transistor S1, and the second end of the resonant control driving circuit is connected to the third end of the switching transistor S2.

[0036] In one embodiment, the capacitor C1 is a polarized capacitor.

[0037] In one embodiment, the capacitor Co is a polarized capacitor.

[0038] In one embodiment, the resonant control driving circuit obtains a desired output voltage Vo and current Io through feedback control; the power factor correction control circuit stabilizes the voltage of the capacitor C1 through feedback control to achieve the power factor correction function.

[0039] In one embodiment, when the current in the inductor L1 flows from right to left in the negative half cycle, the diode D1 conducts, and the rectifier bridge DB1 cuts off, and the current does not pass through the input grid Vin.

[0040] In one embodiment, when the current of inductor L1 flows from left to right during the positive half cycle, if switch S3 is turned on, rectifier bridge DB1 is turned off, and the current does not pass through the input power grid Vin.

[0041] In one embodiment, when the current of inductor L1 flows from left to right during the positive half cycle, if switch S3 is turned off, rectifier bridge DB1 is turned on, and the current passes through the input power grid Vin.

[0042] In one embodiment, the resonant control drive circuit supplies energy to the output capacitor and the load through a transformer and a first output rectifier circuit.

[0043] In one embodiment, the resonant control drive circuit adopts frequency feedback control of the output voltage and the output current. Its control method is similar to that of general series resonance and series-parallel resonance circuits. It symmetrically and complementarily drives switch S1 and switch S2, and obtains the set output voltage Vo and output current Io through frequency control.

[0044] The present invention also provides a drive power supply, which is composed of the above-mentioned power factor correction control circuit.

[0045] In one embodiment, when switch S3 is always on, the input power grid Vin, rectifier bridge DB1, and capacitor C1 form an uncontrolled rectifier circuit without power factor correction function. At this time, the operating voltage of capacitor C1 is the lowest, and the grid current harmonic is also very large; the positive half-cycle resonant current of inductor L1 all passes through rectifier bridge DB1 and input power grid Vin to charge capacitor C1. The current flowing through switch S1 must be less than the positive half-cycle current of inductor L1. Therefore, the charging current is always greater than the discharging current, and the voltage of capacitor C1 will keep rising until the device is damaged; as Figure 2 and Figure 3 shown, the power factor correction control circuit controls the on-time of switch S3, which can limit and stabilize the voltage of capacitor C1. When the positive half-cycle current of inductor L1 flows, by controlling the on-time of switch S3, the magnitude of the current passing through rectifier bridge DB1 and input power grid Vin to charge capacitor C1 can be controlled. The longer the on-time of switch S3, the smaller the current charging capacitor C1. On the contrary, the shorter the on-time of switch S3, the larger the current charging capacitor C1. When the on-time of switch S3 is at a certain value, the charging and discharging currents of capacitor C1 are equal, and the voltage of capacitor C1 is in a steady state. Therefore, by controlling the on-time of switch S3, the voltage of capacitor C1 can be limited and stabilized, avoiding overstress of circuit devices.

[0046] In one embodiment, the power factor correction control circuit controls and modulates the conduction time and conduction duty ratio of the switching transistor S3 according to the input grid voltage, so that the average value of the current flowing through the rectifier bridge DB1 and the grid tracks the input grid voltage in the power frequency cycle, thereby realizing the power factor correction function, improving the power factor, and reducing the current harmonics.

[0047] In one embodiment, the power factor correction control circuit samples the Vir signal, the Vin_rec signal of the sinusoidal voltage obtained by rectifying the grid Vin, and the bus capacitor voltage Vbus, and adopts a dual-loop control method of an outer voltage loop and an inner loop average current control to realize the limitation and stable control of the bus voltage C1 and the power factor correction function of the grid.

[0048] Embodiment 2

[0049] As Figure 4 shown, the power factor correction control circuit according to an embodiment of the present invention includes a grid input Vin, a rectifier bridge DB1, a capacitor C1, a capacitor C2, a switching transistor S1, a switching transistor S2, a switching transistor S3, a diode D1, an inductor L1, a resistor R1, a transformer T1, a first output rectifier circuit, a second output rectifier circuit, an output capacitor Co, a power factor correction control circuit, and a resonant control drive circuit; the grid input Vin is connected to the first end and the third end of the rectifier bridge DB1, the second end of the rectifier bridge DB1 is sequentially connected to the positive electrode of the capacitor C1 and the first end of the switching transistor S1, the second end of the switching transistor S1 is sequentially connected to one end of the resistor R1 and the first end of the switching transistor S2 and grounded, the other end of the resistor R1 is sequentially connected to the first end of the power factor correction control circuit and one end of the inductor L1, the other end of the inductor L1 is connected to the first input terminal of the transformer T1, the second input terminal of the transformer T1 is connected to one end of the capacitor C2, the output terminal of the transformer T1 is connected in parallel with the first output rectifier circuit, the first output rectifier circuit is connected in parallel with the output capacitor Co, the other end of the capacitor C2 is sequentially connected to the first end of the switching transistor S3, the negative electrode of the diode D1, and the fourth end of the rectifier bridge DB1, the positive electrode of the diode D1 is sequentially connected to the negative electrode of the capacitor C1, the second end of the switching transistor S3, and the second end of the switching transistor S2, the Vg_S3 terminal of the power factor correction control circuit is connected to the third end of the switching transistor S3, the Vin_rec terminal of the power factor correction control circuit is connected to the second output rectifier circuit, the Vg_S1 terminal of the resonant control drive circuit is connected to the third end of the switching transistor S1, and the Vg_S2 terminal of the resonant control drive circuit is connected to the third end of the switching transistor S2.

[0050] In one embodiment, see Figure 6, the voltage across the sampling resistor R1 is used as a signal characterizing the resonant current of the inductor L1. Taking the connection midpoint of the switching transistors S1 and S2 as the reference ground for the sampling signal, the voltage across the two ends Vir = IL1 * R1. When the current of the inductor L1 flows forward from left to right, the Vir signal is negative. When the current of the inductor L1 flows backward from right to left, the Vir signal is positive. As Figure 4 shown, Figure 6 the driving signal of S4 in Figure 4 is the same as that of S3 in Figure 6 . After the Vir signal passes through the control of S4 in

[0051] , the obtained signal is proportional to the input current.

[0052] In one embodiment, the power factor correction control circuit samples the Vir signal, the full-wave rectified voltage Vin_rec signal obtained from the rectification of the grid voltage Vin, and the bus capacitor voltage Vbus, and adopts a dual-loop control method of an outer voltage loop and an inner average current loop to achieve the limiting and stable control of the bus voltage C1 and the grid power factor correction function. Figure 6 shown, the output Vcomp of the voltage loop feedback operational amplifier is multiplied by Vin_rec as the reference of the current inner loop, which is superimposed on the input current sampling signal and used as the in-phase input of the operational amplifier of the current inner loop. The output signal Icomp of the operational amplifier is compared with the signal generator signal Vt to trigger the control switching transistor S3 to conduct.

[0053] In one embodiment, when the current of the inductor L1 changes from the positive half-cycle to the negative half-cycle, the switching transistor S3 remains in the conducting state, replacing the diode D1 to conduct, reducing the conduction loss. When the negative half-cycle current flowing through the switching transistor S3 gradually decreases to the set comparison value, the switching transistor S3 is turned off.

[0054] In one embodiment, as Figure 5 and Figure 6 shown, the Vt signal is a sawtooth wave signal obtained by charging a capacitor C with a fixed constant current source. When it is detected that the Vir signal is higher than the set comparison threshold Vth, the constant current source charges the capacitor. When it is detected that the Vir signal is lower than the set comparison threshold Vth, the switch connected in parallel with the capacitor remains conducting and the Vt signal remains zero.

[0055] In one embodiment, as Figure 6 and Figure 7 shown, when it is detected that the Vir signal is lower than the set comparison threshold Vth and during the conduction period of the switching transistor S1, that is, when the driving signal HG is at a high level, the reset trigger latch is reset and the switching transistor S3 is turned off.

[0056] To facilitate the understanding of the above technical solutions of the present invention, the working principle or operation method of the present invention in the actual process will be described in detail below.

[0057] In practical applications, when switch tube S1 is turned on and switch tube S2 is turned off, and switch tube S3 or diode D1 is turned on, the current passes through switch tube S1, inductor L1, transformer T1, resonant capacitor C2, switch tube S3, diode D1 or capacitor C1;

[0058] When switch tube S1 is turned off and switch tube S2 is turned on, and switch tube S3 or diode D1 is turned on, the current passes through diode S2, inductor L1, transformer T1, resonant capacitor C2, switch tube S3 or diode D1;

[0059] When switch tube S1 is turned on and switch tube S2 is turned off, and switch tube S3 and diode D1 are turned off, the current passes through switch tube S1, inductor L1, transformer T1, resonant capacitor C2, rectifier bridge DB1, and input power grid Vin;

[0060] When switch tube S1 is turned off and switch tube S2 is turned on, and switch tube S3 and diode D1 are turned off, the current passes through switch tube S1, inductor L1, transformer T1, resonant capacitor C2, rectifier bridge DB1, and input power grid Vin.

[0061] In summary, for the power factor correction control circuit and the drive power supply of the present invention, by controlling the conduction time of the active switch tube S3, the voltage of the bus capacitor C1 is restricted and stabilized, preventing overstress of circuit devices. At the same time, the input power grid current is sampled, and a dual-loop average current control method is adopted. By controlling the conduction time of the active switch tube S3, the input current tracks the input power grid voltage, realizing the power factor correction function. The power factor correction control circuit and the drive power supply of the present invention have a simple circuit and convenient control. Compared with a two-stage circuit, the circuit cost is lower. Compared with a passive charge pump PFC, it can well balance the bus capacitance voltage and the power factor and can be applicable to a wide range of input and output load ranges.

[0062] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A power factor correction control circuit, characterized in that, It includes grid input Vin, rectifier bridge DB1, capacitor C1, capacitor C2, switching transistor S1, switching transistor S2, switching transistor S3, diode D1, inductor L1, resistor R1, transformer T1, first output rectification circuit, output capacitor Co, power factor correction control circuit and resonant control drive circuit; Among them, the grid input Vin is connected to the first end and the third end of the rectifier bridge DB1. The second end of the rectifier bridge DB1 is sequentially connected to the positive electrode of the capacitor C1 and the first end of the switching transistor S1. The second end of the switching transistor S1 is sequentially connected to one end of the resistor R1 and the first end of the switching transistor S2. The other end of the resistor R1 is connected to one end of the inductor L1. The other end of the inductor L1 is connected to the first input end of the transformer T1. The second input end of the transformer T1 is connected to one end of the capacitor C2. The output end of the transformer T1 is connected in parallel with the first output rectification circuit. The first output rectification circuit is connected in parallel with the output capacitor Co. The other end of the capacitor C2 is sequentially connected to the first end of the switching transistor S3, the negative electrode of the diode D1 and the fourth end of the rectifier bridge DB1. The positive electrode of the diode D1 is sequentially connected to the negative electrode of the capacitor C1, the second end of the switching transistor S3 and the second end of the switching transistor S2 and grounded. The power factor correction control circuit is connected to the third end of the switching transistor S3. The first end of the resonant control drive circuit is connected to the third end of the switching transistor S1. The second end of the resonant control drive circuit is connected to the third end of the switching transistor S2; Among them, the power factor correction control circuit controls the conduction time of the switching transistor S3, and can limit and stabilize the voltage of the capacitor C1. When the current of the inductor L1 flows in the positive half cycle, by controlling the conduction time of the switching transistor S3, the magnitude of the current flowing through the rectifier bridge DB1 and the input grid Vin to the capacitor C1 can be controlled. The longer the conduction time of the switching transistor S3, the smaller the current charging the capacitor C1. On the contrary, the shorter the conduction time of the switching transistor S3, the larger the current charging the capacitor C1. When the conduction time of the switching transistor S3 is at a certain value, the charging and discharging currents of the capacitor C1 are equal, and the voltage of the capacitor C1 is in a steady state. The power factor correction control circuit controls and modulates the conduction time and conduction duty ratio of the switching transistor S3 according to the input grid voltage, so that the average value of the current flowing through the rectifier bridge DB1 and the grid tracks the input grid voltage in the power frequency cycle, thus realizing the power factor correction function; The power factor correction control circuit samples the Vir signal, the chopped-wave voltage Vin_rec signal obtained by rectifying the grid Vin, and the bus capacitor voltage Vbus, and adopts a double-loop control method of voltage loop outer loop and inner loop average current control to realize the limiting and stable control of the bus voltage C1 and the power factor correction function of the grid; The voltage across the sampling resistor R1 is used as the signal characterizing the resonant current of the inductor L1; with the connection midpoint of the switching transistors S1 and S2 as the reference ground for the sampling signal, the voltage across the resistor R1, Vir = IL1 * R1; when the current of the inductor L1 flows forward from left to right, the Vir signal is negative; when the current of the inductor L1 flows backward from right to left, the Vir signal is positive. The Vir signal is connected to the positive terminal of the current inner loop, and also passes through the switch S4 to ground on this path, and the driving signal of S4 is the same as that of S3; after being controlled by S4, the Vir signal obtains the input current sampling signal, and the input current sampling signal is proportional to the input current; the product of the voltage loop feedback operational amplifier output Vcomp and Vin_rec is used as the reference of the current inner loop, which is superimposed on the input current sampling signal and used as the in-phase input of the current inner loop operational amplifier. The operational amplifier output signal Icomp is compared with the signal generator signal Vt to trigger the control of the switching transistor S3 to conduct. The Vt signal is a sawtooth wave signal obtained by charging the capacitor C with a fixed constant current source. When it is detected that the Vir signal is higher than the set comparison threshold Vth, the constant current source charges the capacitor; when it is detected that the Vir signal is lower than the set comparison threshold Vth, the switch connected in parallel with the capacitor remains conducting and the Vt signal remains zero. When it is detected that the Vir signal is lower than the set comparison threshold Vth and during the conduction period of the switching transistor S1, that is, when the driving signal HG is at a high level, the reset trigger latch is reset and the switching transistor S3 is turned off.

2. The power factor correction control circuit according to claim 1, characterized in that The capacitor C1 is a polarized capacitor.

3. A power factor correction control circuit according to claim 1, characterized in that, The capacitor Co is a polarized capacitor.

4. A power factor correction control circuit according to claim 1, characterized in that, The resonant control driving circuit obtains the desired output voltage Vo and current Io through feedback control; the power factor correction control circuit stabilizes the voltage of the capacitor C1 through feedback control to achieve the power factor correction function.

5. A power factor correction control circuit according to claim 1, characterized in that, When the current of the inductor L1 flows in the negative half cycle from right to left, the diode D1 conducts and the rectifier bridge DB1 is cut off, and the current does not pass through the input power grid Vin.

6. The power factor correction control circuit according to claim 1, wherein When the current of the inductor L1 flows in the positive half cycle from left to right, if the switching transistor S3 conducts, the rectifier bridge DB1 is cut off and the current does not pass through the input power grid Vin.

7. A power factor correction control circuit according to claim 1, wherein, When the current of the inductor L1 flows in the positive half cycle from left to right, if the switching transistor S3 is turned off, the rectifier bridge DB1 conducts and the current passes through the input power grid Vin.

8. A power factor correction control circuit according to claim 1, characterized in that, The grid input VIN or the capacitor C1 provides energy to the output capacitor and the load through the transformer and the first output rectification circuit.

9. The power factor correction control circuit according to claim 1, wherein, The resonant control driving circuit uses frequency feedback control of the output voltage and output current to symmetrically and complementarily drive the switching transistors S1 and S2, and obtains the set output voltage Vo and output current Io through frequency control.

10. A driving power supply, characterized in that, It includes the power factor correction control circuit according to any one of claims 1-9.

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