Image processing device

Abstract

An image processing device is provided, the image processing device comprising: a processing unit that performs image processing; a read DMAC (DMA Controller) for reading data from a memory and a write DMAC for writing data to the memory, which control access (Direct Memory Access) to the memory; an upper FIFO (First-In First-Out) unit that is connected to the read DMAC and the write DMAC and has a number of FIFOs corresponding to the number of channels of each DMAC; and a lower FIFO unit that is provided between the upper FIFO unit and the processing unit and has FIFOs corresponding to each FIFO of the upper FIFO unit at a ratio of 1 to F (where F is an integer greater than or equal to 2), and by not using a part of each of the F FIFOs corresponding to each FIFO of the upper FIFO unit, the number of rows of data input to the processing unit can be changed in units of the number of channels of the read DMAC.

Description

Technical Field

[0001] The present disclosure relates to an image processing device. Background Art

[0002] In the image processing device, the image is processed in a window unit of multiple pixels. In this image processing, the image is read line by line and stored in a memory, and the data of the line corresponding to the size of the window is read from the memory and processed. The data transfer between the operation core for image processing and the memory storing the data of each line is performed by DMA (Direct Memory Access).

[0003] Japanese Patent Application Laid-Open No. 2014-35619 discloses an image processing device including a plurality of image processing module units, a memory, and a DMAC (DMA Controller) for controlling memory access by the image processing modules. Summary of the invention

[0004] In image processing in units of windows, the image quality can be controlled by changing the size of the window. Here, in order to change the window size, when changing the number of rows of data corresponding to the window, it is necessary to change the number of channels of the DMAC that controls memory access.

[0005] An object of the present disclosure is to reduce the effort and time required to change the number of channels of a DMAC even when the window size is changed.

[0006] According to a first aspect of the present disclosure, an image processing device is provided, comprising: a processing unit that performs image processing; a read DMAC (DMA Controller) for reading data from a memory and a write DMAC for writing data to the memory, which control access to the memory (Direct Memory Access); an upper FIFO (First-InFirst-Out) unit that is connected to the read DMAC and the write DMAC and has a number of FIFOs corresponding to the number of channels of each DMAC; and a lower FIFO unit that is provided between the upper FIFO unit and the processing unit and has FIFOs corresponding to the respective FIFOs of the upper FIFO unit at a ratio of 1 to F, and by not using a part of each of the F FIFOs corresponding to each of the FIFOs of the upper FIFO unit, the number of rows of data input to the processing unit can be changed in units of the number of channels of the read DMAC, wherein F is an integer greater than or equal to 2.

[0007] According to the second aspect of the present disclosure, by excluding predetermined two lines of data from a plurality of lines of data input to the processing unit, the number of lines of data input to the processing unit can be changed in units of two lines.

[0008] According to the third aspect of the present disclosure, when excluding two lines of data among the plurality of lines of data input to the processing unit, the oldest data among the data read last from the image and the data read from the memory and obtained from the lower-level FIFO unit are excluded.

[0009] According to the fourth scheme of the present disclosure, the processing unit inputs and processes n rows of data consisting of 1 row read from the image and n-1 rows read from the memory and obtained from the lower-level FIFO unit, and outputs 1 row of processed data. The number of the upper-level FIFO units connected to the read DMAC is C corresponding to the number of channels of the read DMAC, where C is an integer greater than 1, and the number of the lower-level FIFO units corresponding to the upper-level FIFO unit connected to the read DMAC is C×F, and is n-1.

[0010] According to the fifth scheme of the present disclosure, the write DMAC is 1 channel, and the processing unit inputs n rows of row data consisting of row data N0 and row data N1~N(n-1) as processing objects, the row data N0 is the data of 1 row read last from the image, the row data N1~N(n-1) is the row data obtained from the lower-level FIFO unit, and is the data of n-1 rows read 1 time ago to n-1 times ago, and the processing unit sends F rows of row data NL among the input row data to the lower-level FIFO unit corresponding to the upper-level FIFO unit connected to the write DMAC, wherein L=C×(P-1), and P is an integer from 1 to F.

[0011] According to the sixth scheme of the present disclosure, in the upper-level FIFO unit and the lower-level FIFO unit on the write DMAC side, the data sent from the processing unit to the lower-level FIFO unit are sent to the upper-level FIFO unit one data at a time from each of the F lower-level FIFO units, and are sequentially written from the upper-level FIFO unit to the memory through the write DMAC, and in the upper-level FIFO unit and the lower-level FIFO unit on the read DMAC side, the data read from the memory through the read DMAC and stored in the C upper-level FIFO units are sequentially stored one data at a time in the F lower-level FIFO units of each of the upper-level FIFO units in the order of rows input to the processing unit.

[0012] (Effect)

[0013] According to the first aspect, compared with a configuration in which a single-stage FIFO unit is provided between the processing unit and the DMAC, it is possible to reduce the effort and time required to change the number of channels of the DMAC when changing the window size of the processing unit.

[0014] According to the second aspect, the window size of the processing unit can be controlled more finely than when the window size is controlled only by the FIFO of the lower-level FIFO unit.

[0015] According to the third aspect, compared with a configuration in which two consecutive lines of data are excluded, when the window size is changed, it is possible to reduce the labor and time required to change the line of output data.

[0016] According to the fourth aspect, compared with a configuration in which a single-stage FIFO unit is provided between the processing unit and the DMAC, the number of FIFOs in the lower-stage FIFO unit can be determined according to the number of channels of the DMAC and the number of inputs to the processing unit.

[0017] According to the fifth aspect, compared with a configuration in which a single-stage FIFO unit is provided between the processing unit and the DMAC, it is possible to extract line data held in the line buffer in accordance with the FIFO of the lower-stage FIFO unit.

[0018] According to the sixth aspect, compared with a configuration in which a single-stage FIFO unit is provided between the processing unit and the DMAC, line data can be written into the memory and provided to the processing unit based on the relationship between the upper-stage FIFO unit and the lower-stage FIFO unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a diagram showing the structure of an image processing device.

[0020] Figure 2 It is a diagram showing a configuration example of a processing unit.

[0021] Figure 3 : is a diagram showing the relationship between each FIFO of the upper FIFO unit and the input port of the processing unit.

[0022] Figure 4 2 is a diagram showing an example of controlling the window size.

[0023] Figure 5 is a diagram showing another configuration example of the image processing device.

[0024] Figure 6 : is a diagram showing the relationship between each FIFO of the upper FIFO unit and the input port of the processing unit.

[0025] Figure 7 2 is a diagram showing an example of controlling the window size.

[0026] Figure 8 FIG. 2 is a diagram showing another example of controlling the window size.

[0027] Fig. 9 is a flowchart showing the design procedure of the image processing apparatus.

[0028] Fig.10 This is a diagram showing the concept of image processing in this embodiment. DETAILED DESCRIPTION

[0029] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0030] <Overview of Image Processing Device>

[0031] The image processing device to which this embodiment is applied obtains data read from an image and performs image processing through a processing unit, i.e., a processor. The image is read for each line of a scanning line of an image reading device (e.g., an image input terminal; IIT), thereby obtaining image data. The image data for each line is referred to as line data. The line data is read line by line and stored in a line buffer.

[0032] The processor receives the last row read out, and obtains the row data of multiple (n-1) rows read out immediately before from the row buffer, performs image processing on the row data of n rows in total, and outputs the processed data of one row. In more detail, the processor performs image processing on the row data of n rows in a window unit of m (pixel) × n (row), and generates processed data representing one pixel of the window. Then, the processor shifts the window by one pixel along the row and performs image processing, obtains and outputs one row of processed data of one pixel.

[0033] Fig.10 FIG. 2 is a diagram showing the concept of image processing in this embodiment. Fig.10 In the example shown, the window size is 5 (pixels) x 5 (rows). Fig.10 The line data lineN0 of one line read out (recorded as “previous stage” in FIG. 1 ) is input to the processing unit 10 and sent to the line buffer for storage. The line data lineN1, lineN2, lineN3, and lineN4 of four lines read out and accumulated until immediately before are read out from the line buffer and input to the processing unit 10 together with the line data lineN0 read out last.

[0034] The processing unit 10 performs image processing on the acquired 5 lines of line data (lineN0 to N4) by shifting the window size of 5 (pixels) × 5 (lines) by one pixel and applying the shifted window to generate processed data. The processed data is generated as data of the position of any pixel in the window. In the example shown in the figure, the processed data is generated as data of the position of the third pixel from the left end (or right end) of the pixel (lineN2) in the center of the 5 (pixel) × 5 (line) window. Then, the line data of one line generated by shifting the window by one pixel is output as the processed data of lineN2 and sent to the subsequent device (for example, the image output terminal: IOT).

[0035] In addition, the window size is set to a square of 5 (pixels) × 5 (rows) for explanation. In more detail, the number of rows of the window size is determined by the number of row data input to the processing unit 10, but the number of pixels can be set according to the processing capacity of the processing unit 10, etc. Therefore, the window set in the processing unit 10 is not necessarily limited to a square window with the same number of pixels as the number of rows. In the following, when the window size is mentioned, only the number of rows is determined, and the number of pixels is not determined.

[0036] <Structure of Image Processing Device>

[0037] Figure 1 1 is a diagram showing the structure of an image processing device. The image processing device 1 includes a processing unit 10, a memory 20 constituting a line buffer, a DMAC 30, an upper FIFO unit 40, a lower FIFO unit 50, and a bus bridge 60. The DMAC 30 includes a write DMAC 31 and a read DMAC 32. The upper FIFO unit 40 and the lower FIFO unit 50 are each configured to have a plurality of FIFOs.

[0038] The processing unit 10 is a processor that performs filtering processing on electronic data of an image, and is a so-called digital filter. The processing unit 10 performs processing in units of windows composed of a plurality of pixels. As described above, the processing unit 10 reads in a number of line data corresponding to the window size (in Figure 1 In the example, lineN0 to N8), output the processed row data of one row (in Figure 1 In the example, lineN4). In addition, the processing unit 10 directly outputs a portion of the line data read in (in Figure 1 In the example, lineN0 and lineN4 are transmitted to the line buffer. The line data to be transmitted will be described later.

[0039] The memory 20 is a storage unit that stores the line data of the image read out line by line. As the memory 20, for example, a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory) is used. The memory 20 may also be a memory shared with a working memory in the calculation processing performed by the CPU.

[0040] The DMAC 30 is a DMA controller that controls memory access in the image processing apparatus 1 .

[0041] The DMAC 30 includes a write DMAC 31 for writing data to the memory 20 and a read DMAC 32 for reading data from the memory 20. The write DMAC 31 writes data using one channel. The read DMAC 32 reads data using multiple channels. Figure 1 In the illustrated configuration example, the read DMAC 32 has four channels.

[0042] The upper FIFO unit 40 and the lower FIFO unit 50 are buffers for the DMAC 30 to read and write data to and from the memory 20. The upper FIFO unit 40 is connected to the DMAC 30. The lower FIFO unit 50 is provided between the upper FIFO unit 40 and the processing unit 10.

[0043] The upper FIFO unit 40 has a number of FIFOs (First-In First-Out) corresponding to the number of channels of the write DMAC 31 and the read DMAC 32. Regarding the number of FIFOs of the upper FIFO unit 40 connected to the write DMAC 31, there is one FIFO 45 corresponding to the number of channels of the write DMAC 31. The number of FIFOs of the upper FIFO unit 40 connected to the read DMAC 32 is C (where C is an integer greater than 1) corresponding to the number of channels of the read DMAC 32. Figure 1 In the illustrated configuration example, C=4, and four FIFOs 41 to 44 are provided.

[0044] The lower FIFO unit 50 has FIFOs corresponding to the FIFOs 41 to 45 of the upper FIFO unit 40 at a ratio of 1 to F (where F is an integer greater than or equal to 2). Figure 1 In the illustrated configuration example, F = 2. Therefore, the total number of FIFOs of the lower FIFO unit 50 corresponding to the FIFOs 41 to 44 of the upper FIFO unit 40 connected to the read DMAC 32 is C×F.

[0045] Here, the total number of row data input to the processing unit 10 is assumed to be n. That is, the number of row data read from the memory 20 among the row data input to the processing unit 10 is n-1. On the other hand, the lower-level FIFO unit 50 is connected to the processing unit 10, so the number of FIFOs of the lower-level FIFO unit 50 is n-1 corresponding to the number of row data read from the memory 20 and input to the processing unit 10. That is, regarding the number of FIFOs of the lower-level FIFO unit 50 on the read DMAC 32 side,

[0046] C×F=n-1

[0047] Established.

[0048] exist Figure 1 In the illustrated configuration example, C=4, n=9 (9 lines N0 to N8), and therefore F=2. That is, the lower FIFO unit 50 has two FIFOs 51a, b to 54a, b for each of the FIFOs 41 to 44 of the upper FIFO unit 40 on the read DMAC 32 side. In addition, similarly on the write DMAC 31 side, the lower FIFO unit 50 has two FIFOs 55a, b for each of the FIFOs 41 to 44 of the upper FIFO unit 40.

[0049] The bus bridge 60 is a bridge circuit interposed between the memory 20 and the DMAC 30. The DMAC 30 is connected to the memory 20 via the bus bridge 60 to read and write data.

[0050] <Data Transfer Between Processing Unit 10 and Line Buffer>

[0051] Next, refer to Figure 1 The configuration example shown in FIG. 1 illustrates data transfer between the processing unit 10 and the line buffer. Figure 1 In the illustrated configuration example, the processing unit 10 has 9 input ports (N0 to N8). The line data read out last from the image is input to the input port N0. The line data of 8 lines obtained from the line buffer is input to the input ports N1 to N8. Generally speaking, the line data read out last from the image is input to the input port N0 among the n input ports, and the line data of n-1 lines obtained from the line buffer is input to the input ports N1 to N(n-1).

[0052] The arrangement of input ports N1 to N8 corresponds to the age of row data. Specifically, the row data read immediately before the row data input to input port N0 is input to input port N1, and the row data read one row before that is input to input port N2. Similarly, the row data read out of the first eight rows is input to input port N8 in a row-by-row manner.

[0053] Input ports N1 to N8 are connected individually to FIFO51a, b to 54a, b of the lower FIFO unit 50 on the read DMAC 32 side. Specifically, input port N1 is connected to FIFO51a of the lower FIFO unit 50. Input port N2 is connected to FIFO52a of the lower FIFO unit 50. Input port N3 is connected to FIFO53a of the lower FIFO unit 50. Input port N4 is connected to FIFO54a of the lower FIFO unit 50. Input port N5 is connected to FIFO51b of the lower FIFO unit 50. Input port N6 is connected to FIFO52b of the lower FIFO unit 50. Input port N7 is connected to FIFO53b of the lower FIFO unit 50. Input port N8 is connected to FIFO54b of the lower FIFO unit 50.

[0054] In addition, the processing unit 10 has one output port (N4 (output)) for outputting output data of the processing result, and two output ports (N0, N4) for directly outputting row data input from the input port. The output port corresponds to the middle row (N4) of all row data N0 to N8 input from the input port. In addition, in the following description, in order to distinguish from the output port for outputting the processing result, the output port for directly outputting the input row data is referred to as a "transmission port". The row data input to the input port N0 is output from the transmission port N0, and the row data input to the input port N4 is output from the transmission port N4.

[0055] Generally, the transfer ports are set as follows. First, the output port (transfer port N0) corresponding to the input port N0. Then, among the input ports corresponding to the line data from the line buffer, the input ports that are located at positions that are integer multiples of the number of channels C of the read DMAC 32 are set (in the order of N1 (new side)). Figure 1 In the example, N4 and N8), and the input port corresponding to the last (earliest) row data (in Figure 1 In the example, N8) other than the input port (in Figure 1 That is, let C be the number of channels of the read DMAC 32, let P be an integer from 1 to F (F is the number of FIFOs of the lower FIFO unit 50 for one FIFO of the upper FIFO unit 40), and set the output port NL corresponding to the input port NL (L=C×(P-1)) as the transmission port.

[0056] The transmission port N0 is connected to the FIFO55a of the lower FIFO unit 50. The transmission port N4 is connected to the FIFO55b of the lower FIFO unit 50. Then, the line data output from the transmission ports N0 and N4 is supplied to the FIFO55a and b of the lower FIFO unit 50 on the write DMAC 31 side. Figure 1 In the example of , specifically, the output of the transmission port N0 is supplied to the FIFO 55a, and the output of the transmission port N4 is supplied to the FIFO 55b.

[0057] exist Figure 1 , the (L N0, P 1 ) etc. represent the information (corresponding port, synchronization information) inherent to each line of data supplied to and held by FIFO55a, b. For example, (L N0, P 1 ) and FIFO55b's (L N4 ,P 1 ) means that in the same P 1 The row data is output from the transmission port N0 and the transmission port N4 at the timing of FIFO55b. N4 ,P 1 )(L N4 ,P 2 )(L N4 ,P 3 )(L N4 ,P 4 )…… indicates that the transmission port N4 is 1 , P 2 , P 3 , P 4 ,... The row data is output at each timing in the order of .

[0058] The line data held in the FIFOs 55a and 55b of the lower FIFO unit 50 are alternately transferred to the FIFO 45 of the upper FIFO unit 40. Figure 1 In the example, according to (L N0, P 1 )(L N4 ,P 1 )(L N0, P 2 )(L N4 ,P 2 The write DMAC 31 sequentially reads the line data from the FIFO 45 and stores the line data in the memory 20 via the bus bridge 60 .

[0059] More generally, in the FIFO 45 of the upper FIFO unit 40 and the FIFO 55a, b of the lower FIFO unit 50 on the write DMAC 31 side, the line data sent from the processing unit 10 to the lower FIFO unit 50 are sent one data at a time from each FIFO 55a, b to the FIFO 45 of the upper FIFO unit 40. Then, the line data are sequentially written from the FIFO 45 to the memory 20 via the write DMAC 31.

[0060] The read DMAC 32 reads line data of the number of its own channels from the memory 20 via the bus bridge 60 and stores them in the FIFOs 41 to 44 of the upper FIFO unit 40. The line data supplied to the FIFOs 51a and 51b of the lower FIFO unit 50 are alternately stored in the FIFO 41. Figure 1 In the example shown, if (L N1 ,P 1 )(L N5 ,P 1 )(L N1 ,P 2 )(L N5 ,P 2 ) ... so that the line data is held in the FIFO 41. Here, when the line data is read out from the memory 20, one cycle is advanced from the time when the line data is written into the memory 20, and new line data L is input. N Therefore, from FIFO45 as (L N0, P 1 )(L N4 ,P 1 ) is written into the row data in the memory 20 as (L N1 ,P 1 )(L N5 ,P 1 ) is read out.

[0061] The line data supplied to the FIFO 52a and 52b of the lower FIFO unit 50 are alternately held in the FIFO 42. Figure 1 In the example, such as (L N2 ,P 1 )(L N6 ,P 1 )(L N2 ,P 2 )(L N6 ,P 2 ) ... and the line data is held in FIFO 42. Here, the line data supplied to FIFO 42 is the line data supplied to FIFO 41 in the immediately previous cycle. Then, the new line data L is read in by advancing one cycle. N As a result, each line of data read from the memory 20 is shifted by one line and supplied to the FIFO 42 .

[0062] The line data supplied to the FIFO 53a and 53b of the lower FIFO unit 50 are alternately held in the FIFO 43. Figure 1 In the example, such as (L N3 ,P 1 )(L N7 ,P 1 )(LN3 ,P 2 )(L N7 ,P 2 ) ... and hold the line data in FIFO 43. Here, the line data supplied to FIFO 43 is the line data supplied to FIFO 42 in the immediately previous cycle. Then, the new line data L is read in by advancing one cycle. N As a result, each line of data read from the memory 20 is shifted by one line and supplied to the FIFO 43 .

[0063] The line data supplied to the FIFO 54a and 54b of the lower FIFO unit 50 are alternately held in the FIFO 44. Figure 1 In the example, such as (L N4 ,P 1 )(L N8 ,P 1 )(L N4 ,P 2 )(L N8 ,P 2 ) ... and hold the line data in FIFO 44. Here, the line data supplied to FIFO 44 is the line data supplied to FIFO 43 in the immediately previous cycle. Then, the new line data L is read in by advancing one cycle. N As a result, each line of data read from the memory 20 is shifted by one line and supplied to the FIFO 44 .

[0064] The line data is transferred alternately from the FIFO 41 to the FIFOs 51a and 51b of the lower FIFO unit 50. Figure 1 In the example shown, if (L N1 ,P 1 )(L N1 ,P 2 )(L N1 ,P 3 )(L N1 ,P 4 )... to transfer row data to FIFO51a, such as (L N5 ,P 1 )(L N5 ,P 2 )(L N5 ,P 3 )(L N5 ,P 4 )... and transmit line data to FIFO51b. Similarly, FIFO42 transmits line data to FIFO52a and FIFO52b alternately, FIFO43 transmits line data to FIFO53a and FIFO53b alternately, and FIFO44 transmits line data to FIFO54a and FIFO54b alternately. Figure 1 In the example shown, if (L N2 ,P1 )(L N2 ,P 2 )(L N2 ,P 3 )(L N2 ,P 4 )... to transmit row data to FIFO52a, such as (L N6 ,P 1 )(L N6 ,P 2 )(L N6 ,P 3 )(L N6 ,P 4 )... to transfer row data to FIFO52b. N3 ,P 1 )(L N3 ,P 2 )(L N3 ,P 3 )(L N3 ,P 4 )... to transmit row data to FIFO53a, such as (L N7 ,P 1 )(L N7 ,P 2 )(L N7 ,P 3 )(L N7 ,P 4 )... to transfer line data to FIFO53b. N4 ,P 1 )(L N4 ,P 2 )(L N4 ,P 3 )(L N4 ,P 4 )... to transmit row data to FIFO54a, such as (L N8 ,P 1 )(L N8 ,P 2 )(L N8 ,P 3 )(L N8 ,P 4 )……then transmit row data to FIFO54b.

[0065] More generally speaking, in the FIFOs 41 to 44 of the upper FIFO unit 40 and the FIFOs 51a, b to 54a, b of the lower FIFO unit 50 on the read DMAC 32 side, the row data read from the memory 20 by the read DMAC 32 and stored in the FIFOs 41 to 44 are stored one by one in the order of the rows input to the processing unit 20 in the FIFOs 51a, b to 54a, b of the lower FIFO unit 50 corresponding to the FIFOs 41 to 44 of the upper FIFO unit 40.

[0066] Then, the same synchronization information (P 1 , P 2 , P 3 , P 4 Each time, the newly read row data is input to the input port N0 of the processing unit 10.

[0067] <Structure of Processing Unit 10>

[0068] Figure 2 1 is a diagram showing a configuration example of the processing unit 10. The processing unit 10 includes a computing core 11, an input unit 12, and an output unit 13. The input unit 12 includes a plurality of input interfaces (I / F) 121 constituting input ports, and a data selector 122 for controlling the opening / closing (ON / OFF) of the input ports. Figure 1 In the case of the structure shown in FIG. 1 , the number of input I / Fs 121 is 9 corresponding to the input ports N0, N1 to N8. A data selector 122 is provided for the input I / Fs 121 constituting each input port other than the input port N0. Figure 1 In the case of the structure shown in FIG. 1 , the number of data selectors 122 is 8 corresponding to the input ports N1 to N8. The input I / F 121 constituting the input port N0 inputs the image from the image reading unit (in Figure 2 The data last read out is recorded as "previous stage" in the figure.

[0069] The output unit 13 includes a plurality of output interfaces (I / F) 131 constituting output ports (including transmission ports), and a data selector 132 for controlling the opening / closing (ON / OFF) of the output ports. Figure 1 In the case of the illustrated configuration, the number of output I / Fs 131 is three corresponding to the output port N4 and the transmission ports N0 and N4. A data selector 132 is provided for each of the transmission ports N0 and N4, and the number of data selectors 132 is two.

[0070] <Relationship between the FIFOs 41 to 45 of the upper FIFO unit 40 and the input port of the processing unit 10>

[0071] Figure 3 4 is a diagram showing the relationship between the FIFOs 41 to 45 of the upper FIFO unit 40 and the input port of the processing unit 10. Figure 3 , the timing (each cycle) of inputting the row data of the 100th to 105th rows based on the image reading to the input row (input port N0) is shown, the row data input to each input port N0, N1 to N8 of the processing unit 10, and the row data held in each FIFO41 to 45 of the upper FIFO unit 40.

[0072] Reference Figure 3 For example, when the 100th row of line data is input to the input port N, the following row data is held in the FIFOs 41 to 44 on the read DMAC 32 side. Figure 3 For example, the row data of the 99th row is recorded as "L99".

[0073] FIFO41:(L N1 ,P 1 )(L N5 ,P 1 )→L99, L95

[0074] FIFO42:(L N2 ,P 1 )(L N6 ,P 1 )→L98, L94

[0075] FIFO43:(L N3 ,P 1 )(L N7 ,P 1 )→L97, L93

[0076] FIFO44:(L N4 ,P 1 )(L N8 ,P 1 )→L96, L92

[0077] This is distributed to FIFO51a, b to 54a, b of the lower FIFO unit 50, and is transmitted to the input ports N1 to N8 as follows. That is, the data is input in the order of N8 → N1 from the earlier row data. Figure 3 In FIG. 1 , the input port N1 is represented as “portN1”.

[0078] Input port N8: L92

[0079] Input port N7: L93

[0080] Input port N6: L94

[0081] Input port N5: L95

[0082] Input port N4: L96

[0083] Input port N3: L97

[0084] Input port N2: L98

[0085] Input port N1: L99

[0086] In this cycle, the line data "L100" of the 100th line is input to the input port N0 as described above. In the next cycle, the line data "L101" of the 101st line is input to the input port N0. In addition, the line data read out to the read DMAC 32 and stored in the FIFOs 41 to 44 and the line data assigned to the input ports N1 to N8 are shifted to the newer side one line at a time from the above state.

[0087] Here, we focus on the row data output from the transmission ports N0 and N4. The inputs to the input ports N0 and N4 are directly output from the transmission ports N0 and N4. Therefore, when the row data (L100) of the 100th row is input to the input port N0, the output of the transmission port N0 becomes L100, and the output of the transmission port N4 becomes L96. Therefore, the FIFO 45 on the write DMAC 31 side holds L100. N =L100, L N4 =L96. Figure 3 In the figure, the positions of L100 and L96 are shown by hatching. As shown in the figure, new row data is input from input port N0 every cycle, and the positions of the input ports input to L100 and L96 are shifted one row at a time. Similarly, FIFOs 41 to 44 that hold L100 and L96 read from memory 20 are shifted one by one.

[0088] <Window size control>

[0089] Next, Figure 1 In this embodiment, the control of the window size of the image processing device configured as above is described. In the line buffer of the image processing device, the FIFO for holding the line data read and written by the DMAC 30 is set to multiple stages. Furthermore, the multiple FIFOs (in the lower FIFO section 50) of the lower FIFO section 50 are Figure 1 FIFO 51a, b to 55a, b) and the FIFO of the upper FIFO unit 40 (in Figure 1 Thus, the number of input lines to the processing unit 10 is increased without changing the number of channels of the DMAC 30, thereby expanding the window size in the processing unit 10.

[0090] exist Figure 1 In the example, the number of channels of the read DMAC 32 is 4, and in the case of the 1st-level FIFO (FIFO41~44 of the upper FIFO unit 40), the window size becomes 5 rows together with the input row for the input port N0. However, by adding FIFO51a, b~54a, b of the lower FIFO unit 50, the window size becomes 9 rows in combination with the input row for the input port N0. Here, by making part of the FIFO51a, b~55a, b of the lower FIFO unit 50 corresponding to each FIFO41~45 of the upper FIFO unit 40 inactive, the window size can be changed (reduced).

[0091] Figure 4 FIG. 4 is a diagram showing an example of controlling the window size. Figure 4 In the example shown, FIFO51b, 52b, 53b, 54b, 55b of FIFO51a, b to 55a, b of the lower FIFO unit 50 are deactivated, and only FIFO51a, 52a, 53a, 54a, 55a are used. Thus, the window size is changed (reduced) to 5 rows without changing the structure of DMAC30 and upper FIFO unit 40.

[0092] Regarding the input ports of the processing unit 10, the input port N0 connected to the input row and the input ports N1 to N4 connected to the FIFOs 51a, 52a, 53a, and 54a are used, and the input ports N5 to N8 are not used. In this case, the data selector 122 (see Figure 2 ) The input ports N5 to N8 are blocked. Since there is no input of row data from FIFO51b, 52b, 53b, and 54b, the input ports N5 to N8 do not need to be blocked intentionally.

[0093] The valid input ports of the processing unit 10 are N0 to N4, so the output port is changed to the middle row of them, that is, N2. In addition, regarding the transmission port of the processing unit 10, the transmission port N0 that outputs the input to the input port N0 is used, and the transmission port N4 that outputs the input to the input port N4 is not used. In this case, the data selector 132 (see Figure 2 ) blocks the transmission port N4, and the input to the input port N4 is not transmitted to FIFO55b.

[0094] <Another Configuration Example of Image Processing Device 1>

[0095] Figure 5 is a diagram showing another configuration example of the image processing device. Figure 5 The image processing device 1 shown in FIG. Figure 1Compared with the structure shown in FIG. 1 , the number of FIFOs in the lower FIFO unit 50 is different. The lower FIFO unit 50 has FIFOs corresponding to the FIFOs 41 to 45 of the upper FIFO unit 40 at a ratio of 1 to F. Figure 5 In the structure shown, F=3. That is, the lower FIFO unit 50 has three FIFOs 51a, b, c to 54a, b, c for the FIFOs 41 to 44 of the upper FIFO unit 40 on the read DMAC 32 side. In addition, on the write DMAC 31 side, the lower FIFO unit 50 has three FIFOs 55a, b, c for the one FIFO 45 of the upper FIFO unit 40.

[0096] Furthermore, when C corresponding to the number of channels of the read DMAC 32 and the total number of row data input to the processing unit 10 are n,

[0097] C×F=n-1

[0098] therefore,

[0099] n=C×F+1=4×3+1=13

[0100] The total number of row data input to the processing unit 10 is 13. Figure 5 In the structure shown, line N0 to N12 are input. In addition, the processing unit 10 outputs the processed line data line N6. Furthermore, the processing unit 10 directly outputs the lines N0, N4, and N8 among the read line data, and transfers them to the line buffer.

[0101] exist Figure 5 In the image processing device 1 shown in FIG. Figure 1 The same as the image processing device 1 shown in FIG. Figure 5 In the image processing device 1 shown in FIG. 1 , the number of channels of the read DMAC 32 and the number of FIFOs of the upper FIFO unit 40 are the same as those of the upper FIFO unit 40. Figure 1 The structure shown is the same, but the number of FIFOs of the lower FIFO unit 50 is increased, thereby increasing the number of input lines of the processing unit 10 and enlarging the size of the window of the processing unit.

[0102] < Figure 5 Data transmission between the processing unit 10 and the line buffer in the image processing device 1 shown>

[0103] Next, refer to Figure 5 The configuration example shown in FIG. 1 illustrates data transfer between the processing unit 10 and the line buffer. Figure 5In the illustrated structural example, the processing unit 10 has 13 input ports (N0 to N12). The row data read out last from the image is input to the input port N0. The row data of 12 rows obtained from the row buffer is input to the input ports N1 to N12. The arrangement of the input ports N1 to N12 corresponds to the age of the row data. Specifically, the row data read out immediately before the row data input to the input port N0 is input to the input port N1, and the row data read out one row before is input to the input port N2. Similarly, the row data read out of the first 12 rows is input to the input port N12, tracing back one row at a time.

[0104] Input ports N1 to N12 are individually connected to FIFO51a, b, c to 54a, b, c of the lower-level FIFO unit 50 on the read DMAC 32 side. Specifically, input port N1 is connected to FIFO51a of the lower-level FIFO unit 50. Input port N2 is connected to FIFO52a of the lower-level FIFO unit 50. Input port N3 is connected to FIFO53a of the lower-level FIFO unit 50. Input port N4 is connected to FIFO54a of the lower-level FIFO unit 50. Input port N5 is connected to FIFO51b of the lower-level FIFO unit 50. Input port N6 is connected to FIFO52b of the lower-level FIFO unit 50. Input port N7 is connected to FIFO53b of the lower-level FIFO unit 50. Input port N8 is connected to FIFO54b of the lower-level FIFO unit 50. So far, Figure 1 The connection relationship in the structural example shown is the same. Figure 5 In the illustrated configuration example, the input port N9 is further connected to the FIFO51c of the lower FIFO unit 50. The input port N10 is connected to the FIFO52c of the lower FIFO unit 50. The input port N11 is connected to the FIFO53c of the lower FIFO unit 50. The input port N12 is connected to the FIFO54c of the lower FIFO unit 50.

[0105] In addition, the processing unit 10 has one output port (N6 (output)) for outputting output data of the processing result, and three transmission ports (N0, N4, N8) for directly outputting row data input from the input port. The row data input to the input port N0 is output from the transmission port N0, the row data input to the input port N4 is output from the transmission port N4, and the row data input to the input port N8 is output from the transmission port N8.

[0106] By reference Figure 1The described method for setting the transmission port sets, as the transmission port, an output port corresponding to the input port N0, and input ports (N4, N8, N12) located at positions that are integer multiples of the number of channels C of the read DMAC32 among the input ports corresponding to the row data from the row buffer, and an output port corresponding to the input ports (N4, N8) other than the input port (N12) corresponding to the last row data.

[0107] The transmission port N0 is connected to the FIFO55a of the lower FIFO unit 50. In addition, the transmission port N4 is connected to the FIFO55b of the lower FIFO unit 50. In addition, the transmission port N8 is connected to the FIFO55c of the lower FIFO unit 50. Furthermore, the row data output from the transmission ports N0, N4, and N8 are supplied to the FIFO55a, b, and c of the lower FIFO unit 50 on the write DMAC 31 side. Figure 5 In the example of FIG. 5 , specifically, the output of the transmission port N0 is supplied to the FIFO 55 a , the output of the transmission port N4 is supplied to the FIFO 55 b , and the output of the transmission port N8 is supplied to the FIFO 55 c .

[0108] The line data held in the FIFOs 55a, b, and c of the lower FIFO unit 50 are alternately transferred to the FIFO 45 of the upper FIFO unit 40. Figure 5 In the example, according to (L N0, P 1 )(L N4 ,P 1 )(L N8 ,P 1 )(L N0, P 2 The write DMAC 31 sequentially reads the line data from the FIFO 45 and stores the line data in the memory 20 via the bus bridge 60 .

[0109] The read DMAC 32 reads out line data of the number of its own channels from the memory 20 via the bus bridge 60 and stores them in the FIFOs 41 to 44 of the upper FIFO unit 40. The line data supplied to the FIFOs 51a, b, and c of the lower FIFO unit 50 are alternately stored in the FIFO 41. Figure 5 In the example shown, if (L N1 ,P 1 )(L N5 ,P 1 )(L N9 ,P 1 )(L N1 ,P 2 )……..so as to maintain the row data in FIFO41.

[0110] The line data supplied to the FIFO 52a, b, and c of the lower FIFO unit 50 are alternately held in the FIFO 42. Figure 5 In the example, such as (L N2 ,P 1 )(L N6 ,P 1 )(L N10 ,P 1 )(L N2 ,P 2 ) ... and hold the line data in the FIFO 42. The line data supplied to the FIFO 42 was supplied to the FIFO 41 in the immediately preceding cycle, and is supplied from the memory 20 to the FIFO 42 with a shift of one line.

[0111] The line data supplied to the FIFO 53a, b, and c of the lower FIFO unit 50 are alternately held in the FIFO 43. Figure 5 In the example, such as (L N3 ,P 1 )(L N7 ,P 1 )(L N11 ,P 1 )(L N3 ,P 2 ) ... and hold the line data in the FIFO 43. The line data supplied to the FIFO 43 was supplied to the FIFO 42 in the immediately preceding cycle, and is supplied to the FIFO 43 from the memory 20 with a shift of one line.

[0112] The line data supplied to the FIFO 54a, b, and c of the lower FIFO unit 50 are alternately held in the FIFO 44. Figure 5 In the example, such as (L N4 ,P 1 )(L N8 ,P 1 )(L N12 ,P 1 )(L N4 ,P 2 ) ... and hold the line data in the FIFO 44. The line data supplied to the FIFO 44 was supplied to the FIFO 43 in the immediately preceding cycle, and is supplied from the memory 20 to the FIFO 44 with a shift of one line.

[0113] The line data is transferred alternately from the FIFO 41 to the FIFOs 51a, b, and c of the lower FIFO unit 50. Figure 5 In the example shown, if (L N1 ,P 1 )(L N1 ,P 2 )(L N1 ,P3 )(L N1 ,P 4 )... to transfer row data to FIFO51a, such as (L N5 ,P 1 )(L N5 ,P 2 )(L N5 ,P 3 )(L N5 ,P 4 )... to transfer row data to FIFO51b, such as (L N9 ,P 1 )(L N9 ,P 2 )(L N9 ,P 3 )(L N9 ,P 4 )... and transmit line data to FIFO51c. Similarly, FIFO42 transmits line data to FIFO52a, b, and c alternately, FIFO43 transmits line data to FIFO53a, b, and c alternately, and FIFO44 transmits line data to FIFO54a, b, and c alternately. Figure 5 In the example shown, if (L N2 ,P 1 )(L N2 ,P 2 )(L N2 ,P 3 )(L N2 ,P 4 )... to transmit row data to FIFO52a, such as (L N6 ,P 1 )(L N6 ,P 2 )(L N6 ,P 3 )(L N6 ,P 4 )... to transmit row data to FIFO52b, such as (L N10 ,P 1 )(L N10 ,P 2 )(L N10 ,P 3 )(L N10 ,P 4 )... to transfer line data to FIFO52c. N3 ,P 1 )(L N3 ,P 2 )(L N3 ,P 3 )(L N3 ,P4 )... to transmit row data to FIFO53a, such as (L N7 ,P 1 )(L N7 ,P 2 )(L N7 ,P 3 )(L N7 ,P 4 )... to transmit row data to FIFO53b, such as (L N11 ,P 1 )(L N11 ,P 2 )(L N11 ,P 3 )(L N11 ,P 4 )... to transfer line data to FIFO53c. N4 ,P 1 )(L N4 ,P 2 )(L N4 ,P 3 )(L N4 ,P 4 )... to transmit row data to FIFO54a, such as (L N8 ,P 1 )(L N8 ,P 2 )(L N8 ,P 3 )(L N8 ,P 4 )... to transmit row data to FIFO54b, such as (L N12 ,P 1 )(L N12 ,P 2 )(L N12 ,P 3 )(L N12 ,P 4 )……and the row data is transmitted to FIFO54c in this way.

[0114] Then, the same synchronization information (P 1 , P 2 , P 3 , P 4 Each time, the newly read row data is input to the input port N0 of the processing unit 10.

[0115] < Figure 5The relationship between the FIFOs 41 to 45 of the upper FIFO unit 40 and the input port of the processing unit 10>

[0116] Figure 6 4 is a diagram showing the relationship between the FIFOs 41 to 45 of the upper FIFO unit 40 and the input port of the processing unit 10. Figure 6 , the timing (each cycle) of inputting the row data of the 100th to 105th rows based on the image reading to the input row (input port N0) is shown, the row data input to the input ports N0, N1 to N12 of the processing unit 10, and the row data held in the FIFOs 41 to 45 of the upper FIFO unit 40.

[0117] Reference Figure 6 For example, when the line data of the 100th line is input to the input port N, the following line data is held in the FIFOs 41 to 44 on the read DMAC 32 side.

[0118] FIFO41:(L N1 ,P 1 )(L N5 ,P 1 )(L N9 ,P 1 )→L99, L95, L91

[0119] FIFO42:(L N2 ,P 1 )(L N6 ,P 1 )(L N10 ,P 1 )→L98, L94, L90

[0120] FIFO43:(L N3 ,P 1 )(L N7 ,P 1 )(L N11 ,P 1 )→L97, L93, L89

[0121] FIFO44:(L N4 ,P 1 )(L N8 ,P 1 )(L N12 ,P 1 )→L96, L92, L88

[0122] This is distributed to the FIFOs 51a, b, c to 54a, b, c of the lower FIFO unit 50, and is transferred to the input ports N1 to N12 as follows: That is, the data is input in the order of N12 → N1 from the earlier row data.

[0123] Input port N12: L88

[0124] Input port N11: L89

[0125] Input port N10: L90

[0126] Input port N9: L91

[0127] Input port N8: L92

[0128] Input port N7: L93

[0129] Input port N6: L94

[0130] Input port N5: L95

[0131] Input port N4: L96

[0132] Input port N3: L97

[0133] Input port N2: L98

[0134] Input port N1: L99

[0135] In this cycle, the line data "L100" of the 100th line is input to the input port N0 as described above. In the next cycle, the line data "L101" of the 101st line is input to the input port N0. In addition, the line data read out to the read DMAC 32 and stored in the FIFOs 41 to 44 and the line data assigned to the input ports N1 to N12 are shifted to the newer side one line at a time from the above state.

[0136] Here, attention is paid to the row data output from the transmission ports N0, N4, and N8. The inputs to the input ports N0, N4, and N8 are directly output from the transmission ports N0, N4, and N8. Therefore, when the row data (L100) of the 100th row is input to the input port N0, the output of the transmission port N0 becomes L100, the output of the transmission port N4 becomes L96, and the output of the transmission port N8 becomes L92. Therefore, the FIFO 45 on the write DMAC 31 side holds L100. N0 =L100, L N4 =L96, L N8 =L92. Figure 6 In the figure, the positions of L100, L96 and L92 are shown by hatching. As shown in the figure, new row data is input from input port N0 every cycle, and the positions of the input ports to which L100, L96 and L92 are input are shifted row by row. Similarly, FIFOs 41 to 44 that hold L100, L96 and L92 read from memory 20 are shifted one by one.

[0137] < Figure 5 The structure of the window size control>

[0138] Next, Figure 5 The control of the window size of the image processing device constructed in this way is described below. Figure 5 In the structure shown, the FIFOs 51a, b, c to 55a, b, c of the lower FIFO unit 50 correspond to the FIFOs 41 to 45 of the upper FIFO unit 40, and the window size in the processing unit 10 is enlarged. In addition, by making part of the FIFOs 51a, b, c to 55a, b, c of the lower FIFO unit 50 corresponding to the FIFOs 41 to 45 of the upper FIFO unit 40 inactive, the window size can be changed (reduced).

[0139] Figure 7 FIG. 4 is a diagram showing an example of controlling the window size. Figure 7 In the example shown, FIFO51c, 52c, 53c, 54c, 55c of FIFO51a, b, c to 55a, b, c of the lower FIFO unit 50 are deactivated, and only FIFO51a, 51b, 52a, 52b, 53a, 53b, 54a, 54b, 55a, 55b are used. Thus, the window size is changed (reduced) to 9 rows without changing the structure of DMAC 30 and upper FIFO unit 40.

[0140] Regarding the input ports of the processing unit 10, the input port N0 connected to the input row and the input ports N1 to N8 connected to the FIFOs 51a, 51b, 52a, 52b, 53a, 53b, 54a, 54b, 55a, and 55b are used, and the input ports N9 to N12 are not used. In this case, the data selector 122 (see Figure 2 ) The input ports N9 to N12 are blocked. Since there is no input of row data from FIFOs 51c, 52c, 53c, and 54c, the input ports N9 to N12 do not need to be blocked intentionally.

[0141] The valid input ports of the processing unit 10 are N0 to N8, so the output port is changed to N4, which is the middle row among them. In addition, regarding the transmission ports of the processing unit 10, the transmission port N0 that outputs the input to the input port N0 and the transmission port N4 that outputs the input to the input port N4 are used, and the transmission port N8 that outputs the input to the input port N8 is not used. In this case, the data selector 132 (see Figure 2 ) blocks the transmission port N8, and the input of the input port N8 is not transmitted to FIFO55c.

[0142] Figure 8FIG. 4 is a diagram showing another example of controlling the window size. Figure 8 In the example shown, FIFO51b, 51c, 52b, 52c, 53b, 53c, 54b, 54c, 55b, 55c of FIFO51a, b, c to 55a, b, c of the lower FIFO unit 50 are deactivated, and only FIFO51a, 52a, 53a, 54a, 55a are used. Thus, the window size is changed (reduced) to 5 rows without changing the structure of DMAC30 and upper FIFO unit 40.

[0143] Regarding the input ports of the processing unit 10, the input port N0 connected to the input row and the input ports N1 to N4 connected to the FIFOs 51a, 52a, 53a, 54a, and 55a are used, and the input ports N5 to N12 are not used. In this case, the data selector 122 (see Figure 2 ) The input ports N5 to N12 are blocked. Since there is no input of row data from FIFOs 51b, 51c, 52b, 52c, 53b, 53c, 54b, and 55c, the input ports N5 to N12 do not need to be blocked intentionally.

[0144] The valid input ports of the processing unit 10 are N0 to N4, so the output port is changed to the middle row of them, that is, N2. In addition, regarding the transmission ports of the processing unit 10, the transmission port N0 that outputs the input to the input port N0 is used, and the transmission port N4 that outputs the input to the input port N4 and the transmission port N8 that outputs the input to the input port N8 are not used. In this case, the data selector 132 (see Figure 2 ) blocks the transmission port N4 and the input port N8, and the inputs to the input port N4 and the input port N8 are not transmitted to the FIFO55b, c.

[0145] <Control of window size based on other methods>

[0146] In the above example, the window size in the processing unit 10 is controlled by using all or only a part of the FIFO of the lower FIFO unit 50. In this case, as described above, the number of rows of row data can be increased or decreased in units of the number of channels of the read DMAC 32. On the other hand, by switching the validity and invalidity of the row input to the processing unit 10, the window size of the processing unit 10 can be controlled in units finer than the number of channels of the read DMAC 32.

[0147] As an example, refer to Figure 1 The structural example shown is specifically described. Figure 1In the structure of , 9 lines of line data are input to the processing unit 10. One line of the 9 lines, line N0, is line data read by the image reading device (previous stage). The other 8 lines, line N1 to line N8, are line data read from the line buffer.

[0148] When all FIFOs 51a, b to 54a, b of the lower FIFO unit 50 are used, 9 lines of line data are input to the processing unit 10. Therefore, the window size of the processing unit 10 is 9 lines. Figure 4 As described above, when the FIFOs 51b, 52b, 53b, and 54b of the lower FIFO unit 50 are not used, the line data input to the processing unit 10 becomes 5 lines. Therefore, the window size of the processing unit 10 is 5 lines. The difference between these window sizes is 4 lines, which corresponds to the number of channels of the read DMAC 32.

[0149] On the other hand, in the processing unit 10, the input ports of the two rows are set to be invalid. Figure 2 ) to switch the input port between valid and invalid. Thus, the processing unit 10 only receives and processes the valid 7 rows of row data. Therefore, the window size also becomes 7 rows. Thus, compared with the control of the window size of the FIFO based on the lower FIFO unit 50, it is possible to control more finely.

[0150] Here, it is sufficient to determine which row is to be set as an invalid row in such a way that the remaining valid rows become 7 consecutive rows. For example, the row data (lineN0) read out last from the image and the earliest row data (in Figure 1 In the example shown, lineN8) is set to invalid, and the row data between them (in Figure 1 In the example shown, lines N1 to N7 are made valid. Alternatively, the two lines starting from the earlier side (in Figure 1 In the example shown, line N8 to N7) are set to invalid, and the other line data (in Figure 1 In the example shown, lineN0 to N6) are set to be valid. If it is the former, both ends of the input line will be invalid. Therefore, in the reference Figure 1 , 5 , 10, etc., when the row data corresponding to the center row in the input row is set as the output data, even after the window size is changed, the row data corresponding to the same row becomes the output data, so there is no need to change the output row.

[0151] Above, Figure 1 The structure shown is an example, however, Figure 5The same can be applied to the structure shown in FIG. Figure 4 , Figure 7 , Figure 8 The control of the window size described above, which is achieved by not using a part of the FIFO of the lower-level FIFO unit 50, can achieve control of various window sizes.

[0152] <Designing Steps for Image Processing Device 1>

[0153] Fig. 9 1 is a flowchart showing the design steps of the image processing device 1. First, the performance (required performance) required for the computing core 11 of the processing unit 10 is determined (S901). As the required performance, when the performance (image quality) of image processing is prioritized, the processing amount is large, so the processing speed is reduced. On the contrary, when the processing speed is prioritized, the image quality is reduced. Therefore, it is required to strike a balance between image quality and processing speed according to the requirements of the system to which the image processing device 1 is applied.

[0154] Next, the transmission performance of each channel of DMAC30 is determined based on the bus width and delay (S902). The transmission performance is an indicator indicating how many rows of data can be transmitted to the memory 20 by one channel of DMAC30 in one cycle of processing. The bus width is one of the parameters directly related to the transmission performance, indicating how many bits of data can be read (written) in one read (or write). The delay is one of the parameters directly related to the transmission performance, indicating the number of clocks required from issuing the read / write command of the data to the actual completion of the processing.

[0155] Next, the number of channels of the DMAC 30 is determined so as to satisfy the required performance of the computing core 11 of the processing unit 10 determined in S901 (S903). More specifically, the number of channels of the read DMAC 32 for supplying line data to the processing unit 10 is determined. Then, with respect to the determined number of channels of the DMAC 30 (particularly the read DMAC 32), it is determined whether the number of FIFOs of the lower FIFO unit 50 for determining the number of line data supplied to the processing unit 10 is appropriate (in other words, whether it is excessive or insufficient).

[0156] If the number of FIFOs in the lower FIFO unit 50 is not appropriate (S904: No), the number of FIFOs in the lower FIFO unit 50 is adjusted (S905), and the operation from S902 is performed. Next, the setting of the DMAC 30 and the lower FIFO unit 50 corresponding to the required performance is repeated. If it is determined that the number of FIFOs in the lower FIFO unit 50 is appropriate (S904: Yes), the design of the image processing device 1 is completed.

[0157] Although the embodiments of the present disclosure have been described above, the technical scope of the present disclosure is not limited to the above embodiments. Various changes and structural substitutions that do not depart from the technical concept of the present disclosure are included in the present disclosure.

Claims

1. An image processing device, comprising: a processing unit that performs image processing; A read DMAC (DMA Controller) for reading data from the memory and a write DMAC for writing data to the memory, which control access to the memory (Direct Memory Access); An upper FIFO (First-In First-Out) unit connected to the read DMAC and the write DMAC and having a number of FIFOs corresponding to the number of channels of each DMAC; as well as A lower-level FIFO unit is arranged between the upper-level FIFO unit and the processing unit, and has corresponding F FIFOs for each FIFO of the upper-level FIFO unit. By not using a part of each of the F FIFOs of the lower-level FIFO unit corresponding to each FIFO of the upper-level FIFO unit, the number of rows of data input to the processing unit can be changed in units of the number of channels of the read DMAC, wherein F is an integer greater than 2.

2. The image processing device according to claim 1, wherein: By excluding predetermined two lines of data from among a plurality of lines of data input to the processing unit, the number of lines of data input to the processing unit can be changed in units of two lines.

3. The image processing device according to claim 2, wherein: When excluding two lines of data among a plurality of lines of data input to the processing unit, the oldest data among the data read out last from the image and the data read out from the memory and acquired from the lower-stage FIFO unit are excluded.

4. The image processing device according to claim 1, wherein: The processing unit inputs n lines of data consisting of one line read from the image and n-1 lines read from the memory and obtained from the lower FIFO unit, processes the data, and outputs one line of processed data. The number of the upper FIFO units connected to the read DMAC is C corresponding to the number of channels of the read DMAC, where C is an integer greater than or equal to 1. The number of the lower-level FIFO units corresponding to the upper-level FIFO units connected to the read DMAC is C×F, and C×F=n-1.

5. The image processing device according to claim 4, wherein: The write DMAC is 1 channel. The processing unit inputs n rows of row data consisting of row data N0 and row data N1 to N(n-1) as processing objects, wherein the row data N0 is the last row of data read from the image, and the row data N1 to N(n-1) are the row data obtained from the lower-level FIFO unit and are n-1 rows of data read 1 time ago to n-1 times ago, and the processing unit sends F rows of row data NL among the input row data to the lower-level FIFO unit corresponding to the upper-level FIFO unit connected to the write DMAC, wherein L=C×(P-1), and P is an integer from 1 to F.

6. The image processing device according to claim 5, wherein: In the upper FIFO unit and the lower FIFO unit on the write DMAC side, data sent from the processing unit to the lower FIFO unit is sent to the upper FIFO unit one by one from each of the F lower FIFO units in sequence, and is sequentially written from the upper FIFO unit to the memory through the write DMAC. In the upper FIFO unit and the lower FIFO unit on the read DMAC side, the data read from the memory by the read DMAC and stored in the C upper FIFO units are stored one by one in the order of the rows input to the processing unit in sequence in the F lower FIFO units of each upper FIFO unit.

Images