Method for controlling core critical dimension variation using fast trimming sequence

Abstract

A pattern of core material is formed on a wafer to include a core feature having a critical dimension. A trim amount indicates an average amount of thickness to be removed from a vertically oriented surface of the core feature. A trim profile indicates how much variation in thickness removal from the vertically oriented surface of the core feature is applied as a function of radial position on the wafer. A first set of data associates the trim amount with one or more plasma trim process parameters. A second set of data associates the trim profile with one or more plasma trim process parameters. Based on the trim amount, the trim profile, and the first and second sets of data, a set of plasma trim process parameters that achieves the trim amount and the trim profile on the wafer is determined, and a corresponding plasma trim process is performed on the wafer.

Description

Technical Field

[0001] The present disclosure relates to semiconductor device processing. Background Art

[0002] Plasma etching processes are often used in semiconductor device manufacturing. In a plasma etching process, a semiconductor wafer containing a semiconductor device being manufactured is exposed to a plasma that interacts with at least one material on the semiconductor wafer to remove the at least one material. The plasma can be generated using a specific reactive gas that will cause the components of the plasma to interact with the material to be removed from the semiconductor wafer without significantly interacting with other materials on the wafer that are not desired to be removed. Also, in some plasma etching processes, a bias voltage can be applied to the semiconductor wafer to enable anisotropic etching of features on the semiconductor wafer by attracting charged components of the plasma toward the semiconductor wafer in a more vertical direction. It is in this context that the present disclosure was created. Summary of the invention

[0003] In an exemplary embodiment, a method for controlling a core critical dimension is disclosed. The method includes: obtaining a wafer, wherein a pattern of core material is formed on the wafer. The pattern of the core material includes one or more core features having a critical dimension measured in a horizontal direction. The horizontal direction is parallel to the bottom surface of the wafer. The method includes receiving a target trim amount as an input parameter. The target trim amount indicates an average amount of thickness to be removed from a vertically oriented surface of the one or more core features. The method also includes receiving a target trim profile as an input parameter. The target trim profile indicates how much of a variation in thickness removal from a vertically oriented surface of the one or more core features is applied as a function of a radial position on the wafer between a center of the wafer and a peripheral edge of the wafer when performing the target trim amount on the wafer. The method also includes: accessing a first set of data that associates a trim amount with one or more plasma trim process parameters. The method also includes: accessing a second set of data that associates a trim profile with one or more plasma trim process parameters. The method further includes determining a set of plasma trim process parameters for achieving the target trim amount and the target trim profile on the wafer based on the target trim amount, the target trim profile, the first set of data, and the second set of data. The method further includes performing a plasma trim process on the wafer using the set of plasma trim process parameters to create a modified pattern of the core material including the one or more core features having an adjusted critical dimension measured in the horizontal direction.

[0004] In an exemplary embodiment, a method is disclosed for controlling a core critical dimension. The method includes obtaining a plurality of wafers, and a pattern of core material is formed on each of the plurality of wafers. The pattern of core material includes a core feature having a critical dimension measured in a horizontal direction, wherein the horizontal direction is substantially parallel to the bottom surface of a given wafer. The method also includes receiving a target trimming amount as an input parameter for each of the plurality of wafers. Each of the plurality of wafers has a respective target trimming amount. The target trimming amount for a particular wafer indicates an average amount of thickness to be removed from a vertically oriented surface of a core feature of the particular wafer. The method also includes receiving a target trimming profile as an input parameter for each of the plurality of wafers. Each of the plurality of wafers has a respective target trimming profile. The target trimming profile for the particular wafer indicates: when performing the target trimming amount on the particular wafer, how much variation in thickness removal from a vertically oriented surface of a core feature is applied as a function of radial position on the particular wafer between a center of the particular wafer and a peripheral edge of the particular wafer. The method further includes: for each of the plurality of wafers, accessing a first set of data, the first set of data associating a trim amount for the particular wafer with one or more plasma trim process parameters. The first set of data is applicable to a particular plasma processing station in which the particular wafer is processed. The method further includes: for each of the plurality of wafers, accessing a second set of data associating a trim profile for the particular wafer with one or more plasma trim process parameters. The second set of data is applicable to the particular plasma processing station in which the particular wafer is processed. The method further includes determining a base set of plasma trim process parameters for a base trim process on each of the plurality of wafers. The base set of plasma trim process parameters is determined based on the target trim amount for each of the plurality of wafers, the target trim profile for each of the plurality of wafers, the first set of data for the plurality of plasma processing stations, and the second set of data for the plurality of plasma processing stations. The base trim process is the same for each of the plurality of wafers. The method also includes determining, for each of the plurality of wafers, a respective supplemental set of plasma trim process parameters for a respective fast trim process on each of the plurality of wafers to achieve a target trim amount for the particular wafer and a target trim profile for the particular wafer. The respective supplemental set of plasma trim process parameters is determined for each of the plurality of wafers based on the target trim amount for each of the plurality of wafers, the target trim profile for each of the plurality of wafers, the first set of data for the plurality of plasma processing stations, the second set of data for the plurality of plasma processing stations, and the base set of plasma trim process parameters.The rapid trim process is customized for each of the plurality of wafers. The method further includes performing the basic trim process on each of the plurality of wafers in the particular plasma processing station where the particular wafer is processed. The method further includes: after the basic trim process is completed, performing a respective rapid trim process on each of the plurality of wafers in the particular plasma processing station where the particular wafer is processed.

[0005] In an exemplary embodiment, a controller for controlling a core critical dimension is disclosed. The controller includes: an input module configured to obtain a target trim amount as an input parameter. The target trim amount indicates an average amount of thickness to be removed from a vertically oriented surface of a core feature on a wafer. The core feature forms a portion of a pattern of core material on the wafer. The core feature has a critical dimension measured in a horizontal direction parallel to a bottom surface of the wafer. The input module is configured to obtain a target trim profile as an input parameter. The target trim profile indicates how much of a change in thickness removal from a vertically oriented surface of the core feature is applied as a function of a radial position on the wafer between a center of the wafer and a peripheral edge of the wafer when performing the target trim amount on the wafer. The input module is configured to obtain a first set of data that associates a trim amount with one or more plasma trim process parameters. The input module is configured to obtain a second set of data that associates a trim profile with one or more plasma trim process parameters. The controller further comprises: an analysis module configured to use a set of plasma trimming process parameters to achieve the target trimming amount and the target trimming profile on the wafer based on an analysis of the first set of data and the second set of data. The controller further comprises: an execution module configured to use the set of plasma trimming process parameters to direct execution of a plasma trimming process on the wafer to establish a modified pattern of the core material including the core feature having an adjusted critical dimension measured in the horizontal direction.

[0006] In an exemplary embodiment, a method for controlling core critical dimensions on a plurality of wafers is disclosed. The method includes: obtaining a plurality of wafers, wherein a pattern of core material is formed on each of the plurality of wafers. The pattern of the core material includes a core feature having a critical dimension measured in a horizontal direction. The horizontal direction is substantially parallel to a bottom surface of a given wafer. Each of the plurality of wafers is present in a separate one of a plurality of plasma processing stations. The method further includes: performing a basic trimming process on each of the plurality of wafers in a simultaneous manner in the plurality of plasma processing stations. The basic trimming process is defined to reduce the critical dimension of the core feature on the plurality of wafers. The basic trimming process is performed in the same manner in each of the plurality of plasma processing stations. The method further includes: performing a wafer-specific rapid trimming process on each of the plurality of wafers in the plurality of plasma processing stations after the basic trimming process is completed. The wafer-specific rapid trimming process is defined to further reduce the critical dimension of the core feature on the plurality of wafers. The wafer-specific rapid trimming process is performed in a separately defined manner in each of the plurality of plasma processing stations. The wafer-specific rapid trimming process for a given wafer of the plurality of wafers is defined such that a combination of the basic trimming process and the wafer-specific rapid trimming process for the given wafer achieves a wafer-specific target trimming amount on the given wafer and achieves a wafer-specific target trimming profile on the given wafer.

[0007] In an exemplary embodiment, a method for controlling a core critical dimension is disclosed. The method includes obtaining a wafer, wherein a pattern of core material is formed on the wafer. The pattern of the core material includes one or more core features having a critical dimension measured in a horizontal direction. The horizontal direction is parallel to a bottom surface of the wafer. The method also includes receiving a target trim amount as an input parameter. The target trim amount indicates an average thickness amount to be removed from a vertically oriented surface of the one or more core features. The method also includes accessing a set of data that associates a trim amount with one or more plasma trim process parameters. The method includes determining a set of plasma trim process parameters for achieving the target trim amount on the wafer based on the target trim amount and the set of data. The method also includes performing a plasma trim process on the wafer using the set of plasma trim process parameters to establish a modified pattern of the core material, which includes the one or more core features having an adjusted critical dimension measured in the horizontal direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A ,1B , 1C, 1D, and 1E show vertical cross-sectional views through a portion of a wafer undergoing multiple operations in a SADP process according to some embodiments.

[0009] Figure 2 A vertical cross-section through a plasma processing station that may be used to perform the methods disclosed herein is shown according to some embodiments.

[0010] Figure 3 A top view of a multi-station processing tool including four plasma processing stations is shown according to some embodiments.

[0011] Figure 4 A schematic diagram of a multi-station processing tool interfaced with inbound loadlocks and outbound loadlocks is shown according to some embodiments.

[0012] Figure 5 A flow chart of a method for controlling core critical dimensions is shown, according to some embodiments.

[0013] Figure 6 A flow chart of a method for controlling core critical dimensions is shown, according to some embodiments.

[0014] Figure 7 A method is shown for controlling core critical dimensions across multiple wafers, according to some embodiments.

[0015] Figure 8 According to some embodiments, a controller is shown for controlling a core critical dimension. DETAILED DESCRIPTION

[0016] In the following description, many specific details are described to provide an understanding of the embodiments of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without all or part of these specific details. On the other hand, well-known process operations are no longer described in detail to avoid unnecessarily making the present disclosure difficult to understand.

[0017] In semiconductor wafer (hereinafter referred to as "wafer") processing, the core material layer can be deposited on the wafer and patterned, used as a mask in the operation of one or more underlying materials on / in the processing wafer. In various embodiments, the wafer can change in form, shape and / or size. For example, in some embodiments, the wafer referred to herein can correspond to a semiconductor wafer with a diameter of 200mm (millimeter), a semiconductor wafer with a diameter of 300mm, or a semiconductor wafer with a diameter of 450mm. And, in some embodiments, the wafer referred to herein can have a non-circular shape, such as a rectangular substrate for a flat display, etc., and other shapes.

[0018] The core material layer is exposed to a light pattern that passes through a photomask and reaches a wafer in a photolithography process so that the core material can be developed into a specified feature pattern, wherein some of the core features have a critical dimension. The critical dimension in this context means the minimum size that is controlled in a particular process. The critical dimension of the core feature is controlled by the ability of the photolithography process used to pattern the core material layer. There are limitations on the extent to which the critical dimensions of the core feature can be reduced using a standard photolithography process (e.g., using a photolithography process based on 193 nanometer light). Intent to establish a core feature with too small a critical dimension may cause problems in the operation of patterning the core material layer using a standard photolithography process. Therefore, the standard photolithography process effectively limits how small the critical dimensions of the core feature can be made. However, once the core feature is formed with the minimum critical dimension that the photolithography process can accurately provide, these core features can be used to create a mask with features based on this photolithography patterned core feature by performing a series of etching processes to make features with even smaller critical dimensions. Such an etching process includes a self-aligned multiple patterning (SAMP) process, and in particular may include a self-aligned double patterning (SADP) process and a self-aligned quadruple patterning (SAQP) process.

[0019] Figures 1A-1E A vertical cross-sectional view through a portion of a wafer 101 undergoing various operations in a SADP process is shown in accordance with some embodiments. Figure 1A A vertical cross-section through a portion of a wafer 101 is shown, wherein a layer 105 of a target material to be etched is deposited on the wafer 101 , ie, on an underlying material 107 of the wafer 101 . Figure 1A Also shown is a patterned core feature 103 formed on the target material 105. In various embodiments, the core feature 103 can be made of a photoresist material or a carbon material, such as spin-on carbon, chemical vapor deposition (CVD) carbon, plasma enhanced chemical vapor deposition (PECVD) carbon, or a flowable carbon mixture, etc. The core feature 103 has a critical dimension CD1, which is measured in a horizontal direction substantially parallel to the bottom surface 102 of the wafer 101. In some cases, the patterned core feature 103 can be referred to as a core mandrel. In some embodiments, the critical dimension CD1 of the core feature 103 can be processed at the minimum size that can be accurately provided by the lithography process. From Figure 1A In the illustrated configuration, the SADP process continues with a core trimming process, wherein the core feature 103 is laterally trimmed in a plasma etching process. In some embodiments, the plasma etching process is an oxygen-based plasma etching process. However, in other embodiments, the plasma etching process can use substantially any process gas suitable for etching the core feature 103 material. Figure 1B shows a vertical cross-section of a portion of a wafer 101 after a core trimming process that laterally trims a core feature 103 Figure 1A through. Figure 1B It shows that, after the core trimming process, the critical dimension CD1 of the core feature 103 is reduced to a smaller critical dimension CD2, i.e., CD2 < CD1. In various embodiments, the core trimming process can be performed using a suitably defined and controlled plasma etching process.

[0020] From Figure 1B the shown configuration, the SADP process continues with a conformal deposition of a mask material 109 (e.g., an oxide material) on the core feature 103. Figure 1C shows a vertical cross-section of a portion of a wafer 101 after the conformal deposition of the mask material 109 on the core feature 103 Figure 1B through. In some embodiments, the mask material 109 is deposited using an atomic layer deposition process. From Figure 1C the shown configuration, the SADP process continues with a plasma etching process in which the top portion of the mask material 109 is removed to expose the underlying core feature 103, and in which the core feature 103 is removed. In some embodiments, the plasma etching process for removing the top portion of the mask material 109 and the core feature 103 can be an anisotropic etching process, which is defined to remove material in a substantially top-down manner. After the plasma etching process for removing the top portion of the mask material 109 and the core feature 103, the side spacers of the mask material 109 remain on the wafer 101.

[0021] Figure 1D shows a vertical cross-section of a portion of a wafer 101 after a plasma etching process for removing the top portion of the mask material 109 and the core feature 103 to form side spacers of the mask material 109 Figure 1C through. Figure 1D The side spacers of the mask material have a thickness LW measured in the horizontal direction. The thickness LW can be referred to as the line width. As Figure 1D shown, the pitch P is defined as the sum of twice the horizontal thickness LW of the side spacers of the mask material 109a, a first spacing S1, and a second spacing S2. As Figure 1EIt is shown that after a plasma etching process for forming features from a target material 105, a Figure 1D A vertical cross-sectional view of a portion of wafer 101.

[0022] It is desirable that the first spacing S1 is substantially equal to the critical dimension CD2 of the core feature 103 after the core trimming process. And, it is desirable that the second spacing S2 is substantially equal to the first spacing S1. The variation in the critical dimensions CD1, CD2 of the core feature 103 across the entire wafer 101 is referred to as critical dimension non-uniformity (CDNU). It is desirable that CDNU be minimized across the entire wafer 101. And, it should be understood that CDNU may exist within a particular wafer 101 (WiW (within wafer)) and / or between different wafers 101 (WTW (between wafers)). CDNU (WiW and WTW) may cause device failure for several dies formed on the wafer 101, and / or may cause variations in device performance for different dies formed on different wafers 101. The critical dimension ununiformity (CDIMB) is equal to the absolute value of the difference between the first spacing S1 and the second spacing S2. For example, the CDIMB for a particular region / area of ​​the wafer 101 is equal to the absolute value of the difference between the average S1 and average S2 values ​​within the particular region / area of ​​the wafer 101. If the critical dimensions CD1, CD2 of the core features 103 vary across the wafer 101, the first spacing S1 and the second spacing S2 may be different across the wafer 101 and may result in an increase in CDIMB. It is desirable that the CDIMB be as close to zero as possible. It should be understood that the core trimming process controls the reduced critical dimension CD2 of the core features 103 across the wafer 101 and therefore has a direct impact on the first spacing S1 and has a contributing effect on the second spacing S2. Also, if the core trimming process is non-uniform across the wafer 101, the reduced critical dimension CD2 of the core features 103 may be non-uniform across the wafer 101 and this may result in a non-zero CDIMB across the wafer 101.

[0023] Furthermore, even if the same etching process recipe is performed in each of the different plasma processing stations, different plasma processing stations may provide different etching results. This station-to-station variation in etching results may be caused in part by variations in tolerances on chamber components, and / or in part by variations in internal chamber surface conditions. Therefore, the reduced critical dimension CD2 of the core feature 103 achieved by performing the core trim process in different plasma processing stations may vary from station to station, even if the same core trim process is performed in each station. Furthermore, each plasma processing station may have its own WiW CDNU. Therefore, the WiW CDNU may vary from station to station.

[0024] The methods and systems disclosed herein are used to perform a core critical dimension trimming process on a wafer undergoing a SAMP processing process to reduce and / or eliminate WiW CDNU and / or WTW CDNU. The reduction and / or elimination of WiW CDNU and / or WTW CDNU will be used to reduce and / or eliminate WiW CDIMB and / or WTW CDIMB. If it is known in advance how the core critical dimension trimming process will perform in terms of CDNU (WiW and / or WTW), the core critical dimension trimming process can be adjusted in advance to compensate for CDNU. For example, if it is known that the core critical dimension trimming process provides a higher etch rate at the center of the wafer than at the edge of the wafer, the core critical dimension trimming process can be adjusted in advance to reduce the etch rate at the center of the wafer and / or increase the etch rate at the edge of the wafer. The methods and systems disclosed herein provide for adjusting the core critical dimension trimming process to compensate for expected WiW CDNU and / or WTW CDNU that may occur during the SAMP processing process. Reference Figures 1A-1E , the core critical dimension trimming process can be controlled to modify the critical dimension of the core feature 103 (change CD1 to CD2) in a manner that controls the first spacing S1 and the second spacing S2 of the final mask defined for etching the target material 105, so that the first spacing S1 is substantially equal to the second spacing S2 (WiW and / or WTW).

[0025] According to some embodiments, Figure 2 A vertical cross-sectional view through a substrate processing system 200 that can be used to perform the methods disclosed herein is shown. The substrate processing system 200 includes a plasma chamber 202 having an upper chamber portion 202A and a lower chamber portion 202B. The central column is constructed to support a pedestal 240, which, in one embodiment, includes a powered lower electrode. The pedestal 240 is electrically connected to a combiner and distributor 221, which is further connected to a plurality of matching networks 206. The matching networks 206 are connected to a plurality of radio frequency (RF) generators 204. The RF generators 204 are controlled by a detection control and system control section 210 (e.g., a controller, etc.). Examples of controllers include processors and memory devices. For example, the processor is an application specific integrated circuit (ASIC), a programmable logic device (PLD), a central processing unit (CPU), or a microprocessor, etc. Examples of memory devices include read-only memory (ROM), random access memory (RAM), storage disk arrays, hard disks, flash memory, etc. The detection control and system control section 210 operates the substrate processing system 200 by executing the process input and control specifications 208. The process input and control specifications 208 include process recipes, such as power levels, timing parameters, process gases, mechanical movement of the wafer 201, etc., to etch the wafer 201 and / or deposit or form a film on the wafer 201.

[0026] The center column is also shown to include lift pins 220, which are controlled by a lift pin control 222. The lift pins 220 are used to lift the wafer 201 from the pedestal 240 so that the end effector can pick up the wafer 201, and to lower the wafer 201 after the wafer 201 is placed by the end effector. The substrate processing system 200 also includes a gas supply manifold 212, which is connected to process gases 214, such as gas chemical supplies from a facility, etc. Depending on the process being performed, the detection control and system control 210 controls the delivery of the process gases 214 through the gas supply manifold 212. The selected gas is then flowed into the showerhead 250 and distributed in the spatial volume (e.g., gap, etc.) defined between the face of the showerhead 250 facing the wafer 201 and the pedestal 240.

[0027] In addition, in various embodiments, the process gas 214 is pre-mixed or not. Appropriate valve control and mass flow control mechanisms are used to ensure that the correct process gas is delivered during the deposition and plasma treatment stages of the process. The process gas 214 leaves the plasma chamber 202 through an outlet. A vacuum pump (e.g., a primary or secondary mechanical dry pump, a turbomolecular pump, etc.) pumps the process gas out and maintains a suitable low pressure in the plasma chamber 202 through a closed loop control flow restriction device (e.g., a throttle valve or a pendulum valve).

[0028] Also shown is a carrier ring 251 that surrounds an outer region of the pedestal 240. The carrier ring 251 sits on a carrier ring support area that is a step down from the wafer support area in the center portion of the pedestal 240. The carrier ring 251 includes an outer edge side of its dish structure, such as an outer diameter, etc., and a wafer edge side of its dish structure, such as an inner diameter, etc., which is closest to where the wafer 201 sits. The wafer edge side of the carrier ring 251 includes a plurality of contact support structures that lift the wafer 201 when the carrier ring 251 is lifted by the plurality of spider forks 280. The carrier ring 251 is thus lifted with the wafer 201 and rotated to another station, such as in a multi-station system.

[0029] In some embodiments, when RF power is supplied from RF generator 204 to the lower electrode in pedestal 240, the upper electrode in showerhead 250 is grounded. In some embodiments, instead of electrically connecting pedestal 240 to RF generator 204 via matching network 206, the upper electrode in showerhead 250 is connected to RF generator 204 via matching network 206 to receive power from RF generator 204, while the lower electrode in pedestal 240 is grounded. In some embodiments, RF generators 204 generate RF signals having different frequencies, for example, one of RF generators 204 generates an RF signal having a low frequency, and another of the RF generators generates an RF signal having a high frequency higher than the low frequency.

[0030] According to some embodiments, Figure 3 A top view of a multi-station processing tool 300 is shown, which includes four plasma processing stations 340A, 340B, 340C, 340D. The four plasma processing stations 340A, 340B, 340C, 340D are accessed by spider forks 280. In one embodiment, there is no isolation wall or other mechanism to isolate one station from another. Each spider fork 280 includes a first and a second arm, each disposed around a portion of each side of the base 240. In this view, the spider forks 280 are drawn in dashed lines to indicate that they are below the carrier ring 251. Using the engagement and rotation mechanism 320, the spider fork 280 raises and simultaneously lifts the carrier ring 251 from the lower surface of the carrier ring 251 from the plasma processing stations 340A, 340B, 340C, 340D, and then rotates between two or more plasma processing stations 340A, 340B, 340C, 340D before lowering the carrier ring 251. During the rotation, at least one of the carrier rings 251 supports the wafer 201 to the next position to allow further plasma processing, treatment and / or film deposition to occur on the wafer 201.

[0031] According to some embodiments, Figure 4A cluster tool system 400 is shown, which is used to process substrates. The cluster tool system 400 is generally installed in a processing facility. A transport container 402 (e.g., a front-opening wafer transport box (FOUP)) is used to carry substrates (e.g., wafers) to and from the cluster tool system 400. An equipment front end module (EFEM) 404 includes a robot 406, which is configured to transport wafers between the transport container 402 and a load lock 408. A transport module 410 includes a robot 412, which is configured to transport wafers between the load lock 408 and one of a plurality of process tools 414. In some embodiments, each of the process tools 414 is a multi-station processing tool 300 having four processing stations 340A, 340B, 340C, 340D to allow multiple wafers to be processed simultaneously. However, it should be understood that in other embodiments, each process tool 414 may include less than or more than four processing stations.

[0032] In some embodiments, the controller 420 is a component of a processing system that includes the cluster tool system 400. Such a processing system may include a semiconductor processing device that includes one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These processing systems can be integrated with electronic devices for controlling their operation before, during, and after the processing of semiconductor wafers or substrates. The electronic device can be referred to as a controller 420, which can control various components or subcomponents of the processing system. Depending on the processing requirements and / or the type of processing system, the controller 420 can be programmed to control any process disclosed herein, including the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer in and out of tools and other transfer tools and / or load locks connected to or interfaced with a specific system.

[0033] In general, the controller 420 can be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable processing operations, enable cleaning operations, enable endpoint measurements, etc. The integrated circuits may include a chip in the form of firmware that stores program instructions, a digital signal processor (DSP), a chip defined as an application specific integrated circuit (ASIC), and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). The program instructions may be instructions sent to the controller 420 in the form of various individual settings (or program files) that define operating parameters for performing a particular process on or for a semiconductor wafer or system. In some implementations, the operating parameters may be part of a recipe defined by a process engineer to complete one or more processing steps during the processing of one or more (kinds of) layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0034] In some implementations, the controller 420 may be part of or coupled to a computer that is integrated with the system, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller 420 may be in the "cloud" or may be all or part of a semiconductor processing facility host system that may allow remote access to wafer processing. The computer may enable remote access to the system to monitor the current progress of a processing operation, examine the history of past processing operations, examine trends or performance criteria for multiple processing operations, change parameters of a current process, set processing steps to follow a current process, or start a new process. In some examples, a remote computer (e.g., a server) may provide a process recipe to the system via a network (which may include a local network or the Internet). The remote computer may include a user interface that enables input or programming of parameters and / or settings, which are then sent from the remote computer to the system. In some examples, the controller 420 receives instructions in the form of data that specify parameters for each processing step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller 420 is configured to interface with or control. Thus, as described above, the controller 420 can be distributed, for example, by including one or more discrete controllers networked together and working toward a common purpose (e.g., the processes and controls described herein). An example of a distributed controller for such a purpose is one or more integrated circuits on a chamber communicating with one or more integrated circuits remotely (e.g., at a platform level or as part of a remote computer), which combine to control the process on the chamber.

[0035] Example systems may include, but are not limited to, plasma etch chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, chamfer edge etch chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etch (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing system that may be associated with or used in the processing and / or preparation of semiconductor wafers. As described above, the controller 420 may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, a host computer, another controller, or a tool used in the transport of materials to transport wafer containers to and from tool locations and / or load ports in a semiconductor processing facility, depending on one or more processing steps to be performed by the tool.

[0036] It should be understood that the plasma processing stations 340A, 340B, 340C, 340D and cluster tool system 400 are provided as examples. The methods disclosed herein for performing a core critical dimension trimming process on a wafer undergoing a SAMP process to reduce and / or eliminate WiWCDNU and / or WTW CDNU can be performed in an equivalent manner in a suitably configured plasma processing chamber / station other than the exemplary plasma processing stations 340A, 340B, 340C, 340D and cluster tool system 400.

[0037] In various embodiments, a core critical dimension trimming process is used to improve WTW CDNU by compensating for input WTW variations in critical dimension CD1 of core feature 103 due to lithography for a wafer-specific core trim amount and / or trim profile (e.g., center to edge) on each wafer. Similarly, variations in reduced critical dimension CD2 of core feature 103 due to differences in performance of one plasma processing station compared to another plasma processing station can be compensated for by targeting wafer-specific and station-specific core trim amounts and / or trim profiles on each wafer. Also, WiW CDNU due to lithography can be compensated by defining a core critical dimension trimming process to adjust WiW CDNU in further processing operations.

[0038] After the photolithography process is completed and a core feature with a critical dimension CD1 is formed on the input wafer, the input wafer undergoes a measurement procedure, wherein the critical dimension CD1 of the core feature 103 is measured at various different locations on the input wafer. Next, the WiW CDNU for the input wafer is determined based on the measured value of the critical dimension CD1 of the core feature 103. In addition, in some embodiments, the wafer undergoes a measurement procedure after the core critical dimension trimming process is completed to measure the reduced critical dimension CD2 at various different locations on the wafer and determine the WiW CDNU for the reduced critical dimension CD2. The critical dimension measurement value of the core feature 103 of the wafer serves as a reference for the specific plasma processing station in which the wafer is processed. Therefore, it is possible to analyze the critical dimension measurement values ​​(CD1, CD2) of the core feature 103 for a wafer for a given plasma processing station, and perform a station-to-station comparative analysis of the critical dimension measurement values ​​(CD1, CD2) of the core feature 103 for the wafer.

[0039] Figure 5 A flow chart of a method for controlling a core critical dimension is shown according to some embodiments. The method includes operation 501, which is used to obtain a wafer, wherein a core material pattern is formed on the wafer. The pattern of the core material includes one or more core features (e.g., 103) having a critical dimension (e.g., CD1) measured in a horizontal direction, wherein the horizontal direction is parallel to the bottom surface of the wafer. The method also includes operation 503, which is used to receive a target trimming amount as an input parameter. The target trimming amount indicates the average thickness amount to be removed from the vertically oriented surface of one or more core features. For example, referring to Figures 1A-1E , the target trim amount is the horizontal thickness of the core material that needs to be removed to reach the reduced critical dimension CD2 from the input critical dimension CD1. The method also includes an operation 505 for receiving a target trim profile as an input parameter. The target trim profile indicates how much of a change in thickness removal from a vertically oriented surface of one or more core features is applied as a function of radial position on the wafer between the center of the wafer and the peripheral edge of the wafer when performing the target trim amount on the wafer. The target trim amount received in operation 503 can be received on a single wafer basis or on a wafer batch basis. Similarly, the target trim profile received in operation 505 can be received on a single wafer basis or on a wafer batch basis.

[0040] The method further includes an operation 507 for accessing a first set of data that relates the trim amount to one or more plasma trim process parameters. The method further includes an operation 509 for accessing a second set of data that relates the trim profile to one or more plasma trim process parameters. The first set of data accessed in operation 507 and the second set of data accessed in operation 509 may be derived by performing a design of experiments (DOE). For example, a correlation between a trim rate and various plasma etching process parameters may be derived from the DOE for a given plasma processing station. Also, a correlation between a trim profile and various plasma etching process parameters may be derived from the DOE for a given plasma processing station.

[0041] The method further includes an operation 511 for determining a set of plasma trim process parameters for achieving the target trim amount and the target trim profile on the wafer, wherein the set of plasma trim process parameters is based on the target trim amount, the target trim profile, the first set of data from operation 507, and the second set of data from operation 509. In some embodiments, a computer program is used to determine / calculate plasma etch process recipe parameters to achieve the target trim amount and the target trim profile for a given wafer in a given plasma processing station based on the corresponding first set of data and second set of data for the given plasma processing station. More specifically, using the trim rate relative process parameter data and the trim profile relative process parameter data for the given plasma processing station, the computer program determines / calculates the plasma etch process recipe parameters required to achieve the target trim amount and the target trim profile for a given wafer in the given plasma processing station.

[0042] In various embodiments, the set of plasma trimming process parameters determined in operation 511 may include substantially any one or more plasma etching process recipe parameters, such as one or more process gas types and corresponding flow rates, pressures, temperatures, radio frequency (RF) powers, RF frequencies, bias voltages, etc. In some embodiments, the set of plasma trimming process parameters may specify process gas compositions including one or more of the following: oxygen (O 2 ), nitrous oxide (N 2 O), carbon monoxide (CO), carbon dioxide (CO 2 ), ozone (O 3 ), alcohols (including but not limited to, methanol (CH 3 OH), ethanol (C 2 H 5 OH), propanol (CH 3 CH 2 CH 3 OH), isopropanol (C 3 H8 O), and other alcohols), and mixtures thereof. Also, in some embodiments, the set of plasma trim process parameters may include specifications of an activation source, such as a capacitively coupled plasma (CCP) source, an inductively coupled plasma (ICP) source, a microwave source, a visible ultraviolet (VuV) source, an ozone source, a hot filament source, or another type of activation source. In some embodiments, the set of plasma trim process parameters determined in operation 511 include a temperature setting in a range from about -25°C to about 100°C, or in a range from about 0°C to about 75°C. The method also includes an operation 513 for performing a plasma trim process on a wafer using the set of plasma trim process parameters determined / calculated in operation 511 to create a modified pattern of core material, including one or more core features having an adjusted critical dimension (e.g., CD2) measured in a horizontal direction corresponding to a target trim amount and a target trim profile.

[0043] In some embodiments, the method includes operations for measuring the values ​​of critical dimensions of one or more core features on a wafer, and determining a target trim amount and a target trim profile based on the measured values ​​of the critical dimensions of the one or more core features. In some embodiments, the target trim amount and the target trim profile are determined to compensate for WTW variations in the critical dimensions of the one or more core features on the wafer. In some embodiments, the target trim amount and the target trim profile are determined to compensate for plasma processing station performance. In some embodiments, the target trim amount and the target trim profile are determined to reduce non-uniformity of critical dimensions of the one or more core features across the wafer.

[0044] In some embodiments, the wafer includes a core material pattern formed on a target material layer, and a device structure is formed in the target material layer. For example, the wafer can be prepared for a SADP process. In these embodiments, after performing a plasma trimming process on the wafer, a mask material layer is conformally deposited on the modified core material pattern. Then, the mask material layer is etched to form a side spacer structure of the mask material on the core material and expose the top surface of the core material. Then, the core material is removed to leave a side spacer structure of the mask material above the target material layer. Then, the target material layer is etched to form a device structure in the target material below the side spacer structure of the mask material. Then, the side spacer structure of the mask material is removed from the wafer.

[0045] In some embodiments, the adjusted critical dimensions of the one or more core features are set at a first horizontal spacing between adjacent device structures within the target material. And, the combination of the adjusted critical dimensions of the one or more core features and the horizontal thickness of one of the side spacer structures of the mask material sets a second horizontal spacing between adjacent device structures within the target material. The first horizontal spacing and the second horizontal spacing occur between adjacent device structures within the target material in an alternating manner. In some embodiments, the target trim amount received in operation 503 and the target trim profile received in operation 505 are set to achieve substantial equality between the first horizontal spacing and the second horizontal spacing across the wafer. In some embodiments, the target trim amount received in operation 503 and the target trim profile received in operation 505 are set to partially control the horizontal spacing between device structures within the target material.

[0046] In some embodiments, the core feature 103 is formed by a first core material layer, the first core material layer is formed on a second core material layer, and the second core material layer is formed on a third core material layer, and the third core material layer is formed on a target material layer, and a device structure is formed in the target material layer. For example, the wafer can be prepared for a SAQP process. In these embodiments, after performing a plasma trimming process on the core feature 103 in operation 513, the second core material layer is etched to form a core structure of the second core material below the adjusted pattern of the core feature 103. Then, the core feature 103 is removed. After removing the core feature 103, a first mask material layer is conformally deposited on the core structure of the second core material. Then, the first mask material is etched to form a side spacer of the first mask material on the core structure of the second core material and expose the top surface of the core structure of the second core material. Then, the core structure of the second core material is removed. After removing the core structure of the second core material, etch the third core material layer to form a core structure of the third core material below the side spacers of the first mask material. Then, remove the side spacers of the first mask material. After removing the side spacers of the first mask material, conformally deposit the second mask material layer on the core structure of the third core material. Then, etch the second mask material to form the side spacers of the second mask material on the core structure of the third core material, and expose the top surface of the core structure of the third core material. Then, remove the core structure of the third core material. After removing the core structure of the third core material, etch the target material layer to form a device structure in the target material below the side spacers of the second mask material. Then, remove the side spacers of the second mask material.

[0047] In some embodiments, the operation 511 for determining the set of plasma trim process parameters to be used to achieve a target trim amount and a target trim profile on the wafer includes: determining / calculating a first set of plasma trim process parameters to be used for a base trim process; and determining / calculating a second set of plasma trim process parameters to be used for a flash trim process. In some embodiments, the second set of plasma trim process parameters or their values ​​for the flash trim process are different from the first set of plasma trim process parameters for the base trim process. For example, in some embodiments, the second set of plasma trim process parameters for the flash trim process may specify a process gas composition that is different from the first set of plasma trim process parameters for the base trim process. The difference between the second set of plasma trim process parameters for the flash trim process and the first set of plasma trim process parameters for the base trim process may be defined to provide more precise control over the etch amount achieved in the flash trim process compared to the base trim process. For example, the second set of plasma trim process parameters for the rapid trim process may specify a process gas composition that provides more precise control over the amount of etching achieved in the rapid trim process as compared to the base trim process.

[0048] In addition, the operation 513 of performing a plasma trim process on the wafer includes: performing a basic trim process on the wafer using a first set of plasma trim process parameters, and then performing a fast trim process on the wafer using a second set of plasma trim process parameters. In some embodiments, the basic trim process is performed on different wafers in different plasma processing stations in the same manner, while the fast trim process is different for different wafers in different plasma processing stations. In some embodiments, the basic trim process is performed simultaneously on different wafers in different plasma processing stations, while the fast trim process is performed sequentially on different wafers in different plasma processing stations.

[0049] In some embodiments, multiple wafers are processed simultaneously in multiple plasma processing stations (e.g., 340A, 340B, 340C, 340D) of a given multi-station processing tool (e.g., 300). In some embodiments, the basic trim process is performed simultaneously on multiple wafers in multiple plasma processing stations. Then, the rapid trim process for each wafer is performed in its respective plasma processing station. In some embodiments, the rapid trim process for multiple wafers is performed in a sequential manner, such that after the rapid trim process for a particular wafer is performed and completed in its corresponding plasma processing station, the rapid trim process for another wafer is performed in its corresponding plasma processing station.

[0050] In some embodiments, the critical dimensions of the core are controlled by Figure 5The method may be included in the overall method of combining the plasma trimming process of operation 513 with a deposition process. For example, in some embodiments, the overall method of combining the plasma trimming process of operation 513 with a deposition process may include alternating execution of the plasma trimming process and the deposition process. In this way, different on-wafer profiles can be coupled additively to produce a preferred compensation uniformity profile. For example, the dish-shaped profile plasma trimming process of operation 513 can be combined with a dome-shaped deposition profile to produce a differentiated and preferred net profile. And, in some embodiments, during the execution of the overall method, the cycle between the plasma trimming process of operation 513 and the deposition process can be performed two or more times, for example, first performing the plasma trimming process, then performing the deposition process, then performing the plasma trimming process, then performing the deposition process, and so on.

[0051] According to some embodiments, Figure 6 A flow chart of a method is shown for controlling a core critical dimension. The method includes an operation 601 for acquiring a plurality of wafers, wherein a pattern of core material is formed on each of the plurality of wafers. The pattern of core material includes a core feature having a critical dimension measured in a horizontal direction, wherein the horizontal direction is substantially parallel to a bottom surface of a given wafer. The method also includes an operation 603 for receiving a target trimming amount as an input parameter for each of the plurality of wafers. Each of the plurality of wafers has a respective target trimming amount. The target trimming amount for a particular wafer indicates an average thickness amount to be removed from a vertically oriented surface of a core feature of the particular wafer. The method also includes an operation 605 for receiving a target trimming profile as an input parameter for each of the plurality of wafers. Each of the plurality of wafers has a respective target trimming profile. The target trim profile for the particular wafer indicates how much variation in thickness removal from vertically-oriented surfaces of core features is applied as a function of radial position on the particular wafer between the center of the particular wafer and the peripheral edge of the particular wafer when performing the target trim amount on the particular wafer.

[0052] The method further includes an operation 607, wherein, for each of the plurality of wafers, a first set of data is accessed, the first set of data correlating a trim amount for the particular wafer with one or more plasma trim process parameters. The first set of data is applicable to a particular plasma processing station in which the particular wafer is to be processed. The method further includes an operation 609, wherein, for each of the plurality of wafers, a second set of data is accessed, correlating a trim profile for the particular wafer with one or more plasma trim process parameters. The second set of data is applicable to the particular plasma processing station in which the particular wafer is to be processed.

[0053] The method further includes an operation 611 for determining a base set of plasma trim process parameters for a base trim process on each of the plurality of wafers, wherein the base trim process is the same for each of the plurality of wafers. The determination of the base set of plasma trim process parameters in operation 611 is based on a target trim amount for each of the plurality of wafers, a target trim profile for each of the plurality of wafers, the first set of data for a plasma processing station, and the second set of data for a plasma processing station. In some embodiments, the base trim process is defined to process WTW CDNU. In various embodiments, the base set of plasma trim process parameters determined in operation 611 may substantially include any one or more plasma etch recipe parameters, such as parameters related to Figure 5 The method further includes an operation 613 for determining, for each of the plurality of wafers, a respective supplementary set of plasma trim process parameters for a respective rapid trim process performed on each of the plurality of wafers to achieve a target trim amount for a particular wafer and a target trim profile for a particular wafer, wherein the rapid trim process is customized for each of the plurality of wafers. The determination of the respective supplementary set of plasma trim process parameters in operation 613 is based on the target trim amount for each of the plurality of wafers, the target trim profile for each of the plurality of wafers, the first set of data for a plasma processing station, the second set of data for the plasma processing station, and the base set of plasma trim process parameters. In some embodiments, the rapid trim process is defined to handle WTW radial CD variations across the wafer. In various embodiments, the supplementary set of plasma trim process parameters determined in operation 613 may substantially include one or more of any plasma etching process recipe parameters, such as Figure 5 Operation 511 in the method has the parameters mentioned previously.

[0054] In some embodiments, the supplemental set of plasma trim process parameters, or values ​​thereof, determined in operation 613 may be different from the base set of plasma trim process parameters determined in operation 611. For example, in some embodiments, the supplemental set of plasma trim process parameters for the rapid trim process may specify a different process gas composition than the process gas composition specified in the base set of plasma trim process parameters for the base trim process. The difference between the supplemental set of plasma trim process parameters for the rapid trim process and the base set of plasma trim process parameters for the base trim process may be defined to provide more precise control over the amount of etching achieved in the rapid trim process as compared to the base trim process. For example, the supplemental set of plasma trim process parameters for the rapid trim process may specify a process gas composition that provides more precise control over the amount of etching achieved in the rapid trim process as compared to the base trim process.

[0055] The method further includes an operation 615 for performing the base trim process on each of the plurality of wafers in the particular plasma processing station in which the particular wafer is to be processed. The method further includes an operation 617, wherein, after the base trim process is completed, a respective rapid trim process is performed on each of the plurality of wafers in the particular plasma processing station in which the particular wafer is to be processed. In some embodiments, the base trim process is performed on each of the plurality of wafers in a simultaneous manner, while the rapid trim process is performed on different wafers in the plurality of wafers in a sequential manner.

[0056] In some embodiments, the critical dimensions of the core are controlled by Figure 6 The method may be included in the overall method of combining the basic trimming process of operation 615 and the rapid trimming process of operation 617 with the deposition process. For example, in some embodiments, the overall method of combining the basic trimming process of operation 615 and the rapid trimming process of operation 617 with the deposition process may include: the execution of the combination of the basic trimming process and the rapid trimming process is alternated with the execution of the deposition process. In this way, the profiles on different wafers can be coupled additively to produce a preferred compensated uniform profile. For example, the combination of the basic trimming process and the rapid trimming process that provide a dish-shaped profile can be combined with a dome-shaped deposition profile to produce a differentiated and preferred net profile. And, in some embodiments, the cycle operation between the combination of the basic trimming process and the rapid trimming process and the deposition process can be performed two or more times during the execution of the overall method, for example, the basic / rapid trimming process is performed first, followed by the deposition process, followed by the basic / rapid trimming process, followed by the deposition process, and so on.

[0057] According to some embodiments, Figure 7 A method is shown for controlling core critical dimensions on a plurality of wafers. The method includes an operation 701 for acquiring a plurality of wafers, wherein a pattern of core material is formed on each of the plurality of wafers. The pattern of core material includes core features having critical dimensions measured in a horizontal direction, wherein the horizontal direction is substantially parallel to a bottom surface of a given wafer. Each of the plurality of wafers is present in a separate one of a plurality of plasma processing stations. The method further includes an operation 703 for performing a basic trimming process on each of the plurality of wafers in a simultaneous manner in the plurality of plasma processing stations. The basic trimming process is defined to reduce the critical dimensions of the core features on the plurality of wafers. The basic trimming process is performed in the same manner in each of the plurality of plasma processing stations. The method further includes an operation 705, wherein, after the basic trimming process is completed, a wafer-specific rapid trimming process is performed on each of the plurality of wafers in the plurality of plasma processing stations. The wafer-specific rapid trimming process is defined to further reduce the critical dimensions of the core features on the plurality of wafers. A wafer-specific rapid trim process is performed in each of the plurality of plasma processing stations in an individually defined manner. The wafer-specific rapid trim process for a given wafer of the plurality of wafers is defined such that a combination of the base trim process for the given wafer and the wafer-specific rapid trim process achieves a wafer-specific target trim amount on the given wafer and achieves a wafer-specific target trim profile on the given wafer. In some embodiments, the wafer-specific rapid trim process is performed in a sequential manner on the plurality of wafers in the plurality of plasma processing stations such that one of the plurality of plasma processing stations is operated at a given time to perform the wafer-specific rapid trim process.

[0058] In some embodiments, the wafer-specific target trim amount and the wafer-specific target trim profile are received as input parameters for each of the plurality of wafers. Furthermore, a station-specific trim rate performance as a function of one or more plasma process parameters is received as an input parameter for each of the plurality of plasma processing stations. Furthermore, a station-specific trim profile performance as a function of one or more plasma process parameters is received as an input parameter for each of the plurality of plasma processing stations. Furthermore, the method further comprises: using the wafer-specific target trim amount, the wafer-specific target trim profile, the station-specific trim rate performance, and the station-specific trim profile performance, determining the specifications of the basic trim process and the wafer-specific rapid trim process for each of the plurality of wafers in the respective plurality of plasma processing stations. In various embodiments, for each of the plurality of wafers, the specifications of the basic trim process and the wafer-specific rapid trim process may substantially include one or more of any plasma etching process recipe parameters, for example Figure 5 The parameters of operation 511 of the method are mentioned previously.

[0059] To further explain Figure 6 and 7 In a method of processing a wafer, consider an example in which four wafers are to be processed in a four-station tool comprising four plasma processing stations. The target trim amounts for the four wafers are 78 angstroms for wafer 1, 79 angstroms for wafer 2, 76 angstroms for wafer 3, and 77 angstroms for wafer 4. And, the target trim profiles for the four wafers are specified in terms of P2%. P2% is defined as the difference between the average critical dimension value for the central region of the wafer and the average critical dimension value for the outer radial region of the wafer. The target trim amounts and target trim profiles for the four wafers are provided to a computer program to determine the specifications of the base trim process and the specifications of the fast trim process for each of the four wafers. The computer program may also access a first set of data that provides station-specific trim rate performance as a function of one or more plasma process parameters, such as an etch rate as a function of one or more process parameters for each plasma processing station. Furthermore, the computer program may access a second set of data that provides station-specific trim profile performance as a function of one or more plasma process parameters, such as P2% for each plasma processing station as a function of one or more plasma process parameters. In the first and second sets of data, the one or more plasma processing parameters may substantially include any plasma etching process recipe parameters, such as one or more process gas types and corresponding flow rates, pressures, temperatures, radio frequency (RF) powers, RF frequencies, bias voltages, etc. Based on the target trim amounts and target trim profiles for the four wafers and the first and second sets of data, the computer program determines a base trim process specification to be performed in an equivalent manner on all four wafers. For example, the base trim process specification may be set to trim 74 angstroms on all four wafers with a common trim profile (P2%). Furthermore, based on the target trim amounts and target trim profiles for the four wafers and the first and second sets of data, the computer program determines the specifications of the fast trim process to be performed on each of the four wafers. For example, the fast trim process for wafer 1 is defined to trim an additional 4 angstroms. The fast trim process for wafer 2 is defined to trim an additional 5 angstroms. The fast trim process for wafer 3 is defined to trim an additional 2 angstroms. The fast trim process for wafer 4 is defined to trim an additional 3 angstroms. The trim profile (P2%) used in the fast trim process for each wafer can be customized to achieve a target trim profile for each wafer.

[0060] In some embodiments, the base trim process is performed on all four wafers simultaneously. Then, the fast trim process is performed on the four wafers in a sequential manner, i.e., first on wafer 1, then on wafer 2, then on wafer 3, and then on wafer 4. In some embodiments, if the plasma processing stations can be operated in a completely independent manner (e.g., with separate and independently controllable power supply sources and gas supply sources), the fast trim processes can also be performed in a simultaneous manner.

[0061] According to some embodiments, Figure 8 Controller 800 is shown for controlling the core critical dimensions. In some embodiments, controller 800 may be Figure 2 The detection control and system control unit 210 and / or Figure 4 Also, in some embodiments, the controller 800 may be implemented separately and provide output to Figure 2 The controller 800 includes an input module 801, an analysis module 803, and an execution module 805. The input module 801 is configured to obtain a target trimming amount as an input parameter. The target trimming amount indicates the average thickness amount to be removed from the vertically oriented surface of the core feature on the wafer. The core feature forms a portion of a pattern of a core material on the wafer. The core feature has a critical dimension measured in a horizontal direction parallel to the bottom surface of the wafer. The input module 801 is configured to obtain a target trimming profile as an input parameter. The target trimming profile indicates how much of the variation in thickness removal from the vertically oriented surface of the core feature is applied as a function of the radial position on the wafer between the center of the wafer and the peripheral edge of the wafer when the target trimming amount is performed on the wafer. In some embodiments, the input module 801 is configured to obtain a measured value of the critical dimension of the core feature on the wafer, and determine the target trimming amount and the target trimming profile based on the measured value of the critical dimension of the core feature. The input module 801 is configured to obtain a first set of data that relates a trim amount to one or more plasma trim process parameters. The input module 801 is also configured to obtain a second set of data that relates a trim profile to one or more plasma trim process parameters.

[0062] The analysis module 803 is configured to determine a set of plasma trim process parameters for achieving a target trim amount and a target trim profile on the wafer based on the analysis of the first set of data and the second set of data. The execution module 805 is configured to direct the execution of a plasma trim process on the wafer using the set of plasma trim process parameters to establish a modified pattern of core material including core features having an adjusted critical dimension measured in a horizontal direction.

[0063] In some embodiments, the input module 801 is configured to obtain the target trim amount and the target trim profile as input parameters for a plurality of wafers, wherein each of the plurality of wafers has a separate target trim amount and a separate target trim profile. Furthermore, the input module 801 is configured to obtain the first set of data and the second set of data for each of a plurality of plasma processing stations. The analysis module 803 is configured to analyze the target trim amount for each of the plurality of wafers, the target trim profile for each of the plurality of wafers, the first set of data for each of the plurality of plasma processing stations, and the second set of data for each of the plurality of plasma processing stations to determine a basic set of plasma trim process parameters for a basic trim process performed on each of the plurality of wafers in a corresponding one of the plurality of plasma processing stations. The basic trim process is the same for each of the plurality of wafers. In addition, the analysis module 803 is configured to analyze the target trim amount for each of the plurality of wafers, the target trim profile for each of the plurality of wafers, the first set of data for each of the plurality of plasma processing stations, the second set of data for each of the plurality of plasma processing stations, and the basic set of plasma trim process parameters to determine a respective supplementary set of plasma trim process parameters for each of the plurality of wafers, the plasma trim process parameters being used for a respective rapid trim process performed on each of the plurality of wafers in a corresponding one of the plurality of plasma processing stations to achieve the target trim amount for the specific wafer and the target trim profile for the specific wafer. The rapid trim process is customized for each of the plurality of wafers. The execution module 805 is configured to direct the execution of the basic trim process on each of the plurality of wafers in the corresponding plasma processing station. And, the execution module 805 is configured to direct the execution of the rapid trim process on each of the plurality of wafers in the corresponding plasma processing station after the completion of the basic trim process.

[0064] In various embodiments, the controller 800 may include a processor, a memory, and one or more interfaces. The controller 800 may be used to control devices in one or more plasma processing stations based in part on sensed values. For example, the controller 800 may control one or more of the valve 802, the filter heater 804, the pump 806, and other components 808 based on sensed values ​​and other control parameters. The controller 800 receives sensed values ​​from, for example, a pressure gauge 810, a flow meter 812, a temperature sensor 814, and / or other sensors 816. The controller 800 may also be used to control process conditions during etching and deposition on one or more wafers. The controller 800 may include one or more memory devices and one or more computer processors.

[0065] The controller 800 can control activities associated with the core trim process in a given plasma processing station. The controller 800 executes a computer program that includes a set of instructions for controlling process timing, process gas delivery system temperature, and pressure differentials, valve positions, gas mixtures, process gas flow rates, chamber pressures, chamber temperatures, substrate temperatures, RF power levels, substrate chuck or pedestal positions, bias power, and other parameters of a particular process. Other computer programs stored on a memory device associated with the controller 800 may be used in some embodiments. Typically, there will be a user interface associated with the controller 800. The user interface may include a display 818 (e.g., a display screen and / or graphical software display of equipment and / or process conditions) and a user input device 820, such as a pointing device, keyboard, touch screen, microphone, etc.

[0066] The computer program for controlling the core trim process and other processes in the process sequence can be written in any conventional computer readable programming language: such as assembly language, C, C++, Pascal, Fortran or others. The compiled object code or script is executed by a processor to perform the work specified in the program. The control module parameters are related to process conditions, such as filter pressure difference, process gas composition and flow rate, temperature, pressure, plasma conditions (such as RF power level and low frequency RF frequency), cooling gas pressure and chamber wall temperature. The system software can be designed or configured in different ways. For example, various chamber component subroutines or control objects can be written to control the operation of chamber components required to perform the core trim process disclosed herein.

[0067] Examples of sensors that may be monitored during the core trim process include, but are not limited to: mass flow control modules, pressure sensors such as pressure gauge 810, thermocouples located in the delivery system, pedestal or chuck (e.g., temperature sensor 814 / 220). Appropriately programmed feedback and control algorithms may be used with data from these sensors to maintain desired process conditions. The foregoing describes the implementation of embodiments of the present disclosure in single or multi-chamber semiconductor processing tools.

[0068] In some implementations, the controller 800 is part of a system, which can be part of the above examples. Such a system can include a semiconductor processing device, which includes one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (substrate pedestals, gas flow systems, etc.). These systems can be integrated with electronic devices for controlling their operation before, during, and after the processing of semiconductor wafers or substrates. The controller 800 can control various components or subcomponents of one or more systems. Depending on the processing requirements and / or system type, the controller 800 can be programmed to control any process disclosed herein, including the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, substrate transfer in and out of tools and other transfer tools and / or load locks connected to or connected to a specific system through an interface.

[0069] In general, the controller 800 can be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. The integrated circuits can include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). The program instructions can be instructions sent to the controller 800 in the form of various individual settings (or program files) that define operating parameters for performing a particular process on a semiconductor substrate or system or for a semiconductor wafer or system. In some embodiments, the operating parameters can be part of a recipe defined by a process engineer to complete one or more processing steps during the processing of one or more (kinds of) layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0070] In some implementations, the controller 800 can be part of or coupled to a computer that is integrated with the system, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller 800 can be in the "cloud" or all or part of a wafer fab host system that can allow remote access to substrate processing. The computer can enable remote access to the system to monitor the current progress of processing operations, check the history of past processing operations, check trends or performance standards for multiple processing operations, change parameters of the current processing, set processing steps to follow the current processing, or start a new processing. In some examples, a remote computer (e.g., a server) can provide process recipes to the system over a network (which can include a local network or the Internet).

[0071] The remote computer may include a user interface that enables the input or programming of parameters and / or settings, which are then sent from the remote computer to the system. In some examples, the controller 800 receives instructions in the form of data that specify parameters for each processing step to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller 800 is configured to interface with or control. Thus, as described above, the controller 800 may be distributed, for example, by including one or more discrete controllers that are networked together and work toward a common purpose (e.g., the processes and controls described herein). An example of a distributed controller for such a purpose would be one or more integrated circuits on a plasma processing station that communicate with one or more integrated circuits located remotely (e.g., at a platform level or as part of a remote computer), which combine to control a process on the plasma processing station.

[0072] Exemplary systems that the controller 800 may interface with may include, but are not limited to, plasma etching chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, chamfer edge etching chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etching (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing system that may be associated with or used for processing and / or manufacturing of semiconductor wafers.

[0073] As described above, depending on one or more processing steps to be performed by the tool, the controller 800 can communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, a host computer, another controller, or tools used in material transport for transporting wafer containers to and from tool locations and / or load ports in a semiconductor processing factory.

[0074] Double patterning (DPT) processes using sacrificial spacer layers, such as SADP, have been used to process semiconductor chips at the latest technology nodes (e.g., 45 nanometers and below). One of the biggest challenges in the DPT process is to achieve tight control over the variability of CDNU and CDIMB of WiW and WTW. One of the main factors of CDNU and CDIMB of WiW and WTW is lithography. A core trimming process is used between the lithography process (in which the core mandrel is formed) and the side spacer deposition process to further reduce the critical dimensions of the core features. The main goal of the core trimming process is to reduce the critical dimensions of the core features of the patterned core mandrel. However, as shown by the methods and systems disclosed herein, the core trimming process can also be used to compensate for the input WiW and WTW critical dimension differences. As disclosed herein, a fast trimming process is provided, in which the core feature trimming amount, trimming profile, and CDNU can be controlled individually at each plasma processing station. The fast trimming process is achieved by first analyzing the input critical dimension measurements for WiW and WTW CDNU. The wafers are then processed through a common base trim process across multiple plasma processing stations. After the common base trim process, a rapid trim process is performed on each wafer to compensate for core feature trim amount, trim profile, and CDNU at each plasma processing station based on the input critical dimension metrology data.

[0075] Current double patterning techniques face issues such as CDNU and CDIMB. Prior to the methods and systems disclosed herein, there were no viable solutions to mitigate / reduce / eliminate CDNU and CDIMB. In the SADP spacer deposition method, CDNU and CDIMB are a result of both core lithography non-uniformity and sidewall spacer thickness non-uniformity. The methods and systems disclosed herein provide control over the core trimming step in the SADP process to improve WTW or WiW critical dimension variability. Specifically, the rapid trimming process disclosed herein provides flexibility to improve WTW variability of critical dimensions and enables control over WTW CDNU. The methods and systems disclosed herein provide wafer-level control over critical dimensions and CDNU.

[0076] Prior to the methods and systems disclosed herein, in SADP processes, the critical dimensions and CDNU were determined by how well the core lithography non-uniformity could be controlled and how well the side spacer thickness could be controlled. The methods and systems disclosed herein realize that the core feature trimming step can affect the core critical dimensions and can assist in modulating both the core critical dimensions and the gap critical dimensions. Thus, by providing flexible control over the core trimming process, the methods and systems disclosed herein provide improved control of the WTW critical dimensions and WTW CDNU.

[0077] The foregoing description of these embodiments is provided for the purpose of description and illustration. The above description is not intended to be comprehensive or to limit the present disclosure. The individual elements or features of a particular embodiment are generally not limited to that particular embodiment, but are replaceable and can be used in selected embodiments, even if not specifically shown or described, where applicable. It can also be varied in many ways. Such changes are not considered to depart from the present disclosure, and all such modifications are intended to be included within the scope of the present disclosure.

[0078] Although the foregoing disclosure is described in considerable detail for the purpose of clear understanding, it is apparent that some changes and modifications may be practiced within the scope of the embodiments disclosed herein. Therefore, the disclosure is considered to be illustrative rather than restrictive, and the disclosure is not limited to the details provided herein, but may be modified within the scope and equivalents of the embodiments.

Claims

1. A method for controlling a core critical dimension, comprising: obtaining a wafer having a pattern of core material formed thereon, the pattern of core material comprising one or more core features having a critical dimension measured in a horizontal direction, wherein the horizontal direction is parallel to a bottom surface of the wafer; receiving as an input parameter a target trim amount indicative of an average amount of thickness to be removed from a vertically-oriented surface of the one or more core features; receiving as an input parameter a target trim profile indicating how much of a variation in thickness removal from vertically-oriented surfaces of the one or more core features is applied as a function of radial position on the wafer between a center of the wafer and a peripheral edge of the wafer when performing the target trim amount on the wafer; accessing a first set of data that relates a trim amount to one or more plasma trim process parameters; accessing a second set of data relating the trim profile to one or more plasma trim process parameters; determining a set of plasma trimming process parameters for achieving the target trimming amount and the target trimming profile on the wafer based on the target trimming amount, the target trimming profile, the first set of data, and the second set of data; as well as A plasma trim process is performed on the wafer using the set of plasma trim process parameters to create a modified pattern of the core material including the one or more core features having an adjusted critical dimension measured in the horizontal direction.

2. The method according to claim 1, further comprising: measuring a value of the critical dimension of the one or more core features on the wafer; and Based on the values ​​of the measurements of the critical dimensions of the one or more core features, the target trim amount and the target trim profile are determined. 3 . The method of claim 2 , wherein the target trim amount and the target trim profile are determined to compensate for wafer-to-wafer variations in the critical dimensions of the one or more core features on the wafer. 4 . The method of claim 2 , wherein the target trim amount and the target trim profile are determined to compensate for plasma processing station performance.

5. The method of claim 2, wherein the target trim amount and the target trim profile are determined to reduce non-uniformity in the critical dimension of the one or more core features across the wafer.

6. The method of claim 1 , wherein determining a set of plasma trim process parameters for achieving the target trim amount and the target trim profile on the wafer comprises: determining a first set of plasma trim process parameters for a base trim process; and determining a second set of plasma trim process parameters for a fast trim process, and The performing of the plasma trimming process on the wafer comprises: performing the basic trimming process on the wafer using the first set of plasma trimming process parameters; and then performing the rapid trimming process on the wafer using the second set of plasma trimming process parameters.

7. The method of claim 6, wherein the base trim process is performed in the same manner on different wafers in different plasma processing stations, and wherein the fast trim process is different for different wafers in different plasma processing stations.

8. The method of claim 7, wherein the base trim processes are performed simultaneously on the different wafers in the different plasma processing stations, and wherein the fast trim processes are performed sequentially on the different wafers in the different plasma processing stations.

9. The method of claim 1, wherein the wafer comprises the pattern of the core material formed on a target material layer, wherein: A device structure will be formed in the target material layer.

10. The method according to claim 9, further comprising: after performing said plasma trimming process on said wafer, conformally depositing a layer of mask material on said modified pattern of said core material; etching the mask material layer to form side spacer structures of the mask material on the core material and expose a top surface of the core material; removing the core material and leaving the side spacer structures of the mask material over the target material layer; etching the target material layer to form the device structure in the target material below the side spacer structure of the mask material; as well as The side spacer structures of the mask material are removed.

11. The method of claim 10, wherein the adjusted critical dimensions of the one or more core features are set at a first horizontal spacing between adjacent device structures within the target material, wherein a combination of the adjusted critical dimensions of the one or more core features and a horizontal thickness of one of the side spacer structures of the mask material is set at a second horizontal spacing between adjacent device structures within the target material, and wherein the first horizontal spacing and the second horizontal spacing occur in an alternating manner between adjacent device structures within the target material.

12. The method of claim 11, wherein the target trim amount and the target trim profile are set to achieve substantial equality between the first horizontal pitch and the second horizontal pitch across the wafer.

13. A method according to claim 1, wherein the pattern of the core material is formed by a first core material layer, wherein the wafer includes the pattern of the core material formed on a second core material layer, wherein the second core material layer is formed on a third core material layer, wherein the third core material layer is formed on a target material layer, and a device structure will be formed in the target material layer.

14. The method according to claim 13, further comprising: after performing the plasma trimming process on the wafer, etching the second core material layer to form a core structure of the second core material beneath the adjusted pattern of the core material formed from the first core material layer; removing the first core material; conformally depositing a layer of a first mask material over the core structure of the second core material; etching the first mask material to form side spacers of the first mask material on the core structure of the second core material and to expose a top surface of the core structure of the second core material; removing the core structure of the second core material; etching the third core material layer to form a core structure of the third core material beneath the side spacers of the first mask material; removing the side spacers of the first mask material; conformally depositing a second mask material layer over the core structure of the third core material; etching the second mask material to form side spacers of the second mask material on the core structure of the third core material and to expose a top surface of the core structure of the third core material; removing the core structure of the third core material; etching the target material layer to form the device structure in the target material beneath the side spacers of the second mask material; as well as The side spacers of the second mask material are removed.

15. The method of claim 11, wherein the target trim amount and the target trim profile are set to partially control a horizontal spacing between device structures within the target material.

16. A controller for controlling a core critical dimension, comprising: an input module configured to obtain as an input parameter a target trim amount indicative of an average thickness amount to be removed from a vertically oriented surface of a core feature on a wafer, the core feature forming part of a pattern of core material on the wafer, the core feature having a critical dimension measured in a horizontal direction parallel to a bottom surface of the wafer, the input module being configured to obtain as an input parameter a target trim profile indicating how much of a variation in thickness removal from a vertically-oriented surface of the core feature is applied as a function of radial position on the wafer between a center of the wafer and a peripheral edge of the wafer when performing the target trim amount on the wafer; The input module is configured to obtain a first set of data that relates a trim amount to one or more plasma trim process parameters, The input module is configured to obtain a second set of data that relates the trimming profile to one or more plasma trimming process parameters; an analysis module configured to determine a set of plasma trimming process parameters for achieving the target trimming amount and the target trimming profile on the wafer based on an analysis of the first set of data and the second set of data; as well as An execution module is configured to direct execution of a plasma trim process on the wafer using the set of plasma trim process parameters to create a modified pattern of the core material including the core features having an adjusted critical dimension measured in the horizontal direction.

17. The controller of claim 16, wherein the input module is configured to obtain a measurement value of the critical dimension of the core feature on the wafer, and wherein the input module is configured to determine the target trimming amount and the target trimming profile based on the measurement value of the critical dimension of the core feature.

18. The controller of claim 16, wherein the input module is configured to obtain the target trim amount and the target trim profile as input parameters for a plurality of wafers, wherein each of the plurality of wafers has a separate target trim amount and a separate target trim profile, wherein the input module is configured to obtain the first set of data and the second set of data for each of a plurality of plasma processing stations, wherein the analysis module is configured to analyze the target trim amount for each of the plurality of wafers, the target trim profile for each of the plurality of wafers, the first set of data for each of the plurality of plasma processing stations, and the second set of data for each of the plurality of plasma processing stations to determine a base set of plasma trim process parameters for a base trim process on each of the plurality of wafers in a corresponding one of the plurality of plasma processing stations, wherein the base trim process is the same for each of the plurality of wafers, wherein the analysis module is configured to analyze the target trim amount for each of the plurality of wafers, the target trim profile for each of the plurality of wafers, the first set of data for each of the plurality of plasma processing stations, the second set of data for each of the plurality of plasma processing stations, and the base set of plasma trim process parameters to determine a respective supplementary set of plasma trim process parameters for each of the plurality of wafers, the respective supplementary set of plasma trim process parameters for a respective rapid trim process on each of the plurality of wafers in the corresponding one of the plurality of plasma processing stations to achieve the target trim amount for a particular wafer and the target trim profile for the particular wafer, wherein the rapid trim process is customized for each of the plurality of wafers, in, The execution module is configured to direct the execution of the base trim process on each of the plurality of wafers in a corresponding plasma processing station, and The execution module is configured to direct execution of the rapid trim process on each of the plurality of wafers in a corresponding plasma processing station after the basic trim process is completed.

19. A method for controlling a core critical dimension, comprising: obtaining a wafer having a pattern of core material formed thereon, the pattern of core material comprising one or more core features having a critical dimension measured in a horizontal direction, wherein the horizontal direction is parallel to a bottom surface of the wafer; receiving as an input parameter a target trim amount indicative of an average amount of thickness to be removed from a vertically-oriented surface of the one or more core features; accessing sets of data relating a trim amount to one or more plasma trim process parameters; determining a set of base trim plasma trim process parameters to be used in a base trim process based on the target trim amount and the set of data; and determining a set of rapid trim plasma trim process parameters to be used in a rapid trim process, wherein a combination of the base trim process and the rapid trim process is used to achieve the target trim amount on the wafer; as well as A plasma trim process is performed on the wafer, comprising using the set of base trim plasma trim process parameters and the set of fast trim plasma trim process parameters to create a modified pattern of the core material including the one or more core features having an adjusted critical dimension measured in the horizontal direction.

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