Display device

Abstract

The present disclosure relates to a display device, comprising: a substrate, comprising a display area and a pad area; a first conductive layer, located on the substrate; a first insulating film, located on the first conductive layer, the first insulating film having a first contact hole and a pad opening, the first contact hole being located in the display area to expose the first conductive layer, the pad opening exposing the first conductive layer in the pad area, the first conductive layer being arranged such that: in a first area covered by the first insulating film, a second conductive coating of the first conductive layer is completely located on the first conductive coating of the first conductive layer; in a second area overlapping with the first contact hole, the second conductive coating is completely located on the first conductive coating; and in a third area exposed by the pad opening, at least a portion of the first conductive coating is not covered by the second conductive coating.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0116542 filed on September 23, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a display device and a method of manufacturing the display device. Background Art

[0004] Electronic devices that provide images, such as televisions, smartphones, tablet PCs, digital cameras, notebook computers, and navigation devices, include display devices for displaying the images.

[0005] The display device may include a plurality of pixels and a pixel circuit for driving each pixel. Each pixel circuit includes a wiring and a thin film transistor located on an insulating substrate. A wiring pad is provided at the end of each wiring, and an external device is mounted on the wiring pad.

[0006] Such a display device can be formed by a multi-pass mask process. The mask process can be used to pattern wiring, insulating films, etc., but as the mask processes are added one by one, the process efficiency (e.g., the efficiency of the entire manufacturing process) will decrease. In addition, chemical materials are used in the mask process, and the chemical materials used as reaction materials have different etching selectivities depending on the materials included in the conductive layer. When the etching selectivities of the stacked conductive layers are different, during the mask process, a tip protruding from the surface of the conductive layer stacked above (e.g., the top conductive layer in the stacked conductive layers) may appear. When the tip of the conductive layer stacked above appears, cracks may appear in the passivation layer. Summary of the invention

[0007] Aspects of embodiments of the present disclosure provide a display device including a data conductive layer having high reliability.

[0008] However, aspects of the embodiments of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the embodiments of the present disclosure will become more apparent to one of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0009] According to an embodiment of the present disclosure, a display device includes: a substrate including a display area and a pad area; a first conductive layer located on the substrate; a first insulating film located on the first conductive layer; and a second conductive layer located on the first insulating film, the first conductive layer including a base layer, a main metal layer located on the base layer and including copper, a first conductive coating located on the main metal layer, and a second conductive coating located on the first conductive coating, the first insulating film having a first contact hole and a pad opening, the first contact hole being located in the display area and passing through the first insulating film in a thickness direction to expose the first conductive layer, the pad opening exposing the first conductive layer in the pad area, the first conductive layer being arranged such that: in a first area covered by the first insulating film, the second conductive coating is completely located on the first conductive coating; in a second area overlapping with the first contact hole, the second conductive coating is completely located on the first conductive coating; and in a third area exposed by the pad opening, at least a portion of the first conductive coating is not covered by the second conductive coating.

[0010] In an exemplary embodiment, the second conductive cladding layer includes Cu or ZIO.

[0011] In an exemplary embodiment, the first conductive cladding layer includes a material different from a material of the main metal layer.

[0012] In an exemplary embodiment, the first conductive cladding layer includes Ti.

[0013] In an exemplary embodiment, the base layer and the first conductive cladding layer include the same material.

[0014] In an exemplary embodiment, side surfaces of the base layer, the main metal layer, the first conductive cladding layer, and the second conductive cladding layer of the first conductive layer are aligned parallel to each other.

[0015] In an exemplary embodiment, the second conductive coating includes the same material as that of the main metal layer.

[0016] In an exemplary embodiment, the first conductive cladding layer and the base layer include the same material.

[0017] In an exemplary embodiment, the first conductive layer is connected to the second conductive layer through the first contact hole in the second region.

[0018] In an exemplary embodiment, the first conductive cladding layer of the first conductive layer is exposed by the pad opening in the third region.

[0019] According to the display device of the embodiment, the side surfaces of the conductive layer may be aligned in parallel to prevent cracks from occurring in the passivation layer.

[0020] Furthermore, according to the display device of the embodiment, the direct contact between the conductive layer constituting the wiring pad and the reaction material can be prevented to improve reliability.

[0021] Although some embodiments of the present disclosure have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and / or substitutions are possible, without departing from the scope and spirit of the disclosure as disclosed in the accompanying claims and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and other aspects and features of the present disclosure will become more apparent by describing in more detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0023] Figure 1 is a plan view of a display device according to an embodiment;

[0024] Figure 2 is a cross-sectional view of a display device according to an embodiment;

[0025] Figure 3 is a schematic layout diagram of a circuit layer of a first display substrate of a display device according to an embodiment;

[0026] Figure 4 is an equivalent circuit diagram of one pixel of a display device according to an embodiment;

[0027] Figure 5A is a cross-sectional view of a portion of a first display substrate of a display device according to an embodiment;

[0028] Figure 5B According to the embodiment Figure 5A An enlarged view of part A in FIG.

[0029] Figures 6 to 15 The manufacturing method according to the embodiment is shown in FIG. Figure 5A A cross-sectional view of a process step of a method for forming a portion of a first display substrate of a display device;

[0030] Fig.16 is a cross-sectional view of a first display substrate of a display device according to an embodiment;

[0031] Fig.17 and Fig.18 The manufacturing method according to the embodiment is shown in FIG. Fig.16 A cross-sectional view of a process step of a method for forming a portion of a first display substrate of a display device;

[0032] Fig.19According to the embodiment Figure 5A An enlarged view of part A in FIG.

[0033] Fig. 20 According to the embodiment Figure 5A An enlarged view of part A in FIG.

[0034] Fig.21 According to the embodiment Figure 5A an enlarged view of portion A in FIG. 1 ; and

[0035] Fig. 22 According to the embodiment Figure 5A Magnified view of part A in FIG. DETAILED DESCRIPTION

[0036] Some embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings, in which some embodiments of the present disclosure are shown. However, the present disclosure may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art.

[0037] It will also be understood that when a layer or substrate is referred to as being "on" another layer or substrate, the layer or substrate may be directly on the other layer or substrate, or one or more intermediate layers may be interposed therebetween. Throughout the specification, the same reference numerals indicate the same components. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. As used herein, terms in the singular are intended to include the plural form as well, unless the context clearly indicates otherwise.

[0038] It will be understood that, although terms such as "first", "second", etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. For example, without departing from the teachings of the present disclosure, the first element discussed below may be named as the second element. Similarly, without departing from the teachings of the present disclosure, the second element may also be named as the first element.

[0039] Hereinafter, some embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0040] Figure 1 is a plan view of a display device according to an embodiment.

[0041] The display device 1 may refer to any suitable electronic device that provides a display screen. Examples of the display device 1 may include a television, a notebook computer, a monitor, a billboard, a mobile phone, a smart phone, a tablet personal computer (tablet PC), an electronic watch, a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigator, a game console, a digital camera, and the Internet of Things (IoT).

[0042] The display device 1 can be classified in various ways according to the display method. For example, the display device 1 can be divided into an organic light-emitting display (OLED), an inorganic light-emitting display (inorganic EL), a quantum dot light-emitting display (QED), a micro-LED display (micro-LED), a nano-LED display (nano-LED), a plasma display panel (PDP), a field emission display device (FED), a cathode ray display device (CRT), a liquid crystal display (LCD), or an electrophoretic display device (EPD). In the following, an embodiment using an organic light-emitting display device as the display device 1 is described as an example, and unless other classifications are mentioned, the organic light-emitting display device applied to the embodiment is referred to as the display device 1. However, the embodiment is not limited to the organic light-emitting display device, and other suitable display devices, such as those listed above or generally available in the art, can be applied within the scope of the present disclosure.

[0043] The display device 1 may have a rectangular shape in a plan view (e.g., when viewed in a plan view). When the display device 1 is a television, the long side is generally oriented in a horizontal direction. However, the present disclosure is not limited thereto. The long side may be oriented in a vertical direction and may also be rotatable in a horizontal or vertical direction.

[0044] The display device 1 may include a display area DPA and a non-display area NDA. The display area DPA is an active area for displaying an image. In some embodiments, the display area DPA may have a similar shape to the entire display device 1. For example, when the display device 1 is rectangular in a plan view, the display area DPA may also be rectangular in a plan view.

[0045] The display area DPA may include a plurality of pixels PX. The plurality of pixels PX may be arranged in a matrix direction (e.g., in a matrix pattern). In a plan view, the shape of each pixel PX may be rectangular or square, but is not limited thereto. For example, each pixel PX may have a rhombus, each side of which is inclined relative to the direction of an edge of the display device 1. The plurality of pixels PX may include various color pixels PX. For example, the plurality of pixels PX may include, but are not limited to, a first color pixel PX of red, a second color pixel PX of green, and a third color pixel PX of blue. The color pixels PX may be arranged alternately in a stripe type or kind (e.g., a stripe pattern) or in a pentile type or kind (e.g., a pentile pattern).

[0046] The non-display area NDA may be around the display area DPA. The non-display area NDA may surround the display area DPA in whole or in part. The display area DPA may have a rectangular shape, and the non-display area NDA may be adjacent to four sides of the display area DPA. The non-display area NDA may constitute a frame of the display device 1.

[0047] A driving circuit or a driving element for driving the display area DPA may be located in the non-display area NDA. Figure 1 ) adjacent to a first non-display area NDA (e.g., a first portion of the non-display area NDA, such as a bottom side) and adjacent to a second long side (e.g., a top side, such as a bottom side) of the display device 1. Figure 1 In a second non-display area NDA (e.g., a second portion of the non-display area NDA, such as a top side) adjacent to the first short side (e.g., the left side, such as shown in FIG. 1 ), a pad unit may be provided on the display substrate of the display device 1, and an external device EXD may be mounted on a pad electrode of the pad unit. Examples of the external device EXD may include a connection film, a printed circuit board, a driver chip DIC, a connector, and a wiring connection film. Figure 1 In a third non-display area NDA (eg, a third portion of the non-display area NDA, such as the left side) adjacent to the display substrate of the display device 1 (as shown in FIG. 1 ), the scan driver SDR may be directly located on the display substrate of the display device 1 .

[0048] Figure 2 is a cross-sectional view of a display device according to an embodiment.

[0049] Figure 2 A front emission type or kind of display device in which light L is emitted from the light emitting layer EML in a direction toward the second substrate 210 rather than in a direction toward the first substrate 110 is shown, but the display device 1 is not limited thereto.

[0050] Reference Figure 2, the display device 1 may include a light emitting layer EML, an encapsulation structure 170 covering the light emitting layer EML, and color control structures WCL, TPL, and CFL located on the encapsulation structure 170. In an embodiment, the display device 1 may include a first display substrate 100 and a second display substrate 200 facing the first display substrate 100. The light emitting layer EML, the encapsulation structure 170, and the color control structures WCL, TPL, and CFL may be included in any one selected from the first display substrate 100 and the second display substrate 200.

[0051] For example, the first display substrate 100 may include a first substrate 110, a light emitting layer EML located on one surface of the first substrate 110, and an encapsulation structure 170 located on the light emitting layer EML. In some embodiments, the second display substrate 200 may include a second substrate 210, and a color control structure WCL, TPL, and CFL located on one surface of the second substrate 210 facing the first substrate 110. The color control structure may include a color filter layer CFL and a wavelength conversion layer WCL. In some pixels PX, the color control structure may further include a light transmission layer TPL at the same level (e.g., located on the same layer) as the wavelength conversion layer WCL.

[0052] The filling layer 300 may be located between the encapsulation structure 170 and the color control structures WCL, TPL, and CFL. The filling layer 300 may fill the space between the first display substrate 100 and the second display substrate 200 and combine them together.

[0053] The first substrate 110 of the first display substrate 100 may be an insulating substrate. The first substrate 110 may include a transparent material. For example, the first substrate 110 may include a transparent insulating material such as glass and / or quartz. The first substrate 110 may be a rigid substrate. However, the first substrate 110 is not limited thereto. The first substrate 110 may include a plastic such as polyimide and may have a flexible property that can be twisted, bent, folded and / or rolled.

[0054] A plurality of pixel electrodes PXE may be located on one surface of the first substrate 110. A plurality of pixel electrodes PXE may be used for each pixel PX (e.g., each corresponding pixel PX). The pixel electrodes PXE of adjacent (e.g., neighboring) pixels PX may be separated from each other. A circuit layer CCL for driving the pixel PX may be located on the first substrate 110. The circuit layer CCL may be located between the first substrate 110 and the pixel electrodes PXE. The circuit layer CCL will be described in more detail herein below.

[0055] The pixel electrode PXE may be a first electrode of a light emitting diode, for example, an anode. The pixel electrode PXE may have a laminated film structure in which indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) and / or indium oxide (In 2 O 3 ) and a reflective material layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) and / or a mixture thereof. The high work function material layer may be located above the reflective material layer and thus may be closer to the light emitting layer EML. The pixel electrode PXE may have a multilayer structure of ITO / Mg, ITO / MgF, ITO / Ag or ITO / Ag / ITO, but its structure is not limited thereto.

[0056] The pixel defining layer PDL may be located on a surface (e.g., upper surface) of the first substrate 110 along the boundary of the pixel PX (e.g., at the boundary of the pixel PX). The pixel defining layer PDL may be located on the pixel electrode PXE and may include an opening exposing the pixel electrode PXE. For example, in some embodiments, the pixel defining layer PDL may be located on a first portion of the pixel electrode PXE and may include an opening exposing a second portion of the pixel electrode PXE. The light emitting area EMA and the non-light emitting area NEM may be divided by the pixel defining layer PDL and its opening, respectively. For example, the light emitting area EMA may be separated by the pixel defining layer PDL, and the non-light emitting area NEM may be separated by the opening in the pixel defining layer PDL. The pixel defining layer PDL may include an organic insulating material, such as a polyacrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin and / or benzocyclobutene (BCB). The pixel defining layer PDL may include an inorganic material.

[0057] The light-emitting layer EML is located on the pixel electrode PXE exposed by the pixel defining layer PDL (for example, on a portion of the pixel electrode PXE). In an embodiment in which the display device 1 is an organic light-emitting display device, the light-emitting layer EML may include an organic layer, and the organic layer includes an organic material. The organic layer may include an organic light-emitting layer, and in some cases, may further include a hole injection / transport layer and / or an electron injection / transport layer as an auxiliary layer that facilitates light emission. In some embodiments in which the display device is a micro-LED display device or a nano-LED display device, etc., the light-emitting layer EML may include an inorganic material such as an inorganic semiconductor.

[0058] In some embodiments, the light-emitting layer EML may have a laminated structure including a plurality of organic light-emitting layers overlapping each other in the thickness direction and a charge generation layer located therebetween. As used herein, the thickness direction may refer to a direction perpendicular to the plane of the first display substrate 100 and extending from the first display substrate 100 to the second display substrate 200. The organic light-emitting layers overlapping each other may emit light of the same (e.g., substantially the same) wavelength, but are not limited thereto, and in some embodiments, they may emit light of different wavelengths. At least a portion of the light-emitting layer EML of each pixel PX may be separated from the same layer (e.g., light-emitting layer EML) of the adjacent (e.g., adjacent) pixel PX.

[0059] In an embodiment, the wavelength of light emitted from each light emitting layer EML may be the same for each color pixel PX. For example, the light emitting layer EML of each color pixel PX may emit blue light or ultraviolet light, and the color control structure may include a wavelength conversion layer WCL, thereby displaying a color for each pixel PX.

[0060] In some embodiments, the wavelength of light emitted from each light emitting layer EML may be different for each color pixel PX. For example, the light emitting layer EML of the first color pixel PX may emit light of a first color, the light emitting layer EML of the second color pixel PX may emit light of a second color, and the light emitting layer EML of the third color pixel PX may emit light of a third color.

[0061] The common electrode CME may be located on the light emitting layer EML. The common electrode CME may be in contact (eg, in physical contact or direct contact) not only with the light emitting layer EML but also with an upper surface of the pixel defining layer PDL.

[0062] The common electrode CME may be connected without distinguishing the pixels PX. For example, the common electrode CME may be commonly connected to the pixels PX. The common electrode CME may be a front (e.g., upper) electrode located over the entire surface of the light emitting layer EML without distinguishing the pixels PX. The common electrode CME may be a second electrode of the light emitting diode, e.g., a cathode.

[0063] The common electrode CME may include a material layer having a low work function, which includes Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF, Ba, a compound thereof and / or a mixture thereof (e.g., a mixture of Ag and Mg). The common electrode CME may also include a transparent metal oxide layer located on the low work function material layer.

[0064] The pixel electrode PXE, the light emitting layer EML, and the common electrode CME may constitute a light emitting element (eg, an organic light emitting element). Light emitted from the light emitting layer EML may be emitted upward through the common electrode CME.

[0065] The encapsulation structure 170 may be located on the common electrode CME. In some embodiments, the encapsulation structure 170 may be a thin film encapsulation structure. In some embodiments, the encapsulation structure 170 may include at least one thin film encapsulation layer. For example, the thin film encapsulation layer may include a first inorganic film 171, an organic film 172, and a second inorganic film 173. The first inorganic film 171 and the second inorganic film 173 may each include silicon nitride, silicon oxide, and / or silicon oxynitride. The organic film 172 may include an organic insulating material such as a polyacrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and / or benzocyclobutene (BCB).

[0066] The second display substrate 200 may be located above the encapsulation structure 170 to face the encapsulation structure 170. The second substrate 210 of the second display substrate 200 may include a transparent material. The second substrate 210 may include a transparent insulating material such as glass and / or quartz. The second substrate 210 may be a rigid substrate. However, the second substrate 210 is not limited thereto. The second substrate 210 may include a plastic such as polyimide and may have a flexible property that can be twisted, bent, folded and / or rolled.

[0067] The second substrate 210 may be the same substrate as the first substrate 110 (e.g., may have the same or substantially the same structure), but is not limited thereto, and in some embodiments, the second substrate 210 may have a different material, thickness, and / or transmittance, etc. from the first substrate 110. For example, the second substrate 210 may have a higher transmittance than the first substrate 110. The second substrate 210 may be thicker or thinner than the first substrate 110.

[0068] The light blocking member BML may be located on one surface (e.g., lower surface) of the second substrate 210 facing the first substrate 110 along the boundary (e.g., corresponding to the boundary) of the pixel PX. The light blocking member BML may overlap the pixel defining layer PDL of the first display substrate 100 and may be located in the non-emission area NEM. The light blocking member BML may include an opening that exposes one surface (e.g., a portion of the lower surface) of the second substrate 210 and overlaps the emission area EMA. In a plan view, the light blocking member BML may have a mesh shape.

[0069] The light blocking member BML may include an organic material. The light blocking member BML may reduce color distortion caused by external light reflection by absorbing external light. In some embodiments, the light blocking member BML may be used to prevent or reduce light emitted from the light emitting layer EML from intruding (eg, passing through or penetrating) into adjacent pixels PX.

[0070] In an embodiment, the light blocking member BML may absorb light of all visible wavelengths. The light blocking member BML may include a light absorbing material. For example, the light blocking member BML may include a material to be used as a black matrix of the display device 1 .

[0071] In some embodiments, the light blocking member BML may absorb light from a wavelength (e.g., a wavelength range) in the visible wavelengths and may transmit light from other wavelengths (e.g., other wavelength ranges) in the visible wavelengths. For example, the light blocking member BML may include the same material as the color filter layer CFL. For example, the light blocking member BML may include the same material as the blue color filter layer (e.g., the third color filter layer CFL3). In some embodiments, the light blocking member BML may be integrated with the blue color filter layer.

[0072] The light blocking member BML may be omitted.

[0073] The color filter layer CFL may be located on one surface (e.g., lower surface) of the second substrate 210 on which the light blocking member BML is located. The color filter layer CFL may be located on one surface (e.g., a portion of the lower surface) of the second substrate 210 exposed by the opening of the light blocking member BML. In addition, the color filter layer CFL may be located on a portion of the adjacent light blocking member BML.

[0074] The color filter layer CFL may include a first color filter layer CFL1 located on the first color pixel PX, a second color filter layer CFL2 located on the second color pixel PX, and a third color filter layer CFL3 located on the third color pixel PX. Each color filter layer CFL may include a colorant, such as a dye and / or a pigment, that absorbs light of a wavelength other than the corresponding color wavelength. The first color filter layer CFL1 may be a red color filter layer, the second color filter layer CFL2 may be a green color filter layer, and the third color filter layer CFL3 may be a blue color filter layer. Although it is shown in the figure that adjacent color filter layers CFL are separated from each other on the light blocking member BML, the adjacent color filter layers CFL may at least partially overlap each other on the light blocking member BML.

[0075] The first overcoat 220 may be located on the color filter layer CFL. The first overcoat 220 may prevent or reduce the occurrence of impurities such as moisture and / or air penetrating from the outside (e.g., penetrating through the color filter layer CFL or penetrating into the color filter layer CFL) to damage and / or contaminate the color filter layer CFL. In addition, the first overcoat 220 may prevent or reduce the color material of the color filter layer CFL from diffusing into another component.

[0076] The first overcoat layer 220 may be bonded to one surface (eg, a lower surface, such as a Figure 2 ) is in direct contact with the first coating 220. The first coating 220 may include an inorganic material. For example, the first coating 220 may include silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, and / or silicon oxynitride.

[0077] The partition wall PTL may be located on the first overcoat layer 220. The partition wall PTL may be located in the non-light emitting area NEM. The partition wall PTL may overlap with the light blocking member BML. The partition wall PTL may include an opening exposing the color filter layer CFL. In some embodiments in which the first overcoat layer 220 is included on the color filter layer CFL, the opening of the partition wall PTL may expose the first overcoat layer 220. The partition wall PTL may include, but is not limited to, a photosensitive organic material. The partition wall PTL may also include a light blocking material.

[0078] The wavelength conversion layer WCL and / or the light transmission layer TPL may be located in the space exposed by the opening of the partition wall PTL. The wavelength conversion layer WCL and the light transmission layer TPL may be formed by an inkjet process using the partition wall PTL as a bank (eg, well), but the present disclosure is not limited thereto.

[0079] In an embodiment where the light emitting layer EML of each pixel PX emits light of a third color (e.g., blue), the wavelength conversion layer WCL may include a first wavelength conversion pattern WCL1 located in the first color pixel PX and a second wavelength conversion pattern WCL2 located in the second color pixel PX. The light transmission layer TPL may be located in the third color pixel PX.

[0080] The first wavelength conversion pattern WCL1 may include a first base resin BRS1 and a first wavelength conversion material WCP1 in the first base resin BRS1. The second wavelength conversion pattern WCL2 may include a second base resin BRS2 and a second wavelength conversion material WCP2 in the second base resin BRS2. The light transmission layer TPL may include a third base resin BRS3 and a scatterer SCP therein.

[0081] The first base resin BRS1, the second base resin BRS2 and the third base resin BRS3 may include a transparent organic material. For example, the first base resin BRS1, the second base resin BRS2 and the third base resin BRS3 may include epoxy resin, acrylic resin, cardo resin and / or imide resin. The first base resin BRS1, the second base resin BRS2 and the third base resin BRS3 may include the same material, but the material thereof is not limited thereto.

[0082] The scatterer SCP may include metal oxide particles and / or organic particles. Examples of metal oxides may include titanium oxide (TiO 2 )、zirconia (ZrO2), aluminum oxide (Al 2 O 3 ), indium oxide (In 2 O 3 ), zinc oxide (ZnO) and / or tin oxide (SnO 2 ). Examples of the material of the organic particles may include acrylic resin and / or polyurethane resin.

[0083] The first wavelength conversion material WCP1 may convert light of a third color (e.g., blue) into light of a first color (e.g., red), and the second wavelength conversion material WCP2 may convert light of a third color (e.g., blue) into light of a second color (e.g., green). The first wavelength conversion material WCP1 and the second wavelength conversion material WCP2 may be quantum dots, quantum rods, and / or phosphors, etc. The quantum dots may include group IV nanocrystals, group II-VI compound nanocrystals, group III-V compound nanocrystals, group IV-VI compound nanocrystals, and / or combinations thereof. The first wavelength conversion pattern WCL1 and the second wavelength conversion pattern WCL2 may further include a scatterer SCP for improving wavelength conversion efficiency.

[0084] The light transmission layer TPL in the third color pixel PX transmits the light of the third color incident on the light emitting layer EML (e.g., emitted from the light emitting layer EML) while maintaining its wavelength. The scatterer SCP of the light transmission layer TPL can be used to control the emission path of the light emitted by (e.g., transmitted through) the light transmission layer TPL. The light transmission layer TPL may not include a wavelength conversion material.

[0085] The second cladding layer 230 is located on the wavelength conversion layer WCL and the light transmission layer TPL. In some embodiments, the second cladding layer 230 may be located on the partition wall PTL. The second cladding layer 230 may include an inorganic material. The second cladding layer 230 may include a material selected from the materials that may be included in the first cladding layer 220. The second cladding layer 230 and the first cladding layer 220 may include the same material, but the material thereof is not limited thereto.

[0086] The filling layer 300 may be located between the first display substrate 100 and the second display substrate 200. The filling layer 300 may fill the space between the first display substrate 100 and the second display substrate 200 and may combine them together. The filling layer 300 may be located between the encapsulation structure 170 of the first display substrate 100 and the second cover layer 230 of the second display substrate 200. The filling layer 300 may include Si-based organic materials and / or epoxy-based organic materials, etc., but its material is not limited thereto.

[0087] Hereinafter, the circuit layer CCL of the display device 1 will be described in more detail.

[0088] Figure 3 is a schematic layout diagram of a circuit layer of a first display substrate of a display device according to an exemplary embodiment.

[0089] Reference Figure 3 , a plurality of wirings are arranged on the first substrate 110. The plurality of wirings may include a scan line SCL, a sensing signal line SSL, a data line DTL, a reference voltage line RVL, and / or a first power line ELVDL.

[0090] The scan lines SCL and the sensing signal lines SSL may extend in the first direction DR1. The scan lines SCL and the sensing signal lines SSL may be connected to a scan driver SDR. The scan driver SDR may include a circuit layer CCL (see Figure 2 ) formed by the scanning driver SDR. For example, the scanning driver SDR may be connected to the circuit layer CCL. The scanning driver SDR may be located in the third non-display area NDA on the first substrate 110 (e.g., on the left side of the non-display area NDA), but the present disclosure is not limited thereto. For example, the scanning driver SDR may be located in the fourth non-display area NDA (e.g., on the right side of the non-display area NDA) or in both the third non-display area NDA and the fourth non-display area NDA. The scanning driver SDR may be connected to the signal connection wiring CWL, and at least one end of the signal connection wiring CWL may be formed (e.g., may be constituted or may be connected to) a signal connection wiring pad WPD_CW in the first non-display area NDA (e.g., the bottom side of the non-display area NDA) and / or the second non-display area NDA (e.g., the top side of the non-display area NDA) to be connected to an external device (EXD, such as Figure 1 ).

[0091] The data line DTL and the reference voltage line RVL may extend in a second direction DR2 that crosses (e.g., crosses perpendicularly or substantially crosses perpendicularly) the first direction DR1. The first power line ELVDL may include a portion extending in the second direction DR2. The first power line ELVDL may also include a portion extending in the first direction DR1. The first power line ELVDL may have a mesh structure (e.g., a mesh shape), but its structure (e.g., shape) is not limited thereto.

[0092] The wiring pad WPD may be at least one end of the data line DTL, the reference voltage line RVL, and the first power line ELVDL. In some embodiments, the wiring pad WPD may be at least one end of the signal connection wiring CWL. In some embodiments, the wiring pad WPD may include a data pad WPD_DT, a reference voltage pad WPD_RV, a first power pad WPD_ELVD, and a signal connection wiring pad WPD_CW. Each wiring pad WPD may be located in the non-display area NDA. In an embodiment, the data pad WPD_DT of the data line DTL may be located in the first non-display area NDA, and the reference voltage pad WPD_RV of the reference voltage line RVL and the first power pad WPD_ELVD of the first power line ELVDL may be located in the second non-display area NDA. In some embodiments, the data pad WPD_DT, the reference voltage pad WPD_RV, and the first power pad WPD_ELVD may all be located in the same area, for example, in the first non-display area NDA. As described above herein, the external device (EXD, such as Figure 1 The external device EXD may be mounted on the wiring pad WPD by an anisotropic conductive film and / or ultrasonic bonding or the like.

[0093] Each pixel PX located on the first substrate 110 includes a pixel driving circuit. The above wiring can apply a driving signal to each pixel driving circuit while passing through each pixel PX or its periphery (for example, while the driving signal passes through its wiring). The pixel driving circuit may include transistors and / or capacitors. The number of transistors and the number of capacitors in each pixel driving circuit may be any appropriate number and may be changed (for example, may be changed with different embodiments or with different pixels in the embodiments). Hereinafter, as an example, a pixel driving circuit having a 3T1C structure including three transistors and one capacitor will be described, but the present disclosure is not limited thereto. Pixel driving circuits having various appropriate structures such as a 2T1C structure, a 7T1C structure, and a 6T1C structure may be applied.

[0094] Figure 4 is an equivalent circuit diagram of one pixel of the display device according to the embodiment.

[0095] Reference Figure 4 , each pixel PX of the display device according to the embodiment includes three transistors DTR, STR1 and STR2 and one storage capacitor CST in addition to the light emitting element EMD.

[0096] The light emitting element EMD may emit light according to the current supplied through the driving transistor DTR. The light emitting element EMD may be implemented as an organic light emitting diode, a micro light emitting diode, a nano light emitting diode, or the like.

[0097] A first electrode (e.g., an anode electrode) of the light emitting element EMD can be connected (e.g., electrically connected) to the source electrode of the driving transistor DTR, and a second electrode (e.g., a cathode electrode) of the light emitting element EMD can be connected (e.g., electrically connected) to a second power line ELVSL, which is supplied with a low potential voltage (second power supply voltage) lower than a high potential voltage (first power supply voltage) of the first power line ELVDL.

[0098] The driving transistor DTR adjusts the current flowing from the first power line ELVDL supplied with the first power supply voltage to the light emitting element EMD according to the voltage difference between the gate electrode and the source electrode of the driving transistor DTR. The gate electrode of the driving transistor DTR can be connected (e.g., electrically connected) to the first source / drain electrode of the first switching transistor STR1, the source electrode of the driving transistor DTR can be connected (e.g., electrically connected) to the first electrode of the light emitting element EMD, and the drain electrode of the driving transistor DTR can be connected (e.g., electrically connected) to the first power line ELVDL supplied with the first power supply voltage.

[0099] The first switching transistor STR1 is turned on by a scanning signal of the scanning line SCL to connect (e.g., electrically connect) the data line DTL to the gate electrode of the driving transistor DTR. The gate electrode of the first switching transistor STR1 can be connected (e.g., electrically connected) to the scanning line SCL, the first source / drain electrode of the first switching transistor STR1 can be connected (e.g., electrically connected) to the gate electrode of the driving transistor DTR1, and the second source / drain electrode of the first switching transistor STR1 can be connected (e.g., electrically connected) to the data line DTL.

[0100] The second switch transistor STR2 is turned on by the sensing signal of the sensing signal line SSL to connect (e.g., electrically connect) the reference voltage line RVL to the source electrode of the drive transistor DTR. The gate electrode of the second switch transistor STR2 can be connected (e.g., electrically connected) to the sensing signal line SSL, the first source / drain electrode of the second switch transistor STR2 can be connected (e.g., electrically connected) to the reference voltage line RVL, and the second source / drain electrode of the second switch transistor STR2 can be connected (e.g., electrically connected) to the source electrode of the drive transistor DTR.

[0101] In an embodiment, the first source / drain electrode of each of the first switch transistor STR1 and the second switch transistor STR2 may be a source electrode, and the second source / drain electrode thereof may be a drain electrode. However, the present disclosure is not limited thereto. For example, in some embodiments, for at least one selected from the first switch transistor STR1 and the second switch transistor STR2, the first source / drain electrode and the second source / drain electrode may be a drain electrode and a source electrode, respectively.

[0102] The storage capacitor CST is located (eg, connected) between the gate electrode and the source electrode of the driving transistor DTR. The storage capacitor CST stores the difference voltage between the gate voltage (eg, the voltage at the gate electrode) and the source voltage (eg, the voltage at the source electrode) of the driving transistor DTR.

[0103] The driving transistor DTR and the first switching transistor STR1 and the second switching transistor STR2 may be thin film transistors. Figure 4 , the driving transistor DTR and the first switch transistor STR1 and the second switch transistor STR2 are shown as N-type metal oxide semiconductor field effect transistors (MOSFETs), but the present disclosure is not limited thereto. For example, the driving transistor DTR and the first switch transistor STR1 and the second switch transistor STR2 may be P-type MOSFETs, or some of them may be N-type MOSFETs and the others may be P-type MOSFETs.

[0104] Figure 5A is a cross-sectional view of a portion of a first display substrate of a display device according to an embodiment, Figure 5B yes Figure 5A Magnified view of part A in FIG.

[0105] exist Figure 5A , a cross section of a portion of the display area DPA and a cross section of a portion of the non-display area NDA are shown together. A cross section of the transistor area TRR and a cross section of the capacitor area CPR of the pixel are shown as being included in the cross section of the display area DPA, and a cross section of the pad area PDA is shown as being included in the cross section of the non-display area NDA. Figure 5AThe transistor region TRR shows the region where the drive transistor DTR among the three transistors is located. Figure 5A , for ease of illustration, only the pixel defining layer PDL in the stacked structure (eg, the stacked structure of the display device) is shown on the circuit layer CCL of the first display substrate 100 (eg, mainly on the circuit layer CCL of the first display substrate 100). Figure 5B is a cross-sectional view of a wiring pad WPD in the pad area PDA according to the embodiment.

[0106] Reference Figure 5A The circuit layer CCL includes a semiconductor layer 150, a plurality of conductive layers, and a plurality of insulating layers on the first substrate 110. The semiconductor layer 150 may include an oxide semiconductor. The plurality of conductive layers may include a lower metal layer 120, a gate conductive layer 130, and a data conductive layer 140. The plurality of insulating layers may include a buffer layer 161, a gate insulating film 162, an interlayer insulating film 163, a passivation layer 164, and a path layer 165.

[0107] For example, the lower metal layer 120 is located on the first substrate 110. The lower metal layer 120 may be a light blocking layer for protecting the semiconductor layer 150 from external light. The lower metal layer 120 has a patterned shape. The lower metal layer 120 may be located in the transistor region TRR. For example, in some embodiments, the lower metal layer 120 is not located in the capacitor region CPR. The lower metal layer 120 may be located below the semiconductor layer 150 to cover the semiconductor layer 150 on the lower metal layer 120 (e.g., overlap with it). For example, in some embodiments, the lower metal layer 120 is not located below the capacitor CST. The lower metal layer 120 may be located below the semiconductor layer 150 to cover at least the channel region of the semiconductor layer 150 (e.g., overlap with it), and in some embodiments, may cover the entire semiconductor layer 150 (e.g., overlap with it). The lower metal layer 120 may be electrically connected to the source electrode SEL of the driving transistor DTR through the first contact hole CNT1 to prevent or reduce the change in the voltage of the driving transistor DTR. The lower metal layer 120 may include a Ti / Cu double-layer film in which a titanium layer and a copper layer are stacked, but is not limited thereto.

[0108] The buffer layer 161 is located on the lower metal layer 120. The buffer layer 161 may cover the entire surface of the first substrate 110 on which the lower metal layer 120 is disposed. The buffer layer 161 may include silicon nitride, silicon oxide, and / or silicon oxynitride. In an embodiment, the buffer layer 161 may include SiN X / SiO X Double layer membrane.

[0109] The semiconductor layer 150 is located on the buffer layer 161. The semiconductor layer 150 is located in the transistor region TRR and forms a channel of the driving transistor DTR. The semiconductor layer 150 may include an oxide semiconductor. Examples of the oxide semiconductor may include a binary compound (AB X ), ternary compounds (AB X C Y ) and quaternary compounds (AB X C Y D Z ), each of which contains (e.g., includes) two, three, and four elements selected from indium, zinc, gallium, tin, titanium, aluminum, hafnium (Hf), zirconium (Zr), and magnesium (Mg), respectively. In an embodiment, the semiconductor layer 150 may include indium gallium zinc oxide (IGZO). In an embodiment, the semiconductor layer 150 may include indium tin zinc oxide (ITZO).

[0110] The gate insulating film 162 is located on the buffer layer 161. The gate insulating film 162 may have the same pattern as the gate conductive layer 130 described in more detail below. The gate insulating film 162 in the transistor region TRR (e.g., the portion of the gate insulating film 162 located in the transistor region TRR) may be located on the semiconductor layer 150, and the gate insulating film 162 in the capacitor region CPR may be located on the buffer layer 161. The sidewalls of the gate insulating film 162 may be substantially aligned with the sidewalls of the gate conductive layer 130 described in more detail below. The gate insulating film 162 may include a silicon compound and / or a metal oxide. For example, the gate insulating film 162 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, and / or titanium oxide. In an embodiment, the gate insulating film 162 may include SiO X membrane.

[0111] The gate conductive layer 130 is located on the gate insulating film 162. The gate electrode GEL in the transistor region TRR and the capacitor first electrode CEL1 (or lower electrode) in the capacitor region CPR may include the gate conductive layer 130. In addition, the scan line SCL and the sensing signal line SSL may include the gate conductive layer 130. The gate conductive layer 130 may not overlap with the data conductive layer 140 in the pad area PDA, which will be described in more detail below. In some embodiments, the gate conductive layer 130 is not located in the pad area PDA, but the present disclosure is not limited thereto. For example, in some embodiments, the gate conductive layer 130 is also formed in the pad area PDA.

[0112] The gate conductive layer 130 may include a single layer, or may include multiple layers. In an embodiment, the gate conductive layer 130 may include a gate main metal layer 130a and a gate base layer 130b located below the gate main metal layer 130a. Both the gate main metal layer 130a and the gate base layer 130b may include a conductive material. The insulating layer may not be between the corresponding constituent films of the gate conductive layer 130 that overlap each other in the thickness direction (e.g., between the gate main metal layer 130a and the gate base layer 130b). The gate main metal layer 130a and the gate base layer 130b may be patterned by a mask process.

[0113] The gate base layer 130b may be located below the gate main metal layer 130a to facilitate the film-forming properties of the gate main metal layer 130a such as adhesion (e.g., the gate main metal layer 130a adheres to the gate insulating film 162), and / or prevent or reduce the occurrence of reactive materials entering the gate main metal layer 130a from the gate insulating film 162 disposed below. In addition, the gate base layer 130b may prevent or reduce the diffusion of the material (e.g., copper) constituting the gate main metal layer 130a toward the adjacent lower film (e.g., the gate insulating film 162). The gate base layer 130b may include materials such as titanium (Ti), tantalum (Ta), calcium (Ca), chromium (Cr), magnesium (Mg) and / or nickel (Ni), but its materials are not limited thereto. The gate main metal layer 130a may be used to transmit signals and may include low resistance materials. The gate main metal layer 130a may be thicker than the gate base layer 130b and may include a material having a resistance lower than the resistance of the gate base layer 130b. The gate main metal layer 130 a may include a material such as copper (Cu), molybdenum (Mo), aluminum (Al), and / or silver (Ag), but the material thereof is not limited thereto.

[0114] The gate conductive layer 130 may further include a gate capping layer located on the gate main metal layer 130a. The gate capping layer covers the upper side of the gate main metal layer 130a to protect the gate main metal layer 130a. The gate capping layer may be in direct contact with the gate main metal layer 130a. However, the present disclosure is not limited thereto, and the gate capping layer may be thinner than the gate main metal layer 130a, and may include a material having a resistance higher than that of the gate main metal layer 130a. The gate capping layer may be used to protect the gate main metal layer 130a from the influence of a layer located on the gate conductive layer 130 or from the influence of an etchant or other chemical used during the process of manufacturing the display device 1. In addition, the gate capping layer may prevent or reduce the diffusion of a material (e.g., copper) constituting the gate main metal layer 130a toward an adjacent upper film (e.g., an interlayer insulating film 163).

[0115] The interlayer insulating film 163 is located on the gate conductive layer 130. The interlayer insulating film 163 may be completely located on the following layers: the gate conductive layer 130; the semiconductor layer 150 exposed by the gate conductive layer 130 and the gate insulating film 162; and the buffer layer 161 exposed by the gate conductive layer 130, the gate insulating film 162, and the semiconductor layer 150. The interlayer insulating film 163 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, and / or zinc oxide. In an embodiment, the interlayer insulating film 163 may include SiON.

[0116] Despite Figure 5A , the upper surface of the interlayer insulating film 163 is shown to be flat in the display area DPA, but the upper surface of the interlayer insulating film 163 including an inorganic material may have a step down (e.g., a step down shape or structure). Therefore, the thickness of the interlayer insulating film 163 of each segment may vary along the horizontal direction and may be measured from the same flat reference surface (e.g., the upper surface of the buffer layer 161) that does not have a step down structure.

[0117] The data conductive layer 140 is located on the interlayer insulating film 163. The source electrode SEL and the drain electrode DEL in the transistor region TRR, the capacitor second electrode CEL2 (or upper electrode) in the capacitor region CPR, and the wiring pad WPD in the pad area PDA may each include a portion of the conductive layer 140. The source electrode SEL and the drain electrode DEL may each be connected to the semiconductor layer 150 through a second contact hole CNT2 passing through the interlayer insulating film 163. The source electrode SEL may also be connected to the lower metal layer 120 through a first contact hole CNT1 passing through the interlayer insulating film 163 and the buffer layer 161. In addition, the data line DTL, the reference voltage line RVL, and the first power line ELVDL may each include a portion of the data conductive layer 140.

[0118] Reference Figure 5A and Figure 5B , the data conductive layer 140 may have a stacked structure including a data conductive metal layer 141, a first data cover layer 142 located on the data conductive metal layer 141, and a second data cover layer 143 located on the first data cover layer 142. The data conductive metal layer 141 may include a single layer, or may include a plurality of layers. In an embodiment, the data conductive metal layer 141 may include a data main metal layer 141a and a data base layer 141b located below the data main metal layer 141a.

[0119] The data base layer 141b, the data main metal layer 141a, the first data cover layer 142 and the second data cover layer 143 may all include a conductive material. An insulating layer may not be interposed between the corresponding component layers of the data conductive layer 140 that overlap each other in the thickness direction. The data base layer 141b, the data main metal layer 141a, the first data cover layer 142 and the second data cover layer 143 may be patterned through a mask process. The process of forming the stacked structure of the data conductive layer 140 will be described in more detail below.

[0120] Similar to the gate base layer 130b, the data base layer 141b may contribute to film forming properties of the data main metal layer 141a, such as adhesion (e.g., the data main metal layer 141a adheres to the first data cap layer 142), and / or prevent or reduce the occurrence of reactive materials entering the data main metal layer 141a from the interlayer insulating film 163 disposed therebelow. The data base layer 141b may include materials such as titanium (Ti), tantalum (Ta), calcium (Ca), chromium (Cr), magnesium (Mg), and / or nickel (Ni), but the materials thereof are not limited thereto.

[0121] The data main metal layer 141a may be used to transmit a signal and may include a low resistance material. The data main metal layer 141a may be thicker than the data base layer 141b, the first data cover layer 142, and the second data cover layer 143. The data main metal layer 141a may include a material having a lower resistance than the first data cover layer 142 directly on the data main metal layer 141a and / or the data base layer 141b directly below the data main metal layer 141a. The data main metal layer 141a may include a material such as copper (Cu), aluminum (Al), silver (Ag), and / or molybdenum (Mo), but the material thereof is not limited thereto.

[0122] The first data overlay layer 142 covers and protects the data main metal layer 141a from above. During a manufacturing process (e.g., a process of forming the pixel electrode PXE) after forming the data conductive layer 140 described in more detail below, even when the second data overlay layer 143 is exposed to an etchant or other chemical used in the manufacturing process and is etched, the first data overlay layer 142 (e.g., a portion of the first data overlay layer 142 located in the pad area PDA) can still be located on the uppermost layer of the data conductive layer 140 (e.g., can be the uppermost layer of the data conductive layer 140), thereby serving to protect the data main metal layer 141a. In addition, during the manufacturing process, the first data overlay layer 142 can prevent or reduce the path layer 165 located on the data conductive layer 140 from directly contacting the data main metal layer 141a, thereby preventing or reducing the data main metal layer 141a from being corroded by the material of the path layer 165. In addition, the first data cover layer 142 may prevent or reduce diffusion of a material (eg, copper) constituting the data main metal layer 141a toward an adjacent upper film (eg, the passivation layer 164). The first data cover layer 142 may directly contact the data main metal layer 141a.

[0123] The first data cover layer 142 may include Ti, ZIO and / or IZO. For example, the first data cover layer 142 may include a single film such as a Ti film, a ZIO film or an IZO film, but the present disclosure is not limited thereto, and in some embodiments, the first data cover layer 142 may include a plurality of films thereof.

[0124] The second data overlay layer 143 is located on the first data overlay layer 142. The second data overlay layer 143 may include a material having the same selectivity as the data main metal layer 141a for an etchant used in the same etching process. For example, in some embodiments, the selectivity of the second data overlay layer 143 may be the same or similar to the selectivity of the data main metal layer 141a for the same etchant. For example, when the data main metal layer 141a includes copper (Cu), the second data overlay layer 143 may include copper (Cu) or ZIO, etc., which has the same or similar selectivity as the selectivity of copper (Cu) included in the data main metal layer 141a.

[0125] When the second data cover layer 143 includes a material having a selectivity similar to that of the data main metal layer 141a for the same etchant, even when the first data cover layer 142 located on the data main metal layer 141a includes a material having a selectivity different from that of the data main metal layer 141a for the same etchant, the occurrence of a tip formed by protrusion of the first data cover layer 142 outwardly (e.g., away from the upper surface of the data main metal layer 141a) may be suppressed (e.g., reduced). More details thereof will be described herein below.

[0126] When a tip appears in the first data overlay layer 142 located on the data main metal layer 141a, during the deposition process of the passivation layer 164 to be described in more detail herein below, the tip of the first data overlay layer 142 may cause the occurrence of a crack (e.g., a crack in the passivation layer 164) due to poor step coverage. For example, in the second data overlay layer 143 including a material having a selectivity similar to that of the material included in the data main metal layer 141a for the same etchant, during the process of forming the conductive pattern of the data conductive layer 140, its selectivity varies depending on the material included in each constituent layer of the data conductive layer 140. Therefore, the second data overlay layer 143 may be used to prevent or reduce the occurrence of a tip formed on the upper surface of the data main metal layer 141a. Therefore, the reliability of the circuit layer CCL may be improved.

[0127] In an embodiment, the data conductive layer 140 may include a data base layer 141b including titanium (Ti), a data main metal layer 141a including copper (Cu), a first data cladding layer 142 including titanium (Ti), and a second data cladding layer 143 including copper (Cu). For example, the data conductive layer 140 may include a four-layer film of Ti / Cu / Ti / Cu. When the data conductive layer 140 includes a four-layer film of Ti / Cu / Ti / Cu, the side surfaces (or side walls) of the data base layer 141b, the data main metal layer 141a, the first data cladding layer 142, and the second data cladding layer 143 may be aligned with each other. For example, the upper surface of a layer constituting the data conductive layer 140 and the lower surface of another layer constituting the data conductive layer 140 located on the upper surface and in contact with the upper surface may be aligned without protruding from each other. For example, in some embodiments, the upper surface of a first layer included in the data conductive layer 140 and the lower surface of a second layer included in the data conductive layer 140 located on the upper surface of the first layer and in contact with the upper surface of the first layer may be aligned without protruding from each other. In some embodiments, ZIO is applied to the second data cap layer 143 (eg, the second data cap layer 143 includes ZIO, or is ZIO), so that the data conductive layer 140 may have a stacked structure of Ti / Cu / Ti / ZIO.

[0128] Reference Figure 5B , the thicknesses of the data main metal layer 141a, the data base layer 141b, the first data cover layer 142, and the second data cover layer 143 of the data conductive layer 140 may be different from each other. The respective thicknesses t1, t2, t3, and t4 of the layers 141a, 141b, 142, and 143 constituting the data conductive layer 140 will each be defined as the distance from the lower surface to the upper surface of each respective layer.

[0129] As described above herein, the thickness t1 of the data main metal layer 141a may be greater than the thickness t2 of the data base layer 141b, the thickness t3 of the first data cover layer 142, and the thickness t4 of the second data cover layer 143. The respective thicknesses t2 and t3 of the data base layer 141b and the first data cover layer 142, which are in direct contact with the lower and upper surfaces of the data main metal layer 141a and protect the data main metal layer 141a, respectively, may be sufficiently (e.g., appropriately) thick. The thickness t4 of the second data cover layer 143, which is not in direct contact with the data main metal layer 141a and is partially removed in a subsequent process (described in more detail herein below), may not be as thick as the respective thicknesses t2 or t3 of the data base layer 141b or the first data cover layer 142. In an exemplary embodiment, when the data conductive layer 140 is a four-layer film of Ti / Cu / Ti / Cu, the thickness t1 of the data main metal layer 141a is t2. The thickness t2 of the data base layer 141b is The thickness t3 of the first data cover layer 142 is And the thickness t4 of the second data cover layer 143 can be or greater and or smaller (e.g., in to As used herein, the term refers to angstroms, which is equal to 10 -10 The unit of distance is meter. The thickness t4 of the second data cover layer 143 can be or greater and or less, so that the second data cover layer 143 exposed by the pad opening PDOP can be easily etched in an etching process of a material layer for the pixel electrode PXE, which will be described in more detail herein below.

[0130] Refer to Figure 5A The data conductive layer 140 may include a first region 140B, a second region 140A, and a third region 140C, depending on the structure of the second data cover layer 143 as the uppermost layer of the data conductive layer 140 and / or the structure of a layer located on the data conductive layer 140 and contacting the upper surface of the second data cover layer 143. In the first region 140B, the second region 140A, and the third region 140C of the data conductive layer 140, the structure of the second data cover layer 143 of the data conductive layer 140 may be different, and / or the layer contacting the upper surface of the second data cover layer 143 may be different. More details of the respective regions 140A, 140B, and 140C of the data conductive layer 140 will be described in more detail herein below.

[0131] The passivation layer 164 is located on the data conductive layer 140. The passivation layer 164 is used to cover and protect the data conductive layer 140. The passivation layer 164 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, and / or zinc oxide.

[0132] The passivation layer 164 may be completely in the display area DPA (e.g., in the entire display area DPA) and not exist in at least a portion of the non-display area NDA. The passivation layer 164 may not be located in (e.g., may not exist in) at least a portion of the third area 140C of the data conductive layer 140 or the wiring pad WPD included in the pad area PDA in the non-display area NDA. In some embodiments, the passivation layer 164 does not overlap at least a portion of the third area 140C of the data conductive layer 140.

[0133] The via layer 165 is located on the passivation layer 164. The via layer 165 may cover an upper surface of the passivation layer 164 (eg, an upper surface of the passivation layer 164 in the display area DPA and in the non-display area NDA), and may cover a side surface of an end portion of the passivation layer 164 in the pad area PDA.

[0134] The path layer 165 may be provided with a pad opening PDOP, and the pad opening PDOP exposes at least a portion of the passivation layer 164 in the pad area PDA and the third area 140C of the data conductive layer 140. The path layer 165 (e.g., a portion of the path layer 165) constituting the inner wall of the pad opening PDOP may cover the side surface of the end of the passivation layer 164 in the pad area PDA, but the present disclosure is not limited thereto. For example, the pad opening PDOP may be formed by the passivation layer 164 and the path layer 165 in the pad area PDA, and the inner walls of the passivation layer 164 and the path layer 165 forming the pad opening PDOP may be aligned with each other.

[0135] The path layer 165 may include an organic insulating material, such as a polyacrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene oxide resin, a polyphenylene sulfide resin, and / or benzocyclobutene (BCB). The path layer 165 may also include a photosensitive material, but the material thereof (e.g., the path layer 165) is not limited thereto. In an embodiment, the path layer 165 may include polyimide.

[0136] The pixel electrode PXE is located on the path layer 165. The material constituting the pixel electrode PXE is similar to the reference Figure 2 The material described is the same as that of the pixel electrode PXE, for example. In an embodiment, the pixel electrode PXE may include a three-layer film of ITO / Ag / ITO.

[0137] The pixel electrode PXE may be located in the display area DPA and not in the non-display area NDA. The pixel electrode PXE may overlap with the transistor region TRR and the capacitor region CPR of the display area DPA, but the present disclosure is not limited thereto. The pixel electrode PXE may be connected to the source electrode SEL of the driving transistor DTR through the third contact hole CNT3 passing through the path layer 165 and the passivation layer 164.

[0138] The pixel defining layer PDL may be located in the display area DPA and not in the non-display area NDA. The pixel defining layer PDL overlaps the edge portion of the pixel electrode PXE. The pixel defining layer PDL is also located on the path layer 165 where the pixel electrode PXE is not formed. For example, in some embodiments, the pixel defining layer PDL may not exist in the non-display area NDA.

[0139] Hereinafter, the above-mentioned regions 140A, 140B, 140C of the data conductive layer 140 will be described in more detail.

[0140] The data conductive layer 140 may include a first region 140B completely covered by the passivation layer 164, a second region 140A overlapping the third contact hole CNT3, and a third region 140C exposed by the pad opening PDOP. The first region 140B and the second region 140A of the data conductive layer 140 are located in the display area DPA, and the third region 140C of the data conductive layer 140 is located in the non-display area NDA.

[0141] The second region 140A of the data conductive layer 140 may be located in the transistor region TRR. The source electrode SEL of the driving transistor DTR may include (e.g., may be) the second region 140A of the data conductive layer 140 located in the transistor region TRR. The first region 140B of the data conductive layer 140 may be located in the transistor region TRR of the display region DPA and / or in the capacitor region CPR. The source / drain electrode of the transistor (e.g., the drain electrode DEL of the driving transistor DTR) and / or the capacitor second electrode CEL2 of the storage capacitor CST may include (e.g., may be) the first region 140B of the data conductive layer 140.

[0142] In the data conductive areas 140A and 140B in the display area DPA, the second data cover layer 143 may completely cover the upper surface of the first data cover layer 142. For example, the first data cover layer 142 of the second area 140A of the data conductive layer 140 and the first data cover layer 142 of the first area 140B of the data conductive layer 140 may not be exposed by the second data cover layer 143.

[0143] The passivation layer 164 and the pixel electrode PXE may be located on the upper surface of the second region 140A of the data conductive layer 140. The second region 140A of the data conductive layer 140 may be connected to the pixel electrode PXE through the third contact hole CNT3. For example, the passivation layer 164 and the pixel electrode PXE may be located on the upper surface of the second data overlay layer 143 of the second region 140A of the data conductive layer 140. The pixel electrode PXE may be located on at least a portion of the upper surface of the second data overlay layer 143 of the second region 140A of the data conductive layer 140 overlapping the third contact hole CNT3, and the passivation layer 164 may be located on the rest of the upper surface of the second data overlay layer 143 of the second region 140A of the data conductive layer 140. The pixel electrode PXE may fill the inner space of the third contact hole CNT3 and contact the upper surface of the second data overlay layer 143 of the second region 140A of the data conductive layer 140 overlapping the third contact hole CNT3 to electrically connect the upper surfaces thereof.

[0144] The passivation layer 164 may be located on an upper surface of the first region 140B of the data conductive layer 140. For example, the passivation layer 164 may be located on an upper surface of the second data cover layer 143 of the first region 140B of the data conductive layer 140. The passivation layer 164 located on an upper surface of the second data cover layer 143 of the first region 140B of the data conductive layer 140 may be located on an entire surface of the second data cover layer 143 of the first region 140B of the data conductive layer 140 to completely cover the first region 140B of the data conductive layer 140.

[0145] The third region 140C of the data conductive layer 140 may be located in the pad area PDA. The wiring pad WPD of the pad area PDA may include (eg, may be) the third region 140C of the data conductive layer 140 located in the pad area PDA.

[0146] In the data conductive layer 140 in the non-display area NDA, for example, in the third area 140C of the data conductive layer 140, the second data cover layer 143 of the third area 140C of the data conductive layer 140 may not at least partially overlap with the first data cover layer 142. Therefore, the second data cover layer 143 of the third area 140C of the data conductive layer 140 may expose at least a portion of the upper surface of the first data cover layer 142 of the third area 140C of the data conductive layer 140. The second data cover layer 143 of the third area 140C of the data conductive layer 140 may not be located in an area overlapping with the pad opening PDOP. Therefore, the upper surface (for example, at least a portion of the upper surface) of the first data cover layer 142 of the third area 140C of the data conductive layer 140 may be exposed by the pad opening PDOP.

[0147] The second data cover layer 143 of the third region 140C of the data conductive layer 140 may include an inner side surface located at the pad opening PDOP side and an outer side surface located at a side opposite to the side where the inner side surface is located. In an embodiment, the inner side surface of the second data cover layer 143 of the third region 140C of the data conductive layer 140 may be aligned with the inner wall of the path layer 165 constituting the pad opening PDOP. However, the present disclosure is not limited thereto, and the inner side surface of the second data cover layer 143 of the third region 140C of the data conductive layer 140 may not be aligned with the inner wall of the path layer 165. As described above, the outer side surface of the second data cover layer 143 of the third region 140C of the data conductive layer 140 may be aligned with the side surface of the first data cover layer 142 below the second data cover layer 143.

[0148] The data conductive layer 140 may be referred to as a first conductive layer, the pixel electrode PXE may be referred to as a second conductive layer, and the gate conductive layer 130 may be referred to as a third conductive layer. The data base layer 141b, the data main metal layer 141a, the first data overlay layer 142, and the second data overlay layer 143 constituting the first conductive layer (e.g., the data conductive layer 140) may be referred to as a base layer, a main metal layer, a first conductive overlay layer, and a second conductive overlay layer, respectively. The passivation layer 164 located between the first conductive layer (e.g., the data conductive layer 140) and the second conductive layer (e.g., the pixel electrode PXE) may be referred to as a first insulating film, and the interlayer insulating film 163 located between the first conductive layer (e.g., the data conductive layer 140) and the third conductive layer (e.g., the gate conductive layer 130) may be referred to as a second insulating layer.

[0149] Hereinafter, a method of manufacturing a display device will be described.

[0150] Figures 6 to 15 The manufacturing method according to the embodiment is shown in FIG. Figure 5A A cross-sectional view of a process step of a method for forming a portion of a first display substrate of a display device.

[0151] Reference Figure 6 First, a patterned lower metal layer 120 is formed on the first substrate 110. The patterned lower metal layer 120 may be formed by a mask process. For example, a material layer for the lower metal layer 120 is completely deposited on the first substrate 110, and the material layer for the lower metal layer 120 is patterned by a photolithography process, thereby forming Figure 6 The lower metal layer 120 is shown in FIG.

[0152] Then, refer to Figure 7, a buffer layer 161 is formed on the entire surface of the first substrate 110 on which the lower metal layer 120 is formed. For example, the buffer layer 161 may be located on the first substrate 110 and on the lower metal layer 120. Subsequently, a semiconductor layer 150 is formed on the buffer layer 161. The semiconductor layer 150 may be formed by a mask process. For example, an oxide semiconductor is completely deposited on the buffer layer 161, and the oxide semiconductor is patterned by a photolithography process, thereby forming Figure 7 The semiconductor layer 150 is shown in FIG.

[0153] Then, refer to Figure 8 A patterned gate insulating film 162 and a gate conductive layer 130 are formed on the buffer layer 161 on which the semiconductor layer 150 is formed. For example, the gate insulating film 162 and the gate conductive layer 130 may be formed on the buffer layer 161 and on the semiconductor layer 150. The patterned gate insulating film 162 and the gate conductive layer 130 may be formed by one mask process.

[0154] For example, a material layer for the gate insulating film 162 is deposited on the buffer layer 161 on which the semiconductor layer 150 is formed. For example, a material layer for the gate insulating film 162 may be deposited on the buffer layer 161 and on the semiconductor layer 150. Then, a material layer for the gate base layer 130b and a material layer for the gate main metal layer 130a are sequentially deposited on the material layer for the gate insulating film 162. Then, a photoresist layer is applied on the material layer for the gate main metal layer 130a, a photoresist pattern is formed by exposure and development, and then the material layer for the gate main metal layer 130a, the material layer for the gate base layer 130b, and the material layer for the gate insulating film 162 are sequentially etched using the photoresist pattern as a mask. Then, the photoresist pattern is removed by a stripping or ashing process. Although the case where the photoresist pattern is used as an etching mask until the gate insulating film 162 is patterned has been described above, the embodiments of the present disclosure are not limited thereto. In some embodiments, the patterned upper layer can be used as a hard mask for etching its lower layer. In this case, the photoresist pattern can be used together with the hard mask as an etching mask. For example, in some embodiments, the photoresist pattern can be used to pattern the upper layer (e.g., the material layer for the gate main metal layer 130a), and the patterned upper layer (e.g., the gate main metal layer 130a) can be used as an etching mask to etch the lower layer (e.g., the material layer for the gate base layer 130b and the gate insulating film 162). In some embodiments, a hard mask is formed, the photoresist pattern is removed, and then the hard mask is used as an etching mask to etch the lower layer.

[0155] Then, refer to Fig. 9, an interlayer insulating film 163 is stacked (e.g., formed) on the buffer layer 161 on which the gate conductive layer 130 is formed, and a first contact hole CNT1 exposing a portion of the lower metal layer 120 and a second contact hole CNT2 exposing a portion of the semiconductor layer 150 (e.g., the source region and the drain region) are formed. The contact holes CNT1 and CNT2 may be formed by a mask process. The first contact hole CNT1 and the second contact hole CNT2 may be sequentially formed by different masks. For example, an insulating layer for the interlayer insulating film 163 is completely deposited on the buffer layer 161 on which the gate conductive layer 130 is formed. Then, a first photoresist pattern exposing a portion of the lower metal layer 120 is formed on the insulating layer for the interlayer insulating film 163, and the insulating layer for the interlayer insulating film 163 and the buffer layer 161 are etched using the first photoresist pattern as an etching mask, thereby forming a first contact hole CNT1 exposing a portion of the lower metal layer 120. After removing the first photoresist pattern, a second photoresist pattern for exposing a portion of the semiconductor layer 150 is formed on the insulating layer for the interlayer insulating film 163, and the insulating layer for the interlayer insulating film 163 is etched using the second photoresist pattern as an etching mask, thereby forming a second contact hole CNT2.

[0156] The first contact hole CNT1 and the second contact hole CNT2 may be formed through the same mask, but in this case, the semiconductor layer 150 may be exposed to an etchant while the buffer layer 161 is etched to form the first contact hole CNT1 .

[0157] As described above, when the first contact hole CNT1 is first formed and then the second contact hole CNT2 is formed using separate masks, damage to the surface of the semiconductor layer 150 exposed by the second contact hole CNT2 may be prevented or reduced.

[0158] Then, refer to Fig.10, a patterned data conductive layer 140 is formed on the interlayer insulating film 163. The patterned data conductive layer 140 may be formed by a mask process. For example, a material layer for a data conductive metal layer 141, a material layer for a first data cover layer 142, and a material layer for a second data cover layer 143 are sequentially deposited on the interlayer insulating film 163. In some embodiments, the material layer for the data conductive metal layer 141 may include a material layer for a data base layer 141b and a material layer for a data main metal layer 141a, which may be sequentially deposited on the interlayer insulating film 163. In an exemplary embodiment, when the data conductive layer 140 is formed to have a four-layer structure of Ti / Cu / Ti / Cu, a structure in which a material layer containing copper (Cu) (e.g., containing Cu) for the data main metal layer 141a and the second data cover layer 143 is respectively deposited on a material layer containing titanium (Ti) (e.g., containing Ti) for the data base layer 141b and the first data cover layer 142 may be formed by physical vapor deposition or sputtering. For example, in the deposition process, a material layer for the data conductive metal layer 141, a material layer for the first data cover layer 142, and / or a material layer for the second data cover layer 143 are deposited inside the first contact hole CNT1 and the second contact hole CNT2, and thus, may be connected (e.g., electrically connected) to the lower metal layer 120 and the semiconductor layer 150, respectively.

[0159] Subsequently, a photoresist layer is applied on (e.g., formed on) the material layer for the second data cover layer 143; a photoresist pattern is formed by exposure and development; and the material layer for the second data cover layer 143, the material layer for the first data cover layer 142, and the material layer for the data conductive metal layer 141 are etched using the photoresist pattern as an etching mask. Then, the photoresist pattern is removed by a stripping or ashing process to complete the Fig.10 The patterned data conductive layer 140 shown in FIG. Fig.10 As shown in , through this process, in the data conductive layer 140 in the transistor region TRR, the data conductive layer 140 in the capacitor region CPR, and the data conductive layer 140 in the pad area PDA, the second data cover layer 143 can be located on the entire upper surface of the first data cover layer 142, and the sidewalls of the second data cover layer 143 and the sidewalls of the first data cover layer 142 can be parallel (e.g., substantially parallel).

[0160] As described above, in an exemplary embodiment, when the material layer for the second data clad layer 143 includes a material having a selectivity similar to copper (Cu) included in the material layer for the data main metal layer 141a (e.g., copper (Cu)) for the same etchant, even when the material layer for the data main metal layer 141a includes copper (Cu) and the material layer for the first data clad layer 142 includes titanium (Ti) having a different selectivity from copper (Cu) for the same etchant, the sidewalls of the data conductive layer 140 may be etched to be aligned with each other. Therefore, since the material layer for the second data clad layer 143 is formed to include a material having the same or similar selectivity to the material included in the material layer for the data main metal layer 141a for the same etchant, the formation of the tips of the data clad layers 142 and 143 that may occur due to a difference in selectivity of the materials included in each layer of the data conductive layer 140 for the same etchant may be prevented or reduced.

[0161] Then, refer to Fig.11 , a passivation layer 164 may be formed on the interlayer insulating film 163 on which the data conductive layer 140 is formed, and a photoresist pattern may be formed on the passivation layer 164 .

[0162] For example, a material layer for the passivation layer 164 is completely deposited on the interlayer insulating film 163 on which the data conductive layer 140 is formed. Subsequently, a photoresist layer is formed on the material layer for the passivation layer 164, and then a photoresist pattern is formed by exposure and development. The photoresist pattern may include a first opening OP1 and a second opening OP2, the first opening OP1 exposing an area overlapping with the source electrode SEL (e.g., the source electrode SEL of the driving transistor DTR) in the transistor region TRR, and the second opening OP2 exposing an area overlapping with the wiring pad WPD in the pad area PDA. In an embodiment, the width of the first opening OP1 may be less than or equal to the width of the corresponding source electrode SEL, and the width of the second opening OP2 may be less than or equal to the width of the data conductive layer (e.g., the wiring pad WPD) formed in the pad area PDA, but the present disclosure is not limited thereto.

[0163] Subsequently, the material layer for the passivation layer 164 is etched using the photoresist pattern as an etching mask. Through this process, the material layer for the passivation layer 164 exposed by the first opening OP1 is etched to form a contact hole exposing the source electrode SEL in the transistor region TRR. In addition, the material layer for the passivation layer 164 exposed by the second opening OP2 is removed (e.g., etched) together (e.g., together with the etching of the material layer for the passivation layer 164 exposed by the first opening OP1) to expose the second data cover layer 143 of the data conductive layer 140 in the pad area PDA. For example, the passivation layer 164 is not located on at least a portion of the data conductive layer 140 in the pad area PDA, and at least a portion of the data conductive layer 140 in the pad area PDA does not overlap with the passivation layer 164 in the thickness direction.

[0164] Then, refer to Fig.12 , a patterned via layer 165 is formed on the passivation layer 164. The patterned via layer 165 includes a third opening OP3 and a fourth opening OP4, the third opening OP3 exposing the first opening OP1 formed in the passivation layer 164, and the fourth opening OP4 exposing at least a portion of the data conductive layer 140 in the pad area PDA. The third opening OP3 may form a third contact hole CNT3 together with the first opening OP1 of the passivation layer 164 exposing the source electrode SEL. The fourth opening OP4 may form a pad opening PDOP. In an embodiment, the width of the third opening OP3 may be greater than the width of the first opening OP1 of the passivation layer 164, and the width of the fourth opening OP4 may be less than the width of the second opening OP2 of the passivation layer 164 in the pad area PDA, the second opening OP2 being formed by referring to Fig.11 Therefore, the path layer 165 in the pad area PDA may cover at least a portion of the upper surface of the data conductive layer 140 in the pad area PDA that is exposed by the passivation layer 164 in the pad area PDA. In addition, as described above, the path layer 165 constituting the inner wall of the fourth opening OP4 (or the pad opening PDOP) may cover the side surface of the end of the passivation layer 164 in the pad area PDA.

[0165] The path layer 165 may include, for example, an organic material including a photosensitive material. In this case, the patterned path layer 165 may be formed by applying (e.g., forming) an organic material layer for the path layer 165 and then forming the openings OP3 and OP4 by exposure and development. The path layer 165 may have a different height for each region, and the path layer 165 having a different height for each region may be formed using a halftone mask or a slit mask.

[0166] Meanwhile, when the path layer 165 is applied (e.g., formed), the path layer 165 and the data conductive layer 140 (e.g., a portion of the data conductive layer 140) may be in contact (e.g., in physical contact or direct contact) with each other. In this case, since the first data cover layer 142 and / or the second data cover layer 143 are formed as an upper layer of the data conductive layer 140, direct contact between the path layer 165 and the data conductive metal layer 141 may be prevented or reduced. Therefore, corrosion failure due to direct contact between the path layer 165 and the data conductive metal layer 141 may be prevented or reduced.

[0167] Then, refer to Fig.13 and Fig.14 , a patterned pixel electrode PXE is formed on the via layer 165. The patterned pixel electrode PXE may be formed through a mask process.

[0168] Reference Fig.13 , for example, the material layer PXM for the pixel electrode PXE is completely deposited on the path layer 165. In the deposition process, the material layer PXM for the pixel electrode PXE may be deposited inside the third contact hole CNT3 to be connected to the source electrode SEL, and may be deposited inside the pad opening PDOP to be located on the data conductive layer 140 in the pad area PDA, and the data conductive layer 140 in the pad area PDA is exposed by the pad opening PDOP. For example, the material layer PXM for the pixel electrode PXE may be deposited with the second area 140A of the data conductive layer 140 (see Figure 5A ), the second region 140A constitutes the source electrode SEL. Similarly, the material layer PXM for the pixel electrode PXE may contact (e.g., physically contact or directly contact) at least a portion of the upper surface of the second data cover layer 143 of the data conductive layer 140 in the pad area PDA.

[0169] Subsequently, a photoresist layer is applied (e.g., formed) on the material layer PXM for the pixel electrode PXE, and a photoresist pattern PR is formed, the photoresist pattern PR having a pattern shape of the pixel electrode PXE to be left by exposure and development. Subsequently, the material layer PXM for the pixel electrode PXE is etched using the photoresist pattern PR as an etching mask. The etching of the material layer PXM for the pixel electrode PXE can be performed by wet etching, but the present disclosure is not limited thereto.

[0170] In this process, the material layer PXM for the pixel electrode PXE on which the photoresist pattern PR is positioned may be patterned by wet etching to form the pixel electrode PXE. In addition, the material layer PXM for the pixel electrode PXE on the data conductive layer 140 located in the pad area PDA where the photoresist pattern PR is not disposed is etched, so that the data conductive layer 140 of the pad area PDA is in contact with (e.g., physically in contact with or directly in contact with) the etchant used to etch the material layer PXM for the pixel electrode PXE, and thus, the data conductive layer 140 may be damaged. Therefore, due to Fig.14 At least a portion of the second data cover layer 143 of the data conductive layer 140 located in the pad area PDA exposed by the pad opening PDOP may be in contact (e.g., physically or directly in contact) with an etchant used to etch the material layer PXM for the pixel electrode PXE, and thus may be damaged and removed. Therefore, in this process, the data conductive layer 140 may be formed, for example, Figure 5A The third region 140C of the data conductive layer 140 in the pad area PDA of the photoresist layer 140 is formed. Thereafter, the photoresist pattern PR may be removed by a stripping and / or ashing process.

[0171] Then, refer to Fig.15 , a patterned pixel defining layer PDL is formed on the path layer 165 on which the pixel electrode PXE is formed. The pixel defining layer PDL may include, for example, an organic material, and the organic material includes a photosensitive material. In this case, after applying an organic material layer for the pixel defining layer PDL, the patterned pixel defining layer PDL may be formed by exposure and development.

[0172] The pixel defining layer PDL may be formed along the boundary of the pixel PX and may partially overlap the pixel electrode PXE. The pixel defining layer PDL may be formed to overlap the third contact hole CNT3. In some embodiments, when a passage layer 165 having a relatively low height is formed (e.g., a portion of the passage layer 165 having a relatively low height to form a recessed portion in the passage layer 165), the pixel defining layer PDL may fill the passage layer 165 having a relatively low height (e.g., fill the recessed portion of the passage layer 165, in which the height of the passage layer 165 is relatively low) to compensate for the step of the corresponding area.

[0173] In this embodiment, the second data cladding layer 143 formed together with the data conductive metal layer 141 through one mask process can prevent or reduce the occurrence of a tip in the first data cladding layer 142, and in a subsequent process, the first data cladding layer 142 exposed by the second data cladding layer 143 can be used as a contact electrode of the wiring pad WPD. Therefore, the formation of a tip in the data conductive layer 140 can be prevented or reduced, and therefore, the occurrence of cracks of a plurality of insulating layers on the data conductive layer 140 can be prevented or reduced. In addition, since an additional mask process for forming a contact electrode of a separate wiring pad WPD is not required, process efficiency can be improved.

[0174] Hereinafter, some embodiments will be described. In the following embodiments, the same configuration as the previously described configuration will be simplified or will not be repeated, and the differences will be mainly described.

[0175] Fig.16 is a cross-sectional view of a first display substrate of a display device according to an embodiment.

[0176] Reference Fig.16 , this embodiment and Figure 5A The difference between the embodiments lies in the stacking or cross-sectional structure of the insulating layers in the pad area PDA.

[0177] For example, in the present embodiment, the path layer 165_1 may include a step. The path layer 165_1 may include a stepped structure having different heights for each region. The path layer 165_1 may include a first region 165a_1 having a first height and a second region 165b_1 having a second height lower than the first height. The height of the path layer 165_1 may be measured from a reference plane such as a surface of the first substrate 110. For example, the height of the path layer 165_1 may refer to the distance between the upper surface of the first substrate 110 and the upper surface of the path layer 165_1. The path layer 165_1 may have a substantially flat surface (e.g., a substantially flat upper surface in each region), regardless of the shape or presence of the underlying pattern in each region. At the boundary of each region, the path layer 165_1 may have a stepped structure (e.g., height variation).

[0178] Portions of the first region 165a_1 and the second region 165b_1 of the passage layer 165_1 are located in the display area DPA. The first region 165a_1 of the passage layer 165_1 may overlap the pixel electrode PXE located thereover. At least a portion of the second region 165b_1 of the passage layer 165_1 may be located in the non-emission region NEM (see Figure 2), and may not overlap with the pixel electrode PXE. The second region 165b_1 of the path layer 165_1 may be along the periphery of the pixel electrode PXE (e.g., at its boundary), and may form a lattice-shaped pit in the display area DPA. The other portion of the second region 165b_1 of the path layer 165_1 is located in the pad area PDA of the non-display area NDA.

[0179] The path layer 165_1 may form a pad opening PDOP_1 that exposes the third area 140C_1 of the data conductive layer 140 in the pad area PDA and exposes the passivation layer 164. The passivation layer 164 and the path layer 165_1 constituting the inner wall of the pad opening PDOP_1 may be aligned with each other, but the present disclosure is not limited thereto. The inner wall of the pad opening PDOP_1 may overlap with the third area 140C_1 of the data conductive layer 140. However, the present disclosure is not limited thereto. The passivation layer 164 and the path layer 165_1 constituting the inner wall of the pad opening PDOP_1 may be aligned with the side wall (e.g., inner side wall) of the second data cover layer 143_1 in the third area 140C_1 of the data conductive layer 140. Therefore, the upper surface of the second data cover layer 143_1 in the third area 140C_1 of the data conductive layer 140 may be covered by the passivation layer 164.

[0180] Fig.17 and Fig.18 The manufacturing method according to the embodiment is shown in FIG. Fig.16 A cross-sectional view of a process step of a method for forming a portion of a first display substrate of a display device.

[0181] The process for forming a patterned lower metal layer 120, a buffer layer 161, a semiconductor layer 150, a patterned gate insulating film 162, a gate conductive layer 130, an interlayer insulating film 163 provided with a first contact hole CNT1 and a second contact hole CNT2, a patterned data conductive layer 140, a passivation layer 164, and a path layer 165 (to be formed as a path layer 165_1 having a step) on a first substrate 110, a process for completely applying a material layer for a pixel electrode PXE (for example, applying a material layer for a pixel electrode PXE on the entire path layer 165 and an exposed portion of the data conductive layer 140), and a process for subsequently forming a photoresist pattern PR on the material layer for the pixel electrode PXE, is similar to the process described with reference to FIG. Figures 6 to 13 The processes are the same as those described in the embodiments.

[0182] For example, the material layer for the pixel electrode PXE is etched using the photoresist pattern PR formed on the material layer for the pixel electrode PXE as an etching mask. Fig.17, after the process of etching the material layer for the pixel electrode PXE, the second data cover layer 143 of the data conductive layer 140 in the pad area PDA may be partially left without being etched and thus may be located on the first data cover layer 142 .

[0183] Then, refer to Fig.18 , in a state where the photoresist pattern PR on the pixel electrode PXE remains (e.g., during the process), the photoresist pattern PR is removed by an ashing process, and in this process, the second data cover layer 143 (e.g., a portion of the second data cover layer 143) of the data conductive layer 140 in the pad area PDA exposed by the fourth opening OP4 may be removed. For example, when the second data cover layer 143 includes copper (Cu), the copper (Cu) may be corroded by the ashing process, and as described above, since the second data cover layer 143 is relatively thin, oxides generated by the corrosion of the copper (Cu) may be removed by the ashing process. In this process, the photoresist pattern PR remaining on the pixel electrode PXE is removed, and at least a portion of the path layer 165_1 on which the photoresist pattern PR is not provided is etched to form the path layer 165_1 having a step. Furthermore, at least a portion of the via layer 165_1 covering the side surface of the passivation layer 164 in the pad area PDA is etched so that the side surfaces of the passivation layer 164 and the via layer 165_1 in the pad area PDA may be aligned in parallel (eg, substantially parallel).

[0184] Fig.19 According to the embodiment Figure 5A Another enlarged view of portion A in FIG.

[0185] Fig.19 FIG. 1 shows a third region 140C_19 of the data conductive layer 140_19 in the pad region PDA according to an embodiment. It should be understood that the pad region PDA and the pixel electrode PXE may refer to Figure 5A . Reference Fig.19 , this embodiment and Figure 5A The embodiment of FIG. 1 is different in that a side surface (eg, an inner sidewall) of the second data cover layer 143_19 in the third region 140C_19 of the data conductive layer 140_19 in the pad area PDA is not aligned with a side surface of the via layer 165 .

[0186] For example, a portion of the path layer 165 on the second data cover layer 143_19 in the third region 140C_19 of the data conductive layer 140_19 may cover the upper surface of the second data cover layer 143_19, and the other portion of the path layer 165 may protrude outward from the second data cover layer 143_19 (e.g., may protrude inward toward the center of the pad opening PDOP). Therefore, at least a portion of the lower surface of the path layer 165 that protrudes outward from the second data cover layer 143_19 may face the upper surface of the first data cover layer 142 in the region overlapping with the first data cover layer 142 (e.g., may face the upper surface of the first data cover layer 142 without the second data cover layer 143_19 therebetween).

[0187] In the present embodiment, in the etching process for forming the pixel electrode PXE, when the material layer for the pixel electrode PXE located in the pad area PDA is etched and exposed to the etchant used in etching the second data cover layer 143_19 of the data conductive layer 140_19 in the pad area PDA (for example, used in the same process for etching the second data cover layer 143_19) (for example, during the same process as this time), the pixel electrode PXE may be formed. For example, in some embodiments, during the process for forming the pixel electrode PXE, the material layer for the pixel electrode PXE may be etched both in the display area DPA and in the pad area PDA, and a portion of the data cover layer 143_19 of the data conductive layer 140_19 in the pad area PDA may be etched. In an exemplary embodiment, when the second data overlay layer 143_19 contains (e.g., includes) copper (Cu) having a relatively high selectivity, when the material layer for the pixel electrode PXE and the second data overlay layer 143_19 are etched (e.g., during the same process as this time), the second data overlay layer 143_19 may be etched from the side surface of the path layer 165 on the data conductive layer 140_19 in the pad area PDA (e.g., toward the outer sidewall of the second data overlay layer 143_19) to the inner side (e.g., to form the inner sidewall of the second data overlay layer 143_19). Although Fig.1914 shows that at least a portion of the lower surface of the path layer 165 may be exposed by the second data cover layer 143_19 on the first data cover layer 142 (for example, at least a portion of the lower surface of the path layer 165 may face the upper surface of the first data cover layer 142 without the second data cover layer 143_19 therebetween), but the present disclosure is not limited thereto. In this case, because the material included in the second data cover layer 143_19 has a relatively high selectivity, the second data cover layer 143_19 may expose the entire lower surface of the path layer 165 overlapping the data conductive layer 140_19 (for example, the entire lower surface of the path layer 165 overlapping the data conductive layer 140_19 without the passivation layer 164 therebetween), and may extend inward (for example, toward the outside of the second data cover layer 143_19) to expose at least a portion of the lower surface of the passivation layer 164.

[0188] Fig. 20 According to the embodiment Figure 5A Another enlarged view of part A in FIG.

[0189] Fig. 20 FIG. 1 shows a third region 140C_20 of the data conductive layer 140_20 in the pad region PDA according to an embodiment. It should be understood that the pad region PDA and the pixel electrode PXE may refer to Figure 5A . Reference Fig. 20 , this embodiment and Figure 5A The embodiment of the present invention is different in that the first data cover layer 142_20 in the third area 140C_20 of the data conductive layer 140_20 located in the pad area PDA may include surface steps having different thicknesses.

[0190] For example, in the present embodiment, the first data cover layer 142_20 in the third region 140C_20 of the data conductive layer 140_20 may include a first section of the first data cover layer 142_20 located in a region overlapping the passivation layer 164 and the path layer 165 and a second section of the first data cover layer 142_20 having a thickness smaller than that of the first section (e.g., a height lower than that of the first section). The second section of the first data cover layer 142_20 in the third region 140C_20 of the data conductive layer 140_20 may be located in a region exposed by the pad opening PDOP. Therefore, the side surface of the path layer 165, the side surface of the second data cover layer 143, and the side surface of the first data cover layer 142_20 (e.g., the inner sidewall of the first segment of the first data cover layer 142_20 at the boundary between the first segment and the second segment of the first data cover layer 142_20) aligned in parallel (e.g., substantially in parallel) with the second data cover layer 143 (e.g., the inner sidewall of the second data cover layer 143) may be aligned with each other to form the pad opening PDOP in the pad area PDA.

[0191] In the present embodiment, in the etching process for forming the pixel electrode PXE, when the material layer for the pixel electrode PXE located in the pad area PDA and the second data cover layer 143 located on the entire surface of the first data cover layer 142_20 are etched and exposed to the etchant used when etching the second data cover layer 143 (for example, used in the same process for etching the second data cover layer 143) (for example, during the same process as this time), the pixel electrode PXE can be formed. In an exemplary embodiment, when the material layer for the pixel electrode PXE and the second data cover layer 143 are etched, at least a portion of the first data cover layer 142_20 may also be etched. However, when the first data cover layer 142_20 is formed of a material containing (for example, including) titanium (Ti) having a relatively low selectivity and the first data cover layer 142_20 has a sufficient thickness (for example, as Fig. 20 ), only a portion of the first data cover layer 142_20 may be etched. Even in this case, the first data cover layer 142_20 (e.g., a portion of the first data cover layer 142_20, such as the second segment of the first data cover layer 142_20) located on the data main metal layer 141a may remain to cover and protect the upper surface of the data main metal layer 141a.

[0192] Fig.21 According to the embodiment Figure 5A Another enlarged view of part A in FIG.

[0193] Fig.21 The third area 140C_21 of the data conductive layer 140_21 in the pad area PDA is shown. It should be understood that the pad area PDA and the pixel electrode PXE can refer to Figure 5A . Reference Fig.21 , this embodiment and Figure 5A The difference between the embodiment of the present invention and the embodiment of the present invention is that the second data cover layer 143_21 in the third area 140C_21 of the data conductive layer 140_21 located in the pad area PDA exposes at least a portion of the upper surface of the first data cover layer 142 located below the second data cover layer 143_21 (for example, at least a portion of the upper surface of the first data cover layer 142 is exposed to the lower surface of the passivation layer 164_21). For example, the outer side wall of the second data cover layer 143_21 may retreat away from the outer side wall of the first data cover layer 142 (for example, toward the center of the pad opening PDOP) and is not aligned with the outer side wall of the first data cover layer 142, so that a portion of the upper surface of the first data cover layer 142 at the outer side of the first data cover layer 142 (for example, close to the outer side of the first data cover layer 142) is exposed to the lower surface of the passivation layer 164_21 (for example, directly contacting or physically contacting the lower surface of the passivation layer 164_21).

[0194] For example, the second data overlay layer 143_21 in the third region 140C_21 of the data conductive layer 140_21 may be located on the first data overlay layer 142. The lower surface of the second data overlay layer 143_21 may be in direct contact with the upper surface of the first data overlay layer 142. The second data overlay layer 143_21 may not be located in at least a portion of the region where the first data overlay layer 142 and the passivation layer 164_21 overlap each other. Therefore, the upper surface of the first data overlay layer 142 exposed by the second data overlay layer 143_21 may be in direct contact with the passivation layer 164_21.

[0195] In the present embodiment, in the process of forming the pattern of the data conductive layer, when the sequentially stacked material layers of the data conductive layer have different selectivities, the pattern of the data conductive layer can be formed. For example, when the material included in the material layer for the second data cladding layer has a higher selectivity than the material included in the material layer for the data main metal layer, the etching rate of the material layer for the second data cladding layer can be faster than the etching rate of the material layer for the data main metal layer. In this case, because the material layer for the second data cladding layer 143_21 is higher than the material layer for the data main metal layer 141a (e.g., Fig.21 ) is etched faster, so the outer surface (e.g., outer sidewall) of the second data cover layer 143_21 can retreat inward from the side surface (e.g., outer sidewall) of the data main metal layer 141a. For example, the outer sidewall of the second data cover layer 143_21 can be closer to the center of the pad opening PDOP than the outer sidewall of the data main metal layer 141a, so that the outer sidewall of the second data cover layer 143_21 is not aligned with the outer sidewall of the data main metal layer 141a. Even in this case, because the material included in the second data cover layer 143_21 has a higher selectivity than the material included in the data main metal layer 141a in the etching process for forming the pattern of the data conductive layer 140_21, the occurrence of a tip in the first data cover layer 142 located below the second data cover layer 143_21 can be prevented or reduced.

[0196] Fig. 22 According to the embodiment Figure 5A Another enlarged view of part A in FIG.

[0197] Fig. 22 FIG. 1 shows a third region 140C_22 of the data conductive layer 140_22 in the pad region PDA according to an embodiment. It should be understood that the pad region PDA and the pixel electrode PXE may refer to Figure 5A . Reference Fig. 22 , this embodiment and Figure 5AThe difference between the embodiment of FIG. 1 and FIG. 2 is that the third area 140C_22 of the data conductive layer 140_22 in the pad area PDA does not include the second data cover layer.

[0198] For example, the second data cover layer may not be located on the first data cover layer 142 in the third region 140C_22 of the data conductive layer 140_22. Fig.21 , the passivation layer 164_22 may be located (e.g., directly located) on at least a portion of the upper surface of the first data cover layer 142. Therefore, the upper surface (e.g., a portion of the upper surface) of the first data cover layer 142 located in an area of ​​the first data cover layer 142 where there is no passivation layer 164_22 thereon may be exposed. A space may be formed between the path layer 165_22 (e.g., a portion of the path layer 165_22 where the passivation layer 164_22 is not located between the path layer 165_22 and the first data cover layer 142) and the first data cover layer 142 near the sidewall of the pad opening PDOP in the thickness direction.

[0199] In the present embodiment, in the process of forming the pattern of the data conductive layer, when the sequentially stacked material layers of the data conductive layer have different selectivities, the pattern of the data conductive layer can be formed. For example, when the material included in the material layer for the second data cladding layer has a higher selectivity to the etchant than the material included in the material layer for the data main metal layer 141a, the etching rate of the material layer for the second data cladding layer can be faster than the etching rate of the material layer for the data main metal layer 141a. In this case, because the material layer for the second data cladding layer is etched faster than the material layer for the data main metal layer 141a, the side surface (e.g., outer side wall) of the material layer for the second data cladding layer formed during the etching process of the data conductive layer can be retreated inward from the side surface (e.g., outer side wall) of the data main metal layer 141a. For example, the outer side wall of the material layer for the second data cladding layer can be closer to the center of the pad opening PDOP than the outer side wall of the data main metal layer 141a, so that the outer side wall of the material layer for the second data cladding layer is not aligned with the outer side wall of the data main metal layer 141a. Then, the material layer for the second data cover layer that has been completely arranged is overetched through a subsequent process so that a Fig. 22 Even in this case, as described above, since the material included in the material layer for the second data cladding layer has a higher selectivity than the material included in the data main metal layer 141a in the etching process for forming the pattern of the data conductive layer, the occurrence of a tip in the first data cladding layer 142 located under the material layer for the second data cladding layer can be prevented or reduced.

[0200] After forming the patterned data conductive layer, the passivation layer 164_22, the via layer 165_22 and the pixel electrode PXE may be sequentially formed. In the etching process for forming the patterned pixel electrode PXE, the material layer for the second data cover layer exposed by the pad opening PDOP in the pad area PDA may be completely removed by an etchant.

[0201] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the disclosed embodiments without departing substantially from the principles of the present disclosure. Therefore, the disclosed embodiments of the present disclosure are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A display device, wherein: The display device comprises: A substrate, comprising a display area and a pad area; A first conductive layer, located on the substrate; a first insulating film, located on the first conductive layer; and a second conductive layer, located on the first insulating film, The first conductive layer includes a base layer, a main metal layer located on the base layer and including copper, a first conductive coating layer located on the main metal layer, and a second conductive coating layer located on the first conductive coating layer. The first insulating film has a first contact hole and a pad opening, the first contact hole is located in the display area and passes through the first insulating film in a thickness direction to expose the first conductive layer, and the pad opening exposes the first conductive layer in the pad area. The first conductive layer is arranged such that: In a first region covered by the first insulating film, the second conductive coating is completely located on the first conductive coating; In a second region overlapping the first contact hole, the second conductive cladding layer is completely located on the first conductive cladding layer; and In a third region exposed by the pad opening, at least a portion of the first conductive cladding layer is not covered by the second conductive cladding layer.

2. The display device according to claim 1, wherein: The second conductive cladding layer includes Cu or ZIO.

3. The display device according to claim 2, wherein: The first conductive coating includes a material different from that of the main metal layer.

4. The display device according to claim 3, wherein: The first conductive cladding layer includes Ti.

5. The display device according to claim 2, wherein: The base layer and the first conductive coating layer include the same material.

6. The display device according to claim 5, wherein: Side surfaces of the base layer of the first conductive layer, the main metal layer, the first conductive cladding layer, and the second conductive cladding layer are aligned parallel to each other.

7. The display device according to claim 1, wherein: The second conductive coating includes the same material as that of the main metal layer.

8. The display device according to claim 7, wherein: The first conductive coating layer and the base layer include the same material.

9. The display device according to claim 1, wherein: The first conductive layer is connected to the second conductive layer through the first contact hole in the second region.

10. The display device according to claim 1, wherein: The first conductive cladding layer of the first conductive layer is exposed by the pad opening in the third region.

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