Optical Engine

Abstract

A system including an optical engine. In some embodiments, the system includes an integrated circuit in a first level package, and the system includes an optical engine in the first level package, and the optical engine includes an electro-optical chip.

Description

[0001] Cross-reference to related application(s)

[0002] This application claims priority to and the benefit of U.S. Provisional Application No. 62 / 656,748, filed April 12, 2018, entitled “OPTICAL ENGINE,” and is a continuation-in-part of U.S. Patent Application No. 15 / 982,928, filed May 17, 2018, entitled “DRIVER FOR OPTICAL MODULATOR,” which claims the benefit of U.S. Provisional Application No. 62 / 510,211, filed May 23, 2017. The entire contents of all applications identified in this paragraph are incorporated herein by reference. Technical Field

[0003] One or more aspects of embodiments according to the present disclosure relate to optical communications, and more particularly, to optical engines. Background Art

[0004] Higher density and reach in communications systems require optical interconnects. Optical transceivers placed far from host or switch application-specific integrated circuits (ASICs) can be physically large and consume a lot of power, in part because they are designed to communicate electrically with the host or switch ASIC over a relatively large distance. This can limit system density in 12, 25, and 50 Tb / s systems.

[0005] Therefore, there is a need for an improved optical engine. Summary of the invention

[0006] According to some embodiments, a system is provided, comprising: a first integrated circuit in a first level package; and an optical engine in the first level package, the optical engine comprising a first electro-optical chip.

[0007] In some embodiments, the optical engine further includes: a second integrated circuit including a first analog circuit for interfacing with the first electro-optical chip.

[0008] In some embodiments: the first electro-optical chip includes a photodetector; the optical engine further includes a second electro-optical chip, the second electro-optical chip includes an optical modulator; and the second integrated circuit further includes a second analog circuit for interfacing with the optical modulator.

[0009] In some embodiments, the first analog circuit is a linear modulator driver and the second analog circuit is a transimpedance amplifier.

[0010] In some embodiments, the second integrated circuit further includes a retiming circuit.

[0011] In some embodiments, the second integrated circuit further includes physical coding sublayer circuitry.

[0012] In some embodiments, the optical engine is connected to the substrate of the first level packaging through a reworkable interface.

[0013] In some embodiments, the reworkable interface is a socket interface.

[0014] In some embodiments, the second integrated circuit includes an equalization circuit.

[0015] In some embodiments, the first electro-optical chip includes an optical PAM-4 modulator configured to be driven by a two-bit signal.

[0016] In some embodiments, the system includes: a plurality of optical engines including the optical engine; and a management circuit configured to manage the plurality of optical engines.

[0017] In some embodiments, the optical engine is configured to exchange data with the first integrated circuit at a first symbol rate, and the electrical connection between the optical engines exhibits a loss of less than 10 dB at a Nyquist frequency corresponding to the first symbol rate.

[0018] In some embodiments, the system includes a housing having a front panel, the first level package being within the housing, the system further including a front panel package including a laser connected to the first level package via an optical fiber.

[0019] In some embodiments, the front panel package has a QSFP-DD or OSFP-DD form factor, and an optical fiber connects a first interface of the front panel package to a first level package, the first interface being external to the front panel.

[0020] In some embodiments, the first integrated circuit is a packet-switched digital integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] These and other features and advantages of the present disclosure will be appreciated and understood with reference to the specification, claims and drawings, in which:

[0022] Figure 1 is a perspective view of a first level package according to an embodiment of the present disclosure; and

[0023] Figure 2 is a block diagram of an optical engine according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of exemplary embodiments of the optical engine provided according to the present disclosure, and is not intended to represent the only form in which the present disclosure can be constructed or utilized. The description sets forth the features of the present disclosure in conjunction with the illustrated embodiments. However, it should be understood that the same or equivalent functions and structures can be implemented by different embodiments, and the different implementations are also intended to be covered within the scope of the present disclosure. As indicated elsewhere herein, similar element numbers are intended to indicate similar elements or features.

[0025] Reference Figure 1 , including a switch ASIC 105 (e.g., a CMOS packet-switched digital integrated circuit) in or on the first-level package 115 and a first-level package 115 of multiple optical engines 110, as described in further detail below, can overcome some of the disadvantages of systems in which the transceiver is farther away from the host or switch ASIC 105. The electrical connections between each optical engine 110 and the switch ASIC may be short enough to significantly simplify the circuitry at both ends of those connections. In some embodiments, each connection is shorter than 10 mm, such as shorter than 5 mm. In some embodiments, the interface between the optical engine 110 and the switch ASIC 105 employs (electrical) PAM-4 signaling. In some embodiments, each optical engine is configured to exchange data with the switch ASIC 105 at a first symbol rate (e.g., 25 Gigasymbols per second (GS / s), 50 GS / s, or 100 GS / s (corresponding to 50 Gb / s, 100 Gb / s, and 200 Gb / s of PAM-4 (PAM-4 is four-level pulse amplitude modulation), respectively), and the electrical connection is short enough (e.g., 40 mm, 20 mm, or 15 mm, respectively) to exhibit less than 4 dB loss (in a connection without retiming, or less than 8 dB or 10 dB loss in a connection with retiming) at the corresponding Nyquist frequency (i.e., twice the symbol rate).

[0026] The optical engine 110 can be connected to the substrate of the first level package using a reworkable (or pluggable) interface, such as a socket. Such a reusable interface can make it possible to easily replace the optical engine 110 with a new one if one optical engine fails, or to replace the optical engine with a different kind of optical engine (e.g., one with different optical characteristics or different electrical functions). The high-speed routing from the optical engine 110 to the switch ASIC 105 can be limited to the top layer of a standard 5-2-5 / 4-2-4 organic BGA substrate. This (i) allows excellent high-speed performance by avoiding lossy transitions through the core of the substrate, and (ii) can enable large form factor substrates (to support, for example, 16 optical engines) and larger cores.

[0027] Figure 2 is a block diagram of an optical engine in some embodiments. The optical engine may include a physical layer (Phy) circuit 205 and an optical interface 210. The optical interface 210 may include an array of modulators 215 (each of the modulators may be an electro-absorption modulator (EAM) or another type of modulator, such as a Mach-Zehnder modulator, a ring modulator, or a polymer modulator), coupled to a first optical fiber array 220 for receiving unmodulated laser light, and coupled to a second optical fiber array 225 for transmitting modulated light. The optical interface may further include a photodetector (PD) array 230 coupled to a corresponding third optical fiber array 227 for receiving modulated light.

[0028] Phy circuit 205 includes a transmitting portion (or "Phy transmitter") 235 and a receiving portion (or "Phy receiver") 240. The transmitting portion 235 ( Figure 2 200 ) includes an analog front end (AFE) 242 for receiving signals from the switch ASIC 105. The signals may be carried, for example, over a plurality (e.g., 16) of serial connections, each operating at 53.125 Gb / s (or "53.125G"), and each implementing a low-complexity interface (such as NRZ) that is superior to very simple short-reach industry-standardized interfaces (such as ultra-short reach (USR) or extra-short reach (XSR)). This use of a low-complexity interface between the switch ASIC 105 and the Phy circuit 205 (both in the transmit direction and in the receive direction (discussed below)) may significantly simplify the circuitry required in the switch ASIC 105, thereby reducing power consumption in the switch ASIC 105, or making die area in the switch ASIC 105 available for other functions, or both. Clock recovery of the signals received from the switch ASIC 105 may be performed by a clock recovery circuit 244 on the output of the analog front end of the Phy receiver 240.

[0029] The deserializer (De-SER) (or "deserialization circuit") 246 converts the received signal into a lower speed signal of a larger bus width. Based on the output of the deserializer 246, a circuit 248 (or one or more circuits, each circuit performing a combination of one or more of these functions) including a physical coding sublayer (PCS) circuit, a forward error correction (FEC) encoding circuit, and a lane alignment circuit generates a parallel output data stream, which is converted by the 50G signal conditioner 250 into a smaller number of higher data rate data streams. The voltage mode logic (VML) driver circuit 252 receives the output of the 50G signal conditioner and drives an octal driver circuit 254 (e.g., a circuit including eight similar or identical driver circuits), which is connected to the transmit portion 235 of the Phy circuit 205, and which generates a signal suitable for generating PAM-4 modulation in each modulator. The octal driver circuit may include, for example, the circuit disclosed in U.S. Patent Application Publication No. 2018 / 0341125 (which is incorporated herein by reference). In some embodiments, the transmitted optical signal includes 2×4 (i.e., eight) data streams (e.g., two optical fibers, each carrying four wavelengths, or four optical fibers, each carrying two wavelengths), each data stream having a data rate of 106.25G (i.e., 106.25 Gb / s, or 53.125 symbols per second, each symbol being a PAM-4 symbol carrying two bits).

[0030] The receiving portion 240 of the Phy circuit 205 ( Figure 2The optical signals of the optical fiber array 227 are connected to an octal linear transimpedance amplifier (TIA) 256 (e.g., a circuit including eight similar or identical transimpedance amplifier circuits), which receives signals from corresponding photodetectors 230, each of which is coupled to an optical fiber of the third optical fiber array 227. In some embodiments, the received optical signal includes 2×4 data streams, each of which has a data rate of 106.25G, like the transmitted optical signal. The output of the TIA 256 is received by an analog front end 260 including a continuous time linear equalization (CTLE) circuit, which is fed to an analog signal processing (ASP) / digital signal processing (DSP) circuit (or "analog and digital signal processing circuit") 262 to provide feed forward equalization (FFE) or decision feedback equalization (DFE), or both. The signal is clock recovered by a clock recovery circuit 264 and deserialized by a deserializer (De-SER) 266. Circuitry 268 (or one or more circuits, each performing a combination of one or more of these functions) including physical coding sublayer (PCS) circuitry, forward error correction (FEC) decoding circuitry, and lane alignment circuitry produces parallel data streams that are converted by 50G signal conditioners 270 into a smaller number of higher data rate data streams that are fed to voltage mode logic (VML) driver circuitry 272, which drives corresponding inputs of the switch ASIC 105. On the receive side (as on the transmit side), the use of a low complexity interface between the switch ASIC 105 and the Phy circuit 205 can significantly simplify the circuitry required in the switch ASIC 105 and in the Phy circuit 205.

[0031] Phy circuit 205 may further include control circuit 274, which may include a set of state machines or microcontrollers (uC) and Energy Efficient Ethernet (EEE) circuit 276, which may turn certain components of integrated circuit 280 on or off depending on the load to save power. Phy circuit 205, octal driver circuit 254, and octal linear transimpedance amplifier (TIA) 256 may all be part of an integrated circuit (e.g., "second integrated circuit") 280, which may be a single complementary metal oxide semiconductor (CMOS) integrated circuit.

[0032] As mentioned above, the electrical connection between the Phy circuit and the switch ASIC can be relatively short, for example, less than 25 mm in length (or less than 1 mm in length). Some embodiments not only save the switch ASIC 105 from having to include relatively complex circuitry that would be required if the switch ASIC 105 were connected to a state-of-the-art optical front panel transceiver via a relatively long electrical high-speed serial data link, but also make it possible to completely eliminate such circuitry from the system because, in some embodiments, the long electrical high-speed serial data link is not used.

[0033] In some embodiments, an external reference clock signal (e.g., at 100 MHz) is fed into the Phy circuit 205, where it is multiplied (by the clock frequency multiplication circuit 278) and used to retime the signals at the output of the transmit portion of the Phy circuit (to the octal driver circuit) and at the output of the receive portion of the Phy circuit (to the switch ASIC). The same reference clock signal may also be fed to the switch ASIC and used to clock in serial data from the Phy circuit. This arrangement may obviate the need for the switch ASIC to include a voltage controlled oscillator (VCO) (e.g., an inductor-capacitor VCO (LC VCO)) array for clocking in serial data from the Phy circuit.

[0034] In some embodiments, portions of the second integrated circuit 280 may not be present, or the second integrated circuit 280 may not be present at all. For example, the second integrated circuit 280, if present, may perform only analog functions on the high-speed signal path (e.g., amplifying the signal from the photodetector 230 and amplifying the drive signal for the modulator 215), or it may perform only analog functions and retiming. In some such embodiments, the second integrated circuit 280 includes only analog interface circuits on the high-speed signal path, for example, it includes analog interface circuits for interfacing with the modulator 215 (e.g., a linear driver) and analog interface circuits for interfacing with the photodetector 230 (e.g., a linear transimpedance amplifier), and simple digital configuration circuits, for example, for setting the amplitude of the modulator driver and for setting the loss of the signal detector threshold in the transimpedance amplifier. In some embodiments, the second integrated circuit 280 also includes only retiming circuits, which include, for example, the clock recovery circuit 244 of the transmit portion 235 and the clock recovery circuit 264 of the receive portion 240. In some embodiments, the second integrated circuit 280 may also include physical coding sublayer circuits (including Figure 2), and as a result, the second integrated circuit 280 may be capable of performing channel alignment, performing forward error correction, and assigning channel numbers. In various embodiments (e.g., with or without retiming circuits, and with or without physical coding sublayer circuits), the second integrated circuit 280 may include one or more equalization circuits (such as continuous time linear equalization (CTLE) circuits of the analog front end 260).

[0035] In some embodiments, each of the modulators 215 is a simple modulator, and each of the driver circuits 254 for the modulators can apply four different voltages to (or drive four different currents through) the corresponding modulator 215 to produce PAM-4 modulation. In other embodiments, each of the modulators 215 is an optical PAM-4 modulator (e.g., a composite modulator that can include a cascade of independently controllable modulators (e.g., a cascade of two, three, or four electro-absorption modulators)) configured to be driven by a two-bit signal (e.g., a two-bit NRZ control signal) to produce four different attenuation levels corresponding to PAM-4 modulation.

[0036] In some embodiments, a management circuit external to the second integrated circuit 280 can manage multiple optical engines 110 (e.g., it can manage multiple second integrated circuits 280, each second integrated circuit in a corresponding one of the multiple optical engines 110). Such a management circuit can be a third integrated circuit (internal or external to the first level package), or it can be part of the first integrated circuit (switch ASIC 105). The management circuit can be connected to the control circuit 274 in the optical engine 110, and it can manage the optical engine by, for example, configuring the chip, reporting loss of signal, reporting configuration, detecting faults, and performing status reporting. Using a single circuit to manage multiple optical engines 110 can make it unnecessary for the second integrated circuit 280 to provide this function.

[0037] In some embodiments, the first level package (e.g., on a printed circuit board) is in a housing with a front panel (which may be the front panel of a rack mount card in the housing), and the laser used to supply unmodulated light to the modulator 215 is mounted in an industry standard form factor (e.g., QSFP-DD or OSFP-DD form factor) front panel package in the front panel. Such an industry standard form factor package may have a fiber optic interface on the outside of the front panel; a fiber optic loopback may be used to direct light from the laser in the front panel package back into the housing and back to the first level package, where it can supply light to the optical engine 110 (i.e., to the modulator 215 in the optical engine 110).

[0038] As used herein, an electro-optical chip is a semiconductor chip (such as one of the photodetectors 230) configured to convert optically transmitted data into electrically transmitted data, or a semiconductor chip (such as one of the modulators 215) configured to convert electrically transmitted data into optically transmitted data. The optically transmitted data may be, for example, light that is amplitude modulated (e.g., using PAM-4 modulation) and carries the resulting data. Similarly, the electrically transmitted data may be a time-varying voltage or current that carries the data. As used herein, a first-level package is a package having a substrate and containing one or more integrated circuit dies connected to the substrate. The integrated circuit die may be directly connected to the substrate (e.g., wire bonded to the substrate, or flip-chip mounted on the substrate), or it or they may be indirectly mounted on the substrate (e.g., it or they may be wire bonded to a redistribution layer, which in turn is directly mounted on the substrate). The first-level package may be suitable, for example, for direct mounting on a printed circuit board (e.g., the substrate may have a ball grid array on its lower surface, allowing it to be mounted on the printed circuit board using a reflow process) or indirectly mounted on a printed circuit board (e.g., it may be contained in a second-level package that may be mounted on a printed circuit board). As used herein, the word “or” is inclusive; thus, for example, “A or B” means any one of (i) A, (ii) B, and (iii) A and B.

[0039] Although exemplary embodiments of optical engines have been specifically described and illustrated herein, many modifications and variations will be apparent to those skilled in the art. Therefore, it should be understood that an optical engine constructed according to the principles of the present disclosure may be embodied differently than as specifically described herein. The present invention is further defined in the appended claims and their equivalents.

Claims

1. A system comprising: a first integrated circuit in a first level package; and The optical engine in the first level packaging, The optical engine comprises a first electro-optical chip, The optical engine is configured to exchange data with the first integrated circuit at a first symbol rate, and an electrical connection between the optical engine and the first integrated circuit exhibits a loss of less than 10 dB at a Nyquist frequency corresponding to the first symbol rate.

2. The system according to claim 1, wherein: The optical engine further comprises: A second integrated circuit includes a first analog circuit for interfacing with the first electro-optical chip.

3. The system of claim 2, wherein: The first electro-optical chip includes a photodetector; The optical engine further includes a second electro-optical chip, the second electro-optical chip including an optical modulator; and The second integrated circuit also includes a second analog circuit for interfacing with the optical modulator.

4. The system according to claim 3, wherein: The first analog circuit is a linear modulator driver and the second analog circuit is a transimpedance amplifier.

5. The system according to any one of claims 2 to 4, wherein: The second integrated circuit also includes a retiming circuit.

6. The system according to any one of claims 2 to 4, wherein: The second integrated circuit also includes a physical coding sublayer circuit.

7. The system according to any one of claims 1 to 4, wherein: The optical engine is connected to the substrate of the first level package through a reworkable interface.

8. The system according to claim 7, wherein: The reworkable interface is a socket interface.

9. The system according to any one of claims 2 to 4, wherein: The second integrated circuit includes an equalization circuit.

10. The system according to claim 2, wherein: The first electro-optical chip includes an optical PAM-4 modulator configured to be driven by a two-bit signal.

11. The system according to any one of claims 1 to 4, 8 and 10, comprising: a plurality of optical engines including said optical engine; and A management circuit is configured to manage the plurality of optical engines.

12. The system of any of claims 1-4, 8 and 10, comprising a housing having a front panel, the first stage package being in the housing, the system further comprising a front panel package comprising a laser connected to the first stage package by an optical fiber.

13. The system according to claim 12, wherein: The front panel package has a QSFP-DD or OSFP-DD form factor, and the optical fiber connects a first interface of the front panel package to the first level package, the first interface being located outside the front panel.

14. The system according to any one of claims 1-4, 8, 10 and 13, wherein: The first integrated circuit is a packet-switched digital integrated circuit.

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