Integrated chip and method for forming the same

Abstract

Embodiments of the present disclosure relate in some embodiments to a method for forming an integrated chip. The method includes forming a plurality of bonding pad structures above an interconnect structure on the front side of a semiconductor body, and the plurality of bonding pad structures respectively have a titanium contact layer. Patterning the interconnect structure and the semiconductor body to form a groove extending into the semiconductor body. Forming a dielectric filling material in the groove. Before bonding the semiconductor body to a carrier substrate, etching the dielectric filling material to expose the titanium contact layer. Thinning the semiconductor body to expose the dielectric filling material along the back side of the semiconductor body and forming a plurality of integrated chip dies; and removing the dielectric filling material to separate the plurality of integrated chip dies. Embodiments of the present application also provide an integrated chip and a method for forming the same.

Description

Technical Field

[0001] Embodiments of the present application relate to an integrated chip and a method for forming the same. Background Art

[0002] Integrated chip manufacturing is a complex, multi-step process in which circuits are formed on a wafer made of semiconductor material (e.g., silicon). Integrated chip manufacturing can be broadly divided into front-end-of-line (FEOL) processes and back-end-of-line (BEOL) processes. FEOL processes generally involve the formation of devices (e.g., transistors) within the semiconductor material, while BEOL processes generally involve the formation of conductive interconnects within a dielectric structure above the semiconductor material. After the BEOL process is completed, bonding pads are formed and the wafer is then singulated (e.g., diced) to form multiple independent integrated chip dies. Summary of the invention

[0003] An embodiment of the present disclosure relates to a method for forming an integrated chip, comprising: forming a plurality of bonding pad structures above an interconnect structure on the front side of a semiconductor body, wherein the plurality of bonding pad structures respectively include a titanium contact layer; patterning the interconnect structure and the semiconductor body to form a groove extending into the semiconductor body; forming a dielectric filling material in the groove; before bonding the semiconductor body to a carrier substrate, etching the dielectric filling material to expose the titanium contact layer; thinning the semiconductor body to expose the dielectric filling material along the back side of the semiconductor body and forming a plurality of integrated chip dies; and removing the dielectric filling material to separate the plurality of integrated chip dies.

[0004] In other embodiments, the present disclosure relates to a method for forming an integrated chip, comprising: forming a bonding pad stack above an interconnect structure of a semiconductor body, the bonding pad stack comprising a contact layer; patterning the bonding pad stack according to a first mask layer to form a plurality of bonding pad structures, wherein the first mask layer comprises a metal oxide; patterning the interconnect structure and the semiconductor body to have sidewalls forming a groove extending into the semiconductor body; forming a dielectric filling material within the groove; etching the dielectric filling material and the first mask layer to expose the contact layer; removing a portion of the semiconductor body so that the dielectric filling material extends completely through the semiconductor body, wherein removing the portion of the semiconductor body forms a plurality of integrated chip dies; and exposing the dielectric filling material to an etchant to remove the dielectric filling material and separate the plurality of integrated chip dies.

[0005] In yet other embodiments, the present disclosure relates to an integrated chip, comprising: an interconnect structure disposed above a substrate, wherein the interconnect structure comprises a plurality of interconnect layers disposed within a dielectric structure; a bonding pad structure disposed above the interconnect structure, wherein the bonding pad structure comprises a contact layer; a first mask layer comprising a metal oxide disposed above the bonding pad structure, the first mask layer having an inner sidewall disposed directly above the bonding pad structure to form an opening; and a conductive bump disposed within the opening and on the contact layer.

[0006] Embodiments of the present application provide a thin film structure for a bonding pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention can be better understood according to the specific description in conjunction with the reference drawings. It should be emphasized that, according to standard practice in the industry, the various components are not drawn to scale and are only used for the purpose of illustration. In fact, for clear discussion, the size of the various components can be arbitrarily increased or reduced.

[0008] Figure 1 Cross-sectional views of some embodiments of an integrated chip die having a bond pad structure including a contact layer that is resistant to fluorine-based etches are shown.

[0009] Figure 2A-2B Cross-sectional views of some additional embodiments of integrated chip dies having disclosed bond pad structures are shown.

[0010] Figure 3 Cross-sectional views of some additional embodiments of integrated chip dies having disclosed bond pad structures are shown.

[0011] Figure 4 Cross-sectional views of some additional embodiments of integrated chip dies having disclosed bond pad structures are shown.

[0012] Figure 5 Cross-sectional views of some embodiments of integrated chip packages having the disclosed bond pad structures are shown.

[0013] Figure 6A-6B Cross-sectional views of some additional embodiments of integrated chip packages, each having a plurality of the disclosed integrated chip dies, are shown.

[0014] Figure 7-21D Cross-sectional views of some embodiments of methods of forming an integrated chip die having a bond pad structure including a contact layer that is resistant to fluorine-based etches are shown.

[0015] Fig. 22 A flow chart illustrating some embodiments of a method of forming an integrated chip die having a bond pad structure including a contact layer that is resistant to fluorine-based etches. DETAILED DESCRIPTION

[0016] Specific embodiments or examples of components and arrangements are described below to simplify the present invention. These are, of course, examples only and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. As used herein, forming a first component on a second component refers to forming a first component in direct contact with the second component. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0017] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein likewise interpreted accordingly.

[0018] Integrated chips are typically manufactured by forming transistor devices within a semiconductor wafer and then forming an interconnect structure above the semiconductor wafer. The interconnect structure includes a plurality of conductive interconnect layers that increase in size as the distance from the semiconductor wafer increases. The interconnect layers terminate at bonding pads formed above the top of the interconnect structure. After the bonding pads are formed, the semiconductor wafer is singulated by a dicing process that cuts the wafer into a plurality of individual integrated chip dies. The dicing process is performed by mounting the wafer on an adhesive surface of a piece of dicing tape. A wafer saw then cuts the wafer along scribe lines to separate the wafer into individual integrated chip dies.

[0019] Since the wafer sawing process generates mechanical stress on the wafer, crack stoppers can be provided in the interconnect structure along the periphery of each integrated chip die of the wafer. The crack stoppers include densely arranged conductive interconnect layers configured to prevent cracks caused by the wafer sawing process from propagating into the interior of the integrated chip die. It has been recognized that conventional sawing processes may not be suitable for wafers with relatively small dimensions (less than 5 mm). 2 ) of an integrated chip die, because the size of the crack stop member will proportionally consume most of the area of ​​the integrated chip die.

[0020] Therefore, an alternative process to the conventional dicing process may be to etch deep trenches between adjacent integrated chip dies within a wafer, the deep trenches extending through the interconnect structure to the front side of the wafer. The trenches are filled with dielectric material before thinning the back side of the wafer to expose the dielectric material within the trenches. The dielectric material is then treated with a fluorine-based gas to remove the dielectric material and separate the adjacent integrated chip dies. In some processes, a bonding pad may be formed within the integrated chip die before forming the deep trenches. A bonding pad is formed by depositing a bonding pad stack including an aluminum-copper layer placed between a lower titanium layer and an upper titanium nitride layer. Subsequently, the bonding pad stack is patterned according to a silicon oxynitride hard mask to form a bonding pad. In the process of patterning the bonding pad, the titanium nitride layer protects the aluminum-copper layer, and the titanium nitride layer is then etched to expose the aluminum-copper layer before the dielectric material is exposed to the fluorine-based gas.

[0021] Although the titanium nitride layer protects the aluminum-copper layer during patterning, the etchant used to remove the silicon nitride hard mask can penetrate the titanium nitride layer and damage the underlying aluminum-copper layer. Damage to the aluminum-copper layer increases the resistance of the aluminum-copper layer and the bonding pad. In addition, the fluorine-based gas used to remove the dielectric material may interact with the exposed aluminum-copper layer and leave byproducts (e.g., aluminum fluoride byproducts) on the surface of the aluminum-copper layer, which further increase the resistance of the aluminum-copper layer (e.g., to a resistance greater than or equal to 100 ohms). The increase in the resistance of the aluminum-copper layer and the bonding pad will increase the power consumption of the integrated chip, thereby reducing the performance and / or battery life of the device using the integrated chip.

[0022] The present disclosure relates to a method for forming an integrated chip die having a low resistance bonding pad (e.g., a bonding pad having a resistance of less than 20 ohms). In some embodiments, the method forms a bonding pad stack on an interconnect structure above a semiconductor body, and the bonding pad stack may include a titanium contact layer. The bonding pad stack is selectively etched according to a first mask layer to form a bonding pad structure, and then an etching process is performed to form a groove extending through the interconnect structure and into the semiconductor body. The groove is filled with a dielectric material, and the titanium contact layer is exposed by etching the dielectric material and the first mask layer. The back side of the semiconductor body is then thinned to expose the dielectric filling material in the groove, and the back side of the semiconductor body is thinned before a fluorine-based gas is applied to the node material to remove the dielectric material and separate the semiconductor body into a plurality of integrated chip dies. Since the first mask layer remains in place after the bonding pad structure is formed, damage to the titanium contact layer is reduced. In addition, the titanium contact layer largely prevents the formation of damage and / or byproducts caused by the fluorine-based gas, and therefore, the resistance of the titanium contact layer is lower than the damaged aluminum-copper layer.

[0023] Figure 1A cross-sectional view of some embodiments of an integrated chip die 100 having a bond pad structure including a contact layer that is resistant to fluorine-based etches is shown.

[0024] The integrated chip die 100 includes a transistor device 104 disposed within a substrate 102. An interconnect structure 106 is disposed over the substrate 102 and surrounds the transistor device 104. The interconnect structure 106 includes a plurality of interconnect layers 108 disposed within a dielectric structure 110. The plurality of interconnect layers 108 are electrically coupled to the transistor device 104. In some embodiments, the transistor device 104 may include a MOSFET, a bipolar junction transistor (BJT), a high electron mobility transistor (HEMT), or the like.

[0025] The bonding pad structure 112 is arranged above the interconnect structure 106. The bonding pad structure 112 includes one or more conductive layers 114, which are electrically coupled to the plurality of interconnect layers 108. The bonding pad structure 112 also includes a contact layer 116 disposed above the one or more conductive layers 114. The contact layer 116 is highly resistant to fluorine-based etchants, so that the fluorine-based etchants (e.g., gaseous hydrofluoric acid) do not form byproducts on the contact layer 116. For example, in some embodiments, the contact layer 116 may include titanium, chromium, platinum, gold, or the like. In some embodiments, the contact layer 116 may include a metal alloy that is completely free of aluminum and / or copper.

[0026] A first mask layer 118 is disposed over the contact layer 116, and a second mask layer 120 is disposed over the first mask layer 118. In some embodiments, the first mask layer 118 is completely confined over the contact layer 116. The first mask layer 118 and the second mask layer 120 have sidewalls forming an opening 122 that extends through the first mask layer 118 and the second mask layer 120 to the contact layer 116. In some embodiments, the second mask layer 120 extends continuously from directly over the contact layer 116 to along the sidewalls of the bond pad structure 112, the sidewalls of the interconnect structure 106, and the sidewalls of the substrate 102. In some embodiments, the second mask layer 120 may extend to a horizontal line disposed along the bottommost surface 103 of the substrate 102. In some embodiments, the second mask layer 120 may have a bottommost surface 120b that is substantially coplanar with the bottommost surface 103 of the substrate 102.

[0027] In some embodiments, the first mask layer 118 and the second mask layer 120 may include or be the same material. For example, the first mask layer 118 and the second mask layer 120 may include or be a metal oxide, such as aluminum oxide, magnesium oxide, iron oxide, or the like. In other embodiments, the first mask layer 118 and the second mask layer 120 may include or be different materials. For example, the first mask layer 118 and the second mask layer 120 may include or be different metal oxides.

[0028] Conductive bumps 124 are disposed on contact layer 116 and extend vertically from contact layer 116 to over first mask layer 118 and second mask layer 120. Conductive bumps 124 are configured to electrically couple contact layer 116 to another substrate (eg, an integrated chip die, a package substrate, an interposer substrate, etc.).

[0029] During the manufacture of the integrated chip die 100, the first mask layer 118 is maintained above the contact layer 116 to prevent damage to the contact layer 116. In addition, during the manufacturing process, the upper surface of the contact layer 116 may be exposed to a fluorine-based etchant (e.g., gaseous hydrofluoric acid). Because the contact layer 116 is a material that is highly resistant to fluorine-based etchants, the formation of byproducts on the contact layer 116 can be prevented, and therefore the contact layer 116 is not covered by fluorine-based byproducts. By preventing the formation of byproducts on the contact layer 116, the resistance of the contact layer 116 can be kept relatively low (e.g., less than or equal to about 12 ohms). In addition, omitting the aluminum-copper layer from the bonding pad structure 112 can reduce some deposition processes used in its formation process, thereby reducing the cost of forming the bonding pad structure 112.

[0030] Figure 2A Cross-sectional views of some additional embodiments of an integrated chip die 200 having a bond pad structure including a contact layer that is resistant to fluorine-based etches are shown.

[0031] The integrated chip die 200 includes a transistor device 104 disposed within a substrate 102. In some embodiments, the transistor device 104 includes a source region 104s and a drain region 104d disposed within the substrate 102. A gate 104e is disposed above the substrate 102 at a location between the source region 104s and the drain region 104d. The gate 104e is separated from the substrate 102 by means of a gate dielectric layer 104g.

[0032] The interconnect structure 106 is arranged above the substrate 102 and surrounds the gate electrode 104e of the transistor device 104. The interconnect structure 106 includes a plurality of interconnect layers 108 disposed within the dielectric structure 110. In some embodiments, the plurality of interconnect layers 108 may include conductive contacts 108a, interconnect lines 108b, and interconnect vias 108c. In some embodiments, the plurality of interconnect layers 108 may include copper, tungsten, aluminum, or the like. In some embodiments, the dielectric structure 110 may include a plurality of stacked interlayer dielectric (ILD) layers vertically separated from each other by an etch stop layer. In some embodiments, the plurality of stacked ILD layers may include one or more silicon dioxide, doped silicon dioxide (e.g., carbon-doped silicon dioxide), silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), or the like. In some embodiments, the interconnect structure 106 has no crack stop region around the integrated chip die 200.

[0033] Redistribution structure 202 is disposed over interconnect structure 106. Redistribution structure 202 includes a passivation layer 204 surrounding a conductive redistribution layer 206. In some embodiments, passivation layer 204 may include a nitride (e.g., silicon nitride), a carbide (e.g., silicon oxycarbide), an oxide (e.g., PESiON), or the like. In some embodiments, conductive redistribution layer 206 may include a conductive contact having a vertically extending sidewall extending completely through passivation layer 204. In some embodiments, conductive redistribution layer 206 may include tungsten. In other embodiments, conductive redistribution layer 206 may additionally or alternately include one or more other types of metals (e.g., aluminum, copper, etc.).

[0034] The bonding pad structure 112 is disposed over the redistribution structure 202. In some embodiments, the bonding pad structure 112 may include a first conductive layer 208, a diffusion barrier layer 210 disposed over the first conductive layer 208, and a contact layer 116 disposed over the diffusion barrier layer 210 and comprising a material resistant to fluorine-based etchants. In some embodiments, the first conductive layer 208 may include or be titanium. In some embodiments, the diffusion barrier layer 210 may include or be titanium nitride. In some embodiments, the contact layer 116 may include or be titanium. In some embodiments, the first conductive layer 208 may have a thickness ranging between about 50 angstroms and about 150 angstroms. In some embodiments, the diffusion barrier layer 210 may have a thickness ranging between about 100 angstroms and about 5000 angstroms. In some embodiments, the contact layer 116 may have a thickness ranging between about 100 angstroms and about 5000 angstroms.

[0035] The first mask layer 118 is disposed over the bonding pad structure 112. The first mask layer 118 has an inner sidewall disposed directly over the upper surface of the bonding pad structure 112 and an outermost sidewall substantially aligned with the outermost sidewall of the bonding pad structure 112. In some embodiments, the thickness of the contact layer 116 directly under the first mask layer 118 may be greater than the thickness located laterally outward of the first mask layer 118 (e.g., between the inner sidewalls of the first mask layer 118). In some embodiments, the first mask layer 118 may have a thickness ranging between about 150 angstroms and about 450 angstroms. In other embodiments, the first mask layer 118 may have a thickness of about 300 angstroms.

[0036] The second mask layer 120 is disposed over the first mask layer 118. The second mask layer 120 has an inner sidewall disposed directly over the upper surface of the bond pad structure 112. The second mask layer 120 extends along the outermost sidewall of the bond pad structure 112 and is located over the top of the redistribution structure 202. In some embodiments, the second mask layer 120 may have a thickness ranging between about 150 angstroms and about 450 angstroms. In other embodiments, the second mask layer 120 may have a thickness of about 300 angstroms.

[0037] Figure 2B Cross-sectional views of some additional embodiments of an integrated chip die 212 having a bond pad structure including a contact layer that is resistant to fluorine-based etches are shown.

[0038] Integrated chip die 212 includes a redistribution structure 202 disposed above an interconnect structure 106, the interconnect structure 106 including a plurality of interconnect layers 108 within a dielectric structure 110 above substrate 102. Redistribution structure 202 includes a first passivation layer 204a having sidewalls forming a first opening directly above one of the plurality of interconnect layers 108. A conductive redistribution layer 214 is disposed above an upper surface of the first passivation layer 204a and extends through the first opening to the plurality of interconnect layers 108. In some embodiments, the conductive redistribution layer 214 may include a vertical extension extending through the first opening and a horizontal extension protruding outward from the sidewall of the vertical extension. A second passivation layer 204b is disposed above the first passivation layer 204a and the conductive redistribution layer 214. The second passivation layer 204b has sidewalls forming a second opening directly above the conductive redistribution layer 214.

[0039] The bonding pad structure 112 is disposed above the upper surface of the second passivation layer 204b and extends through the second opening to the conductive redistribution layer 214. The bonding pad structure 112 includes a first conductive layer 208, a diffusion barrier layer 210 disposed above the first conductive layer 208, and a contact layer 116 disposed above the diffusion barrier layer 210. The first conductive layer 208, the diffusion barrier layer 210, and the contact layer 116 are generally consistent with the sidewalls and upper surface of the second passivation layer 204b. The contact layer 116 has an inner sidewall coupled with a horizontally extending surface to form a groove in the upper surface of the contact layer 116. The conductive bump 124 fills the groove and extends from the groove to above the second passivation layer 204b.

[0040] Figure 3 Cross-sectional views of some additional embodiments of an integrated chip die 300 having a bond pad structure including a contact layer that is resistant to fluorine-based etches are shown.

[0041] The integrated chip die 300 includes an interconnect structure 106 including a dielectric structure 110 disposed above a substrate 102. A redistribution structure 202 is disposed on a passivation layer 204 above the interconnect structure 106. In some embodiments, the passivation layer 204, the dielectric structure 110, and the substrate 102 may have sidewalls that form an obtuse angle α with the bottommost surface of the substrate 102. For example, in some embodiments, the obtuse angle α ranges between about 90° and about 95°. In some embodiments (not shown), the sidewalls of the passivation layer 204, the dielectric structure 110, and the substrate 102 may have a scalloped profile including a plurality of arcuate surfaces.

[0042] The redistribution structure 202 couples the interconnect structure 106 to the bonding pad structure 112. The bonding pad structure 112 includes a conductive bonding pad 302 that is laterally surrounded by an additional passivation layer 304. The additional passivation layer 304 extends continuously from a sidewall of the conductive bonding pad 302 to over the conductive bonding pad 302. The additional passivation layer 304 includes a sidewall disposed on the conductive bonding pad 302, the sidewall forming an opening in the additional passivation layer 304. The first conductive layer 208 is disposed over the additional passivation layer 304 and extends through the opening to the conductive bonding pad 302. The diffusion barrier layer 210 is disposed over the first conductive layer 208, and the contact layer 116 is disposed over the diffusion barrier layer 210.

[0043] Figure 4 Cross-sectional views of some additional embodiments of an integrated chip die 400 having a bond pad structure including a contact layer that is resistant to fluorine-based etches are shown.

[0044] The integrated chip die 400 includes a plurality of transistor devices 104a-104b disposed within a substrate 102. A plurality of bonding pad structures 112a-112b are arranged above a redistribution structure 202 on the substrate 102. The plurality of bonding pad structures 112a-112b include a first bonding pad structure 112a electrically coupled to a first transistor 104a and a second bonding pad structure 112b electrically coupled to a second transistor 104b. The first bonding pad structure 112a has an outermost wall laterally spaced apart from an outermost wall of the second bonding pad structure 112b by a non-zero distance.

[0045] The first mask layer 118 is disposed over the first and second bonding pad structures 112a and 112b. The second mask layer 120 is disposed on the first mask layer 118. The second mask layer 120 extends along the outermost sidewalls of the first and second bonding pad structures 112a and 112b.

[0046] Figure 5-6B Some embodiments of integrated chip packages including the disclosed integrated chip dies are shown. It is noteworthy that Figure 5-6B are some examples of applicable packages, but the application of the integrated chip die is not limited to such packages and may also be implemented in a wider range of packages.

[0047] Figure 5 A cross-sectional view of some embodiments of an integrated chip package 500 including the disclosed integrated chip die is shown.

[0048] The integrated chip package 500 includes a package substrate 502 having a first horizontal routing layer 504 coupled to a second horizontal routing layer 508 by way of a vertical routing layer 506 extending through a substrate 507. The first horizontal routing layer 504 is coupled to a plurality of solder bumps 510. The second horizontal routing layer 508 is coupled to one or more bump structures 512, which are further coupled to an integrated chip die 514 disposed above the package substrate 502. In various embodiments, the one or more bump structures 512 may include solder bumps, copper pillars, micro bumps (having a width ranging from about 5 μm to 30 μm), or other suitable bump structures.

[0049] The integrated chip die 514 includes an interconnect structure 518 disposed above the substrate 516. In some embodiments, the interconnect layer within the interconnect structure 518 is coupled to one or more bump structures 512 by way of through substrate vias (TSVs) 517 extending through the substrate 516. The redistribution structure 520 couples the interconnect structure 518 to a first bonding pad 522a and a second bonding pad 522b. The first bonding pad 522a and the second bonding pad 522b are further coupled to a first microbump 524a and a second microbump 524b, respectively. The first microbump 524a couples the integrated chip die 514 to the first integrated chip die 526a, and the second microbump 524b couples the integrated chip die 514 to the second integrated chip die 526b. The first integrated chip die 526a and the second integrated chip die 526b include a second mask layer 120 disposed along the outer sidewalls of the first integrated chip die 526a and the second integrated chip die 526b, respectively.

[0050] The dielectric material 528 is disposed above the integrated chip die 514 and surrounds the first integrated chip die 526a and the second integrated chip die 526b. In some embodiments, the dielectric material 528 may contact the second mask layer 120 along the opposite sides of the first integrated chip die 526a and the second integrated chip die 526b. In different embodiments, the dielectric material 528 may include an oxide, a polymer, a resin, or the like. The molding compound 530 is disposed above the package substrate 502 and surrounds the dielectric material 528. In different embodiments, the molding compound 530 may include a polymer, a resin, or the like.

[0051] Fig. 6A Cross-sectional views of some additional embodiments of an integrated chip package 600 having multiple integrated chip dies are shown.

[0052] The integrated chip package 600 includes a first integrated chip die 526a, which is coupled to the package substrate 502 by means of a first micro-bump 602a. The first integrated chip die 526a includes a first bonding pad structure 112a coupled to a second micro-bump 602b. The second micro-bump 602b is further coupled to a second bonding pad structure 112b of the second integrated chip die 526b. The molding compound 530 is disposed above the package substrate 502 and surrounds the first integrated chip die 526a and the second integrated chip die 526b.

[0053] Figure 6B Cross-sectional views of some additional embodiments of integrated chip packages 604 having multiple integrated chip dies are shown.

[0054] The integrated chip package 604 includes a first integrated chip die 526a coupled to the package substrate 502 by means of a first micro bump 602a. The first integrated chip die 526a includes a first bonding pad structure 112a coupled to a conductive bonding structure 606. The conductive bonding structure 606 is further coupled to a second bonding pad structure 112b of a second integrated chip die 526b. The first integrated chip die 526a and the second integrated chip die 526b are respectively surrounded by a second mask layer 120. The second mask layer 120 surrounding the first integrated chip die 526a and the second mask layer 120 surrounding the second integrated chip die 526b are in contact with each other along a hybrid bonding interface 608 including the conductive bonding structure 606 and the second mask layer 120.

[0055] Figure 7-21D Cross-sectional views 700-2100 illustrate some embodiments of methods of forming an integrated chip die having a bond pad structure including a contact layer that is resistant to fluorine-based etches. Figure 7-21D described as being about a method, but it is worth noting that Figure 7-21D The disclosed structure is not limited to this method, but may alternatively be a structure independent of this method.

[0056] like Figure 7 As shown in the cross-sectional view 700 of , a semiconductor body 702 is provided. In various embodiments, the semiconductor body 702 may be any type of substrate (e.g., silicon, silicon germanium, silicon on insulator, etc.), such as a semiconductor wafer, and any other type of semiconductor and / or epitaxial layer associated therewith. The semiconductor body 702 includes a plurality of integrated chip die regions 704-706. A plurality of transistor devices 104 are formed along a first side 702s1 (e.g., a front side) of the semiconductor body 702 within each of the plurality of integrated chip die regions 704-706.

[0057] like Figure 8As shown in the cross-section 800 of FIG. 8 , an interconnect structure 106 is formed along a first side 702s1 of a semiconductor body 702. The interconnect structure 106 includes a plurality of interconnect layers 108 formed within a dielectric structure 110. In some embodiments, the dielectric structure 110 may include a plurality of stacked interlayer dielectric (ILD) layers formed above the semiconductor body 702. In some embodiments (not shown), the plurality of stacked ILD layers are separated by an etch stop layer. In some embodiments, the plurality of interconnect layers 108 may include conductive contacts 108a, interconnect lines 108b, and interconnect vias 108c. The plurality of interconnect layers are formed by forming one or more ILD layers (e.g., oxide, low dielectric constant, or ultra-low dielectric constant) above the semiconductor body 702, selectively etching the ILD layers to form vias and / or trenches within the ILD layers, forming a conductive material (e.g., copper, aluminum, etc.) within the vias and / or trenches, and performing a planarization process (e.g., a chemical mechanical planarization process).

[0058] like Fig. 9 As shown in cross-sectional view 900 of FIG. 1 , a redistribution structure 202 is formed over the interconnect structure 106. In some embodiments, the redistribution structure 202 can be formed by depositing a passivation layer 204 over the interconnect structure 106. The passivation layer 204 is then etched to expose one or more of the plurality of interconnect layers 108 within the interconnect structure 106. A conductive material (e.g., tungsten) is deposited over the passivation layer 204. A portion of the conductive material is then removed to form a conductive redistribution layer 206 within the redistribution structure 202.

[0059] like Fig.10 As shown in the cross-sectional view 1000 of FIG. 1 , a bonding pad stack 1002 including a contact layer 1008 is formed above the redistribution structure 202. In some embodiments, the bonding pad stack 1002 may include a first conductive layer 1004, a diffusion barrier layer 1006 disposed above the first conductive layer 1004, and a contact layer 1008 disposed above the diffusion barrier layer 1006. In some embodiments, the first conductive layer 1004 may include a metal, such as titanium, tantalum, or the like. In some embodiments, the diffusion barrier layer 1006 may include a metal nitride, such as titanium nitride, tantalum nitride, or the like. The contact layer 1008 is a conductive material that is highly resistant to fluorine-based etchants. For example, in some embodiments, the contact layer 1008 may include or be titanium, chromium, platinum, gold, or the like. In some embodiments, the contact layer 1008 may include a metal alloy that is completely free of aluminum and / or copper. In some embodiments, the bond pad stack 1002 may be formed by a plurality of deposition processes [eg, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, plasma enhanced chemical vapor deposition (PE-CVD), etc.].

[0060] like Fig.11As shown in the cross-sectional view 1100 of , a first mask layer 118 is formed over the bonding pad stack 1002. In some embodiments, the first mask layer 118 may include a metal oxide, such as aluminum oxide, magnesium oxide, or the like. The first mask layer 118 may be formed by depositing a first mask material over the bonding pad stack 1002, performing a photolithography patterning process to pattern the first mask material, and forming the first mask layer 118. In some embodiments, the first mask material may be formed to a thickness between about 250 angstroms and about 350 angstroms. Such a thickness of the first mask material may prevent damage to the contact layer 1008 below.

[0061] like Fig.12 As shown in the cross-sectional view 1200 of the patterned bonding pad stack ( Fig.11 1002 in the figure) to form a plurality of bonding pad structures 112a-112d. In some embodiments, the bonding pad stack can be patterned by selectively exposing the bonding pad stack to an etchant 1202 according to the first mask layer 118. Fig.11 In some embodiments, the etchant 1202 may include a dry etchant (eg, having a chlorine-based chemistry).

[0062] like Fig.13 As shown in the cross-sectional view 1300 of , the dielectric structure 110 and the semiconductor body 702 are patterned to form trenches 1302a-1302c extending into the first side 702s1 of the semiconductor body 702. The trenches 1302a-1302c include a first trench 1302a disposed along a first side of the first integrated chip region 704, a second trench 1302b disposed between a second side of the first integrated chip region 704 and a first side of the second integrated chip region 706, and a third trench 1302c disposed along a second side of the second integrated chip region 706.

[0063] In some embodiments, the dielectric structure 110 and the semiconductor body 702 can be patterned by selectively exposing the dielectric structure 110 and the semiconductor body 702 to the etchant 1306 according to the trench mask layer 1304. The trench mask layer 1304 extends above the plurality of bonding pad structures 112a-112d and includes sidewalls that form openings disposed between adjacent integrated chip die regions 704-706. In some embodiments, the trench mask layer 1304 may include an oxide, a nitride, a carbide, or the like. In some embodiments, the etchant 1306 may include a dry etchant. In some embodiments, the etchant 1306 may be part of a deep reactive ion etching process [e.g., a Bosch etching process]. The trench mask layer 1304 may be removed after the dielectric structure 110 and the semiconductor body 702 are patterned.

[0064] like Fig.14 As shown in the cross-sectional view 1400 of , a second mask layer 120 is formed over the first mask layer 118 and along the sidewalls of the plurality of pad structures 112a-112d, the redistribution structure 202, the dielectric structure 110, and the semiconductor body 702 forming the trenches 1302a-1302c. In some embodiments, the second mask layer 120 may include, for example, a metal oxide, such as aluminum oxide. In some embodiments, the second mask layer 120 may be formed by a deposition process (e.g., CVD, PE-CVD, PVD, etc.). In some embodiments, the second mask layer 120 is formed to a thickness between about 250 angstroms and about 350 angstroms. Such a thickness of the second mask layer 120 may prevent damage to underlying layers during subsequent exposure to a fluorine-based etchant.

[0065] A dielectric fill material 1402 is formed over the second mask layer 120. The dielectric fill material 1402 fills the trenches 1302a-1302c and extends over the top surfaces of the plurality of bonding pad structures 112a-112d. In some embodiments, the dielectric fill material 1402 may include an oxide (e.g., silicon oxide), a nitride, or the like. In some embodiments, the dielectric fill material 1402 may be formed by a deposition process (e.g., CVD, PE-CVD, PVD, etc.).

[0066] like Fig.15 As shown in the cross-sectional view 1500 of FIG. 1 , the dielectric filling material 1402, the second mask layer 120, and the first mask layer 118 are patterned to form openings 1502, and the openings 1502 expose the contact layers 116 in each of the plurality of bonding pad structures 112a-112d. In some embodiments, the dielectric filling material 1402, the second mask layer 120, and the first mask layer 118 may be selectively patterned using a photolithography process and a dry etching process.

[0067] like Fig.16 As shown in the cross-sectional view 1600 of , an additional dielectric material 1602 is formed over the dielectric filling material 1402. The additional dielectric material 1602 fills the opening 1502 in the dielectric filling material 1402. In some embodiments, the additional dielectric material 1602 may include an oxide formed by a deposition process (e.g., CVD, PE-CVD, PVD, etc.). In some embodiments, after the additional dielectric material 1602 is deposited, a planarization process (e.g., a chemical mechanical planarization process) may be performed to form a substantially planar surface on the semiconductor body 702 with the dielectric filling material 1402 and / or the additional dielectric material 1602.

[0068] like Fig.17As shown in the cross-sectional view 1700 of FIG. 1 , the dielectric fill material 1402 and the additional dielectric material 1602 are bonded to the carrier substrate 1702. In some embodiments, the dielectric fill material 1402 and the additional dielectric material 1602 may be bonded to the carrier substrate 1702 by means of a fusion bonding process. In some embodiments, the fusion bonding process is performed by moving the carrier substrate 1702 into contact with the dielectric fill material 1402 and / or the additional dielectric material 1602 at a relatively high temperature (e.g., a temperature greater than about 500° C.).

[0069] like Fig.18 As shown in the cross-sectional view 1800, a portion of the semiconductor body is removed ( Fig.17 702) to thin the semiconductor body. Thinning the semiconductor body to expose the trench ( Fig.14 The dielectric filling material 1402 in the first substrate 102a-1302c) and the second mask layer 120 are combined to form a plurality of integrated chip dies 1802-1804. The plurality of integrated chip dies 1802-1804 include a first integrated chip die 1802 and a second integrated chip die 1804. The first integrated chip die 1802 has a first dielectric structure 106a disposed above the first substrate 102a. The first dielectric structure 106a is coupled to the bonding pad structures 112a-112b by means of a first redistribution structure 202a. The second integrated chip die 1804 has a second dielectric structure 106b disposed above the second substrate 102b. The second dielectric structure 106b is coupled to the bonding pad structures 112c-112d by means of a second redistribution structure 202b.

[0070] In some embodiments, the semiconductor body may be removed by performing an etching process, a mechanical grinding process, a chemical mechanical polishing process, or the like on the back side of the semiconductor body. Fig.17 Removing portions of the semiconductor body allows the dielectric fill material 1402 to extend continuously between a first horizontal line 1806 extending along the top of the bonding pad structures 112a-112d and a second horizontal line 1808 extending along the bottommost surface of the plurality of integrated chip dies 1802-1804.

[0071] like Fig.19AAs shown in the cross-sectional view 1900 of FIG. 1 , the dielectric fill material 1402 and the additional dielectric material 1602 are removed to separate the plurality of integrated chip dies 1802-1804 from each other and from the carrier substrate 1702. In some embodiments, an etchant 1902 containing gaseous hydrofluoric acid (VHF) may be used to remove the dielectric fill material 1402 and the additional dielectric material 1602. The second mask layer 120 prevents the VHF from damaging the plurality of integrated chip dies 1802-1804. In addition, the contact layer 116 has a low reactivity with fluorine-based etchants, thereby preventing the VHF from forming fluorine-based byproducts on the contact layer 116 (so that the upper surface of the contact layer 116 has no fluorine-based byproducts) and maintaining a low resistance (e.g., less than about 12 ohms).

[0072] Fig.19B The cross-sectional view 1904 shows a cross-sectional view of the integrated chip die 1802 after the dielectric fill material 1402 and the additional dielectric material 1602 are removed.

[0073] Figures 20A-21D 1802-1804. Figures 20A-21D The packaging process of is a non-limiting example of a packaging process that may be used to package one or more of the plurality of integrated chip dies 1802 - 1804 .

[0074] Figure 20A-20B Cross-sectional views of some embodiments of a packaging process for packaging one or more of the plurality of integrated chip dies 1802 - 1804 are shown.

[0075] like Fig. 20A As shown in the cross-sectional view 2000 of FIG. 1 , the integrated chip die 1802 is bonded to the package substrate 502 by means of one or more bump structures 512. The one or more bump structures 512 are formed over the package substrate 502 so that the package substrate 502 is coupled to the integrated chip die 1802. In various embodiments, the one or more bump structures 512 may include solder bumps, copper pillars, micro bumps (having a width ranging from about 5 μm to about 30 μm), or other applicable bump structures.

[0076] like Fig. 20B As shown in the cross-sectional view 2002 of FIG. 1 , a molding compound 530 is formed above the package substrate 502 and around the integrated chip die 1802. In some embodiments, the molding compound 530 may include epoxy resin, epoxy resin with thermal conductive filler material, organic cylinder, plastic molding compound, plastic molding compound with fiber, or other suitable materials. In some embodiments, the molding compound 530 may be formed by a spin coating process, an injection molding process, and / or a similar process.

[0077] Figure 21A-Figure 21D Cross-sectional views of some alternative embodiments of packaging processes for packaging one or more of the plurality of integrated chip dies 1802 - 1804 are shown.

[0078] like Fig.21A As shown in the cross-sectional view 2100 of , a plurality of integrated chip dies 1802-1804 are bonded to the wafer 2102 by means of a plurality of bump structures 524. In different embodiments, the plurality of bump structures 524 may include solder bumps, copper pillars, microbumps, or other applicable bump structures. The wafer 2102 includes an interconnect structure 2106 disposed above the substrate 2104. The redistribution structure 2108 couples the interconnect structure 2106 to the plurality of bonding pads 522.

[0079] like Fig.21B As shown in the cross-sectional view 2110 of , a dielectric material 528 is formed over the wafer 2102 and around the plurality of integrated chip dies 1802-1804. In some embodiments, the dielectric material 528 may include an oxide. In other embodiments, the dielectric material 528 may include an epoxy resin, a polymer, or other suitable material.

[0080] like Fig. 21C As shown in the cross-sectional view 2112, the singulated wafer ( Fig.21B 2102 in the figure) to form a plurality of integrated chip dies 514a-514b. In some embodiments, the wafer ( Fig.21B The wafer is singulated by a dicing process by fixing the wafer (2102) to the sticky surface of a dicing tape 2114. The wafer is then cut along the scribe lines 2116 by a wafer saw to separate the wafer into separate integrated chip dies 514a-514b. In some embodiments (not shown), the wafer ( Fig.21B 2102) may have crack stoppers disposed within the interconnect structure 2106 on opposite sides of the scribe line 2116. Crack stoppers are densely arranged interconnect layers that prevent crack propagation caused by the sawing process.

[0081] like Fig.21D As shown in the cross-sectional view 2118 of FIG. 1 , one of the plurality of integrated chip dies 514a is bonded to the package substrate 502 by means of one or more bump structures 512. The one or more bump structures 512 are formed over the package substrate 502 so that the package substrate 502 is coupled to the integrated chip die 1802. In various embodiments, the one or more bump structures 512 may include solder bumps, copper pillars, micro bumps (having a width ranging from about 5 μm to 30 μm), or other suitable bump structures.

[0082] A molding compound 530 is formed over the package substrate 502 and around the integrated chip die 1802. In some embodiments, the molding compound 530 may include epoxy resin, epoxy resin with thermally conductive filler material, organic tubing, plastic molding compound, plastic molding compound with fiber, or other suitable material. In some embodiments, the molding compound 530 may be formed by a spin coating process, an injection molding process, and / or the like.

[0083] Fig. 22 A flow chart illustrating some embodiments of a method 2200 of forming an integrated chip die having a bond pad structure including a contact layer that is resistant to fluorine-based etches.

[0084] Although method 2200 is illustrated and described as a series of actions or events in this article, it should be understood that the illustrated order of such actions or events should not be interpreted in a restrictive sense. For example, in addition to those actions or events illustrated and / or described herein, certain actions may occur in different orders and / or occur simultaneously with other actions or events. In addition, all the actions shown may not be required to realize one or more aspects or embodiments described herein. In addition, one or more actions described herein may be performed in one or more separate actions and / or stages.

[0085] At act 2202, a transistor device is formed within an integrated chip die region of a semiconductor body. Figure 7 A cross-sectional view 700 corresponding to some embodiments of act 2202 is shown.

[0086] At act 2204, an interconnect structure is formed along the front side of the semiconductor body. Figure 8 A cross-sectional view 800 corresponding to some embodiments of act 2204 is shown.

[0087] At act 2206, a bond pad stack including a contact layer is formed over the interconnect structure. In some embodiments, the contact layer may include or be titanium. Fig.10 A cross-sectional view 1000 corresponding to some embodiments of act 2206 is shown.

[0088] At act 2208 , the bond pad stack is patterned according to the first mask layer to form a plurality of bond pad structures. Figure 11-Figure 12 Cross-sectional views 1100 - 1200 corresponding to some embodiments of act 2208 are shown.

[0089] At act 2210, the interconnect structure and the semiconductor body are patterned to form trenches extending into the semiconductor body between adjacent integrated chip die regions. Fig.13 Cross-sectional view 1300 corresponding to some embodiments of act 2210 is shown.

[0090] At act 2212, a second mask layer is formed within the trench and over the first mask layer. Fig.14 A cross-sectional view 1400 corresponding to some embodiments of act 2212 is shown.

[0091] At 2214, a dielectric fill material is formed over the second mask layer. Fig.14 A cross-sectional view 1400 corresponding to some embodiments of act 2214 is shown.

[0092] At activity 2216 , the first mask layer, the second mask layer, and the dielectric fill material are patterned to form openings that expose the contact layer within the bond pad structure. Fig.15 Cross-sectional view 1500 is shown corresponding to some embodiments of act 2216 .

[0093] At activity 2218, additional dielectric material is formed within the opening and over the dielectric fill material. Fig.16 A cross-sectional view 1600 corresponding to some embodiments of act 2218 is shown.

[0094] At act 2220 , additional dielectric material and / or dielectric fill material is bonded to the carrier substrate. Fig.17 Cross-sectional view 1700 corresponding to some embodiments of act 2220 is shown.

[0095] At act 2222 , portions of the semiconductor body are removed to expose a dielectric fill material along a backside of the semiconductor body and form a plurality of integrated chip dies. Fig.18 Cross-sectional view 1800 is shown corresponding to some embodiments of act 2222 .

[0096] At act 2224 , the dielectric fill material and the additional dielectric fill material are removed to separate the plurality of integrated chip dies. Fig.19A Cross-sectional view 1900 is shown corresponding to some embodiments of act 2224 .

[0097] Thus, in some embodiments, the present disclosure relates to a method of forming an integrated chip die having a low resistance bond pad structure (e.g., a bond pad structure having a resistance of less than 20 ohms). The method of forming the contact pad structure is part of a process of singulating a semiconductor body into separate integrated chip dies using deep trenches.

[0098] In some embodiments, the present disclosure relates to a method for forming an integrated chip. The method for forming an integrated chip comprises: forming a plurality of bonding pad structures above an interconnect structure on the front side of a semiconductor body, wherein the plurality of bonding pad structures respectively comprise a titanium contact layer; patterning the interconnect structure and the semiconductor body to form a groove extending into the semiconductor body; forming a dielectric filling material in the groove; etching the dielectric filling material to expose the titanium contact layer before bonding the semiconductor body to a carrier substrate; thinning the semiconductor body to expose the dielectric filling material along the back side of the semiconductor body and forming a plurality of integrated chip dies; and removing the dielectric filling material to separate the plurality of integrated chip dies. In some embodiments, further comprising: forming a bonding pad stack above the interconnect structure; and patterning the bonding pad stack according to a first mask layer to form a plurality of bonding pad structures, wherein the first mask layer comprises a metal oxide. In some embodiments, further comprising: forming a second mask layer in the groove and above the first mask layer; forming a dielectric filling material above the second mask layer; and etching the dielectric filling material, the first mask layer, and the second mask layer to expose the titanium contact layer. In some embodiments, thinning the semiconductor body further exposes a second mask layer along the back side of the semiconductor body. In some embodiments, the first mask layer and the second mask layer include the same material. In some embodiments, the first mask layer and the second mask layer are aluminum oxide. In some embodiments, removing the dielectric fill material includes exposing the dielectric fill material to an etchant containing gaseous hydrofluoric acid. In some embodiments, the plurality of bonding pad structures respectively include: a first conductive layer including titanium; and a diffusion barrier layer including titanium nitride, and the diffusion barrier layer directly contacts the top of the first conductive layer, wherein the titanium contact layer directly contacts the top of the diffusion barrier layer.

[0099] In other embodiments, the present disclosure relates to a method for forming an integrated chip. The method for forming an integrated chip includes: forming a bonding pad stack above an interconnect structure of a semiconductor body, the bonding pad stack including a contact layer; patterning the bonding pad stack according to a first mask layer to form a plurality of bonding pad structures, wherein the first mask layer includes a metal oxide; patterning the interconnect structure and the semiconductor body to have sidewalls forming a groove extending into the semiconductor body; forming a dielectric fill material in the groove; etching the dielectric fill material and the first mask layer to expose the contact layer; removing a portion of the semiconductor body so that the dielectric fill material extends completely through the semiconductor body, wherein the removal of the portion of the semiconductor body forms a plurality of integrated chip dies; and exposing the dielectric fill material to an etchant to remove the dielectric fill material and separate the plurality of integrated chip dies. In some embodiments, further comprising: bonding the front side of the semiconductor body to a carrier substrate so that the dielectric fill material is located between the front side of the semiconductor body and the carrier substrate. In some embodiments, further comprising: forming a second mask layer within the trench and on the upper surface of the first mask layer; and etching the dielectric fill material, the first mask layer, and the second mask layer to expose the contact layer. In some embodiments, removing a portion of the semiconductor body further causes the second mask layer to extend completely through the semiconductor body. In some embodiments, the first mask layer and the second mask layer are aluminum oxide. In some embodiments, the first mask layer and the second mask layer are the same material.

[0100] In other embodiments, the present disclosure relates to an integrated chip. The integrated chip includes: an interconnect structure disposed above a substrate, wherein the interconnect structure includes a plurality of interconnect layers disposed within a dielectric structure; a bonding pad structure disposed above the interconnect structure, wherein the bonding pad structure includes a contact layer; a first mask layer including a metal oxide disposed above the bonding pad structure, the first mask layer having an inner sidewall disposed directly above the bonding pad structure to form an opening; and a conductive bump disposed within the opening and on the contact layer. In some embodiments, the first mask layer is completely confined above the bonding pad structure. In some embodiments, the first mask layer includes aluminum oxide. In some embodiments, further comprising: a second mask layer disposed above the first mask layer and disposed along the sidewalls of the bonding pad structure, the interconnect structure, and the substrate; and wherein the second mask layer has an inner sidewall disposed directly above the bonding pad structure to further form an opening. In some embodiments, the contact layer is titanium. In some embodiments, the bonding pad structure further includes: a titanium layer; and a titanium nitride layer disposed above the titanium layer, wherein the titanium nitride layer contacts the bottom of the contact layer.

[0101] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art should also appreciate that such equivalent structures do not deviate from the spirit and scope of the present invention, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present invention.

Claims

1. A method for forming an integrated chip, comprising: forming a plurality of bond pad structures over the interconnect structure on the front side of the semiconductor body, wherein the plurality of bond pad structures respectively include a titanium contact layer; patterning the interconnect structure and the semiconductor body to form trenches extending into the semiconductor body; forming a dielectric fill material in the trench; before bonding the semiconductor body to a carrier substrate, etching the dielectric fill material to expose the titanium contact layer; thinning the semiconductor body to expose the dielectric fill material along a backside of the semiconductor body and forming a plurality of integrated chip dies; as well as removing the dielectric filling material to separate the plurality of integrated chip dies, Wherein, the method further comprises: forming a bond pad stack over the interconnect structure; patterning the bond pad stack according to a first mask layer to form the plurality of bond pad structures, wherein the first mask layer comprises a metal oxide; forming a second mask layer in the trench and above the first mask layer; forming the dielectric fill material over the second mask layer; and etching the dielectric filling material, the first mask layer, and the second mask layer to form an opening exposing the titanium contact layer, The second mask layer has an inner sidewall directly disposed above the bonding pad structure to further form the opening, and a contact surface between the second mask layer and the first mask layer and a contact surface between the titanium contact layer and the first mask layer are both horizontal.

2. The method according to claim 1, wherein: The first mask layer is completely confined over the bond pad structure.

3. The method according to claim 1, wherein: The second mask layer completely covers the outermost sidewall of the bonding pad structure.

4. The method according to claim 1, wherein: Thinning the semiconductor body further exposes the second mask layer along the backside of the semiconductor body.

5. The method according to claim 1, wherein: The first mask layer and the second mask layer include the same material.

6. The method according to claim 1, wherein: The first mask layer and the second mask layer are aluminum oxide.

7. The method according to claim 1, wherein: Removing the dielectric fill material includes exposing the dielectric fill material to an etchant including gaseous hydrofluoric acid.

8. The method according to claim 1, wherein: The plurality of bonding pad structures respectively include: a first conductive layer comprising titanium; and A diffusion barrier layer includes titanium nitride, and the diffusion barrier layer directly contacts the top of the first conductive layer, wherein the titanium contact layer directly contacts the top of the diffusion barrier layer.

9. A method for forming an integrated chip, comprising: forming a bond pad stack over an interconnect structure of a semiconductor body, the bond pad stack comprising a contact layer; patterning the bond pad stack according to a first mask layer to form a plurality of bond pad structures, wherein the first mask layer comprises a metal oxide; patterning the interconnect structure and the semiconductor body to have sidewalls forming trenches extending into the semiconductor body; forming a dielectric fill material in the trench; etching the dielectric fill material and the first mask layer to expose the contact layer; removing a portion of the semiconductor body such that the dielectric fill material extends completely through the semiconductor body, wherein removing the portion of the semiconductor body forms a plurality of integrated chip dies; and exposing the dielectric fill material to an etchant to remove the dielectric fill material and separate the plurality of integrated chip dies, The method further comprises: forming a second mask layer in the trench and on an upper surface of the first mask layer, wherein the dielectric filling material is formed on the second mask layer; and etching the dielectric filling material, the first mask layer, and the second mask layer to form an opening exposing the contact layer, The second mask layer has an inner sidewall directly disposed above the bonding pad structure to further form the opening, and a contact surface between the second mask layer and the first mask layer and a contact surface between the contact layer and the first mask layer are both horizontal.

10. The method according to claim 9, further comprising: The front side of the semiconductor body is bonded to a carrier substrate such that the dielectric fill material is located between the front side of the semiconductor body and the carrier substrate.

11. The method according to claim 9, wherein: The second mask layer completely covers the outermost sidewall of the bonding pad structure.

12. The method according to claim 9, wherein: Removing the portion of the semiconductor body further causes the second mask layer to extend completely through the semiconductor body.

13. The method according to claim 9, wherein: The first mask layer and the second mask layer are aluminum oxide.

14. The method according to claim 9, wherein: The first mask layer and the second mask layer are made of the same material.

15. An integrated chip, comprising: an interconnect structure disposed over the substrate, wherein the interconnect structure comprises a plurality of interconnect layers disposed within the dielectric structure; a bonding pad structure disposed above the interconnect structure, wherein the bonding pad structure includes a contact layer; a first mask layer including a metal oxide disposed over the bonding pad structure, the first mask layer having an inner sidewall disposed directly over the bonding pad structure to form an opening; a conductive bump disposed in the opening and on the contact layer; and a second mask layer disposed above the first mask layer and along sidewalls of the bonding pad structure, the interconnect structure, and the substrate; The second mask layer has an inner sidewall directly disposed above the bonding pad structure to further form the opening, and a contact surface between the second mask layer and the first mask layer and a contact surface between the contact layer and the first mask layer are both horizontal.

16. The integrated chip according to claim 15, wherein: The first mask layer is completely confined over the bond pad structure.

17. The integrated chip according to claim 15, wherein: The first mask layer includes aluminum oxide.

18. The integrated chip according to claim 17, wherein: The second mask layer has a bottommost surface coplanar with a bottommost surface of the substrate.

19. The integrated chip according to claim 18, wherein: The contact layer is titanium.

20. The integrated chip according to claim 19, wherein: The bonding pad structure further comprises: a titanium layer; and A titanium nitride layer is located above the titanium layer, wherein the titanium nitride layer contacts the bottom of the contact layer.

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