Method for manufacturing high electron mobility transistor and high electron mobility transistor

Abstract

The present invention relates to a method for manufacturing a high electron mobility transistor and a high electron mobility transistor. The method for manufacturing a high electron mobility transistor comprises the following steps: forming a first SiN film on the surface of a semiconductor stack composed of a nitride semiconductor and including a barrier layer by low-pressure chemical vapor deposition at a first furnace temperature of 700°C or higher and 900°C or lower; forming an interfacial oxide layer on the first SiN film by moisture and oxygen in the furnace at a second furnace temperature of 700°C or higher and 900°C or lower and a furnace pressure of 1 Pa or lower; and forming a second SiN film on the interfacial oxide layer by low-pressure chemical vapor deposition at a third furnace temperature of 700°C or higher and 900°C or lower.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2019-183876 filed on October 4, 2019 (including specification, drawings and abstract) is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a method for manufacturing a high electron mobility transistor and a high electron mobility transistor. Background Art

[0004] JP2016-143843A discloses a semiconductor device. The semiconductor device includes a first GaN-based semiconductor layer, a second GaN-based semiconductor layer, a source electrode, a drain electrode, a gate electrode, and a passivation film. The second GaN-based semiconductor layer disposed on the first GaN-based semiconductor layer has a larger band gap than the first GaN-based semiconductor layer. The source electrode and the drain electrode are electrically connected to the second GaN-based semiconductor layer. The gate electrode is disposed between the source electrode and the drain electrode. The passivation film is disposed on the second GaN-based semiconductor layer between the source electrode and the gate electrode and between the drain electrode and the gate electrode. The passivation film includes a first insulating film containing nitrogen and having a thickness of 0.2 nm or more and 2 nm or less, and a second insulating film disposed above the first insulating film and containing oxygen.

[0005] JP2008-034438A discloses a semiconductor device. The semiconductor device includes a main semiconductor region having a crystalline structure, multiple electrodes connected to the main semiconductor region, and a surface-stabilizing semiconductor layer. The surface-stabilizing semiconductor layer is composed of a material different from that of the main semiconductor region and is disposed on at least a portion of the surface between the multiple electrodes of the main semiconductor region. It has the function of eliminating surface charge on the main semiconductor region. The surface-stabilizing semiconductor layer is a p-type metal oxide semiconductor layer or an n-type metal oxide semiconductor layer.

[0006] JP2007-027284A discloses a field-effect transistor. The field-effect transistor includes a semiconductor substrate, a source electrode, a drain electrode, a gate electrode, and an organic semiconductor film. The semiconductor substrate includes a first semiconductor layer and a second semiconductor layer disposed adjacent to the first semiconductor layer to generate a two-dimensional electron gas. The source electrode and the drain electrode are formed on one main surface of the semiconductor substrate. The gate electrode is disposed between the source electrode and the drain electrode on one main surface of the semiconductor substrate. The organic semiconductor film has p-type conductivity and is disposed on at least a portion of the semiconductor substrate between the source electrode and the drain electrode.

[0007] JP2004-214471A discloses a technology related to a field-effect transistor. The field-effect transistor includes a Group III nitride semiconductor layer structure having a heterojunction, a source electrode and a drain electrode spaced apart on the semiconductor layer structure, and a gate electrode disposed between the source and drain electrodes. An electric field control electrode is formed on top of the Group III nitride semiconductor layer structure via an insulating film in the region between the gate and drain electrodes. The insulating film includes a first insulating film containing silicon and nitrogen as constituent elements, and a second insulating film having a lower relative dielectric constant than the first insulating film.

[0008] Document 1 (Shih-Chien Liu et al., “Effective Passivation With High-Density Positive Fixed Charges for GaN MIS-HEMTs,” Journal of the Electron Devices Society, IEEE, Vol. 5, No. 3, May 2017) discloses a technology related to a high electron mobility transistor (HEMT) made primarily of a GaN-based semiconductor. This document describes controlling the surface potential by providing a SiON film on the surface of a semiconductor layer. Summary of the Invention

[0009] According to an embodiment, a method for manufacturing a HEMT includes the steps of forming a first SiN film on a surface of a semiconductor stack composed of a nitride semiconductor and including a barrier layer by low-pressure chemical vapor deposition at a first furnace temperature of 700° C. or higher and 900° C. or lower; forming an interfacial oxide layer on the first SiN film by moisture and oxygen in the furnace at a second furnace temperature of 700° C. or higher and 900° C. or lower and a furnace pressure of 1 Pa or lower; and forming a second SiN film on the interfacial oxide layer by low-pressure chemical vapor deposition at a third furnace temperature of 700° C. or higher and 900° C. or lower.

[0010] The HEMT according to the embodiment includes a semiconductor stack and a surface protection film. The semiconductor stack is composed of a nitride semiconductor and includes a barrier layer. The surface protection film includes a first SiN film disposed on the surface of the semiconductor stack and a second SiN film disposed on the first SiN film. The surface protection film includes an interface oxide layer between the first SiN film and the second SiN film. The interface oxide layer contains more than 5×10 21 atoms / cm 3 of oxygen atoms and more than 1×10 20 atoms / cm 3of chlorine atoms and has a thickness of 1 nm or less. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a cross-sectional view illustrating an example of a transistor manufactured by the manufacturing method according to the embodiment.

[0012] Figure 2A and Figure 2B is a diagram illustrating a method of manufacturing a transistor according to an embodiment.

[0013] Figure 3A and Figure 3B is a diagram illustrating a method of manufacturing a transistor according to an embodiment.

[0014] Figure 4A and Figure 4B is a diagram illustrating a method of manufacturing a transistor according to an embodiment.

[0015] Figure 5 This is a graph showing the results of SIMS analysis of the vicinity of the surface of a transistor produced by the manufacturing method of the example.

[0016] Figure 6 is a graph showing the measurement results of the CV characteristics of the transistor manufactured by the manufacturing method of the embodiment.

[0017] Figure 7 is a graph showing the results of measuring CV characteristics of a transistor having no interface oxide layer.

[0018] Figure 8A is an energy band diagram of the transistor of the embodiment.

[0019] Figure 8B is an energy band diagram when electrons are trapped in the interface states between the SiN film and the AlGaN barrier layer, in one embodiment.

[0020] Figure 9A FIG1 is an energy band diagram of a transistor without an interface oxide layer as a comparative example.

[0021] Figure 9B is an energy band diagram when electrons are trapped in the interface state between the SiN film and the AlGaN barrier layer in the comparative example. DETAILED DESCRIPTION

[0022] In HEMTs, which primarily use nitride-based semiconductors, current collapse has become a problem, as leakage current decreases (on-resistance increases) when high voltage is applied. Specifically, when electrons in the two-dimensional electron gas layer are accelerated by high voltage, they are trapped in interface states in the barrier layer, increasing the semiconductor surface potential. This reduces the number of electrons in the two-dimensional electron gas layer.

[0023] The Si compound film is deposited as a protective film on the surface of the nitride semiconductor layer. If fixed positive charges having a density equal to or greater than the interface state density exist in the Si compound film, the increase in the semiconductor surface potential can be suppressed. For example, Reference 2 (K. Zhang et al., "Observation of threshold voltage instabilities in AlGaN / GaN MIS HEMTs", Semiconductor Science and Technology, Vol. 29, 2014) describes that the interface state density of SiN / GaN is about 1.0×10 12 to 1.0×10 13 cm -2 Reference 1 describes the addition of a 2.7×10 13 cm -2 The SiON film with a fixed positive charge density is used as a surface protection film, whereby an increase in the surface potential of the semiconductor can be suppressed and current collapse can be reduced.

[0024] When a Si oxide film such as a SiON film or a SiO2 film is used as a surface protection film for a nitride semiconductor layer, the following problems arise. Typically, the surface protection film is provided with an opening (gate opening) for contacting a gate electrode and the nitride semiconductor layer. When a Si compound film is used as a surface protection film, when a gate opening is formed by dry etching, a fluorine-based gas having a high etching selectivity to nitride semiconductors is used as an etching gas. When the surface protection film is a Si oxide film such as a SiON film or a SiO2 film, the etching rate of the surface protection film is lower than the etching rate of the SiN film. Therefore, the increase in etching time leads to an increase in cost. In addition, since the overetching time also increases, the damage to the semiconductor surface also increases.

[0025] As described in JP2008-034438A and JP2007-027284A, it is also conceivable to add a p-type semiconductor layer or the like to reduce the semiconductor surface potential. Alternatively, as described in JP2004-214471A, it is also conceivable to add an electric field control electrode between the gate electrode and the drain electrode. These configurations increase the material cost for forming the semiconductor layer and the electrodes.

[0026] Therefore, an object of the present disclosure is to provide a method for manufacturing a HEMT, and a HEMT capable of suppressing a decrease in the etching rate of a surface protection film and reducing current collapse without increasing material costs.

[0027] First, the embodiments of the present disclosure are listed and described. A method for manufacturing a HEMT according to the embodiments includes the steps of: forming a first SiN film on a surface of a semiconductor stack composed of a nitride semiconductor and including a barrier layer by low-pressure chemical vapor deposition at a first furnace temperature of 700°C or higher and 900°C or lower; forming an interfacial oxide layer on the first SiN film by moisture and oxygen in the furnace at a second furnace temperature of 700°C or higher and 900°C or lower and a furnace pressure of 1 Pa or lower; and forming a second SiN film on the interfacial oxide layer by low-pressure chemical vapor deposition at a third furnace temperature of 700°C or higher and 900°C or lower.

[0028] This manufacturing method includes the steps of forming an interfacial oxide layer after forming a first SiN film on the surface of the semiconductor stack by low-pressure chemical vapor deposition and before forming a second SiN film. In this process, the furnace pressure is set to 1 Pa or less, and while the furnace temperature is maintained within the SiN deposition temperature range, the interfacial oxide layer is formed on the first SiN film by moisture and oxygen in the furnace. The interfacial oxide layer formed at this time is an extremely thin layer with a thickness of, for example, 1 nm or less. Therefore, an extremely thin interfacial oxide layer is provided between the first SiN film and the second SiN film. This interfacial oxide layer has a fixed positive charge, forming an interface state. As a result, current collapse can be reduced by suppressing the semiconductor surface potential. In addition, because the interfacial oxide layer is very thin, the disadvantage of a lower etching rate than that of the SiN film is almost eliminated. Therefore, compared to the case where the surface protective film is a silicon oxide film such as a SiON film or a SiO2 film, the reduction in the etching rate of the surface protective film can be suppressed. In addition, because the interfacial oxide layer can be formed simply by suspending the process of forming the SiN film, material costs are not increased.

[0029] In the above manufacturing method, the step of forming the interface oxide layer may last for at least 30 seconds. In this case, the interface oxide layer can be easily formed.

[0030] In the above manufacturing method, in the steps of forming the first and second SiN films, the flow rate ratio of dichlorosilane gas as a silicon raw material to the flow rate of ammonia gas as a nitrogen raw material can be set to 1:1. In this case, high-quality SiN films can be formed.

[0031] In the above manufacturing method, the second temperature and the third temperature may be equal to the first temperature. In this case, the time required for temperature change can be omitted, and the second SiN film can be formed efficiently.

[0032] The HEMT according to the embodiment includes a semiconductor stack and a surface protection film. The semiconductor stack is composed of a nitride semiconductor and includes a barrier layer. The surface protection film has a first SiN film disposed on the surface of the semiconductor stack and a second SiN film disposed on the first SiN film. The surface protection film further includes an interface oxide layer between the first SiN film and the second SiN film. The interface oxide layer includes more than 5×10 21 atoms / cm 3 of oxygen atoms and more than 1×10 20 atoms / cm 3 of chlorine atoms and has a thickness of 1 nm or less.

[0033] This HEMT has an extremely thin interfacial oxide layer with a thickness of less than 1 nm between the first SiN film and the second SiN film. This interfacial oxide layer has a fixed positive charge to form an interface state. As a result, the current collapse can be reduced by suppressing the surface potential of the semiconductor. In addition, since the interfacial oxide layer is very thin, the disadvantage of a slower etching rate than that of the SiN film is almost non-existent. Therefore, compared with the case where the surface protective film is a silicon oxide film such as a SiON film or a SiO2 film, the reduction in the etching rate of the surface protective film can be suppressed. In addition, since the interfacial oxide layer can be formed simply by suspending the process of forming the SiN film, the material cost does not increase.

[0034] In the above HEMT, the first SiN film and the second SiN film may contain more than 1×10 20 atoms / cm 3 When the first SiN film and the second SiN film are formed by the LP CVD method, the first SiN film and the second SiN film contain such a high concentration of chlorine atoms.

[0035] Specific examples of the HEMT and HEMT manufacturing method of the present disclosure are described below with reference to the accompanying drawings. It should be noted that the present disclosure is not limited to these examples, but is indicated by the claims and is intended to encompass all modifications within the meaning and scope equivalent to the claims. In the following description, identical elements are denoted by identical reference numerals throughout the drawings, and any duplicate descriptions are omitted.

[0036] Figure 1 1 is a cross-sectional view showing an example of a transistor 1 manufactured by a manufacturing method according to an embodiment. Figure 1 As shown, transistor 1 includes a substrate 3, a semiconductor stack 7, a surface protection film 10, a source electrode 21, a drain electrode 22, and a gate electrode 23. Semiconductor stack 7 is composed of a nitride semiconductor. Semiconductor stack 7 includes, in order from substrate 3, a channel layer 4 and a barrier layer 5. Transistor 1 is a HEMT, in which a two-dimensional electron gas (2DEG) is generated at the interface between channel layer 4 and barrier layer 5, forming a channel region in channel layer 4.

[0037] Substrate 3 is a substrate for crystal growth. Substrate 3 can be, for example, a SiC substrate, a GaN substrate, or a sapphire (Al2O3) substrate. In this embodiment, substrate 3 is a SiC substrate. Channel layer 4 is a layer epitaxially grown on substrate 3 and has a channel region where the two-dimensional electron gas described above is generated and drain current flows. Channel layer 4 is composed of a nitride semiconductor. For example, channel layer 4 is a GaN layer. The thickness of channel layer 4 is, for example, 400 nm or more and 2000 nm or less.

[0038] The barrier layer 5 is a layer epitaxially grown on the channel layer 4. The barrier layer 5 is composed of a nitride semiconductor having a greater electron affinity than the channel layer 4. For example, the barrier layer 5 is an AlGaN layer, an InAlN layer, or an InAlGaN layer. The barrier layer 5 may contain impurities. In this embodiment, the barrier layer 5 is an n-type AlGaN layer. The thickness of the barrier layer 5 is, for example, 5 nm or more and 30 nm or less.

[0039] A buffer layer (not shown) may be provided between the substrate 3 and the channel layer 4. The buffer layer is a buffer layer for epitaxially growing the channel layer 4 and the barrier layer 5 on the substrate 3 of a different substrate. The buffer layer is composed of a nitride semiconductor. For example, the buffer layer is an AlN layer. The thickness of the buffer layer is, for example, 10 nm or more and 100 nm or less. A capping layer (not shown) may be provided on the barrier layer 5. The capping layer is a layer epitaxially grown on the barrier layer 5. The capping layer is composed of a nitride semiconductor. For example, the capping layer is a GaN layer. The capping layer may further include impurities. In the present embodiment, the capping layer is an n-type GaN layer. The lower limit of the thickness of the capping layer is, for example, 1.5 nm. The upper limit of the thickness of the capping layer is, for example, 5.0 nm.

[0040] The surface protection film 10 is an insulating film provided on the surface of the semiconductor stack 7 (in this embodiment, provided on the barrier layer 5). The surface protection film 10 includes a SiN film 11 (first SiN film), a SiN film 12 (second SiN film), and an interface oxide layer 13. The SiN film 11 is a film made of silicon nitride (SiN) provided on the surface of the semiconductor stack 7 and in contact with the surface of the semiconductor stack 7. As described later, the SiN film 11 is formed by a low-pressure chemical vapor deposition (LPCVD) method. Since the deposition temperature in the LPCVD method is high temperature, for example, the film quality of the SiN film 11 is denser than that formed by a plasma CVD method. The lower limit value of the thickness of the SiN film 11 is, for example, 10 nm, and the upper limit value is, for example, 100 nm. The SiN film 11 formed by the LPCVD method contains more than 1×10 20 atoms / cm 3 of chlorine atoms.

[0041] The SiN film 12 is a film made of SiN provided on the SiN film 11, similar to the SiN film 11. The SiN film 12 is also formed by the LPCVD method. Therefore, as in the case of the SiN film 11, the film quality of the SiN film 12 is also dense. The lower limit value of the thickness of the SiN film 12 is, for example, 10 nm, and the upper limit value is, for example, 100 nm. In one example, the SiN film 12 has the same film thickness as the SiN film 11. The SiN film 12 formed by the LPCVD method contains more than 1×10 20 atoms / cm 3 of chlorine atoms.

[0042] The interface oxide layer 13 is an extremely thin layer located between the SiN film 11 and the SiN film 12. The interface oxide layer 13 contains more than 5×10 21 atoms / cm 3 of oxygen atoms and more than 1×10 20 atoms / cm 3 The interface oxide layer 13 is a layer having a thickness of only a few atoms, for example, 1 nm or less. As described later, between the completion of the formation of the SiN film 11 and the start of the formation of the SiN film 12, the surface of the SiN film 11 is oxidized by moisture and oxygen contained in the degassing released into the furnace by vacuum exhaust, forming the interface oxide layer 13. In other words, the interface oxide layer 13 contains SiON.

[0043] In this embodiment, the method for measuring the density of oxygen atoms and chlorine atoms is secondary ion mass spectrometry.

[0044] The surface protection film 10 has a gate opening 10a, a source opening 10b, and a drain opening 10c. The gate opening 10a is located between the source opening 10b and the drain opening 10c. The surface of the semiconductor stack 7 is exposed in the gate opening 10a, the source opening 10b, and the drain opening 10c.

[0045] The source electrode 21 closes the source opening 10b and is also provided on the semiconductor stack 7 in contact with the barrier layer 5 through the source opening 10b. The drain electrode 22 closes the drain opening 10c and is also provided on the semiconductor stack 7 in contact with the barrier layer 5 through the drain opening 10c. The source electrode 21 and the drain electrode 22 are ohmic electrodes, for example, electrodes formed by alloying a stacked structure of a titanium (Ti) layer and an aluminum (Al) layer. After further stacking another Ti layer on the Al layer, the source electrode 21 and the drain electrode 22 can be alloyed.

[0046] The gate electrode 23 is arranged in the area on the semiconductor stack 7 between the source electrode 21 and the drain electrode 22, contacts the surface of the SiN film 12, and also contacts the capping layer (or barrier layer 5) of the semiconductor stack 7 through the gate opening 10a. Specifically, the gate electrode 23 is embedded in the gate opening 10a and contacts the semiconductor stack 7 in the gate opening 10a and the sidewalls of the gate opening 10a. The gate electrode 23 includes a material that is in Schottky contact with the semiconductor stack 7, for example, a stacked structure of a nickel (Ni) layer and a gold (Au) layer. In this case, the Ni layer is in Schottky contact with the semiconductor stack 7. As a material that can be in Schottky contact with the semiconductor stack 7, in addition to Ni, Pt (platinum) and the like are also listed. The thickness of the Ni layer is, for example, 200nm, and the thickness of the Au layer is, for example, 700nm.

[0047] Here, reference Figure 2A , 2B, 3A, 3B, 4A and 4B describe a method for manufacturing transistor 1 according to this embodiment. Figure 2A , 2B, 3A, 3B, 4A and 4B are diagrams for explaining a method of manufacturing the transistor 1 according to this embodiment.

[0048] First, if Figure 2A As shown, a semiconductor stack 7 including a channel layer 4 and a barrier layer 5 is formed on a substrate 3. For example, a GaN layer serving as the channel layer 4 and an AlGaN layer serving as the barrier layer 5 are sequentially grown on a SiC substrate using metal organic chemical vapor deposition (MOCVD). Before growing the channel layer 4, an AlN layer serving as a buffer layer may be grown. After growing the barrier layer 5, a GaN layer serving as a cap layer may be further grown.

[0049] Next, the temperature in the furnace for forming the SiN films 11 and 12 is raised to a predetermined temperature. This predetermined temperature is lower than the temperature at which the SiN films 11 and 12 are formed, and is, for example, 500°C or lower. By setting the temperature to 500°C or lower, it is possible to prevent the vapor pressure from falling below the equilibrium vapor pressure of GaN during decompression and suppress the decomposition of GaN. Then, the substrate 3 on which the semiconductor stack 7 is formed is set in a transport device, and as shown in FIG. Figure 2B As shown, it is conveyed into furnace D at atmospheric pressure.

[0050] Subsequently, furnace D is checked for leaks. Specifically, the temperature in furnace D is set to a lower temperature than the furnace temperature during the formation of the SiN film 11. In this state, the furnace pressure in furnace D is evacuated to 1 Pa or less. Then, exhaust is stopped and furnace D is maintained in an airtight state. In this state, leaks are checked for a predetermined period of time. While furnace D is maintained in an airtight state, the pressure in the furnace increases slightly due to degassing generated in furnace D. During this leak check, a pressure rise in furnace D is confirmed, which corresponds to a degassing flow rate of, for example, 0.1 sccm (standard cubic centimeter per minute) or more. The degree of pressure increase in the furnace varies with the volume of furnace D. For example, the degassing flow rate can be estimated based on the pressure increase per hour and the volume of furnace D. The leak check time is, for example, 30 seconds or more and 300 seconds or less, and in one example, 90 seconds. After the leak check, the atmosphere in furnace D is evacuated again to a pressure of 1 Pa or less, and then nitrogen is supplied to furnace D to set the pressure in the furnace to, for example, 100 kPa.

[0051] Then, if Figure 3A As shown, a SiN film 11 is formed in a furnace D, covering the surface of semiconductor stack 7. In this process, SiN film 11 is deposited on semiconductor stack 7 using LPCVD, which uses dichlorosilane gas as the silicon source and ammonia gas as the nitrogen source. Specifically, the temperature in furnace D is first set to a first temperature, for example, between 700°C and 900°C. This temperature is significantly higher than the film formation temperature in plasma CVD and is equal to or lower than the growth temperature of semiconductor stack 7. In one example, the temperature is raised to the first temperature over a period of 10 minutes or longer. In one example, the first temperature is 800°C. After the furnace temperature stabilizes, the pressure in furnace D is evacuated to 1 Pa or less. Thereafter, ammonia is supplied to furnace D to set the pressure therein to a predetermined value. The predetermined pressure is, for example, between 5 Pa and 50 Pa, and in one embodiment, is 20 Pa. Thereafter, the supply of dichlorosilane gas is started to form SiN film 11. The flow rate ratio of the dichlorosilane gas to the ammonia gas is set to, for example, 1:1. When the thickness of the SiN film 11 reaches the target value (e.g., 10 nm), the supply of dichlorosilane and ammonia is stopped, and the formation of the SiN film 11 is stopped. The time required to form the SiN film 11 is, for example, several minutes.

[0052] Subsequently, the atmosphere in the furnace D is evacuated to a pressure of 1 Pa or less. In addition, the temperature in the furnace D is set to a second temperature of 700°C or more and 900°C or less. In this state, the surface of the SiN film 11 is exposed to the atmosphere in the furnace D for at least 30 seconds. At this time, the moisture and oxygen remaining on the furnace wall Da and the like in the furnace D are released into the furnace as degassing to oxidize the surface of the SiN film 11. In addition, during the above-mentioned leakage inspection, the moisture and oxygen released as degassing also oxidize the surface of the SiN film 11. In this way, an interface oxide layer 13 is formed on the SiN film 11 by the moisture and oxygen in the furnace D. The interface oxide layer 13 formed at this time is an extremely thin layer having a thickness of, for example, 1 nm or less. The furnace temperature (second temperature) when the surface of the SiN film 11 is exposed to the atmosphere in the furnace D can be equal to or different from the furnace temperature (first temperature) when the SiN film 11 is formed.

[0053] The constituent material of the surface of the furnace wall Da in the furnace D may include an inorganic oxide such as SiO2. In this case, when vacuum evacuation is performed in the above process, moisture and oxygen are easily released from the furnace wall Da as degassing in the surface. Therefore, an interface oxide layer 13 having a sufficient thickness can be easily formed.

[0054] Next, if Figure 3BAs shown, a SiN film 12 is formed on the SiN film 11 (specifically, on the interface oxide layer 13) in a furnace D. In this process, as in the case of the SiN film 11, the SiN film 12 is deposited on the SiN film 11 using the LPCVD method, which uses dichlorosilane gas and ammonia gas as raw materials. Specifically, the temperature in the furnace D is first set to a third temperature, for example, between 700°C or higher and 900°C or lower. This temperature is significantly higher than the film formation temperature in the plasma CVD method and is equal to or lower than the growth temperature of the semiconductor stack 7. In one example, the temperature is raised to the third temperature over a period of 10 minutes or longer. In one example, the third temperature is 800°C. The furnace temperature (third temperature) when forming the SiN film 12 can be equal to or different from the furnace temperature (first temperature) when forming the SiN film 11 and the furnace temperature (second temperature) when the surface of the SiN film 11 is exposed in the furnace D, or they can be different. After the furnace temperature is stabilized, the furnace pressure within the furnace D is evacuated to 1 Pa or lower. Thereafter, ammonia is supplied to the furnace D to set the pressure in the furnace to a predetermined pressure. The predetermined pressure is, for example, 5 Pa or more and 50 Pa or less, and in one embodiment, 20 Pa. Thereafter, the supply of dichlorosilane gas is started to form the SiN film 12. The ratio of the flow rate of the dichlorosilane gas to the flow rate of the ammonia gas is set to, for example, 1:1. When the thickness of the SiN film 12 reaches the target value (for example, 10 nm), the supply of dichlorosilane and ammonia is stopped, and the film formation of the SiN film 12 is stopped. The time required for the film formation of the SiN film 12 is, for example, several minutes. The film formation time of the SiN film 12 can be equal to, for example, the film formation time of the SiN film 11. In this case, the film thickness of the SiN film 11 and the film thickness of the SiN film 12 become equal to each other.

[0055] Subsequently, the temperature in the furnace D is lowered to a predetermined temperature (e.g., 500°C). Then, to exhaust the chlorine gas generated during film formation, a nitrogen gas circulation purge is performed. Once the chlorine gas has been diluted to a dilution limit (e.g., 2 ppm), the substrate 3 is removed from the furnace D. The chlorine gas concentration can be measured, for example, by a gas detector. Through the above steps, the surface protection film 10 including the SiN film 11 and the SiN film 12 is formed.

[0056] Then, if Figure 4A As shown, a portion of the surface protection film 10 is selectively etched to form a source opening 10b and a drain opening 10c. For example, through a resist mask, the source opening 10b and the drain opening 10c are formed in the surface protection film 10 by selective dry etching. Thereafter, as shown in FIG. Figure 4BAs shown, a source electrode 21 is formed in the source opening 10b, and a drain electrode 22 is formed in the drain opening 10c. In this process, the source electrode 21 and the drain electrode 22 are formed by, for example, vacuum metal deposition and lift-off. The lift-off method is a method of removing unnecessary portions of metal. Afterwards, these electrodes are alloyed by heat treatment to form ohmic electrodes.

[0057] Subsequently, dry etching is selectively performed on the surface protection film 10, thereby forming a gate opening 10a in the surface protection film 10 to expose the semiconductor stack 7. The dry etching is, for example, reactive ion etching (RIE). As an etching gas, for example, a fluorine-based gas is used. For example, one or more of the group consisting of SF6, CF4, CHF3, C3F and C2F6 can be selected as a fluorine-based gas. The RIE equipment can be an inductively coupled plasma (ICP) type. When using a fluorine-based gas (SF6), the reaction pressure is set to a furnace pressure in the range of 2 to 3 Pa (2 Pa in one embodiment), the RF power (ICP power) is set to a range of 50 to 300 W (100 W in one embodiment), and the bias power is set to a range of 5 to 50 W (10 W in one embodiment).

[0058] Subsequently, the gate electrode 23 is formed in the gate opening 10a and on the surface of the SiN film 12 around the gate opening 10a by a lift-off method. In this process, a stacked film of nickel (Ni) and gold (Au) as gate metal is deposited on the semiconductor stack 7 and the SiN film 12 by, for example, a resistance heating type vacuum evaporation method. Through the above steps, a gate electrode 23 is manufactured. Figure 1 The transistor 1 of this embodiment is shown.

[0059] The effects obtained by the transistor 1 and the method for manufacturing the transistor 1 according to the present embodiment have been described above. The manufacturing method of the present embodiment includes the steps of forming an interface oxide layer 13 ( Figure 3A In this process, the surface of the SiN film 11 is exposed to the atmospheric pressure in the furnace D under the above-described conditions, so that the moisture and oxygen remaining on the furnace wall Da and the like in the furnace D are released into the furnace as degassing, and the surface of the SiN film 11 is oxidized to form an extremely thin interfacial oxide layer 13. In this way, the moisture and oxygen in the furnace D form an extremely thin interfacial oxide layer 13 between the SiN film 11 and the SiN film 12. The interfacial oxide layer 13 has a fixed positive charge, forming an interface state. As a result, the current collapse can be reduced by suppressing the semiconductor surface potential.

[0060] Furthermore, because the interfacial oxide layer 13 is very thin, the slower etching rate compared to the SiN film is virtually non-issued in dry etching using fluorine-based gases. For example, in dry etching using SF6, the selectivity ratio between the etching rate of the SiN film and the etching rate of the SiO2 film is approximately 1:4. If the total thickness of the SiN films 11 and 12 is 20 nm and the thickness of the interfacial oxide layer 13 is 0.5 nm, the increase in etching time due to the presence of the interfacial oxide layer 13 is approximately 10%. In dry etching, to prevent etching residue, it is generally necessary to ensure an overetching time of several tens of percent. The increase in etching time due to the presence of the interfacial oxide layer 13 is within the range of typical overetching times. As described above, according to this embodiment, compared to the case where the surface protective film is a silicon oxide film such as SiON or SiO2, the decrease in etching rate due to surface protection can be suppressed, and the need for special additional processes when forming the gate opening 10a can be eliminated.

[0061] In addition, the interface oxide layer 13 of this embodiment can be formed simply by suspending the film formation process of the SiN film. Therefore, there is no need to worry about an increase in material cost.

[0062] Here, Figure 5 Graphs showing the results of analysis by secondary ion mass spectrometry (SIMS) near the surface of transistor 1 produced by the manufacturing method of this embodiment. In the graph, the horizontal axis represents the depth position (in nm), and the vertical axis on the left represents the respective concentrations of oxygen atoms (O) and chlorine atoms (Cl) (in atoms / cc). Graph G11 shows the Cl concentration, and graph G12 shows the O concentration. In the graph, range A1 corresponds to semiconductor stack 7, range A2 corresponds to SiN film 11, and range A3 corresponds to SiN film 12.

[0063] refer to Figure 5 At the interface between SiN film 11 and SiN film 12, the O concentration increases significantly, and a peak is formed. The peak concentration of O is about 1×10 22 atoms / cm 3 This means that an interface oxide layer 13 is formed between the SiN film 11 and the SiN film 12. In addition, since there is no flat portion at the top of the peak, it is estimated that the thickness of the interface oxide layer 13 is 1 nm or less.

[0064] Figure 6 1 is a graph showing the measurement results of the capacitance-voltage (CV) characteristics of the transistor 1 manufactured by the manufacturing method of this embodiment. In this figure, the vertical axis represents the capacitance C (unit: nF / cm 2 ), and the horizontal axis represents the gate voltage V G(Unit: V). In this measurement, the CV characteristics were evaluated by arranging a ring-shaped electrode (cathode) around a circular gate electrode (anode). The structure of the semiconductor stack 7 and the SiN films 11 and 12 is the same as that of the present embodiment. In this figure, graph G21 shows an ideal curve assuming that the charge and interface state density in the SiN films 11 and 12 are zero. Graphs G22 to G26 show the cases where the frequencies of the applied voltage are 100 Hz, 1 kHz, 10 kHz, 100 kHz, and 1 MHz, respectively.

[0065] like Figure 6 As shown, under a negative and large gate voltage, the Fermi level E on the gate electrode F The gate voltage is sufficiently raised to discharge all 2DEG in the channel so that the capacitance C becomes almost zero. When the gate voltage becomes close to -12V, 2DEG accumulates in the channel in turn, and this charge contributes to the capacitance C. When the gate voltage ranges from -10V to +5V, the capacitance C is almost constant without change because the capacitance due to the MIM (metal / insulator / metal) structure using the SiN films 11 and 12 as insulators dominates. When the gate voltage exceeds positive 5V, an interface state between the SiN films 11 and 12 with a long lifetime (for example, several microseconds or longer) appears at the Fermi level E F above, and this charge contributes to the capacitance C, making the capacitance C frequency dependent.

[0066] refer to Figure 6 , it can be seen that, compared with the ideal curve G21, in the transistor 1 according to the present embodiment, the threshold voltage Vth shifts in the negative direction. The shift of the measurement result corresponds to 1.7×10 13 cm -2 Therefore, the effect of suppressing current collapse can be expected.

[0067] As a comparative example, Figure 7 This is a graph showing the results of measuring the CV characteristics of a transistor without an interface oxide layer 13 (i.e., without suspending the formation of the SiN film). In the figure, the vertical axis and the horizontal axis are defined as follows: Figure 6 The same. In addition, the graph G21 is an ideal curve, and the graphs G32 to G36 show the cases where the frequencies of the applied voltage are 100 Hz, 1 kHz, 10 kHz, 100 kHz, and 1 MHz, respectively. Figure 7 , it can be seen that the threshold voltage Vth is shifted in the positive direction compared to the ideal curve G21. Therefore, the effect of suppressing the current collapse cannot be expected.

[0068] Figure 8A is an energy band diagram of the transistor 1 of this embodiment. Figure 9A: This is an energy band diagram of a transistor that does not include the interface oxide layer 13 (i.e., the SiN film formation is not interrupted) as a comparative example. In the figure, range A4 corresponds to the channel layer 4, range A5 corresponds to the barrier layer 5, and range A6 corresponds to the surface protection film 10. Incidentally, assuming that a GaN layer is used as the channel layer 4 and an AlGaN layer is used as the barrier layer 5, 2DEG is indicated by hatching. Referring to these figures, when the interface oxide layer 13 is provided ( Figure 8A ), compared with the case where the interface oxide layer 13 is not provided ( Figure 9A ), the potential at the interface between the SiN film 11 and the AlGaN barrier layer 5 is lower.

[0069] Figure 8B and Figure 9B The energy band diagrams when electrons are trapped in the interface state between the SiN film 11 and the AlGaN barrier layer 5 in the present embodiment and the comparative example are shown in FIG. Figure 8A and Figure 9A ) energy band diagram. Figure 9B In the comparative example shown, the effect of electrons trapped by the interface state increases the potential of the interface between the SiN film 11 and the AlGaN barrier layer 5 (B1 in the figure), and also increases the potential of the interface between the AlGaN barrier layer 5 and the GaN channel layer 4 (B2 in the figure). This reduces the number of electrons in the 2DEG. On the other hand, in Figure 8B In the present embodiment shown, even if the potential of the interface between the SiN film 11 and the AlGaN barrier layer 5 rises due to the influence of electrons trapped in the interface state ( Figure 8B The potential drop caused by the fixed positive charges mitigates this effect (B3 in the figure). Therefore, the effect on the potential of the interface between the AlGaN barrier layer 5 and the GaN channel layer 4 is reduced (B4 in the figure), suppressing the reduction of 2DEG electrons.

[0070] As in this embodiment, the interface oxide layer 13 may contain more than 5×10 21 atoms / cm 3 When oxygen atoms with such a concentration exist in the interface oxide layer 13, it can be expected that more than 8.5×10 12 cm -2 Since the fixed positive charge density is equal to or greater than the interface state density of SiN / GaN described in Reference 2 (about 1.0×10 12 cm -2 to 1.0×10 13 cm -2 ), so the collapse suppression effect can be fully expected.

[0071] As in this embodiment, the process of forming the interface oxide layer 13 is to evacuate the pressure in the furnace D to 1 Pa or less, set the temperature in the furnace D to a second temperature of 700° C. or more and 900° C. or less, and maintain this state for at least 30 seconds. In this case, the interface oxide layer 13 can be easily formed.

[0072] As in this embodiment, before the step of forming the SiN film 11, the furnace temperature is set to a temperature lower than the furnace temperature (first temperature) when the SiN film 11 is deposited in the furnace D. Furthermore, after the pressure in the furnace D is evacuated to 1 Pa or less, a step of making the furnace D airtight and confirming a pressure increase corresponding to a flow rate of more than 0.1 sccm in the furnace (a leak check step) can be performed. Thus, it is confirmed that moisture and oxygen can be sufficiently supplied to the surface of the SiN film 11 as degassing in the process of forming the interface oxide layer 13, thereby improving the yield.

[0073] In the process of forming the SiN films 11 and 12 of this embodiment, the flow rate ratio of dichlorosilane gas as a silicon source to ammonia gas as a nitrogen source can be set to 1: 1. In this case, high-quality SiN films can be formed.

[0074] As in this embodiment, the furnace temperature (second temperature) when forming the interface oxide layer 13 and the furnace temperature (third temperature) when forming the SiN film 12 can be made equal to the furnace temperature (first temperature) when forming the SiN film 11. In this case, the time required for temperature change can be omitted, and the SiN film 12 can be efficiently formed.

[0075] As in this embodiment, the film formation time of the SiN film 11 and the film formation time of the SiN film 12 can be made equal to each other. In this case, the thickness of the SiN film 11 and the thickness of the SiN film 12 are made equal to each other, so that the interface oxide layer 13 can be formed at the middle portion in the thickness direction of the surface protection film 10.

[0076] As in this embodiment, the SiN films 11 and 12 may contain more than 1×10 20 atoms / cm 3 When the SiN films 11 and 12 are formed by the LPCVD method, the SiN films 11 and 12 contain such a high concentration of chlorine atoms. By forming the SiN films 11 and 12 by the LPCVD method, it is relatively easy to control the element composition ratio.

[0077] The manufacturing method and HEMT according to the present disclosure are not limited to the above-described embodiment, and various other modifications may be made. For example, in the above-described embodiment, the film formation time of SiN film 11 and the film formation time of SiN film 12 are made equal to each other, so that the film thicknesses of SiN films 11 and 12 are the same, but the thicknesses of SiN films 11 and 12 may be different from each other. In particular, if SiN film 12 is thicker than SiN film 11, the distance between interface oxide layer 13 and semiconductor multilayer 7 is shortened, and the surface of surface protection film 10 moves away from semiconductor stack 7, so that the effect of fixing positive charges can be more stably achieved.

Claims

1. A method for manufacturing a high electron mobility transistor, comprising the steps of: forming a first SiN film on a surface of a semiconductor stack composed of a nitride semiconductor and including a barrier layer by a low pressure chemical vapor deposition method at a first furnace temperature of 700° C. or higher and 900° C. or lower; forming an interfacial oxide layer having a thickness of 1 nm or less on the first SiN film by moisture and oxygen in the furnace at a second furnace temperature of 700° C. or higher and 900° C. or lower and a furnace pressure of 1 Pa or lower; and A second SiN film is formed on the interface oxide layer by the low pressure chemical vapor deposition method at a third furnace temperature of 700° C. or more and 900° C. or less.

2. The method for manufacturing a high electron mobility transistor according to claim 1, in, The step of forming the interfacial oxide layer lasts for at least 30 seconds.

3. The method for manufacturing a high electron mobility transistor according to claim 1 or 2, in, The steps of forming the first SiN film and forming the second SiN film set the flow rate ratio of dichlorosilane gas as a silicon raw material to the flow rate of ammonia gas as a nitrogen raw material to be 1:

1.

4. The method for manufacturing a high electron mobility transistor according to claim 1 or 2, in, The second furnace temperature and the third furnace temperature are equal to the first furnace temperature.

5. A high electron mobility transistor, comprising: A semiconductor stack composed of a nitride semiconductor and including a barrier layer; as well as a surface protection film including a first SiN film provided on the surface of the semiconductor stack and a second SiN film provided on the first SiN film, wherein the surface protection film comprises an interface oxide layer between the first SiN film and the second SiN film, and Wherein, the interface oxide layer contains more than 5×10 21 atoms / cm 3 of oxygen atoms and more than 1×10 20 atoms / cm 3 of chlorine atoms and has a thickness of 1 nm or less.

6. The high electron mobility transistor according to claim 5, in, The first SiN film and the second SiN film contain more than 1×10 20 atoms / cm 3 of chlorine atoms.

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