A power module and packaging method thereof

Abstract

The present invention discloses a power module and a packaging method thereof, comprising an upper power module and a lower power module; the upper power module comprises a copper-clad ceramic substrate unit, a signal collection area unit and a chip parallel unit; the copper-clad ceramic substrate unit comprises a gate, a source, an auxiliary source and a drain copper-clad ceramic substrate; the drain and source copper-clad ceramic substrates are stacked; the signal collection area unit comprises a gate, a source, an auxiliary source and a drain signal collection area; the signal collection areas are respectively arranged on the copper clad of the corresponding copper-clad ceramic substrate; the chip parallel unit comprises three parallel MOSFET chips; the gate, source, auxiliary source and drain of the MOSFET chip are respectively connected to the corresponding signal collection area; the upper power module and the lower power module have the same structure; the source signal collection area of ​​the upper power module is connected to the drain signal collection area of ​​the lower power module. The present invention can improve the uniformity of current distribution.

Description

Technical Field

[0001] The present invention relates to the technical field of module packaging, and in particular to a power module and a packaging method thereof. Background Art

[0002] In recent years, silicon-based (Si) power semiconductor devices have been approaching the intrinsic limit of their materials due to material limitations, making it difficult to meet the higher demands of power electronic equipment. Wide bandgap power semiconductor devices represented by silicon carbide (SiC) have been gradually applied to high-frequency, high-temperature and high-power power electronics due to their high bandgap width, high critical electric field breakdown field strength and high thermal conductivity. Due to the low current rating of commercial mass-produced silicon carbide metal-oxide semiconductor field-effect transistor (MOSFET) devices, the use of low-cost and high-reliability devices in parallel is an important means to meet the needs of higher power applications.

[0003] Currently, multiple chips are connected in parallel inside power modules to achieve a larger current level. However, as the number of parallel chips increases, factors such as asymmetric circuit layout and common branch impedance coupling effect will lead to uneven distribution of branch stray inductance between parallel chips, which in turn leads to unbalanced current distribution between parallel chips, resulting in unbalanced switching losses and electrical stress. In severe cases, it will cause the device with excessive current distribution to fail, thereby endangering the safety of other parallel devices. Summary of the invention

[0004] The object of the present invention is to provide a power module and a packaging method thereof to solve the problem of uneven distribution of branch stray inductance between parallel chips due to the influence of asymmetric circuit layout and common branch impedance coupling effect in the power module in the prior art.

[0005] To achieve the above object, the present invention provides the following solutions:

[0006] A power module comprises an upper power module and a lower power module;

[0007] The upper power module includes a copper-clad ceramic substrate unit, a signal collection area unit and a chip parallel unit;

[0008] The copper-clad ceramic substrate unit comprises a gate copper-clad ceramic substrate, a source copper-clad ceramic substrate, an auxiliary source copper-clad ceramic substrate and a drain copper-clad ceramic substrate; the drain copper-clad ceramic substrate and the source copper-clad ceramic substrate are stacked;

[0009] The signal collection area unit includes a gate signal collection area, a source signal collection area, an auxiliary source signal collection area and a drain signal collection area; the gate signal collection area is arranged on the copper clad of the gate copper-clad ceramic substrate; the source signal collection area is arranged on the copper clad of the source copper-clad ceramic substrate; the auxiliary source signal collection area is arranged on the copper clad of the auxiliary source copper-clad ceramic substrate; the drain signal collection area is arranged on the copper clad of the drain copper-clad ceramic substrate;

[0010] The chip parallel unit comprises a silicon carbide metal-oxide semiconductor field effect transistor MOSFET chip parallel group; the MOSFET chip parallel group is three MOSFET chips connected in parallel and parallel to each other; the MOSFET chip parallel group is arranged on the drain copper-clad ceramic substrate; the gate of the MOSFET chip parallel group is connected to the gate signal collection area through a bonding wire; the source of the MOSFET chip parallel group is connected to the source signal collection area through a bonding wire; the auxiliary source of the MOSFET chip parallel group is connected to the auxiliary source signal collection area through a bonding wire; the drain of the MOSFET chip parallel group is arranged on the copper clad of the drain copper-clad ceramic substrate;

[0011] The upper power module and the lower power module have the same structure; the source signal collection area of ​​the upper power module is connected to the drain signal collection area of ​​the lower power module.

[0012] Optionally, the chip parallel unit also includes: a silicon carbide diode chip parallel group; the diode chip parallel group is three silicon carbide diode chips connected in parallel and parallel to each other; the diode chip parallel group is arranged on the drain copper-clad ceramic substrate; the anode of the diode chip parallel group is connected to the source of the MOSFET chip parallel group through a bonding wire, the anode of the diode chip parallel group is connected to the source signal collection area through a bonding wire, and the cathode of the diode chip parallel group is arranged on the copper clad of the drain copper-clad ceramic substrate.

[0013] Optionally, it further comprises: a signal terminal unit; the signal terminal unit is a flat structure;

[0014] The signal terminal unit includes a gate drive signal terminal, a source power signal terminal, an auxiliary source drive signal terminal and a drain power signal terminal; the gate drive signal terminal is connected to the gate signal collection area; the source power signal terminal is connected to the source signal collection area; the auxiliary source drive signal terminal is connected to the auxiliary source signal collection area; the drain power signal terminal is connected to the drain signal collection area.

[0015] Optionally, the three MOSFET chips connected in parallel and parallel to each other are spaced equally apart.

[0016] Optionally, the three diode chips connected in parallel and parallel to each other are spaced equally apart.

[0017] A power module packaging method, the power module packaging method is applied to the power module described above, the power module packaging method comprises:

[0018] A silicon carbide MOSFET chip region is arranged on the drain copper-clad ceramic substrate of the upper power module; a gate signal collection region is arranged on the copper clad of the gate copper-clad ceramic substrate of the upper power module; a source signal collection region is arranged on the copper clad of the source copper-clad ceramic substrate of the upper power module; an auxiliary source signal collection region is arranged on the copper clad of the auxiliary source copper-clad ceramic substrate of the upper power module; a drain signal collection region is arranged on the copper clad of the drain copper-clad ceramic substrate of the upper power module; the drain copper-clad ceramic substrate and the source copper-clad ceramic substrate in the upper power module are stacked and placed;

[0019] Welding three parallel and mutually parallel silicon carbide MOSFET chips in the silicon carbide MOSFET chip area of ​​the upper power module;

[0020] The drain of the MOSFET chip of the upper power module is welded on the copper clad of the drain copper-clad ceramic substrate; the gate of the MOSFET chip of the upper power module is connected to the gate signal collection area through a bonding wire; the auxiliary source of the MOSFET chip of the upper power module is connected to the auxiliary source signal collection area through a bonding wire; the source of the MOSFET chip of the upper power module is connected to the source signal collection area through a bonding wire;

[0021] Prepare a lower power module with the same structure as the upper power module; connect the source signal collection area of ​​the upper power module and the drain signal collection area of ​​the lower power module; pour a liquid composite into the interior of the upper power module and the interior of the lower power module, and cure the liquid composite into a thermosetting polymer insulating material under normal temperature or heating conditions.

[0022] Optionally, it also includes:

[0023] A silicon carbide diode chip area is set on the drain copper-clad ceramic substrate of the upper power module; three parallel and mutually parallel silicon carbide diode chips are welded in the silicon carbide diode chip area; the cathode of the diode chip is welded on the copper clad of the drain copper-clad ceramic substrate; the anode of the diode chip is connected to the source of the MOSFET chip through a bonding wire, and the anode of the diode chip is connected to the source signal collection area through a bonding wire.

[0024] Optionally, it also includes:

[0025] The gate drive signal terminal is welded in the gate signal collection area of ​​the upper power module; the source power signal terminal is welded in the source signal collection area of ​​the upper power module; the auxiliary source drive signal terminal is welded in the auxiliary source signal collection area of ​​the upper power module; the drain power signal terminal is welded in the drain signal collection area of ​​the upper power module; the gate drive signal terminal, source power signal terminal, auxiliary source drive signal terminal and drain power signal terminal are all welded into a flat structure.

[0026] Optionally, the three MOSFET chips connected in parallel and parallel to each other are spaced equally apart.

[0027] Optionally, the three diode chips connected in parallel and parallel to each other are spaced equally apart.

[0028] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0029] The present invention discloses a power module and a packaging method thereof. By utilizing the characteristics that the currents of the drain side branch and the source side branch between parallel chips in the power module flow in opposite directions, the drain copper-clad ceramic substrate and the source copper-clad ceramic substrate are placed in layers, thereby increasing the distance-to-width ratio between the two substrates, enhancing the magnetic field coupling between the two substrates, and further enhancing the mutual inductance to offset the branch stray inductance between parallel devices, reducing the distribution difference of the stray inductance of the main power circuit between chips, thereby improving the uniformity of current distribution. In addition, a signal terminal with a flat structure is adopted to reduce the complexity of the signal terminal design and improve the convenience of installation. At the same time, the currents of the drain power signal terminal of the upper power module and the source power signal terminal of the lower power module flow in opposite directions. By utilizing the mutual inductance, the stray inductance of the main power circuit can be further reduced, and the electrical stress of the switching transient power module can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0031] Figure 1 A structural diagram of a power module provided by an embodiment of the present invention;

[0032] Figure 2 A structural diagram of an upper power module of a power module provided in an embodiment of the present invention;

[0033] Figure 3 A top view of an upper power module of a power module provided in an embodiment of the present invention;

[0034] Figure 4 A structural diagram of a lower power module of a power module provided in an embodiment of the present invention;

[0035] Figure 5 A schematic diagram of the principle of a double pulse test circuit for a power module provided by an embodiment of the present invention;

[0036] Figure 6 A schematic diagram of placing a copper-clad ceramic substrate of a power module provided in an embodiment of the present invention;

[0037] Figure 7 A schematic diagram of a chip parallel unit of an upper power module provided in an embodiment of the present invention.

[0038] Explanation of symbols: upper power module 1, lower power module 2, bonding wire 3, auxiliary source drive signal terminal 4, gate drive signal terminal 5, drain power signal terminal 6, source power signal terminal 7, MOSFET chip parallel group 8, diode chip parallel group 9, gate copper-clad ceramic substrate 10, auxiliary source copper-clad ceramic substrate 11, source copper-clad ceramic substrate 12, drain copper-clad ceramic substrate 13, drain signal collection area 14, source signal collection area 15, gate signal collection area 16, auxiliary source signal collection area 17, drain power signal terminal of lower power module 18, drain copper-clad ceramic substrate of lower power module 19 , the drain signal collection area 20 of the lower power module, the diode chip parallel group 21 of the lower power module, the source copper-clad ceramic substrate 22 of the lower power module, the MOSFET chip parallel group 23 of the lower power module, the source signal collection area 24 of the lower power module, the auxiliary source copper-clad ceramic substrate 25 of the lower power module, the auxiliary source drive signal terminal 26 of the lower power module, the auxiliary source signal collection area 27 of the lower power module, the source power signal terminal 28 of the lower power module, the gate copper-clad ceramic substrate 29 of the lower power module, the gate drive signal terminal 30 of the lower power module, and the gate signal collection area 31 of the lower power module. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] The object of the present invention is to provide a power module and a packaging method thereof, which utilizes the characteristic that the currents of the drain side branch and the source side branch between parallel devices in the power module flow in opposite directions, and places the drain copper-clad ceramic substrate and the source copper-clad ceramic substrate in layers to enhance the mutual inductance to offset the stray inductance of the branches between the parallel devices, thereby reducing the distribution difference of the stray inductance of the main power circuit between chips, thereby improving the uniformity of the current distribution.

[0041] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0042] Figure 1 The structure diagram of the power module provided by the embodiment of the present invention is as follows: Figure 1 As shown, a power module comprises an upper power module 1 and a lower power module 2;

[0043] Figure 2A structural diagram of an upper power module of a power module provided in an embodiment of the present invention, Figure 3 A top view of an upper power module of a power module provided in an embodiment of the present invention, Figure 7 A schematic diagram of a chip parallel connection unit of an upper power module provided in an embodiment of the present invention, such as Figure 2 , Figure 3 and Figure 7 As shown, the upper power module 1 includes a copper-clad ceramic substrate unit, a signal collection area unit and a chip parallel unit; the copper-clad ceramic substrate unit includes a gate copper-clad ceramic substrate 10, a source copper-clad ceramic substrate 12, an auxiliary source copper-clad ceramic substrate 11 and a drain copper-clad ceramic substrate 13; the drain copper-clad ceramic substrate 13 and the source copper-clad ceramic substrate 12 are stacked.

[0044] The signal collection area unit includes a gate signal collection area 16, a source signal collection area 15, an auxiliary source signal collection area 17 and a drain signal collection area 14; the gate signal collection area 16 is arranged on the copper clad of the gate copper-clad ceramic substrate 10; the source signal collection area 15 is arranged on the copper clad of the source copper-clad ceramic substrate 12; the auxiliary source signal collection area 17 is arranged on the copper clad of the auxiliary source copper-clad ceramic substrate 11; the drain signal collection area 14 is arranged on the copper clad of the drain copper-clad ceramic substrate 13.

[0045] The chip parallel unit includes a silicon carbide metal-oxide semiconductor field effect transistor MOSFET chip parallel group 8; the MOSFET chip parallel group 8 is three MOSFET chips connected in parallel and parallel to each other; the MOSFET chip parallel group 8 is arranged on the drain copper-clad ceramic substrate 13; the gate of the MOSFET chip parallel group 8 is connected to the gate signal collection area 16 through a bonding wire 3; the source of the MOSFET chip parallel group 8 is connected to the source signal collection area 15 through a bonding wire 3; the auxiliary source of the MOSFET chip parallel group 8 is connected to the auxiliary source signal collection area 17 through a bonding wire 3; the drain of the MOSFET chip parallel group 8 is arranged on the copper clad of the drain copper-clad ceramic substrate 13.

[0046] The upper power module 1 and the lower power module 2 have the same structure; the source signal collection area 15 of the upper power module 1 is connected to the drain signal collection area 20 of the lower power module.

[0047] In practical applications, the chip parallel unit also includes: a silicon carbide diode chip parallel group 9; the diode chip parallel group 9 is three silicon carbide diode chips connected in parallel and parallel to each other; the diode chip parallel group 9 is arranged on the drain copper-clad ceramic substrate 13; the anode of the diode chip parallel group 9 is connected to the source of the MOSFET chip parallel group 8 through a bonding wire 3, the anode of the diode chip parallel group 9 is connected to the source signal collection area 15 through a bonding wire 3, and the cathode of the diode chip parallel group 9 is arranged on the copper clad of the drain copper-clad ceramic substrate 13. The cathode of the diode chip parallel group 9 and the drain of the MOSFET chip parallel group 8 are both arranged on the copper clad of the drain copper-clad ceramic substrate 13, so the cathode of the diode chip parallel group 9 and the drain of the MOSFET chip parallel group 8 are electrically connected. Figure 7 As shown, the three MOSFET drains and the three diode cathodes are all welded on the copper clad of the drain copper clad ceramic substrate 13, so the MOSFET drains and the diode cathodes are connected.

[0048] In practical applications, it also includes: a signal terminal unit; the signal terminal unit is a flat structure;

[0049] The signal terminal unit includes a gate drive signal terminal 5, a source power signal terminal 7, an auxiliary source drive signal terminal 4 and a drain power signal terminal 6; the gate drive signal terminal 5 is connected to the gate signal collection area 16; the source power signal terminal 7 is connected to the source signal collection area 15; the auxiliary source drive signal terminal 4 is connected to the auxiliary source signal collection area 17; the drain power signal terminal 6 is connected to the drain signal collection area 14.

[0050] In practical applications, the three MOSFET chips connected in parallel and parallel to each other are spaced equally apart.

[0051] In practical applications, the three diode chips connected in parallel and parallel to each other are spaced equally apart.

[0052] Figure 4 The structure diagram of the lower power module of the power module provided in the embodiment of the present invention is as follows: Figure 4 As shown, the drain copper-clad ceramic substrate 19 of the lower power module and the source copper-clad ceramic substrate 22 of the lower power module are stacked.

[0053] The gate signal collection area 31 of the lower power module is arranged on the copper clad gate copper-clad ceramic substrate 29 of the lower power module; the source signal collection area 24 of the lower power module is arranged on the copper clad source copper-clad ceramic substrate 22 of the lower power module; the auxiliary source signal collection area 27 of the lower power module is arranged on the copper clad auxiliary source copper-clad ceramic substrate 25 of the lower power module; the drain signal collection area 20 of the lower power module is arranged on the copper clad drain copper-clad ceramic substrate 19 of the lower power module.

[0054] The MOSFET chip parallel group 23 of the lower power module is three MOSFET chips connected in parallel and parallel to each other; the MOSFET chip parallel group 23 of the lower power module is arranged on the drain copper-clad ceramic substrate 19 of the lower power module; the gate of the MOSFET chip parallel group 23 of the lower power module is connected to the gate signal collection area 31 of the lower power module through a bonding wire 3; the source of the MOSFET chip parallel group 23 of the lower power module is connected to the source signal collection area 24 of the lower power module through a bonding wire 3; the auxiliary source of the MOSFET chip parallel group 23 of the lower power module is connected to the auxiliary source signal collection area 27 of the lower power module through a bonding wire 3; the drain of the MOSFET chip parallel group 23 of the lower power module is arranged on the copper clad of the drain copper-clad ceramic substrate 19 of the lower power module. The diode chip parallel group 21 of the lower power module is three silicon carbide diode chips connected in parallel and parallel to each other; the diode chip parallel group 21 of the lower power module is arranged on the drain copper-clad ceramic substrate 19 of the lower power module; the anode of the diode chip parallel group 21 of the lower power module is connected to the source of the MOSFET chip parallel group 23 of the lower power module through the bonding wire 3, the anode of the diode chip parallel group 21 of the lower power module is connected to the source signal collection area 24 of the lower power module through the bonding wire 3, and the cathode of the diode chip parallel group 21 of the lower power module is arranged on the copper clad of the drain copper-clad ceramic substrate 19 of the lower power module. The cathode of the diode chip parallel group 21 of the lower power module and the drain of the MOSFET chip parallel group 23 of the lower power module are both arranged on the copper clad ceramic substrate 19 of the drain of the lower power module, so the cathode of the diode chip parallel group 21 of the lower power module and the drain of the MOSFET chip parallel group 23 of the lower power module are electrically connected.

[0055] The gate drive signal terminal 30 of the lower power module is connected to the gate signal collection area 31 of the lower power module; the source power signal terminal 28 of the lower power module is connected to the source signal collection area 24 of the lower power module; the auxiliary source drive signal terminal 26 of the lower power module is connected to the auxiliary source signal collection area 27 of the lower power module; the drain power signal terminal 18 of the lower power module is connected to the drain signal collection area 20 of the lower power module, and the gate drive signal terminal 30 of the lower power module, the source power signal terminal 28 of the lower power module, the auxiliary source drive signal terminal 26 of the lower power module and the drain power signal terminal 18 of the lower power module are all flat structures. The intervals between the three parallel-connected and mutually parallel MOSFET chips of the lower power module are equal, and the intervals between the three parallel-connected and mutually parallel diode chips of the lower power module are equal.

[0056] A power module packaging method, the power module packaging method is applied to the power module described above, the power module packaging method comprises:

[0057] A silicon carbide MOSFET chip area is arranged on the drain copper-clad ceramic substrate 13 of the upper power module 1; a gate signal collection area 16 is arranged on the copper clad of the gate copper-clad ceramic substrate 10 of the upper power module 1; a source signal collection area 15 is arranged on the copper clad of the source copper-clad ceramic substrate 12 of the upper power module 1; an auxiliary source signal collection area 17 is arranged on the copper clad of the auxiliary source copper-clad ceramic substrate 11 of the upper power module 1; a drain signal collection area 14 is arranged on the copper clad of the drain copper-clad ceramic substrate 13 of the upper power module 1; the drain copper-clad ceramic substrate 13 and the source copper-clad ceramic substrate 12 in the upper power module 1 are placed by stacking.

[0058] Three silicon carbide MOSFET chips connected in parallel and parallel to each other are welded in the silicon carbide MOSFET chip region of the upper power module 1 .

[0059] The gate of the MOSFET chip of the upper power module 1 is connected to the gate signal collection area 16 through a bonding wire 3; the auxiliary source of the MOSFET chip of the upper power module 1 is connected to the auxiliary source signal collection area 17 through a bonding wire 3; the source of the MOSFET chip of the upper power module 1 is connected to the source signal collection area 15 through a bonding wire 3; the drain of the MOSFET chip of the upper power module 1 is welded to the copper clad of the drain copper-clad ceramic substrate 13.

[0060] Prepare a lower power module 2 having the same structure as the upper power module 1; connect the source signal collection area 15 of the upper power module 1 and the drain signal collection area 20 of the lower power module; pour a liquid composite into the interior of the upper power module 1 and the interior of the lower power module 2, and cure the liquid composite into a thermosetting polymer insulating material under normal temperature or heating conditions.

[0061] In practical applications, it also includes:

[0062] A silicon carbide diode chip area is set on the drain copper-clad ceramic substrate 13 of the upper power module 1; three parallel and mutually parallel silicon carbide diode chips are welded in the silicon carbide diode chip area; the anode of the diode chip is connected to the source of the MOSFET chip through a bonding wire 3, the anode of the diode chip is connected to the source signal collection area 15 through a bonding wire 3, and the cathode of the diode chip is welded to the copper clad of the drain copper-clad ceramic substrate 13.

[0063] In practical applications, it also includes:

[0064] The gate drive signal terminal 5 is welded in the gate signal collection area 16 of the upper power module 1; the source power signal terminal 7 is welded in the source signal collection area 15 of the upper power module 1; the auxiliary source drive signal terminal 4 is welded in the auxiliary source signal collection area 17 of the upper power module 1; the drain power signal terminal 6 is welded in the drain signal collection area 14 of the upper power module 1; the gate drive signal terminal 5, the source power signal terminal 7, the auxiliary source drive signal terminal 4 and the drain power signal terminal 6 are all welded into a flat structure.

[0065] In practical applications, the three MOSFET chips connected in parallel and parallel to each other are spaced equally apart.

[0066] In practical applications, the three diode chips connected in parallel and parallel to each other are spaced equally apart.

[0067] The power module utilizes the characteristic that the currents of the drain side branch and the source side branch between the parallel devices flow in opposite directions, and places the drain copper-clad ceramic substrate and the source copper-clad ceramic substrate in layers to increase the distance-to-width ratio between the two substrates, thereby enhancing the magnetic field coupling between the two substrates, and further enhancing the mutual inductance to offset the branch stray inductance between the parallel devices, reducing the distribution difference of the stray inductance of the main power loop between the chips, thereby improving the uniformity of the current distribution.

[0068] The principle of enhancing mutual inductance is as follows: Figure 6As shown, the length of the two conductors is l, the width is w, and the distance between the two conductors is d. The stacking arrangement can increase the distance-to-width ratio v of the two conductors, thereby enhancing their magnetic field coupling and thus enhancing the mutual inductance. The mutual inductance calculation formula is as follows: Among them, the distance-to-width ratio v is the ratio of d to w, μ is the ratio of l to w, and μ0 is the vacuum permeability, which is 4π×10 -7 N / A 2 , t is the thickness of the thin copper sheet or the copper-clad ceramic substrate in the present invention. The thickness of the copper-clad ceramic substrate in the present invention is 0.3048 mm and can be ignored. It is considered that t=0. In the present invention, M is used to represent the mutual inductance, and the formula can be expressed as follows: L M(t＝0) It indicates the mutual inductance between two conductors with a length of l when the copper thickness is negligible, i.e. when t=0. Right now It represents the mutual inductance between two conductors per unit length (l=1m).

[0069] The signal terminals are all flat structures, which reduces the complexity of signal terminal design and improves installation convenience;

[0070] The drain power signal terminal 6 of the upper power module 1 and the source power signal terminal 28 of the lower power module are connected to the positive and negative poles of the power supply respectively. The current flow directions of the drain power signal terminal 6 and the source power signal terminal 28 of the lower power module are opposite. When the current flows in opposite directions, the mutual inductance M is negative, and the parasitic inductance is self-inductance L-mutual inductance M. When the current flows in the same direction, the mutual inductance M is positive, and the parasitic inductance is self-inductance L+mutual inductance M. Therefore, when designing, the opposite current flow direction is selected to utilize the mutual inductance M to reduce the parasitic inductance, further reduce the stray inductance of the main power circuit, and reduce the electrical stress of the switching transient power module.

[0071] By adopting the power module and the packaging method thereof of the present invention, the distribution difference of circuit stray inductance caused by circuit layout mismatch and common branch impedance coupling effect can be reduced, and better parallel current sharing characteristics of silicon carbide MOSFET can be achieved.

[0072] The power module in the present invention also has a good heat dissipation effect. In the general design adopted in the prior art, the chip is located at the bottom layer of the module, and the heat sink can only be added to the bottom layer. However, the present invention adopts a stacked arrangement, and the chip is located at the upper and bottom layers of the power module. In this way, two heat sinks can be added to the upper and bottom layers for heat dissipation. Even if a heat sink is not added, the chip can also be cooled on both sides through the upper and lower substrates, that is, two substrates, which is better than the general single-sided heat dissipation effect.

[0073] Figure 5 A schematic diagram of a double pulse test circuit for a power module according to an embodiment of the present invention is shown in FIG. Figure 5 As shown, UDC It is a DC voltage source used to power the power circuit of the power module. Figure 5 The circuit represented by the upper dotted line in the middle is the power circuit, and the circuit represented by the lower dotted line is the drive circuit. DC L is the busbar capacitor, used to maintain DC voltage stability. load is the load inductor, D is the three parallel silicon carbide diodes in the upper power module 1, which are used for freewheeling when the three parallel silicon carbide MOSFETs in the lower power module 2 are turned off. Q1 is the silicon carbide MOSFET closest to the drain power signal terminal 18 in the lower power module 2, Q2 is the silicon carbide MOSFET in the lower power module of the power module with a moderate distance to the drain power signal terminal 18, Q3 is the silicon carbide MOSFET in the lower power module of the power module with the farthest distance to the drain power signal terminal 18, and L d1 is the stray inductance on the drain side of Q1, L s1 is the source side stray inductance of Q1, L as1 is the auxiliary source stray inductance of Q1, L d2 is the stray inductance on the drain side of Q2, L s2 is the source side stray inductance of Q2, L as2 is the auxiliary source stray inductance of Q2, L d3 is the stray inductance on the drain side of Q3, L s3 is the source side stray inductance of Q3, L as3 is the auxiliary source stray inductance of Q3, L d12 is the stray inductance between the drain-side branches of Q1 and Q2, L d23 is the stray inductance between the drain-side branches of Q2 and Q3, L s12 is the stray inductance between the source branches of Q1 and Q2, L s23 is the stray inductance between the source branches of Q2 and Q3, M 12 is the mutual inductance between the drain side branch and the source side branch of Q1 and Q2, M 23 is the mutual inductance between the drain side branches and the source side branches of Q2 and Q3, i L is the current flowing through the load inductor, i d1 is the current flowing through Q1, i d2 is the current flowing through Q2, i d3 is the current flowing through Q3, i d23 is the current flowing through Q2 and Q3, i as1 is the auxiliary source current flowing through Q1, i as2 is the auxiliary source current flowing through Q2, i as3 is the auxiliary source current flowing through Q3. driver It is the gate drive power supply, used to power the drive circuit, R gis the gate drive resistor. The following is a derivation and proof of how the power module uses mutual inductance to reduce the difference in stray inductance between parallel devices and achieve better parallel current sharing characteristics of silicon carbide MOSFETs.

[0074] The drain current of SiC MOSFET chip can be expressed as i d It can be expressed as follows

[0075]

[0076] where g fs is the transconductance of SiC MOSFET, V gs is the gate-source voltage, V th is the threshold voltage. V gs In the drive circuit, it can be expressed as follows

[0077]

[0078] It can be obtained that the unbalanced current of parallel SiC MOSFET chips can be expressed by the following expression:

[0079]

[0080] The KVL equation for the power circuit and drive circuit can be expressed as follows:

[0081]

[0082] The unbalanced current of parallel SiC MOSFET chips can be expressed by the following expression:

[0083]

[0084] The power module of the present invention utilizes the characteristic that the currents of the drain side branch and the source side branch between the parallel devices flow in opposite directions, and the drain copper-clad ceramic substrate and the source copper-clad ceramic substrate are stacked to increase the distance-to-width ratio between the two substrates, thereby enhancing the magnetic field coupling between the two substrates, thereby enhancing the mutual inductance to offset the branch stray inductance between the parallel devices, reducing the unbalanced current between the parallel devices, and achieving better parallel current sharing characteristics of silicon carbide MOSFETs.

[0085] Of course, the above principle description is not limited to the embodiments of the present invention. The above embodiments and drawings are only used to illustrate the technical solution of the present invention and are not a limitation of the present invention. When n devices are connected in parallel, the drain side branch and the source side branch between the two devices can also be stacked to enhance the mutual inductance and reduce the difference in stray inductance between the parallel devices, thereby reducing the unbalanced current of the parallel devices.

[0086] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for those of ordinary skill in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and scope of application. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A power module, characterized in that: including an upper power module and a lower power module; The upper power module includes a copper-clad ceramic substrate unit, a signal collection area unit and a chip parallel unit; The copper-clad ceramic substrate unit includes a gate copper-clad ceramic substrate, a source copper-clad ceramic substrate, an auxiliary source copper-clad ceramic substrate and a drain copper-clad ceramic substrate; The drain copper-clad ceramic substrate and the source copper-clad ceramic substrate are stacked; The signal collection area unit includes a gate signal collection area, a source signal collection area, an auxiliary source signal collection area and a drain signal collection area; the gate signal collection area is arranged on the copper clad of the gate copper-clad ceramic substrate; the source signal collection area is arranged on the copper clad of the source copper-clad ceramic substrate; the auxiliary source signal collection area is arranged on the copper clad of the auxiliary source copper-clad ceramic substrate; the drain signal collection area is arranged on the copper clad of the drain copper-clad ceramic substrate; The chip parallel unit comprises a silicon carbide metal-oxide semiconductor field effect transistor MOSFET chip parallel group; the MOSFET chip parallel group is three MOSFET chips connected in parallel and parallel to each other; the MOSFET chip parallel group is arranged on the drain copper-clad ceramic substrate; the gate of the MOSFET chip parallel group is connected to the gate signal collection area through a bonding wire; the source of the MOSFET chip parallel group is connected to the source signal collection area through a bonding wire; the auxiliary source of the MOSFET chip parallel group is connected to the auxiliary source signal collection area through a bonding wire; the drain of the MOSFET chip parallel group is arranged on the copper clad of the drain copper-clad ceramic substrate; The upper power module and the lower power module have the same structure; the source signal collection area of ​​the upper power module is connected to the drain signal collection area of ​​the lower power module; The power module packaging method comprises the following steps: setting a silicon carbide MOSFET chip region on a drain copper-clad ceramic substrate of an upper power module; setting a gate signal collection region on the copper-clad gate copper-clad ceramic substrate of the upper power module; setting a source signal collection region on the copper-clad source copper-clad ceramic substrate of the upper power module; setting an auxiliary source signal collection region on the copper-clad auxiliary source copper-clad ceramic substrate of the upper power module; setting a drain signal collection region on the copper-clad drain copper-clad ceramic substrate of the upper power module; placing the drain copper-clad ceramic substrate and the source copper-clad ceramic substrate in the upper power module in a stacked manner; Welding three parallel and mutually parallel silicon carbide MOSFET chips in the silicon carbide MOSFET chip area of ​​the upper power module; Welding the drain of the MOSFET chip of the upper power module to the copper clad of the drain copper-clad ceramic substrate; connecting the gate of the MOSFET chip of the upper power module to the gate signal collection area through a bonding wire; Connecting the auxiliary source of the MOSFET chip of the upper power module to the auxiliary source signal collection area through a bonding wire; connecting the source of the MOSFET chip of the upper power module to the source signal collection area through a bonding wire; Prepare a lower power module with the same structure as the upper power module; connect the source signal collection area of ​​the upper power module and the drain signal collection area of ​​the lower power module; pour a liquid composite into the interior of the upper power module and the interior of the lower power module, and cure the liquid composite into a thermosetting polymer insulating material under normal temperature or heating conditions.

2. The power module according to claim 1, characterized in that: The chip parallel unit also includes: a silicon carbide diode chip parallel group; the diode chip parallel group is three silicon carbide diode chips connected in parallel and parallel to each other; the diode chip parallel group is arranged on the drain copper-clad ceramic substrate; the anode of the diode chip parallel group is connected to the source of the MOSFET chip parallel group through a bonding wire, the anode of the diode chip parallel group is connected to the source signal collection area through a bonding wire, and the cathode of the diode chip parallel group is arranged on the copper clad of the drain copper-clad ceramic substrate.

3. The power module according to claim 2, characterized in that: Also includes: A signal terminal unit; the signal terminal unit is a flat structure; The signal terminal unit includes a gate drive signal terminal, a source power signal terminal, an auxiliary source drive signal terminal and a drain power signal terminal; the gate drive signal terminal is connected to the gate signal collection area; the source power signal terminal is connected to the source signal collection area; the auxiliary source drive signal terminal is connected to the auxiliary source signal collection area; the drain power signal terminal is connected to the drain signal collection area.

4. The power module according to claim 3, characterized in that: The three MOSFET chips connected in parallel are equally spaced from each other.

5. The power module according to claim 4, characterized in that: The three diode chips connected in parallel are equally spaced from each other.

6. A power module packaging method, characterized in that: The power module packaging method is applied to the power module according to any one of claims 1 to 5, and the power module packaging method comprises: A silicon carbide MOSFET chip region is arranged on the drain copper-clad ceramic substrate of the upper power module; a gate signal collection region is arranged on the copper clad of the gate copper-clad ceramic substrate of the upper power module; a source signal collection region is arranged on the copper clad of the source copper-clad ceramic substrate of the upper power module; an auxiliary source signal collection region is arranged on the copper clad of the auxiliary source copper-clad ceramic substrate of the upper power module; a drain signal collection region is arranged on the copper clad of the drain copper-clad ceramic substrate of the upper power module; the drain copper-clad ceramic substrate and the source copper-clad ceramic substrate in the upper power module are stacked and placed; Welding three parallel and mutually parallel silicon carbide MOSFET chips in the silicon carbide MOSFET chip area of ​​the upper power module; The drain of the MOSFET chip of the upper power module is welded on the copper clad of the drain copper-clad ceramic substrate; the gate of the MOSFET chip of the upper power module is connected to the gate signal collection area through a bonding wire; the auxiliary source of the MOSFET chip of the upper power module is connected to the auxiliary source signal collection area through a bonding wire; the source of the MOSFET chip of the upper power module is connected to the source signal collection area through a bonding wire; Prepare a lower power module with the same structure as the upper power module; connect the source signal collection area of ​​the upper power module and the drain signal collection area of ​​the lower power module; pour a liquid composite into the interior of the upper power module and the interior of the lower power module, and cure the liquid composite into a thermosetting polymer insulating material under normal temperature or heating conditions.

7. The power module packaging method according to claim 6, characterized in that: Also includes: A silicon carbide diode chip area is set on the drain copper-clad ceramic substrate of the upper power module; three parallel and mutually parallel silicon carbide diode chips are welded in the silicon carbide diode chip area; the cathode of the diode chip is welded on the copper clad of the drain copper-clad ceramic substrate; the anode of the diode chip is connected to the source of the MOSFET chip through a bonding wire, and the anode of the diode chip is connected to the source signal collection area through a bonding wire.

8. The power module packaging method according to claim 7, characterized in that: Also includes: Welding the gate drive signal terminal at the gate signal collection area of ​​the upper power module; Welding a source power signal terminal at the source signal collection area of ​​the upper power module; welding an auxiliary source drive signal terminal at the auxiliary source signal collection area of ​​the upper power module; welding a drain power signal terminal at the drain signal collection area of ​​the upper power module; The gate drive signal terminal, the source power signal terminal, the auxiliary source drive signal terminal and the drain power signal terminal are all welded into a flat structure.

9. The power module packaging method according to claim 8, characterized in that: The three MOSFET chips connected in parallel are equally spaced from each other.

10. The power module packaging method according to claim 9, characterized in that: The three diode chips connected in parallel are equally spaced from each other.

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