Drive circuit

Abstract

The driving circuit includes: a set-side level shift circuit, which outputs a level shift completion set signal from a set-side output node; a reset-side level shift circuit, which outputs a level shift completion reset signal from a reset-side output node; a shielding signal generating circuit, which outputs a shielding signal during a period shorter than an output period of the level shift completion set signal and an output period of the level shift completion reset signal when the voltage of any one of the set-side output node and the reset-side output node changes; and a control circuit, which outputs a driving signal in a state before the shielding signal is input to the power device during a period in which the shielding signal is input, outputs a driving signal that turns off the power device when a level shift completion reset signal is input after the shielding signal is input, and outputs a driving signal that turns on the power device when a level shift completion set signal is input after the shielding signal is input.

Description

Technical Field

[0001] The invention relates to a driving circuit for driving a power device. Background Art

[0002] As disclosed in Patent Documents 1 and 2, a half-bridge circuit has first and second power switching elements connected in series between a high potential terminal and a low potential terminal of a power supply, and a node between the first power switching element and the second power switching element is connected to a load such as a motor. The first power switching element is turned on and off, and the second power switching element is turned on and off complementarily to the first power switching element, thereby driving the load. The second power switching element is turned on and off by being driven by a low-side control circuit, and the low-side control circuit operates with the potential of the low potential terminal of the power supply as a reference potential. The first power switching element is turned on and off by being driven by a high-side control circuit, and the high-side control circuit operates with the potential of the node between the first power switching element and the second power switching element as a reference potential.

[0003] A level shift circuit is connected to the front stage of the high-side control circuit. The level shift circuit, for example, inverts and shifts the DC levels of the set signal and the reset signal, outputs a level shift-completed set signal from an output node on the set side, and outputs a level shift-completed reset signal from an output node on the reset side. The high-side control circuit includes a control circuit that turns on and off the first power switch element according to a signal based on the levels of the level shift-completed set signal and the level shift-completed reset signal output by the level shift circuit.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2013-179501

[0007] Patent Document 2: Japanese Patent Application Publication No. 2011-139423 Summary of the invention

[0008] Technical problem to be solved by the invention

[0009] However, due to external noise such as three-phase current, the voltage of the set output node and the voltage of the reset output node of the level shift circuit may change with a delay compared to the other. In this case, the control circuit malfunctions and cannot normally turn on and off the first power switch element.

[0010] The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to allow a driving circuit to operate normally when noise occurs.

[0011] Technical solutions to technical problems

[0012] The main invention for achieving the above-mentioned purpose is a driving circuit, which includes: a set-side level shift circuit, which performs level shifting on a pulse-shaped set signal and outputs a pulse-shaped level shifted set signal from a set-side output node; a reset-side level shift circuit, which performs level shifting on a pulse-shaped reset signal and outputs a pulse-shaped level shifted reset signal from a reset-side output node; and a shielding signal generating circuit, which generates a shielding signal when the voltage of any one of the set-side output node and the reset-side output node changes. A pulse-shaped shielding signal is output during a period shorter than a first period for outputting the level shift completion set signal and a second period for outputting the level shift completion reset signal; and a control circuit, which outputs a drive signal in a state before the shielding signal is input to a power device during the period when the shielding signal is input, outputs the drive signal for turning off the power device when the level shift completion reset signal is input after the shielding signal is input, and outputs the drive signal for turning on the power device when the level shift completion set signal is input after the shielding signal is input.

[0013] Effects of the Invention

[0014] According to the embodiment of the present invention, when noise is generated, malfunction of the driving circuit can be prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a diagram showing the configuration of the drive circuit according to the first embodiment together with an output circuit, a load, and a power supply.

[0016] Figure 2 It is a diagram for explaining the configuration of the mask signal generating circuit and the control circuit according to the first embodiment.

[0017] Figure 3 It is a timing diagram showing the waveforms of the high-side input signal, the low-side input signal, the set signal, the level shift completion set signal, the reset signal, the level shift completion reset signal, the output signal of the inverter on the set side, the output signal of the inverter on the reset side, the shielding signal on the set side, the shielding signal on the reset side, the output of the protection circuit, the output signal of the latch circuit, and the drive signal.

[0018] Figure 4 It is a timing chart showing the waveform of each signal when external noise occurs.

[0019] Figure 5 It is a timing chart showing the waveform of each signal when external noise occurs.

[0020] Figure 6 It is a timing diagram showing the waveforms of the high-side input signal, the low-side input signal, the set signal, the level shift completion set signal, the reset signal, the level shift completion reset signal, the output signal of the inverter on the set side, the output signal of the inverter on the reset side, the shielding signal on the set side, the shielding signal on the reset side, the output of the protection circuit, the output signal of the latch circuit, and the drive signal in the modified example.

[0021] Figure 7 It is a diagram for explaining the configuration of a mask signal generating circuit and a control circuit according to a modified example.

[0022] Figure 8 It is a timing chart showing the waveforms of each signal when external noise occurs in the modification example.

[0023] Fig. 9 It is a timing chart showing the waveforms of each signal when external noise occurs in the modification example.

[0024] Fig.10 This is a diagram showing the configuration of a drive circuit according to a second embodiment together with an output circuit, a load, and a power supply.

[0025] Fig.11 It is a diagram for explaining the configuration of a differential pulse generating circuit, a pull-down circuit, a pull-up circuit, and a protection circuit according to the second embodiment.

[0026] Fig.12 It is a timing diagram showing the waveforms of a set signal, a level shift completion set signal, a reset signal, a level shift completion reset signal, an output signal of a NAND gate, an output signal of an inverter, a shielding signal, an output signal of an OR gate, an output of a protection circuit, an output signal of a latch, and a drive signal.

[0027] Fig.13 It is a timing chart showing the waveforms of each signal when external noise occurs in the second embodiment.

[0028] Fig.14 It is a timing chart showing the waveforms of each signal when external noise occurs in the second embodiment. DETAILED DESCRIPTION

[0029] Cross-reference to related applications

[0030] This application claims priority based on Japanese Patent Application No. 2019-066332 filed on March 29, 2019, and cites the contents thereof.

[0031] At least the following matters will become clear from the description of this specification and the accompanying drawings.

[0032] =====First Embodiment======

[0033] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, since various technically preferred limitations are added to the embodiments described below to implement the present invention, the scope of the present invention is not limited to the following embodiments and the illustrated examples.

[0034] <<<1. Overview of drive circuit and output circuit>>>

[0035] Figure 1 is a diagram showing a drive circuit 1 , an output circuit 5 , and a load 9 . Figure 2 It is a diagram for explaining the configuration of the differential pulse generating circuits 23 a and 23 b , the protection circuit 24 , and the latch circuit 25 . Figure 3 It is a timing diagram showing the relationship between input signal HIN, input signal LIN, set signal set, level shift completion set signal setdrn, reset signal res, level shift completion reset signal resdrn, output signal S, output signal R, mask signal SMASK, mask signal RMASK, output PO, output signal RO and drive signal HO. Figure 3 The waveforms of the signals shown periodically repeat changes so as to transition from the state at time t1 to the state at time t1 via the state at time t6 .

[0036] Here, the set signal set and the reset signal res are output signals of the pulse generating circuit 12. The level shift completion set signal setdrn is the output signal of the level shift circuit 21a on the set side. The level shift completion reset signal resdrn is the output signal of the level shift circuit 21b on the reset side. The output signal S is the output signal of the inverter 232a. The output signal R is the output signal of the inverter 232b. The mask signal SMASK is the output signal of the mask signal generating circuit 23, and is the output signal of the differential pulse generating circuit 23a on the set side. The mask signal RMASK is the output signal of the mask signal generating circuit 23, and is the output signal of the differential pulse generating circuit 23b on the reset side. The output PO is the output of the protection circuit 24. The output signal RO is the output signal of the latch circuit 25.

[0037] The drive circuit 1 is operated by inputting a high-side input signal HIN and a low-side input signal LIN from a microcomputer (not shown) to the drive circuit 1. The input signal HIN and the input signal LIN are logic input signals that repeatedly switch between a first logic level and a second logic level. Here, the first logic level refers to a low level, and the second logic level refers to a high level.

[0038] The input signal HIN and the input signal LIN are in a complementary relationship. That is, when the input signal HIN is at a high level, the input signal LIN is at a low level, and when the input signal HIN is at a low level, the input signal LIN is at a high level. In addition, the input signal HIN and the input signal LIN also include controls that are both controlled to a low level.

[0039] When the driving circuit 1 drives the output circuit 5 based on the high-side input signal HIN and the low-side input signal LIN, the output circuit 5 alternately and repeatedly switches the load 9 between a voltage application state in which the voltage of the high-voltage DC power supply 8 is applied and a ground voltage application state in which a ground voltage is applied.

[0040] The output circuit 5 is configured to include power switching elements 51 and 52 constituting a half bridge. The power switching elements 51 and 52 are N-channel power MOSFETs, but may also be power devices such as IGBTs or bipolar transistors. The power switching elements 51 and 52 are connected in series between the high potential output terminal and the low potential output terminal of the high voltage DC power supply 8. The node N1 between the power switching element 52 and the low potential output terminal of the high voltage DC power supply 8 is grounded via the reference potential wiring L1 on the low side, and the node N1 is used as the reference potential on the low side. The node N2 between the power switching element 51 and the power switching element 52 is connected to one end of the load 9. The other end of the load 9 is grounded, and the other end of the load 9 is used as the reference potential. The node N2 is connected to the low potential output terminal of the high side DC power supply 6 via the reference potential wiring L2 on the high side. The high potential output terminal of the high side DC power supply 6 is connected to the high potential wiring L7, and the output voltage of the high side DC power supply 6 based on the potential of the node N2 is applied to the high potential wiring L7.

[0041] The drive circuit 1 generates a logic drive signal HO based on the input signal HIN of the high side, and outputs the drive signal HO to the gate of the power switch element 51. Therefore, when the drive signal HO is at a high level, the power switch element 51 is turned on, and when the drive signal HO is at a low level, the power switch element 51 is turned off. In addition, the drive circuit 1 turns on and off the power switch element 52 complementarily with the power switch element 51 based on the input signal LIN of the low side. When the power switch element 51 is turned on and the power switch element 52 is turned off, the potential of the node N2 becomes the output voltage of the high-voltage DC power supply 8, and the load 9 becomes a voltage application state. When the power switch element 51 is turned off and the power switch element 52 is turned on, the potential of the node N2 becomes a reference potential, and the load 9 becomes a ground voltage application state. Therefore, the potential of the node N2 can vary from the reference potential to the output voltage of the high-voltage DC power supply 8. Here, the load 9 is switched from the voltage application state to the ground voltage application state after a dead time, and during the dead time, the two power switch elements 51 and 52 are turned off together, thereby preventing a short circuit and a through current of the high-voltage DC power supply 8. Similarly, the load 9 is switched from the ground voltage application state to the voltage application state after a dead time.

[0042] <<<2. Structure of driving circuit>>>

[0043] The drive circuit 1 includes a front-stage circuit 10 , a rear-stage circuit 20 , and a low-side control circuit 40 .

[0044] The drive circuit 1 is built in a chip. However, the front stage circuit 10 and the rear stage circuit 20 can be built in a common chip, and the low side control circuit 40 can be built in another chip. Or, the front stage circuit 10 and the low side control circuit 40 can be built in a common chip, and the rear stage circuit 20 can be built in another chip. The rear stage circuit 20 and the low side control circuit 40 can be built in a common chip, and the front stage circuit 10 can be built in another chip. Or, the front stage circuit 10, the rear stage circuit 20 and the low side control circuit 40 can be built in respective chips.

[0045] The front stage circuit 10 and the low side control circuit 40 are low voltage system circuits, and the rear stage circuit 20 is a high voltage system circuit. That is, the front stage circuit 10 and the low side control circuit 40 operate at low voltage, and the rear stage circuit 20 operates at high voltage.

[0046] The front-stage circuit 10 is configured to include an input circuit 11 and a pulse generating circuit 12. The rear-stage circuit 20 is configured to include a level shift circuit 21, a mask signal generating circuit 23, a control circuit 27, and diodes 28 and 29. The mask signal generating circuit 23 is configured to include a differential pulse generating circuit 23a on the set side and a differential pulse generating circuit 23b on the reset side. The control circuit 27 is configured to include a protection circuit 24 as a latch control circuit, a latch circuit 25, and a high-side driver 26 as a drive signal output circuit.

[0047] <<<2-1. Low-side control circuit>>>

[0048] The low-side control circuit 40 is powered from the DC power supply 7 of the low side, and an input signal LIN is input from the microcomputer. The low-side control circuit 40 outputs a drive signal to the power switch element 52 based on the input signal LIN to turn on and off the power switch element 52 complementarily to the power switch element 51. The drive signal output by the low-side control circuit 40 is delayed relative to the input signal LIN. The delay time in the low-side control circuit 40 is designed according to the delay time in the delay circuit 231a, 231b described later (i.e., the period during which the shielding signal SMASK and the shielding signal RMASK are at a high level).

[0049] <<<2-2. Input circuit>>>

[0050] The input circuit 11 has a comparator that determines whether the input signal HIN is at a high level or a low level by comparing the input signal HIN with a reference voltage, and a noise filter that outputs the output signal of the comparator after removing noise from it. When the input signal HIN is at a high level, the output signal of the input circuit 11 is at a high level, and when the input signal HIN is at a low level, the output signal of the input circuit 11 is at a low level. Since the noise filter is, for example, a low-pass filter, a signal delay is generated in the input circuit 11, and the output signal of the input circuit 11 is delayed relative to the input signal HIN.

[0051] <<<2-3. Pulse generation circuit>>>

[0052] When the output signal of the input circuit 11 rises from a low level to a high level, the pulse generating circuit 12 outputs a set signal set (see Figure 3 ). In addition, when the output signal of the input circuit 11 drops from a high level to a low level, the pulse generating circuit 12 outputs a reset signal res that changes in a high-level pulse shape (see Figure 3 ). The timing at which the set signal set is at a high level is different from the timing at which the reset signal res is at a high level. The set signal set and the reset signal res are input to the level shift circuit 21 of the subsequent stage circuit 20.

[0053] <<<2-4. Level shift circuit and clamping diode>>>

[0054] like Figure 1 As shown in FIG. 1 , the level shift circuit 21 is configured to include a level shift circuit 21a on the set side and a level shift circuit 21b on the reset side. The level shift circuit 21a on the set side inverts the set signal set output by the pulse generating circuit 12, shifts the DC level of the set signal set, and uses it as a level shifted set signal setdrn (see FIG. 1 ). Figure 3 ) is output to the mask signal generating circuit 23 and the control circuit 27. The level shift circuit 21b on the reset side inverts the reset signal res output by the pulse generating circuit 12, shifts the DC level of the set signal set, and uses it as the level shifted reset signal resdrn (see Figure 3 ) is output to the shielding signal generating circuit 23 and the control circuit 27.

[0055] The level shift circuit 21a on the set side is configured to include a level shift switch element 211a on the set side and a resistor 212a. The level shift circuit 21b on the reset side is configured to include a level shift switch element 211b on the reset side and a resistor 212b.

[0056] The level shift switch elements 211 a and 211 b are high-voltage N-channel MOSFETs, but may be IGBBs or bipolar transistors.

[0057] The resistor 212a and the level shift switch element 211a are connected in series between the high potential wiring L7 and the low-side reference potential wiring L1. That is, the drain of the level shift switch element 211a is connected to the high potential wiring L7 via the resistor 212a, and the source of the level shift switch element 211a is connected to the reference potential wiring L1, and the voltage of the source is set to the reference potential.

[0058] The resistor 212b and the level shift switch element 211b are connected in series between the high potential wiring L7 and the low-side reference potential wiring L1. That is, the drain of the level shift switch element 211b is connected to the high potential wiring L7 via the resistor 212b, and the source of the level shift switch element 211b is connected to the reference potential wiring L1, and the voltage of the source is set to the reference potential.

[0059] The anode of the diode 28 is connected to the reference potential wiring L2, and the cathode of the diode 28 is connected to the node N5 between the resistor 212a and the level shift switch element 211a. Since the diode 28 clamps the potential of the node N5 to the potential of the reference potential wiring L2, the voltage of the node N5 is based on the potential of the reference potential wiring L2. Therefore, an overvoltage is not input to the shielding signal generating circuit 23 and the control circuit 27.

[0060] The anode of the diode 29 is connected to the reference potential wiring L2, and the cathode of the diode 29 is connected to the node N6 between the resistor 212b and the level shift switch element 211b. Since the diode 29 clamps the potential of the node N6 to the potential of the reference potential wiring L2, the voltage of the node N6 is based on the potential of the reference potential wiring L2. Therefore, the overvoltage is not input to the shielding signal generating circuit 23 and the control circuit 27.

[0061] The gate of the level shift switch element 211a is connected to the set side output terminal of the pulse generating circuit 12. The set signal set output from the pulse generating circuit 12 is input to the gate of the level shift switch element 211a. The level shift switch element 211a is turned on and off based on the set signal set. When the level shift switch element 211a is turned off, the drain voltage (the voltage of the node N5) is pulled up by the high-side DC power supply 6 to become a high level. When the level shift switch element 211a is turned on, the voltage of the node N5 is pulled down to a low level by grounding. The voltage of the node N5 is input to the shielding signal generating circuit 23 and the control circuit 27 as the level shift completion set signal setdrn.

[0062] The gate of the level shift switch element 211b is connected to the reset side output terminal of the pulse generating circuit 12. The reset signal res output from the pulse generating circuit 12 is input to the gate of the level shift switch element 211b. The level shift switch element 211b is turned on and off based on the reset signal res. When the level shift switch element 211b is turned off, the voltage of the node N6 is pulled up by the high side DC power supply 6 and becomes a high level. When the level shift switch element 211b is turned on, the voltage of the node N6 is pulled down by the ground and becomes a low level. The voltage of the node N6 is input to the shielding signal generating circuit 23 and the control circuit 27 as the level shift completion reset signal resdrn.

[0063] The timing when the set signal set is at a high level is different from the timing when the reset signal res is at a high level. Therefore, the timing when the level shift completion set signal setdrn is at a low level is different from the timing when the level shift completion reset signal resdrn is at a low level. Figure 3, the timing when the level shift completion set signal setdrn falls is time t1, the timing when the level shift completion set signal setdrn rises is time t3, the timing when the level shift completion reset signal resdrn falls is time t4, and the timing when the level shift completion reset signal resdrn rises is time t6.

[0064] <<<2-5. Shield signal generation circuit>>>

[0065] The mask signal generating circuit 23 generates a set-side mask signal SMASK that varies in a pulse shape according to a change in the voltage of the node N5 , for example, a falling change of the level-shifted set signal setdrn, and outputs it to the protection circuit 24 of the control circuit 27 .

[0066] The mask signal generating circuit 23 generates a reset-side mask signal RMASK that varies in a pulse shape according to a change in the voltage of the node N6 , for example, a falling change of the level-shifted reset signal resdrn, and outputs it to the protection circuit 24 of the control circuit 27 .

[0067] Next, the differential pulse generating circuit 23a of the mask signal generating circuit 23 and the differential pulse generating circuit 23b on the reset side are described. In addition, for the sake of convenience, here, as an example of the voltage change of the node N5, the differential pulse generating circuit 23a is described when the falling edge of the level shift completion setting signal setdrn changes. In addition, as an example of the voltage change of the node N6, the differential pulse generating circuit 23b is described when the falling edge of the level shift completion setting signal setdrn changes.

[0068] <<<2-5-1. Differential pulse generation circuit on the set side>>>

[0069] The differential pulse generating circuit 23a on the set side generates a mask signal SMASK (see FIG. 1 ) which changes in a pulse shape according to the falling change of the level shift completed set signal setdrn. Figure 3 ), and outputs the mask signal SMASK to the protection circuit 24 of the control circuit 27. Here, the period during which the differential pulse generating circuit 23a sets the mask signal SMASK to a high level is shorter than the period during which the pulse generating circuit 12 sets the set signal set to a high level (the period during which the level shift completion set signal setdrn is a low level).

[0070] The differential pulse generating circuit 23 a on the set side is configured to include a delay circuit 231 a on the set side, an inverter 232 a , and a NOR gate 233 a .

[0071] The level shift completion setting signal setdrn is input to the delay circuit 231a and the NOR gate 233a. The delay circuit 231a delays the level shift completion setting signal setdrn and outputs it to the inverter 232a. The inverter 232a inverts the output signal of the delay circuit 231a and outputs it to the NOR gate 233a. The NOR gate 233a calculates the logical negation of the output signal S of the inverter 232a and the level shift completion setting signal setdrn, and outputs the mask signal SMASK indicating the logical negation to the protection circuit 24. Here, the output signal S of the inverter 232a is a signal obtained by delaying and inverting the level shift completion setting signal setdrn. Therefore, during the period Ts from the time t1 when the level shift completion setting signal setdrn falls to the time t2 when the output signal S of the inverter 232a rises, the mask signal SMASK is at a high level.

[0072] The delay time in the delay circuit 231a, that is, the period Ts during which the mask signal SMASK is at the high level, is shorter than the period during which the pulse generating circuit 12 sets the set signal set to the high level (the period during which the level shift completion set signal setdrn is at the low level).

[0073] <<<2-5-2. Differential pulse generation circuit on the reset side>>>

[0074] The differential pulse generating circuit 23b on the reset side generates a reset side mask signal RMASK (see FIG. 1 ) that varies in a pulse shape according to the falling change of the level shift completed reset signal resdrn. Figure 3 ), and outputs the mask signal RMASK to the protection circuit 24. Here, the period during which the differential pulse generating circuit 23b sets the mask signal RMASK to a high level is shorter than the period during which the pulse generating circuit 12 sets the reset signal res to a high level (the period during which the level shifting completion reset signal resdrn is a low level).

[0075] The differential pulse generating circuit 23 b on the reset side is configured to include a delay circuit 231 b on the reset side, an inverter 232 b , and a NOR gate 233 b .

[0076] The level shift completion reset signal resdrn is input to the delay circuit 231b and the NOR gate 233b. The delay circuit 231b delays the level shift completion reset signal resdrn and outputs it to the inverter 232b. The inverter 232b inverts the output signal of the delay circuit 231b and outputs it to the NOR gate 233b. The NOR gate 233b calculates the logical negation of the output signal R of the inverter 232b and the level shift completion reset signal resdrn, and outputs the mask signal RMASK indicating the logical negation to the protection circuit 24 of the control circuit 27. Here, the output signal R of the inverter 232b is a signal obtained by delaying and inverting the level shift completion reset signal resdrn. Therefore, during the period Tr from the time t4 when the level shift completion reset signal resdrn falls to the time t5 when the output signal R of the inverter 232b rises, the mask signal RMASK is at a high level.

[0077] The delay time in the delay circuit 231b, that is, the period Tr during which the mask signal RMASK is at the high level, is shorter than the period during which the pulse generating circuit 12 sets the reset signal res to the high level (the period during which the level shift completion reset signal resdrn is at the low level).

[0078] In addition, a delay time adjustment unit may be provided in the delay circuits 231a and 231b, and the delay time adjustment unit may be processed to adjust the delay time of the delay circuits 231a and 231b according to the use, purpose, use environment, etc. of the driving circuit 1.

[0079] <<<2-6. Control circuit>>>

[0080] The control circuit 27 generates a drive signal HO based on the level shift completion set signal setdrn, the level shift completion reset signal resdrn, the mask signal SMASK, and the mask signal RMASK, and outputs the drive signal HO to the gate of the power switch element 51 .

[0081] Specifically, when the high-level shielding signal SMASK is input to the control circuit 27 during the period from time t1 to time t2, the control circuit 27 maintains the level of the drive signal HO at the level before time t1, that is, the low level during the period. In addition, after the high-level shielding signal SMASK is input to the control circuit 27 during the period from time t1 to time t2, when the low-level level shift completion setting signal setdrn is input to the control circuit 27 at time t2, the control circuit 27 sets the drive signal HO to the high level to turn on the power switch element 51. In addition, when the high-level shift completion setting signal setdrn and the high-level shift completion reset signal resdrn as well as the low-level shielding signal SMASK and the low-level shielding signal RMASK are input to the control circuit 27 during the period from time t3 to time t4, the control circuit 27 maintains the level of the drive signal HO at the level before time t3, that is, the high level during the period. When the high-level mask signal RMASK is input to the control circuit 27 during the period from time t4 to time t5, the control circuit 27 maintains the level of the drive signal HO at the level before time t4, that is, at the high level during the period. In addition, after the high-level mask signal RMASK is input to the control circuit 27 during the period from time t4 to time t5, when the low-level level shift completion reset signal resdrn is input to the control circuit 27 at time t5, the control circuit 27 sets the drive signal HO to the low level to turn off the power switch element 51. When the high-level shift completion set signal setdrn and the high-level shift completion reset signal resdrn and the low-level mask signal SMASK and the mask signal RMASK are input to the control circuit 27 during the period from time t6 to time t1, the control circuit 27 maintains the level of the drive signal HO at the level before time t6, that is, at the low level during the period.

[0082] The control circuit 27 includes a protection circuit 24 , a latch circuit 25 , and a high-side driver 26 .

[0083] <<<2-6-1. Protection circuit>>>

[0084] The voltage of the high-side DC power supply 6 based on the potential of the reference potential wiring L2 is provided to the protection circuit 24. The protection circuit 24 determines the state of the output PO to the latch circuit 25 according to the level shift completion set signal setdrn, the level shift completion reset signal resdrn, the mask signal SMASK, and the mask signal RMASK. Specifically, the protection circuit 24 puts the output PO in a high impedance state during the input of the high-level mask signal SMASK or the high-level mask signal RMASK. The period of this state is Figure 3The period from time t1 to time t2 and the period from time t4 to time t5 are shown.

[0085] In addition, after inputting a high-level shielding signal SMASK or a high-level shielding signal RMASK, the protection circuit 24 outputs a signal corresponding to the level shift completion set signal setdrn and the level shift completion reset signal resdrn. Specifically, when the level shift completion set signal setdrn is at a low level and the level shift completion reset signal resdrn is at a high level, the protection circuit 24 outputs a high-level signal. The period of this state is the period from time t2 to time t3. In addition, when the level shift completion set signal setdrn is at a high level and the level shift completion reset signal resdrn is at a low level, the protection circuit 24 outputs a low-level signal. The period of this state is the period from time t5 to time t6. In addition, when the level shift completion set signal setdrn and the level shift completion reset signal resdrn are both at a high level, the protection circuit 24 puts the output PO in a high impedance state. The period of this state is the period from time t3 to time t4 and the period from time t6 to time t1. In addition, due to Figure 3 The waveforms of the level shift completion set signal setdrn and the level shift completion reset signal resdrn shown are normal waveforms, so Figure 3 Although not shown in the figure, if the level shift completion set signal setdrn and the level shift completion reset signal resdrn are both at a low level due to the influence of noise or the like, the protection circuit 24 puts the output PO in a high impedance state.

[0086] The protection circuit 24 includes inverters 241 and 242 and switching elements 243 to 248 .

[0087] The switch elements 243 to 245 are P-channel MOSFETs, and the switch elements 246 to 248 are N-channel MOSFETs. The switch elements 243 to 248 are arranged from the high potential wiring L7 to the reference potential wiring L2, and are connected in series between the high potential wiring L7 and the reference potential wiring L2. Figure 2 In the example, the source of the switch element 243 is connected to the high potential wiring L7, the drain of the switch element 243 is connected to the source of the switch element 244, the drain of the switch element 244 is connected to the source of the switch element 245, the drain of the switch element 245 is connected to the drain of the switch element 246, the source of the switch element 246 is connected to the drain of the switch element 247, the source of the switch element 247 is connected to the drain of the switch element 248, and the source of the switch element 248 is connected to the reference potential wiring L2. In addition, the arrangement order of the switch elements 243 to 245 as P-channel MOSFETs is not limited to Figure 2The example shown in the figure can change the arrangement order of the switching elements 243 to 245 without changing the connection destination of the gates of the switching elements 243 to 245. The arrangement order of the switching elements 246 to 248 which are N-channel MOSFETs is the same.

[0088] A node N8 between the switch element 245 and the switch element 246 is an output node of the protection circuit 24. The node N8 is connected to an input terminal of the latch circuit 25.

[0089] The gate of the switch element 243 is connected to the output terminal of the NOR gate 233a, and the masking signal SMASK is input to the gate of the switch element 243. Therefore, when the masking signal SMASK is at a low level, the switch element 243 is turned on, and when the masking signal SMASK is at a high level, the switch element 243 is turned off.

[0090] The gates of the switch element 244 and the switch element 246 are connected to the node N5, and the level shift completion setting signal setdrn is input to the gates of the switch element 244 and the switch element 246. Therefore, when the level shift completion setting signal setdrn is at a low level, the switch element 244 is turned on, and the switch element 246 is turned off. When the level shift completion setting signal setdrn is at a high level, the switch element 244 is turned off, and the switch element 246 is turned on.

[0091] The gates of the switch element 245 and the switch element 247 are connected to the node N6 via the inverter 241, and the inversion signal of the level shift completion reset signal resdrn is input to the gates of the switch element 245 and the switch element 247. Therefore, when the level shift completion reset signal resdrn is at a low level, the switch element 245 is turned off, and the switch element 247 is turned on. When the level shift completion reset signal resdrn is at a high level, the switch element 245 is turned on, and the switch element 247 is turned off.

[0092] The gate of the switch element 248 is connected to the output terminal of the NOR gate 233b via the inverter 242, and the inversion signal of the shielding signal RMASK is input to the gate of the switch element 248. Therefore, when the shielding signal RMASK is at a low level, the switch element 248 is turned on, and when the shielding signal RMASK is at a high level, the switch element 248 is turned off.

[0093] The electrical state of the node N8, that is, the state of the output PO of the protection circuit 24, is determined by the combination of the on and off of the switch elements 243 to 248. When all the switch elements 243 to 245 are on, the voltage of the node N8 is pulled up by the high-side DC power supply 6, and the output PO of the protection circuit 24 is at a high level. When all the switch elements 246 to 248 are on, the voltage of the node N8 is reduced to the voltage of the reference potential wiring L2, and the output PO of the protection circuit 24 is at a low level. When at least one of the switch elements 243 to 245 is off and at least one of the switch elements 246 to 248 is off, the node N8 is in a floating state, and the output PO is in a high impedance state.

[0094] Refer to Table 1 and Figure 3 Table 1 shows the relationship between the state of the level shift completion set signal setdrn, the level shift completion reset signal resdrn, the mask signal SMASK, the mask signal RMASK, the switch elements 243 to 248 , and the output PO of the protection circuit 24 .

[0095] [Table 1]

[0096]

[0097] During the period from time t1 to time t2, the level shift completion set signal setdrn is at a low level, the level shift completion reset signal resdrn is at a high level, the mask signal SMASK is at a high level, and the mask signal RMASK is at a low level. During this period, the switch element 243 among the switch elements 243 to 245 is turned off, and the switch elements 246 and 247 among the switch elements 246 to 248 are turned off, so that the output PO of the protection circuit 24 is in a high impedance state.

[0098] During the period from time t2 to time t3, the level shift completion set signal setdrn is at a low level, the level shift completion reset signal resdrn is at a high level, the mask signal SMASK is at a low level, and the mask signal RMASK is at a low level. Therefore, all the switch elements 243 to 245 are turned on, and therefore, the output PO of the protection circuit 24 is at a high level.

[0099] During the period from time t3 to time t4, the level shift completion set signal setdrn is at a high level, the level shift completion reset signal resdrn is at a high level, the mask signal SMASK is at a low level, and the mask signal RMASK is at a low level. During this period, the switch element 244 among the switch elements 243 to 245 is turned off, and the switch element 247 among the switch elements 246 to 248 is turned off, so that the output PO of the protection circuit 24 is in a high impedance state.

[0100] During the period from time t4 to time t5, the level shift completion set signal setdrn is at a high level, the level shift completion reset signal resdrn is at a low level, the mask signal SMASK is at a low level, and the mask signal RMASK is at a high level. Therefore, the switch elements 244 and 245 of the switch elements 243 to 245 are turned off, and the switch element 248 of the switch elements 246 to 248 is turned off, so that the output PO of the protection circuit 24 is in a high impedance state.

[0101] During the period from time t5 to time t6, the level shift completion set signal setdrn is at a high level, the level shift completion reset signal resdrn is at a low level, the mask signal SMASK is at a low level, and the mask signal RMASK is at a low level. During this period, all the switch elements 246 to 248 are turned on, so the output PO of the protection circuit 24 is at a low level.

[0102] During the period from time t6 to time t1, the level shift completion set signal setdrn is at a high level, the level shift completion reset signal resdrn is at a high level, the mask signal SMASK is at a low level, and the mask signal RMASK is at a low level. During this period, the switch element 244 among the switch elements 243 to 245 is turned off, and the switch element 247 among the switch elements 246 to 248 is turned off, so that the output PO of the protection circuit 24 is in a high impedance state.

[0103] In addition, the delay time in the delay circuits 231a and 231b, that is, the period Ts and Tr during which the mask signals SMASK and RMASK are at a high level, is longer than the response time of the protection circuit 24 (that is, the time when the output PO switches) caused by the level switching of the level shift completion set signal setdrn or the level shift completion reset signal resdrn. Therefore, even if the level of the level shift completion set signal setdrn switches at time t1, the output PO of the protection circuit 24 can be prevented from instantaneously becoming a high level. The same is true for the level switching of the level shift completion reset signal resdrn at time t4.

[0104] <<<2-6-1. Latch circuit>>>

[0105] The latch circuit 25 is configured to include inverters 251 and 252 and a resistor 253 .

[0106] The output voltage of the high-side DC power supply 6 based on the potential of the reference potential wiring L2 is supplied to the inverters 251 and 252. The input terminal of the inverter 251 is the input terminal of the latch circuit 25. The input terminal of the inverter 251 is connected to the node N8. The output terminal of the inverter 251 is connected to the input terminal of the inverter 252. The resistor 253 is connected between the output terminal of the inverter 252 and the input terminal of the inverter 251.

[0107] When the output PO of the protection circuit 24 is at a high level or a low level, the latch circuit 25 stores and outputs its value. In addition, when the output PO of the protection circuit 24 changes to a high impedance state, the latch circuit 25 holds / outputs the value stored just before the output PO of the protection circuit 24 changes to a high impedance state.

[0108] During the period from time t2 to time t3, the output PO of the protection circuit 24 is at a high level, so the output signal RO of the latch circuit 25 is at a high level. During the period from time t3 to time t5, the output PO of the protection circuit 24 is in a high impedance state, so the output signal RO of the latch circuit 25 is maintained at a high level. During the period from time t5 to time t6, the output PO of the protection circuit 24 is at a low level, so the output signal RO of the latch circuit 25 is at a low level. During the period from time t6 to time t2, the output PO of the protection circuit 24 is in a high impedance state, so the output signal RO of the latch circuit 25 is maintained at a low level.

[0109] <<<2-6-2. High-side driver>>>

[0110] The output voltage of the high-side DC power supply 6 based on the potential of the reference potential wiring L2 is supplied to the high-side driver 26. In addition, the output signal RO of the latch circuit 25 is input to the high-side driver 26. The high-side driver 26 generates a drive signal HO corresponding to the output signal RO of the latch circuit 25, and outputs the drive signal HO to the gate of the power switching element 51. That is, when the output signal RO of the latch circuit 25 is at a low level, the high-side driver 26 sets the drive signal HO to a low level, and when the drive signal HO of the latch circuit 25 is at a high level, the high-side driver 26 sets the drive signal HO to a high level.

[0111] In addition, although a delay corresponding to the delay time in the delay circuits 231 a and 231 b occurs, the sum of the delay time in the input circuit 11 and the delay time in the delay circuits 231 a and 231 b is appropriately designed.

[0112] <<<3. When external noise is generated>>>

[0113] Due to external noise such as three-phase current, one of the voltage of node N5 and the voltage of node N6 changes with a delay compared to the other, and the voltage of node N5 and the voltage of node N6 may be erroneously reduced. Even in this case, the latch circuit 25 does not malfunction, and the drive signal HO of the high-side driver 26 is maintained in the state before the external noise is generated. The following is a detailed description.

[0114] Figure 4 A timing diagram is shown in the case where external noise is generated during the period from time t6 to time t1. Before the external noise is generated, the level shift completion set signal setdrn (the voltage of the node N5) and the level shift completion reset signal resdrn (the voltage of the node N6) are at a high level, the shielding signal SMASK and the shielding signal RMASK are at a low level, and the drive signal HO is at a low level. Then, the voltage of the node N5 drops due to the external noise at time t11, and the voltage of the node N6 drops with delay at time t12. Thereafter, the voltage of the node N5 and the voltage of the node N6 rise together at time t15. In addition, the delay time of the delay circuits 231a and 232b is set to be longer than the period from when the voltage of the node N5 drops due to the external noise (time t11) to when the voltage of the node N6 drops (time t12). Furthermore, the delay time of the delay circuits 231a and 231b is longer than the response time of the protection circuit 24 (ie, the time when the output PO switches) caused by the voltage drop of the node N5 or the node N6 due to external noise.

[0115] The output signal S of the inverter 232a rises at time t13 with a delay relative to the voltage drop of the node N5. Therefore, during the period from time t11 to time t13, the mask signal SMASK is at a high level. The output signal R of the inverter 232b rises at time t14 with a delay relative to the voltage drop of the node N6. Therefore, during the period from time t12 to time t14, the mask signal RMASK is at a high level.

[0116] During the period from time t11 to time t12, the voltage of the node N5 is at a low level, the voltage of the node N6 is at a high level, the shielding signal SMASK is at a high level, and the shielding signal RMASK is at a low level. During this period, the switch elements 243, 246, and 247 are turned off, so that the output PO of the protection circuit 24 is in a high impedance state. Therefore, the output signal RO of the latch circuit 25 is maintained at a low level, and the drive signal HO also continues to be at a low level.

[0117] During the period from time t12 to time t15, the voltage of the node N5 and the voltage of the node N6 are both at a low level, and the mask signal RMASK and the mask signal SMASK are at a low level. During this period, the switch elements 245 and 246 are turned off, so that the output PO of the protection circuit 24 is in a high impedance state. Therefore, the output signal RO of the latch circuit 25 is maintained at a low level, and the drive signal HO also continues to be at a low level.

[0118] After time t15, the voltage of node N5 and the voltage of node N6 are both at high level. Therefore, since the switch elements 244 and 247 are turned off, the output PO is in a high impedance state. Therefore, the output signal RO of the latch circuit 25 remains at a low level, and the drive signal HO also continues to be at a low level.

[0119] In addition, Figure 3 During the period from time t6 to time t1 shown, even when the voltage of the node N5 drops due to external noise and the voltage of the node N6 drops with delay, the output signal RO of the latch circuit 25 is maintained at a low level and the drive signal HO continues to be at a low level.

[0120] Figure 5 A timing diagram is shown in the case where external noise is generated during the period from time t3 to time t4. Before the external noise is generated, the level shift completion set signal setdrn (the voltage of the node N5) and the level shift completion reset signal resdrn (the voltage of the node N6) are both at a high level, the shielding signal SMASK and the shielding signal RMASK are at a low level, and the drive signal HO is at a high level. Then, the voltage of the node N6 drops due to the external noise at time t21, and the voltage of the node N5 drops with delay at time t22. Thereafter, the voltage of the node N5 and the voltage of the node N6 rise together at time t25. In addition, the delay time of the delay circuits 231a and 231b is set to be longer than the period from when the voltage of the node N6 drops due to the external noise (time t21) to when the voltage of the node N5 drops (time t22).

[0121] The output signal R of the inverter 232b rises at time t23 with a delay relative to the voltage drop of the node N6. Therefore, during the period from time t21 to time t23, the mask signal RMASK is at a high level. The output signal S of the inverter 232a rises at time t24 with a delay relative to the voltage drop of the node N5. Therefore, during the period from time t22 to time t24, the mask signal SMASK is at a high level.

[0122] During the period from time t21 to time t22, the voltage of the node N5 is at a high level, the voltage of the node N6 is at a low level, the mask signal SMASK is at a low level, and the mask signal RMASK is at a high level. During this period, the switch elements 244, 245, and 248 are turned off, so that the output PO of the protection circuit 24 is in a high impedance state. Therefore, the output signal RO of the latch circuit 25 is maintained at a high level, and the drive signal HO also continues to be at a high level.

[0123] During the period from time t22 to time t25, the voltage of the node N6 and the voltage of the node N5 are both at a low level. During this period, the switch elements 245 and 246 are turned off, so that the output PO of the protection circuit 24 is in a high impedance state. Therefore, the output signal RO of the latch circuit 25 is maintained at a high level, and the drive signal HO also continues to be at a high level.

[0124] After time t25, the voltage of the node N5 and the voltage of the node N6 are both at a high level, and the shielding signal RMASK and the shielding signal SMASK are at a low level. Therefore, since the switch elements 244 and 247 are turned off, the output PO is in a high impedance state. The output signal RO of the latch circuit 25 remains at a high level, and the drive signal HO also continues to be at a high level.

[0125] In addition, Figure 3 During the period from time t3 to time t4 shown, even when the voltage of the node N6 drops due to external noise and the voltage of the node N5 drops with delay, the output signal RO of the latch circuit 25 is maintained at a high level and the drive signal HO continues to be at a high level.

[0126] <<<4. Conclusion>>>

[0127] Even when one of the voltage of the node N5 and the voltage of the node N6 is delayed relative to the other due to external noise and the voltage of the node N5 and the voltage of the node N6 erroneously decrease, the latch circuit 25 does not malfunction and the drive signal HO maintains the state before the external noise is generated.

[0128] <<<5. Modifications>>>

[0129] The above-mentioned embodiments are used to facilitate the understanding of the present invention, but are not used to limit and explain the present invention. In addition, without departing from the concept of the present invention, the present invention can be changed and improved, and the equivalent inventions of the present invention are of course also included in the present invention. The present invention of course includes its equivalent inventions. For example, the following deformations shown in (1) to (2) can be performed. The following deformations of (1) and (2) can also be combined and applied.

[0130] (1) First Modification

[0131] In the above embodiment, the mask signal SMASK outputted by the differential pulse generating circuit 23a becomes high level due to the falling change of the level shifting completion set signal setdrn. In addition, the mask signal RMASK outputted by the differential pulse generating circuit 23b becomes high level due to the falling change of the level shifting completion reset signal resdrn.

[0132] In contrast, Figure 6 As shown, the mask signal SMASK outputted by the differential pulse generating circuit 23a can be changed to a high level not only by the falling change of the level shifting completion setting signal setdrn, but also by the rising change of the level shifting completion setting signal setdrn. In addition, the mask signal RMASK outputted by the differential pulse generating circuit 23b can be changed to a high level not only by the falling change of the level shifting completion reset signal resdrn, but also by the rising change of the level shifting completion reset signal resdrn. In addition, Figure 6 The waveforms of the signals shown periodically repeat changes so as to transition from the state at time t1 to the state at time t6a.

[0133] The differential pulse generating circuit 23a and the differential pulse generating circuit 23b are specifically as follows: Figure 7 As shown, the output Figure 6 The waveforms of the mask signal SMASK and the mask signal RMASK are shown.

[0134] like Figure 7 As shown, the differential pulse generating circuit 23a is configured to include an AND gate 234a and an OR gate 235a in addition to a delay circuit 231a, an inverter 232a, and a NOR gate 233a.

[0135] The level shift completion setting signal setdrn is input to the delay circuit 231a, the NOR gate 233a, and the AND gate 234a. The delay circuit 231a delays the level shift completion setting signal setdrn and outputs it to the inverter 232a. The inverter 232a inverts the output signal of the delay circuit 231a and outputs it to the NOR gate 233a and the AND gate 234a. The NOR gate 233a calculates the logical negation of the output signal S of the inverter 232a and the level shift completion setting signal setdrn, and outputs a signal indicating the logical negation to the OR gate 235a. The AND gate 234a calculates the logical AND of the output signal S of the inverter 232a and the level shift completion setting signal setdrn, and outputs a signal indicating the logical AND to the OR gate 235a. The OR gate 235 a calculates a logical sum of the output signal of the NOR gate 233 a and the output signal of the AND gate 234 a , and outputs a mask signal SMASK indicating the logical sum to the gate of the switch element 243 .

[0136] The differential pulse generating circuit 23b includes an AND gate 234b and an OR gate 235b in addition to the delay circuit 231b, the inverter 232b and the NOR gate 233b.

[0137] The level shift completion reset signal resdrn is input to the delay circuit 231b, the NOR gate 233b, and the AND gate 234b. The delay circuit 231b delays the level shift completion reset signal resdrn and outputs it to the inverter 232b. The inverter 232b inverts the output signal of the delay circuit 231b and outputs it to the NOR gate 233b and the AND gate 234b. The NOR gate 233b calculates the logical negation of the output signal R of the inverter 232b and the level shift completion reset signal resdrn, and outputs a signal indicating the logical negation to the OR gate 235b. The AND gate 234b calculates the logical AND of the output signal R of the inverter 232b and the level shift completion reset signal resdrn, and outputs a signal indicating the logical AND to the OR gate 235b. The OR gate 235 b calculates a logical sum of the output signal of the NOR gate 233 b and the output signal of the AND gate 234 b , and outputs a mask signal RMASK indicating the logical sum to the gate of the switch element 248 .

[0138] like Figure 6As shown, when the level shift completion set signal setdrn rises at time t3, the shielding signal SMASK rises. Then, after a period corresponding to the delay time of the delay circuit 231a, the shielding signal SMASK falls at time t3a. During the period from time t3 to time t3a, the level shift completion set signal setdrn is at a high level, the level shift completion reset signal resdrn is at a high level, the shielding signal SMASK is at a high level, and the shielding signal RMASK is at a low level. Therefore, the switch element 244 among the switch elements 243 to 245 is turned off, and the switch element 247 among the switch elements 246 to 248 is turned off. Then, the output PO is in a high impedance state, the output signal RO of the latch circuit 25 is maintained at a high level, and the drive signal HO is at a high level.

[0139] In addition, when the level shift completion reset signal resdrn rises at time t6, the shielding signal RMASK rises. After a period corresponding to the delay time of the delay circuit 231b, the shielding signal RMASK falls at time t6a. During the period from time t6 to time t6a, the level shift completion set signal setdrn is at a high level, the level shift completion reset signal resdrn is at a high level, the shielding signal SMASK is at a low level, and the shielding signal RMASK is at a high level. The switch element 244 of the switch elements 243 to 245 is turned off, and the switch element 247 of the switch elements 246 to 248 is turned off. Then, the output PO is in a high impedance state, the output signal RO of the latch circuit 25 is maintained at a low level, and the drive signal HO is at a low level.

[0140] When the voltages at the nodes N5 and N6 become high due to external noise, the latch circuit 25 does not malfunction even if one of the voltages at the nodes N5 and N6 falls later than the other.

[0141] Figure 8 The timing diagram is shown in the case where external noise is generated during the period from time t6a to time t1. The voltage of the node N5 drops due to the external noise at time t11, and the voltage of the node N6 drops with delay at time t12. Thereafter, the voltage of the node N5 rises at time t15, and the voltage of the node N6 rises with delay at time t16.

[0142] As reference Figure 4 As described, during the period from time t11 to time t15 , the output signal RO of the latch circuit 25 is maintained at a low level, and the drive signal HO is at a low level.

[0143] The output signal S of the inverter 232a is delayed relative to the rise of the voltage of the node N5 at time t15, and falls at time t17. Therefore, during the period from time t15 to time t17, the mask signal SMASK is at a high level. The output signal R of the inverter 232b is delayed relative to the rise of the voltage of the node N6 at time t16, and falls at time t18. Therefore, during the period from time t16 to time t18, the mask signal RMASK is at a high level.

[0144] During the period from time t15 to time t16, the voltage of the node N5 is at a high level, the voltage of the node N6 is at a low level, the shielding signal SMASK is at a high level, and the shielding signal RMASK is at a low level. During this period, the switch elements 243 to 245 are turned off and the switch elements 246 to 248 are turned on, so the output PO of the protection circuit 24 is at a low level. Therefore, the output signal RO of the latch circuit 25 is maintained at a low level, and the drive signal HO also continues to be at a low level.

[0145] During the period from time t16 to time t18, the voltage of the node N6 and the voltage of the node N5 are both at a high level. During this period, the switch elements 244 and 247 are turned off, so the output PO of the protection circuit 24 is in a high impedance state. Therefore, the output signal RO of the latch circuit 25 is maintained at a low level, and the drive signal HO continues to be at a low level.

[0146] Fig. 9 The timing diagram is shown in the case where external noise is generated during the period from time t3a to time t4. The level shift completion reset signal resdrn drops due to the external noise at time t21, and the voltage of the node N5 drops with delay at time t22. Thereafter, the voltage of the node N6 rises at time t25, and the voltage of the node N5 rises with delay at time t26.

[0147] As reference Figure 5 As described above, during the period from time t21 to time t25, the output signal RO of the latch circuit 25 is maintained at a high level, and the drive signal HO is at a high level.

[0148] The output signal R of the inverter 232b is delayed relative to the rise of the voltage of the node N6 at time t25, and falls at time t27. Therefore, during the period from time t25 to time t27, the mask signal RMASK is at a high level. The output signal S of the inverter 232a is delayed relative to the rise of the voltage of the node N5 at time t26, and falls at time t28. Therefore, during the period from time t26 to time t28, the mask signal SMASK is at a high level.

[0149] During the period from time t25 to time t26, the voltage of the node N5 is at a low level, the voltage of the node N6 is at a high level, the shielding signal SMASK is at a low level, and the shielding signal RMASK is at a high level. During this period, the switch elements 243 to 245 are turned on and the switch elements 246 to 248 are turned off, so the output PO of the protection circuit 24 is at a high level. Therefore, the output signal RO of the latch circuit 25 is maintained at a high level, and the drive signal HO continues to be at a high level.

[0150] During the period from time t26 to time t28, the voltage of the node N6 and the voltage of the node N5 are both at a high level. During this period, the switch elements 244 and 247 are turned off, so that the output PO of the protection circuit 24 is in a high impedance state. Therefore, the output signal RO of the latch circuit 25 is maintained at a high level, and the drive signal HO continues to be at a high level.

[0151] (2) Second Modification

[0152] The latch circuit 25 may be a flip-flop circuit. In this case, the node N5 is connected to the S terminal of the flip-flop through the inverter and the protection circuit 24, the node N6 is connected to the R terminal of the flip-flop through the inverter and the protection circuit 24, and the Q terminal of the flip-flop is connected to the high-side driver 26. In this case, although the structure of the protection circuit 24 is different from Figure 1 and Figure 2 The structure shown in the figure, but the protection circuit 24 has the following functions.

[0153] During the period when the high-level mask signal SMASK or the high-level mask signal RMASK is input, the protection circuit 24 does not allow the inversion signal of the level shift completion set signal setdrn and the inversion signal of the level shift completion reset signal resdrn to pass. Therefore, the inversion signal of the level shift completion set signal setdrn is not output from the protection circuit 24 to the S terminal of the flip-flop, and the inversion signal of the level shift completion reset signal resdrn is not output to the R terminal of the flip-flop.

[0154] Furthermore, after the high-level mask signal SMASK or the high-level mask signal RMASK is input, when the inversion signals of the level shift completion set signal setdrn and the level shift completion reset signal resdrn are both at a high level or a low level, the protection circuit 24 does not pass the level shift completion set signal setdrn and the level shift completion reset signal resdrn. Therefore, the inversion signal of the level shift completion set signal setdrn is not output from the protection circuit 24 to the S terminal of the flip-flop, and the inversion signal of the level shift completion reset signal resdrn is not output to the R terminal of the flip-flop.

[0155] Furthermore, after the high-level mask signal SMASK or the high-level mask signal RMASK is input, when one of the level shift completion set signal setdrn and the level shift completion reset signal resdrn is at a high level and the other is at a low level, the protection circuit 24 passes the inversion signal of the level shift completion set signal setdrn and the inversion signal of the level shift completion reset signal resdrn. Therefore, the inversion signal of the level shift completion set signal setdrn is output from the protection circuit 24 to the S terminal of the flip-flop, and the inversion signal of the level shift completion reset signal resdrn is output to the R terminal of the flip-flop.

[0156] Even when the protection circuit 24 and the trigger are provided as described above, the trigger can be prevented from malfunctioning due to external noise. That is, even when one of the voltage of the node N5 and the voltage of the node N6 is delayed relative to the other due to external noise and the voltage of the node N5 and the voltage of the node N6 are erroneously lowered, the trigger does not malfunction and the drive signal HO is maintained in the state before the external noise is generated.

[0157] =====Second Embodiment======

[0158] Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

[0159] <<<1. Overview of drive circuit>>>

[0160] Fig.10 is a diagram showing a drive circuit 1A, an output circuit 5 , and a load 9 . Fig.11 It is a diagram for explaining the configuration of the differential pulse generating circuit 31 , the pull-down circuit 32 , the pull-up circuit 37 , and the protection circuit 24A. Fig.12 It is a timing diagram showing the relationship between the set signal set, the level shift completion set signal setdrn, the reset signal res, the level shift completion reset signal resdrn, the output signal DON, the output signal nDON, the shielding signal NCHON, the output signal nPCHON, the output PO, the output signal RO and the drive signal HO. Fig.12The waveforms of the signals shown are periodically repeated to change from the state at time t40 to the state at time t49. Here, the output circuit 5, the DC power supply 7, the high-side DC power supply 6, the high-voltage DC power supply 8, the load 9 and the low-side control circuit 40 of the first embodiment are arranged in the same manner as the circuits of the first embodiment. In addition, the same reference numerals are given to the common structural elements between the drive circuit 1A of the second embodiment and the drive circuit 1 of the first embodiment. The structural elements with the same reference numerals are arranged to be the same and have the same functions. Therefore, the following mainly describes the differences between the structural elements of the drive circuit 1A of the second embodiment and the drive circuit 1 of the first embodiment.

[0161] The driving circuit 1A of the second embodiment is configured to include a front-stage circuit 10, a level shift circuit 21, a differential pulse generating circuit 31 as a mask signal generating circuit, a control circuit 27A, diodes 28, 29, and a low-side control circuit 40. The control circuit 27A includes a latch control circuit 36, a latch circuit 25, and a high-side driver 26. The latch control circuit 36 ​​is configured to include a pull-down circuit 32, a pull-up circuit 37, and a protection circuit 24A. Here, the front-stage circuit 10, the level shift circuit 21, the latch circuit 25, the high-side driver 26, and the diodes 28, 29 are common components with the driving circuit 1 of the first embodiment, and they are set in the same manner as the first embodiment.

[0162] <<<2. Differential pulse generation circuit>>>

[0163] The differential pulse generating circuit 31 generates a mask signal NCHON that changes in a pulse shape according to a change in the voltage of the node N5 or the voltage of the node N6, for example, a falling change of the level shifting completion set signal setdrn or the level shifting completion reset signal resdrn, and outputs the mask signal NCHON to the pull-down circuit 32 and the pull-up circuit 37. Here, the period during which the differential pulse generating circuit 31 makes the mask signal NCHON high is shorter than the period during which the pulse generating circuit 12 makes the set signal set or the reset signal res high (the period during which the level shifting completion set signal setdrn or the level shifting completion reset signal resdrn is low).

[0164] The differential pulse generating circuit 31 is configured to include a NAND gate 311 , a delay circuit 312 , an inverter 313 , and an AND gate 314 .

[0165] The level shift completion set signal setdrn and the level shift completion reset signal resdrn are input to the NAND gate 311. The NAND gate 311 calculates the logical AND of the level shift completion set signal setdrn and the level shift completion reset signal resdrn, and outputs the output signal DON indicating the logical AND to the delay circuit 312 and the AND gate 314. The delay circuit 312 delays the output signal of the NAND gate 311 and outputs it to the inverter 313. The inverter 313 inverts the output signal of the delay circuit 312 and outputs it to the AND gate 314. The AND gate 314 calculates the logical AND of the output signal DON of the NAND gate 311 and the output signal nDON of the inverter 313, and outputs the mask signal NCHON indicating the logical AND to the pull-down circuit 32 and the OR gate 33.

[0166] Here, the output signal nDON of the inverter 313 is a signal obtained by delaying and inverting the output signal DON of the NAND gate 311. Fig.12 In the period from the time t41 and t46 when the output signal DON rises to the time t42 and t47 when the output signal nDON falls, the mask signal NCHON is at a high level.

[0167] <<<3. Control circuit>>>

[0168] The control circuit 27A generates a drive signal HO based on the level shift completion set signal setdrn, the level shift completion reset signal resdrn, and the mask signal NCHON, and outputs the drive signal HO to the gate of the power switch element 51 .

[0169] Specifically, when the high-level shielding signal NCHON is input to the control circuit 27A during the period from time t41 to time t42, the control circuit 27A sets the level of the drive signal HO to the level before time t41, that is, the low level, during the period from time t41 to time t43. In addition, after the high-level shielding signal NCHON is input to the control circuit 27A during the period from time t41 to time t42, when the low-level level shift completion setting signal setdrn is input to the control circuit 27A at time t43, the control circuit 27A sets the drive signal HO to the high level to turn on the power switch element 51. In addition, when the high-level level shift completion setting signal setdrn, the level shift completion reset signal resdrn, and the low-level shielding signal NCHON are input to the control circuit 27A during the period from time t44 to time t46, the control circuit 27A sets the level of the drive signal HO to the level before time t46, that is, the high level, during this period. Furthermore, when the level shift completion reset signal resdrn of the low level is input to the control circuit 27A at time t48 after the high level shielding signal NCHON is input to the control circuit 27A during the period from time t46 to time t47, the control circuit 27A sets the drive signal HO to the low level to turn on the power switch element 51. When the level shift completion set signal setdrn of the high level, the level shift completion reset signal resdrn and the shielding signal NCHON of the low level are input to the control circuit 27A during the period from time t49 to time t41, the control circuit 27 sets the level of the drive signal HO to the level before time t49, that is, the low level, during this period.

[0170] As described above, the control circuit 27A is configured to include the latch control circuit 36 ​​, the latch circuit 25 , and the high-side driver 26 .

[0171] <<<3-1. Latch control circuit>>>

[0172] The latch control circuit 36 ​​determines the output to the latch circuit 25 according to the level shift completion set signal setdrn, the level shift completion reset signal resdrn and the mask signal NCHON. Specifically, the latch control circuit 36 ​​puts the output PO in a high impedance state during the period when the high-level mask signal NCHON is input. The period of this state is Fig.12 The period shown is from time t41 to time t42 and the period from time t46 to time t47.

[0173] In addition, after the high-level shielding signal NCHON is input, the latch control circuit 36 ​​outputs a signal corresponding to the level shift completion set signal setdrn and the level shift completion reset signal resdrn. Specifically, after the high-level shielding signal NCHON is input, if the level shift completion set signal setdrn is low and the level shift completion reset signal resdrn is high, the latch control circuit 36 ​​outputs a high-level signal. The period of this state is from time t43 to time t44. In addition, after the high-level shielding signal NCHON is input, if the level shift completion set signal setdrn is high and the level shift completion reset signal resdrn is low, the latch control circuit 36 ​​outputs a low-level signal. The period of this state is from time t48 to time t49. Furthermore, after the high-level shielding signal NCHON is input, if the level shifting completion set signal setdrn and the level shifting completion reset signal resdrn are both at the low level, the latch control circuit 36 ​​puts the output PO in the high impedance state. The period of this state is the period from time t42 to time t43 and the period from time t47 to time t48. Furthermore, after the high-level shielding signal NCHON is input, if the level shifting completion set signal setdrn and the level shifting completion reset signal resdrn are both at the high level, the latch control circuit 36 ​​puts the output PO in the high impedance state. The period of this state is the period from time t44 to time t46 and the period from time t49 to time t41.

[0174] As described above, the latch control circuit 36 ​​is configured to include the pull-down circuit 32 , the pull-up circuit 37 , and the protection circuit 24A.

[0175] <<<3-1-1. Pull-down circuit>>>

[0176] When the output signal of the differential pulse generating circuit 31, that is, the shielding signal NCHON, is at a high level (for example, when the voltage of the node N5 or the node N6 is reduced), the pull-down circuit 32 pulls down the voltage of the nodes N5 and N6 to the voltage of the high-side reference potential wiring L2. Therefore, the pull-down circuit 32 sets the voltage level of the node N5 and the node N6 to a low level.

[0177] The pull-down circuit 32 is configured to include a switch element 321 a on the set side and a switch element 321 b on the reset side.

[0178] The switch elements 321a and 321b are N-channel MOSFETs. The drain of the switch element 321a is connected to the node N5, and the source of the switch element 321a is connected to the reference potential wiring L2. The drain of the switch element 321b is connected to the node N6, and the source of the switch element 321b is connected to the reference potential wiring L2. The gates of the switch elements 321a and 321b are connected to the output terminal of the AND gate 314 of the differential pulse generating circuit 31, and the shielding signal NCHON is input to the gates of the switch elements 321a and 321b. Therefore, the switch elements 321a and 321b are turned on and off based on the shielding signal NCHON.

[0179] When the shield signal NCHON is at a high level, the switch elements 321a and 321b are both turned on. Therefore, the voltage of the nodes N5 and N6 is pulled down to the voltage of the reference potential wiring L2. On the other hand, when the shield signal NCHON is at a low level, the switch elements 321a and 321b are both turned off, so that the impedance between the nodes N5 and N6 and the reference potential wiring L2 becomes high.

[0180] <<<3-1-2. Pull-up circuit>>>

[0181] In a short period after the high-level shielding signal NCHON is input to the pull-up circuit 37, the pull-up circuit 37 connects the nodes N5 and N6 and the high-potential wiring L7, thereby applying the voltage of the high-potential wiring L7 to the nodes N5 and N6. This state is from time t42 to time t43 and from time t47 to time t48.

[0182] The pull-up circuit 37 includes an OR gate 33 and a switch circuit 34 , and the switch circuit 34 includes a switch element 341 a on the set side and a switch element 341 b on the reset side.

[0183] The input terminals of the OR gate 33 are respectively connected to the output terminal of the AND gate 314, the node N5 and the node N6. The OR gate 33 calculates the logical sum of the mask signal NCHON, the level shift completion set signal setdrn and the level shift completion reset signal resdrn, and outputs an output signal nPCHON indicating the logical sum.

[0184] Here, when all of the following conditions (a) to (c) are met, the output signal nPCHON of the OR gate 33 becomes a low level, and when any of the following conditions (a) to (c) are not met, the output signal nPCHON of the OR gate 33 becomes a high level.

[0185] (a) The mask signal NCHON is at a low level. That is, no rising change occurs in the level shift completion set signal setdrn and the level shift completion reset signal resdrn, and the differential pulse generating circuit 31 generates no pulse.

[0186] (b) The level shift is completed and the set signal setdrn is set to a low level.

[0187] (c) The level shift is completed and the reset signal resdrn is at a low level.

[0188] The switch elements 341a and 341b are P-channel MOSFETs. The source of the switch element 341a is connected to the high potential wiring L7, and the drain of the switch element 341a is connected to the node N5. The source of the switch element 341b is connected to the high potential wiring L7, and the drain of the switch element 341b is connected to the node N6. The gates of the switch elements 341a and 341b are connected to the output terminal of the OR gate 33, and the output signal nPCHON of the OR gate 33 is input to the gates of the switch elements 341a and 341b. Therefore, the switch elements 341a and 341b are turned on and off based on the output signal nPCHON of the OR gate 33.

[0189] When the output signal nPCHON of the OR gate 33 is at a low level, the switch elements 341a and 341b are both turned on. Therefore, the nodes N5 and N6 are connected to the high potential wiring L7, and the voltage of the high potential wiring L7 is applied to the nodes N5 and N6. On the other hand, when the output signal nPCHON of the OR gate 33 is at a high level, the switch elements 341a and 341b are both turned off, so that the impedance between the nodes N5 and N6 and the high potential wiring L7 becomes high.

[0190] <<<3-1-3. Protection circuit>>>

[0191] The voltage of the high-side DC power supply 6 based on the potential of the reference potential wiring L2 is supplied to the protection circuit 24A. The protection circuit 24A determines the state of the output PO to the latch circuit 25 based on the level shift completion set signal setdrn and the level shift completion reset signal resdrn. Fig.12 As shown, when the level shift completion set signal setdrn is low and the level shift completion reset signal resdrn is high, the protection circuit 24A outputs a high level signal to the latch circuit 25. This state lasts from time t43 to time t44.

[0192] When the level shift completion set signal setdrn is at a high level and the level shift completion reset signal resdrn is at a low level, the protection circuit 24A outputs a low level signal to the latch circuit 25. The period of this state is from time t48 to time t49.

[0193] When the level shift completion set signal setdrn and the level shift completion reset signal resdrn are both at low level or high level, the protection circuit 24A puts the output PO in a high impedance state from time t44 to time t48 and from time t49 to time t43.

[0194] The protection circuit 24A is configured to include an inverter 241A and switching elements 244A to 247A.

[0195] The switch elements 244A and 245A are P-channel MOSFETs, and the switch elements 246A and 247A are N-channel MOSFETs. The switch elements 244A to 247A are arranged from the high potential wiring L7 to the reference potential wiring L2, and are connected in series between the high potential wiring L7 and the reference potential wiring L2. As an example, the source of the switch element 244A is connected to the high potential wiring L7, the drain of the switch element 244A is connected to the source of the switch element 245A, the drain of the switch element 245A is connected to the drain of the switch element 246A, the source of the switch element 246A is connected to the drain of the switch element 247A, and the source of the switch element 247A is connected to the reference potential wiring L2.

[0196] The gates of the switch element 244A and the switch element 246A are connected to the node N5, and the level shift completion setting signal setdrn is input to the gates of the switch element 244A and the switch element 246A. Therefore, when the level shift completion setting signal setdrn is at a low level, the switch element 244A is turned on, and the switch element 246A is turned off. When the level shift completion setting signal setdrn is at a high level, the switch element 244A is turned off, and the switch element 246A is turned on.

[0197] The gates of the switch element 245A and the switch element 247A are connected to the node N6 via the inverter 241A, and the inversion signal of the level shift completion reset signal resdrn is input to the gates of the switch element 245A and the switch element 247A. Therefore, when the level shift completion reset signal resdrn is at a low level, the switch element 245A is turned off, and the switch element 247A is turned on. When the level shift completion reset signal resdrn is at a high level, the switch element 245A is turned on, and the switch element 247A is turned off.

[0198] The electrical state of node N8, that is, the state of output PO of protection circuit 24A is determined by the combination of on and off of switch elements 244A to 247A. When switch elements 244A and 245A are both on and switch elements 246A and 247A are both off, the voltage of node N8 is pulled up by high-side DC power supply 6, and output PO is at a high level. When switch elements 246A and 247A are both on and switch elements 244A and 245A are both off, the voltage of node N8 is pulled down to the voltage of reference potential wiring L2, and output PO is at a low level. When at least one of switch elements 244A and 245A is off and at least one of switch elements 246A and 247A is off, node N8 is in a floating state and output PO is in a high impedance state. As shown in Table 2. Table 2 shows the relationship between the state of the level shift completion set signal setdrn, the level shift completion reset signal resdrn, the switch elements 244A to 247A, and the output PO of the protection circuit 24A.

[0199] [Table 2]

[0200]

[0201] <<<4. Operation of the drive circuit>>>

[0202] Before time t40, the level shift completion set signal setdrn and the level shift completion reset signal resdrn are both at high level, the output PO of the protection circuit 24A is at high impedance, and the output signal RO and the drive signal HO of the latch circuit 25 are at low level. In addition, the output signal DON of the NAND gate 311 is at low level, the output signal nDON of the inverter 313 is at high level, and the output signal nPCHON of the OR gate 33 is at high level.

[0203] At time t40, the level shift switch element 211a is turned on by the set signal set, and the level shift completion set signal setdrn starts to fall. Then, the output signal DON of the NAND gate 311 starts to rise. Then, at time t41, the output signal DON of the NAND gate 311 exceeds the threshold of the AND gate 314, and the mask signal NCHON, which is the output signal of the AND gate 314, becomes a high level. Here, since the charging and discharging time of the switch elements 244A and 246A of the protection circuit 24A is longer than the period from time t40 to time t41, even if the level shift completion set signal setdrn starts to fall at time t40, the switch elements 244A and 246A are not switched on or off.

[0204] By the high-level shielding signal NCHON, the switch elements 321a and 321b of the pull-down circuit 32 are turned on. Therefore, the voltages of the nodes N5 and N6 are pulled down by the voltage of the reference potential wiring L2, and the level shift completion set signal setdrn and the level shift completion reset signal resdrn both become low level. Then, the switch elements 245A and 246A are turned off. Therefore, after time t41, the output PO of the protection circuit 24A continues to be in a high impedance state, and the output signal RO and the drive signal HO of the latch circuit 25 continue to be at a low level.

[0205] Thereafter, the output signal nDON of the inverter 313 falls with a delay from the output signal DON of the NAND gate 311, and the output signal nDON of the inverter 313 becomes below the threshold of the AND gate 314 at time t42, and the shielding signal NCHON, which is the output signal of the AND gate 314, becomes low level. Therefore, the switch elements 321a and 321b of the pull-down circuit 32 are turned off, and the nodes N5 and N6 are open to the reference potential wiring L2, but the level shift completion set signal setdrn and the level shift completion reset signal resdrn are still at low level. Therefore, after time t42, the output PO of the protection circuit 24A continues to be in a high impedance state, and the output signal RO and the drive signal HO of the latch circuit 25 continue to be at a low level.

[0206] At time t42, since the shielding signal NCHON, the level shift completion setting signal setdrn, and the level shift completion reset signal resdrn are all at low levels, the output signal nPCHON of the OR gate 33 becomes low. Therefore, the switch elements 341a and 341b of the pull-up circuit 37 are turned on. As a result, the voltage of the node N6 is pulled up by the voltage of the high potential wiring L7, and at time t43, the level shift completion reset signal resdrn becomes high. On the other hand, the voltage of the node N5 is not pulled up, and the level shift completion setting signal setdrn remains at a low level. This is because the level shift switch element 211a is turned on.

[0207] Therefore, at time t43, the output PO of the protection circuit 24A changes to a high level, and the output signal RO of the latch circuit 25 and the drive signal HO change to a high level.

[0208] At time t43, since the level shift completion reset signal resdrn becomes high, the output signal nPCHON of the OR gate 33 becomes high. Then, the switch elements 341a and 341b of the pull-up circuit 37 are turned off, and the nodes N5 and N6 are opened from the high potential wiring L7.

[0209] Thereafter, the set signal set falls, and the level shift completion set signal setdrn rises. Then, at time t44, the level shift completion set signal setdrn becomes high level, and the level shift switch element 211a is turned off. During the period from time t44 to time t45, the level shift completion set signal setdrn and the level shift completion reset signal resdrn are both at high level. Therefore, the output PO of the protection circuit 24A is in a high impedance state, the output signal RO of the latch circuit 25 is maintained at a high level, and the drive signal HO continues to be at a high level.

[0210] At time t45, the level shift switch element 211b is turned on by the reset signal res, and the level shift completion reset signal resdrn starts to fall. Then, the output signal DON of the NAND gate 311 starts to rise. Then, at time t46, the output signal DON of the NAND gate 311 exceeds the threshold of the AND gate 314, and the shielding signal NCHON, which is the output signal of the AND gate 314, becomes a high level. Here, since the charging and discharging time of the switch elements 245A and 247A of the protection circuit 24A is longer than the period from time t45 to time t46, even if the level shift completion reset signal resdrn starts to fall at time t45, the switch elements 245A and 247A are not switched on or off.

[0211] By the high-level shielding signal NCHON, the switch elements 321a and 321b of the pull-down circuit 32 are turned on. Therefore, the voltages of the nodes N5 and N6 are pulled down by the voltage of the reference potential wiring L2, and the level shift completion set signal setdrn and the level shift completion reset signal resdrn both become low level. Then, the switch elements 245A and 246A are turned off. Therefore, after time t45, the output PO of the protection circuit 24A continues to be in a high impedance state, and the output signal RO and the drive signal HO of the latch circuit 25 continue to be at a high level.

[0212] Thereafter, the output signal nDON of the inverter 313 falls with a delay from the output signal DON of the NAND gate 311, and the output signal nDON of the inverter 313 becomes below the threshold of the AND gate 314 at time t47, and the shielding signal NCHON as the output signal of the AND gate 314 becomes low level. Therefore, the switch elements 321a and 321b of the pull-down circuit 32 are turned off, and the nodes N5 and N6 are open to the reference potential wiring L2, but the level shift completion set signal setdrn and the level shift completion reset signal resdrn are still at low level. Therefore, after time t47, the output PO of the protection circuit 24A continues to be in a high impedance state, and the output signal RO and the drive signal HO of the latch circuit 25 continue to be at a high level.

[0213] At time t47, since the shielding signal NCHON, the level shift completion setting signal setdrn, and the level shift completion reset signal resdrn are all at low levels, the output signal nPCHON of the OR gate 33 becomes low. Therefore, the switch elements 341a and 341b of the pull-up circuit 37 are turned on. As a result, the voltage of the node N5 is pulled up by the voltage of the high potential wiring L7, and at time t48, the level shift completion setting signal setdrn becomes high. On the other hand, the voltage of the node N6 is not pulled up, and the level shift completion reset signal resdrn remains at a low level. This is because the level shift switch element 211b is turned on.

[0214] Therefore, at time t48, the output PO of the protection circuit 24A changes to a high level, and the output signal RO of the latch circuit 25 and the drive signal HO change to a high level.

[0215] At time t48, since the level shift completion setting signal setdrn becomes high, the output signal nPCHON of the OR gate 33 becomes high. Then, the switch elements 341a and 341b of the pull-up circuit 37 are turned off, and the nodes N5 and N6 are opened from the high potential wiring L7.

[0216] After that, the reset signal res falls, and the level shift completion reset signal resdrn rises. Then, at time t49, the level shift completion reset signal resdrn becomes high level, and the level shift switch element 211b is turned off. During the period from time t49 to time t40, the level shift completion set signal setdrn and the level shift completion reset signal resdrn are both at high level. Therefore, the output PO of the protection circuit 24A is at high impedance, the output signal RO of the latch circuit 25 is maintained at low level, and the drive signal HO continues to be at low level.

[0217] <<<5. When external noise is generated>>>

[0218] Due to external noise such as three-phase current, one of the voltage of node N5 and the voltage of node N6 may be delayed relative to the other, and the voltage of node N5 and the voltage of node N6 may be erroneously reduced. Even in this case, the latch circuit 25 will not malfunction, and the drive signal HO will maintain the state before the external noise is generated. The following is a detailed description.

[0219] Fig.13The timing diagram is shown in the case where external noise is generated during the period from time t49 to time t40. Before the external noise is generated, the level shift completion set signal setdrn (the voltage of the node N5) and the level shift completion reset signal resdrn (the voltage of the node N6) are at a high level. In addition, since the shielding signal NCHON, which is the output signal of the differential pulse generating circuit 31, is at a low level, the switch elements 321a and 321b are turned off, and the nodes N5 and N6 are open to the reference potential wiring L2. In addition, since the output signal nPCHON of the OR gate 33 is at a high level, the switch elements 341a and 341b are turned off, and the nodes N5 and N6 are open to the high potential wiring L7.

[0220] Then, the voltage of the node N5 starts to drop due to external noise at time t50, and the voltage of the node N6 starts to drop with a delay at time t51. Then, the output signal DON of the NAND gate 311 starts to rise. Then, at time t52, the output signal DON of the NAND gate 311 exceeds the threshold of the AND gate 314, and the shielding signal NCHON as the output signal of the AND gate 314 becomes a high level. Therefore, the switch elements 321a and 321b of the pull-down circuit 32 are turned on. Therefore, the voltages of the nodes N5 and N6 are pulled down by the voltage of the reference potential wiring L2, and the voltages of the nodes N5 and N6 both become low levels, and the switch elements 245A and 246A are turned off. Therefore, after time t52, the output PO of the protection circuit 24A continues to be in a high impedance state, and the output signal RO and the drive signal HO of the latch circuit 25 continue to be at a low level.

[0221] Thereafter, the output signal nDON of the inverter 313 falls with a delay from the output signal DON of the NAND gate 311, and the output signal nDON of the inverter 313 becomes below the threshold of the AND gate 314 at time t53, and the shielding signal NCHON, which is the output signal of the AND gate 314, becomes low level. Therefore, the switch elements 321a and 321b of the pull-down circuit 32 are turned off, and the circuit between the nodes N5 and N6 and the reference potential wiring L2 is open, but the voltage of the node N5 and the voltage of the node N6 are still at a low level. Therefore, after time t53, the output PO of the protection circuit 24A continues to be in a high impedance state, and the output signal RO and the drive signal HO of the latch circuit 25 continue to be at a low level.

[0222] At time t53, the shielding signal NCHON, the voltage of the node N5, and the voltage of the node N6 are all at a low level, so the output signal nPCHON of the OR gate 33 becomes a low level. Therefore, the switch elements 341a and 341b of the pull-up circuit 37 are turned on. As a result, the voltages of the nodes N5 and N6 are pulled up by the voltage of the high potential wiring L7, and at time t54, the voltages of the node N5 and the node N6 become a high level. Therefore, after time t54, the output PO of the protection circuit 24A continues to be in a high impedance state, and the output signal RO and the drive signal HO of the latch circuit 25 continue to be at a low level.

[0223] Fig.14 The timing diagram is shown in the case where external noise is generated during the period from time t44 to time t45. Before the external noise is generated, the voltage of the node N5 and the voltage of the node N6 are at a high level. In addition, since the shielding signal NCHON, which is the output signal of the differential pulse generating circuit 31, is at a low level, the switch elements 321a and 321b are turned off, and the nodes N5 and N6 are open to the reference potential wiring L2. In addition, since the output signal nPCHON of the OR gate 33 is at a high level, the switch elements 341a and 341b are turned off, and the nodes N5 and N6 are open to the high potential wiring L7.

[0224] Then, the voltage of the node N6 starts to drop due to external noise at time t60, and the voltage of the node N5 starts to drop with a delay at time t61. Then, the output signal DON of the NAND gate 311 starts to rise. Then, at time t62, the output signal DON of the NAND gate 311 exceeds the threshold of the AND gate 314, and the shielding signal NCHON as the output signal of the AND gate 314 becomes a high level. Therefore, the switch elements 321a and 321b of the pull-down circuit 32 are turned on. Therefore, the voltages of the nodes N5 and N6 are pulled down by the voltage of the reference potential wiring L2, and the voltages of the nodes N5 and N6 both become low levels, and the switch elements 245A and 246A are turned off. Therefore, after time t62, the output PO of the protection circuit 24A also continues to be in a high impedance state, and the output signal RO and the drive signal HO of the latch circuit 25 continue to be at a high level.

[0225] Thereafter, the output signal nDON of the inverter 313 falls with a delay from the output signal DON of the NAND gate 311, and the output signal nDON of the inverter 313 becomes below the threshold of the AND gate 314 at time t63, and the shielding signal NCHON becomes low level. Therefore, the switch elements 321a and 321b of the pull-down circuit 32 are turned off, and the circuit between the nodes N5 and N6 and the reference potential wiring L2 is open, but the voltage of the node N5 and the voltage of the node N6 are still at a low level. Therefore, after time t63, the output PO of the protection circuit 24A also continues to be in a high impedance state, and the output signal RO and the drive signal HO of the latch circuit 25 continue to be at a high level.

[0226] At time t63, the shielding signal NCHON, the voltage of the node N5, and the voltage of the node N6 are all at a low level, so the output signal nPCHON of the OR gate 33 becomes a low level. Therefore, the switch elements 341a and 341b of the pull-up circuit 37 are turned on. As a result, the voltages of the nodes N5 and N6 are pulled up by the voltage of the high potential wiring L7, and at time t64, the voltages of the node N5 and the node N6 become a high level. Therefore, after time t64, the output PO of the protection circuit 24A also continues to be in a high impedance state, and the output signal RO and the drive signal HO of the latch circuit 25 continue to be at a high level.

[0227] <<<6. Conclusion>>>

[0228] Even when one of the voltage of the node N5 and the voltage of the node N6 is delayed relative to the other due to external noise and the voltage of the node N5 and the voltage of the node N6 erroneously become a low level, the latch circuit 25 does not malfunction and the drive signal HO maintains the state before the external noise is generated.

[0229] In both the normal operation and the external noise, after the voltage of the node N5 and the voltage of the node N6 are both changed to a low level by the pull-down circuit 32, one or both of the voltage of the node N5 and the voltage of the node N6 are quickly increased by the pull-up circuit 37. Therefore, the driving circuit 1A can be operated at a high speed.

[0230] <<<7. Modifications>>>

[0231] In addition, the above-mentioned embodiments are used to facilitate the understanding of the present invention, and are not used to limit and explain the present invention. In addition, without departing from the concept of the present invention, the present invention can be changed and improved, and the equivalent invention of the present invention is of course also included in the present invention. For example, the following deformations shown in (1) and (2) can be performed. The following deformations of (1) and (2) can also be combined and applied.

[0232] (1) First Modification

[0233] The protection circuit 24A in the second embodiment may be replaced with the protection circuit 24 in the first embodiment. In this case, the differential pulse generating circuit 23a and the differential pulse generating circuit 23b in the first embodiment are also provided in the driving circuit 1A in the second embodiment.

[0234] (2) Second Modification

[0235] The latch circuit 25 may be a flip-flop circuit. In this case, the node N5 is connected to the S terminal of the flip-flop through the inverter and the protection circuit 24A, the node N6 is connected to the R terminal of the flip-flop through the inverter and the protection circuit 24A, and the Q terminal of the flip-flop is connected to the high-side driver 26. In this case, although the structure of the protection circuit 24A is different from Fig.10 and Fig.11 The structure shown in the figure, however, the protection circuit 24A has the following functions.

[0236] When the inversion signals of the level shift completion set signal setdrn and the level shift completion reset signal resdrn are both at a high level or a low level, the protection circuit 24A does not allow the level shift completion set signal setdrn and the level shift completion reset signal resdrn to pass through. Therefore, the inversion signal of the level shift completion set signal setdrn is not output from the protection circuit 24A to the S terminal of the flip-flop, and the inversion signal of the level shift completion reset signal resdrn is not output to the S terminal of the flip-flop.

[0237] Furthermore, after the high-level mask signal SMASK or the high-level mask signal RMASK is input, when one of the level shift completion set signal setdrn and the level shift completion reset signal resdrn is at a high level and the other is at a low level, the protection circuit 24 passes the inversion signal of the level shift completion set signal setdrn and the inversion signal of the level shift completion reset signal resdrn. Therefore, the inversion signal of the level shift completion set signal setdrn is output from the protection circuit 24 to the S terminal of the flip-flop, and the inversion signal of the level shift completion reset signal resdrn is output to the R terminal of the flip-flop.

[0238] Even when the protection circuit 24A and the flip-flop as described above are provided, the flip-flop can be prevented from malfunctioning due to external noise. That is, even when the potentials of the nodes N5 and N6 vary due to external noise and one of the level shift completion set signal setdrn and the level shift completion reset signal resdrn is delayed relative to the other, and the level shift completion set signal setdrn and the level shift completion reset signal resdrn erronely become low levels, the flip-flop does not malfunction, and the drive signal HO is maintained at the state before the external noise is generated.

[0239] Description of symbols

[0240] 1, 1A...Drive circuit

[0241] 21a…Level shift circuit on the set side

[0242] 21b…Level shift circuit on the reset side

[0243] 211a…Level shift switch element on the set side

[0244] 211b…Level shift switch element on the reset side

[0245] 212a…Resistor on the set side

[0246] 212b…Reset side resistor

[0247] 23…Shielding signal generation circuit

[0248] 23a…Differential pulse generation circuit on the set side

[0249] 23b…Differential pulse generation circuit on the reset side

[0250] 24…Protection circuit (latch control circuit)

[0251] 24A...Protection circuit

[0252] 25…Latch circuit

[0253] 27…Control circuit

[0254] 31…Differential pulse generating circuit (shielding signal generating circuit)

[0255] 32…Pull-down circuit

[0256] 33…OR gate

[0257] 36…Latch control circuit

[0258] 37…Pull-up circuit

[0259] 231a…Delay circuit on the set side

[0260] 231b…Delay circuit on the reset side

[0261] 232a…Inverter on the set side

[0262] 232b…Inverter on reset side

[0263] 233a…NOR circuit on the set side

[0264] 233b…NOR circuit on the reset side

[0265] 241…Inverter (first inverter)

[0266] 241A…Inverter (first inverter)

[0267] 242…Inverter (second inverter)

[0268] 243 ...Switching element (first P-channel switching element)

[0269] 244 ... switch element (second P-channel switch element)

[0270] 245 ... switch element (third P-channel switch element)

[0271] 246 ... switch element (first N-channel switch element)

[0272] 247 ... switch element (second N-channel switch element)

[0273] 248 ... switch element (third N-channel switch element)

[0274] 244A...Switching element (first P-channel switching element)

[0275] 245A...Switching element (second P-channel switching element)

[0276] 246A...Switching element (first P-channel switching element)

[0277] 247A...Switching element (second P-channel switching element)

[0278] 312…Delay circuit

[0279] 313…Inverter (second inverter)

[0280] 314…AND gate

[0281] 321a…Switching element on the set side

[0282] 321b…Switching element on the reset side

[0283] 341a ... a switch element on the setting side (a second switch element on the setting side)

[0284] 341b ...switching element on the reset side (second switching element on the reset side)

[0285] L1…reference potential wiring

[0286] L2...reference potential wiring (second reference potential wiring)

[0287] L7…High potential wiring

[0288] N5...node (set side output node)

[0289] N6…node (reset side output node).

Claims

1. A driving circuit, characterized in that: include: A setting side level shift circuit, which performs level shifting on a pulse-shaped setting signal and outputs a pulse-shaped level shifted setting signal from a setting side output node; A reset side level shift circuit, which performs level shifting on a pulse-shaped reset signal and outputs a pulse-shaped level shifted reset signal from a reset side output node; a shielding signal generating circuit, which outputs a pulsed set-side shielding signal during a period shorter than a first period during which the level shifting completion set signal is output when the voltage of the set-side output node changes, and outputs a pulsed reset-side shielding signal during a period shorter than a second period during which the level shifting completion reset signal is output when the voltage of the reset-side output node changes; as well as A control circuit, which outputs a drive signal in a state before the set side shielding signal or the reset side shielding signal is input to a power device during the period when the set side shielding signal or the reset side shielding signal is input, and outputs the drive signal for turning off the power device when the level shifting completion reset signal is input after the reset side shielding signal is input, and outputs the drive signal for turning on the power device when the level shifting completion set signal is input after the set side shielding signal is input.

2. The driving circuit according to claim 1, characterized in that: The control circuit has: a latch control circuit that sets the output to a high impedance state during the period when the set side shield signal or the reset side shield signal is input, or outputs a signal before the set side shield signal or the reset side shield signal is input, and outputs a signal based on the voltage of the reset side output node and the voltage of the set side output node after the set side shield signal or the reset side shield signal is input; a latch circuit that latches and outputs a signal input from the latch control circuit; as well as A drive signal output circuit outputs the drive signal based on the output of the latch circuit.

3. The driving circuit according to claim 2, characterized in that: The shield signal generating circuit outputs the set side shield signal or the reset side shield signal during a period longer than a period during which the output is set to a high impedance state after the set side shield signal or the reset side shield signal is input to the latch control circuit, or a period until the latch control circuit outputs a signal before the set side shield signal or the reset side shield signal is input.

4. The driving circuit according to claim 2 or 3, characterized in that: The latch control circuit sets the output to a high impedance state or outputs a signal before the set side shielding signal or the reset side shielding signal is input when the logic levels of the voltage of the set side output node and the voltage of the reset side output node become the same logic level.

5. The driving circuit according to claim 3, characterized in that: The shielding signal generating circuit comprises: a set-side differential pulse generating circuit, the set-side differential pulse generating circuit generating the set-side shielding signal according to a change in a voltage of the set-side output node to a logic level for turning on the power device; as well as A reset-side differential pulse generating circuit generates the reset-side masking signal in response to a voltage of the reset-side output node changing to a logic level for turning off the power device.

6. The driving circuit according to claim 5, characterized in that: The latch control circuit has: a first P-channel type switching element, a second P-channel type switching element, and a third P-channel type switching element connected in series between a high potential wiring having a potential higher than a reference potential wiring and an output node of the latch control circuit; a first N-channel type switching element, a second N-channel type switching element, and a third N-channel type switching element connected in series between an output node of the latch control circuit and the reference potential wiring; a first inverter that inverts a signal from the reset-side output node and outputs the inverted signal to gates of the third P-channel type switching element and the second N-channel type switching element; as well as a second inverter that inverts the reset side shielding signal outputted from the reset side differential pulse generating circuit and outputs the inverted signal to the gate of the third N-channel type switching element, a signal from the reset side output node is input to the second P-channel type switching element and the first N-channel type switching element, The set-side mask signal outputted from the set-side differential pulse generating circuit is inputted to the first P-channel type switching element.

7. The driving circuit according to claim 5 or 6, characterized in that: The set-side differential pulse generating circuit has: a set-side delay circuit, which delays and outputs a signal from the set-side output node; a set-side inverter that inverts and outputs an output signal of the set-side delay circuit; and A set-side NOR gate outputs a logically negative operation result of an output signal of the set-side inverter and a signal from the set-side output node to the latch control circuit as the set-side mask signal.

8. The driving circuit according to claim 5 or 6, characterized in that: The reset side differential pulse generating circuit has: a reset-side delay circuit, which delays and outputs a signal from the reset-side output node; a reset-side inverter, which inverts and outputs an output signal of the reset-side delay circuit; as well as A reset-side NOR gate outputs a logically negative operation result of an output signal of the reset-side inverter and a signal from the reset-side output node to the latch control circuit as the reset-side mask signal.

9. A driving circuit, characterized in that: include: A setting side level shift circuit, which performs level shifting on a pulse-shaped setting signal and outputs a pulse-shaped level shifted setting signal from a setting side output node; A reset side level shift circuit, which performs level shifting on a pulse-shaped reset signal and outputs a pulse-shaped level shifted reset signal from a reset side output node; a shielding signal generating circuit that outputs a pulse-shaped shielding signal during a period shorter than a first period during which the level shift completion set signal is output and a second period during which the level shift completion reset signal is output when a voltage of any one of the set-side output node and the reset-side output node changes; as well as a control circuit, wherein the control circuit outputs a drive signal in a state before the shielding signal is input to the power device during the period when the shielding signal is input, and outputs the drive signal for turning off the power device when the level shifting completion reset signal is input after the shielding signal is input, and outputs the drive signal for turning on the power device when the level shifting completion set signal is input after the shielding signal is input, The control circuit has: a latch control circuit that sets the output to a high impedance state during the period when the shield signal is input, or outputs a signal before the shield signal is input, and outputs a signal based on the voltage of the reset-side output node and the voltage of the set-side output node after the shield signal is input; a latch circuit that latches and outputs a signal input from the latch control circuit; as well as a drive signal output circuit that outputs the drive signal based on the output of the latch circuit, the mask signal generating circuit outputs the mask signal for a period longer than a period during which the output is set to a high impedance state after the mask signal is input to the latch control circuit or a period until the latch control circuit outputs a signal before the mask signal is input, The shield signal generating circuit generates the shield signal according to the voltage of the set-side output node changing to a logic level for turning on the power device or the voltage of the reset-side output node changing to a logic level for turning on the power device. The latch control circuit has: a pull-down circuit for setting the voltage of the set-side output node and the voltage of the reset-side output node to the same logic level by pulling down the voltages of the set-side output node and the reset-side output node together during the period in which the shielding signal is input; as well as A protection circuit outputs a signal based on a voltage of the set-side output node and a voltage of the reset-side output node to the latch circuit.

10. The driving circuit according to claim 9, characterized in that: The pull-down circuit sets the voltage of the set-side output node and the voltage of the reset-side output node to the same logic level before the protection circuit outputs a signal based on the voltage of the set-side output node and the voltage of the reset-side output node.

11. The driving circuit according to claim 9 or 10, characterized in that: The shielding signal generating circuit comprises: a NAND gate that outputs a logical negation result of a voltage at the set-side output node and a voltage at the reset-side output node; A delay circuit, which delays and outputs an output signal of the NAND gate; a second inverter, which inverts and outputs an output signal of the delay circuit; as well as An AND gate outputs a result of a logical AND operation of an output signal of the NAND gate and an output signal of the second inverter as the mask signal.

12. The driving circuit according to claim 9 or 10, characterized in that: The pull-down circuit has: a set-side switch element connected between the reference potential wiring and the set-side output node; and a reset-side switch element connected between the reset-side output node and the reference potential wiring, The mask signal is input to the set-side switch element and the reset-side switch element.

13. The driving circuit according to claim 9 or 10, characterized in that: The latch control circuit has: A pull-up circuit applies a voltage to the set-side output node and the reset-side output node for a predetermined period after the mask signal is input.

14. The driving circuit according to claim 13, characterized in that: The pull-up circuit has: An OR gate, the OR gate outputting a logical OR operation result of the shielding signal, the signal from the set-side output node, and the signal from the reset-side output node; a second setting-side switch element connected between the high potential wiring and the setting-side output node; as well as a second reset-side switch element connected between the reset-side output node and the high potential wiring, An output signal of the OR gate is input to the second set-side switch element and the second reset-side switch element.

15. The driving circuit according to claim 14, characterized in that: The setting side level shift circuit has: a setting-side level shift switch element that is turned on and off based on the setting signal; and a setting-side resistor connected in series to the setting-side level shift switch element via the setting-side output node between a second reference potential wiring having a lower potential than the high potential wiring and the high potential wiring, The reset side level shift circuit has: a reset-side level shift switch element that is turned on and off based on the reset signal; as well as A reset-side resistor is connected in series to the reset-side level shift switch element via the set-side output node between the second reference potential wiring and the high potential wiring.

16. The driving circuit according to claim 9 or 10, characterized in that: The protection circuit has: a first P-channel type switching element and a second P-channel type switching element connected in series between the high potential wiring and the output node of the protection circuit; a first N-channel type switching element and a second N-channel type switching element connected in series between a reference potential wiring having a potential lower than that of the high potential wiring and an output node of the protection circuit; as well as a first inverter that inverts a signal from the reset-side output node and outputs the inverted signal to gates of the second P-channel type switching element and the second N-channel type switching element, A signal from the set-side output node is input to the first P-channel type switching element and the first N-channel type switching element.

17. The driving circuit according to any one of claims 1 to 3, characterized in that: include: An input circuit, which receives an input signal indicating the on / off state of the power device, delays the input signal by a time corresponding to the period of the set-side shielding signal or the reset-side shielding signal, and outputs the delay signal; as well as A pulse generating circuit generates the set signal and the reset signal based on an output from the input circuit.

18. The driving circuit according to claim 1, wherein: The setting side shielding signal is generated based on the level shift completion setting signal when the voltage of the setting side output node changes, and disappears when a third period shorter than the first period has passed since the voltage of the setting side output node changes. The reset-side shielding signal is generated based on the level-shifted reset signal when the voltage of the reset-side output node changes, and disappears when a fourth period shorter than the second period elapses from the change in the voltage of the reset-side output node.

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