Semiconductor device and memory cell

Abstract

The present invention discloses a semiconductor device and a memory cell. The semiconductor device comprises a first electrode, a second electrode, and an indium-doped chalcogenide-based selector layer disposed between the first electrode and the second electrode, wherein the indium content of the indium-doped chalcogenide-based selector layer is about 2 at.% to about 10 at.%. A memory cell having the indium-doped chalcogenide-based selector layer is also disclosed.

Description

Technical Field

[0001] The invention relates to a semiconductor device and a memory unit. Background Art

[0002] In order to meet the demand for high-density cross-point memory, the size of phase change random access memory (PCRAM) and resistive random access memory (RRAM) is getting smaller and smaller, and the development of selectors with small contact sizes is becoming more and more important. For example, transistors have large contact sizes, which limits the implementation of high-density memories. Two-terminal access devices will be an option for selectors used in micro-scaling technology.

[0003] Cross-point memory arrays usually require a large number of selectors. The threshold voltage of the selector can be adjusted by adjusting the thickness of the selector layer. However, if the thickness of the selector layer is reduced too much, the leakage current (IOFF) of the device will increase, thus wasting power in the memory array. Summary of the invention

[0004] According to some embodiments of the present invention, a semiconductor device includes a first electrode, a second electrode, and an indium-doped chalcogenide-based selector layer disposed between the first electrode and the second electrode, wherein the indium content of the indium-doped chalcogenide-based selector layer is about 2 at.% to about 10 at.%.

[0005] According to some other embodiments of the present invention, a memory cell includes an access device and a phase change material disposed on the access device. The access device includes a first electrode, a second electrode, and an indium-doped sulfur-based selection layer disposed between the first electrode and the second electrode, wherein the indium content of the indium-doped sulfur-based selection layer is about 2 at.% to about 10 at.%.

[0006] The indium-doped sulfur-based selective layer helps improve material stability, adhesion, and process variability. Therefore, the semiconductor device using the indium-doped sulfur-based selective layer has the characteristics of improving yield and reducing periodic degradation. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to make the above and other objects, features, advantages and embodiments of the present invention more clearly understood, the detailed description of the attached drawings is as follows:

[0008] Figure 1 It is a schematic cross-sectional view of a selector according to one embodiment of the present invention.

[0009] FIG. 2A to FIG. 2E According to one embodiment of the present invention, respectively, manufacturing Figure 1 Schematic diagram of the selector method at different stages.

[0010] Figure 3 3D stacked views of devices according to some embodiments of the present invention.

[0011] Figure 4A FIG. 4 is a cross-sectional view of a first group of memory cell stacks on a plane according to some embodiments.

[0012] Figure 4B FIG. 4 is a cross-sectional view of a second group of memory cell stacks on another plane according to some embodiments.

[0013]

Explanation of symbols

[0014] 100: Selector

[0015] 102, 104, 106: Dielectric layer

[0016] 110, 412: First electrode

[0017] 120, 416: Second electrode

[0018] 130, 414: Indium doped sulfur-based selective layer

[0019] 130': Indium doped sulfur-based material layer

[0020] 140, 142, 320, 420: Etch stop layer

[0021] 200: Installation

[0022] 210: Substrate

[0023] 300, 400: Memory unit

[0024] 310, 410: Access device

[0025] 350, 450: Memory

[0026] 454: Phase change materials

[0027] 456: Top electrode

[0028] O1, O2: Open

[0029] BL: Bit Line

[0030] WL: Word Line DETAILED DESCRIPTION

[0031] In order to make the purpose, technical scheme and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings. After understanding the preferred embodiments of the present invention, those skilled in the art may make changes and modifications based on the technology disclosed in the present invention without departing from the spirit and scope of the present invention.

[0032] As used herein, "about", "approximately" or "roughly" generally refers to an error or range of about 20% of the value, preferably about 10%, and more preferably about 5%. If there is no explicit explanation in the text, the numerical values ​​mentioned are all regarded as approximate values, that is, the error or range represented by "about", "approximately" or "roughly".

[0033] In addition, relative terms, such as "lower" or "bottom" and "upper" or "top", are used to describe the relationship of one element to another element shown in the drawings herein. Relative terms are used to describe different orientations of the device than those described in the drawings to be understood. For example, if the device in a drawing is turned over, elements that would be described as being on the "lower" side of other elements would be oriented to be on the "upper" side of other elements. The exemplary term "lower" can include both "lower" and "upper" orientations depending on the particular orientation of the drawing. Similarly, if the device in a drawing is turned over, elements that would be described as being "below" or "beneath" other elements would be oriented to be "above" other elements. The exemplary term "lower" or "beneath" can include both "above" and "above" orientations.

[0034] Reference Figure 1 , which is a cross-sectional schematic diagram of a selector according to an embodiment of the present invention. The selector 100 includes a first electrode 110 and a second electrode 120 disposed on the first electrode 110. In some embodiments, the material of the first electrode 110 may be the same as or different from the material of the second electrode 120. The material of the first electrode 110 may be, for example, tungsten or titanium nitride (TiN). The material of the second electrode 120 may be, for example, tungsten or titanium nitride.

[0035] The first electrode 110 includes an indium-doped sulfur-based selective layer 130, which is disposed between the first electrode 110 and the second electrode 120. The indium-doped sulfur-based selective layer 130 includes a chalcogenide compound, and exemplary chalcogenides may include arsenic (As), germanium (Ge), selenium (Se), and indium (In). In other words, the indium-doped sulfur-based selective layer 130 may be an indium-doped arsenic germanium selenium (In-doped AsGeSe) layer. In some embodiments, the indium content of the indium-doped sulfur-based selective layer 130 is about 2 at.% (atomic percentage) to about 10 at.%. If the indium content is higher than 10 at.%, the leakage current (IOFF) will become more serious, and the threshold voltage of the device will drop too much.

[0036] In some embodiments, the indium-doped sulfur-based selective layer 130 has an indium content of about 2 at.% to about 10 at.%, an arsenic content of about 25 at.% to about 38 at.%, a germanium content of about 8 at.% to about 20 at.%, and a selenium content of about 30 at.% to about 60 at.%.

[0037] In some embodiments, the selector 100 further includes two etch stop layers 140 and 142, respectively disposed between the first electrode 110 and the indium-doped sulfur-based selective layer 130 and between the second electrode 120 and the indium-doped sulfur-based selective layer 130. In some embodiments, the etch stop layers 140 and 142 may be carbon-containing layers or silicon-doped carbon (Si:C) layers.

[0038] The indium-doped sulfur-based selection layer 130 helps to improve the stability, adhesion and variability of the material in the process. Therefore, the selector 100 using the indium-doped sulfur-based selection layer 130 has the characteristics of improving yield and reducing cycling degradation. As mentioned above, the indium content of the indium-doped sulfur-based selection layer 130 is about 2 at.% to about 10 at.%. If the indium content is too low, the improvement is not obvious. In some embodiments, the thickness of the indium-doped sulfur-based selection layer 130 is about 15 nanometers to about 45 nanometers. The selector 100 using the indium-doped sulfur-based selection layer 130 can still provide a sufficiently high threshold voltage and a sufficiently low leakage current even at such a thin thickness, which is beneficial for application in three-dimensional cross-point array technology.

[0039] For example, in an exemplary selector 100 using an indium-doped sulfur-based selection layer 130, when the thickness of the indium-doped sulfur-based selection layer 130 is about 30 nanometers, the threshold voltage of the selector 100 is about 3.7 volts, and the leakage current is about 700 pA at an operating voltage of two volts. This exemplary selector 100 can be turned on in 10 nanoseconds (ns), which has a very fast response speed.

[0040] Please refer to FIG. 2A to FIG. 2E ,in FIG. 2A to FIG. 2E According to one embodiment of the present invention, respectively, manufacturing Figure 1 Schematic diagram of the selector 100 method at different stages.

[0041] like Figure 2A As shown, the first electrode 110 is formed in the dielectric layer 102. The first electrode 110 can extend through the dielectric layer 102 and connect to the access circuit (not shown) in the lower layer. The configuration of the components in the access circuit depends on the array configuration. For example, the access circuit can include transistors and diodes, word lines and source lines, conductive plugs, and doped regions in the semiconductor substrate.

[0042] In some embodiments, the dielectric layer 102 may be formed on the top surface of the access circuit. Next, a photoresist layer is deposited and patterned on the dielectric layer 102, wherein the step of patterning the photoresist layer includes using a photolithography technique to form a patterned photoresist layer overlapping the position of the first electrode 110. Then, the dielectric layer 102 is etched using the patterned photoresist layer as a mask to form a dielectric window in the dielectric layer 102. After the patterned photoresist layer is removed, the dielectric window is filled with a conductive material, such as tungsten or titanium nitride. Then, a planarization process is performed to remove the portion of the conductive material that exceeds the dielectric layer 102, thereby obtaining the first electrode 110 buried in the dielectric layer 102.

[0043] Reference Figure 2B , an etch stop layer 140 and another dielectric layer 104 are formed on the dielectric layer 102. In some embodiments, the material of the etch stop layer 140 is different from the material composition of the dielectric layer 104. For example, the etch stop layer 140 can be a carbon-containing layer or a silicon-doped carbon (Si:C) layer. The dielectric layer 102 and the dielectric layer 104 contain oxides, such as silicon dioxide. The etch stop layer 140 can be formed by any suitable deposition process.

[0044] The dielectric layer 104 is patterned to form an opening O1 on the first electrode 110. The step of patterning the dielectric layer 104 includes forming a patterned photoresist layer on the dielectric layer 104, and then etching the dielectric layer 104 using the patterned photoresist layer as a mask, and the etching step can be stopped when reaching the etch stop layer 140. In some embodiments, the portion of the etch stop layer 140 not covered by the patterned photoresist layer can be completely consumed to expose the first electrode 110 below. In some embodiments, the portion of the etch stop layer 140 not covered by the patterned photoresist layer can still remain on the dielectric layer 102. The patterned photoresist layer is then removed.

[0045] Reference Figure 2C and Figure 2D, the indium-doped sulfur-based material layer 130' is deposited on the opening O1 and fills the opening O1. In some embodiments, the indium-doped sulfur-based material layer 130' is made by a radio frequency sputtering process. The target is disposed adjacent to the substrate, such as above the first electrode 110, the dielectric layer 104, and the etch stop layer 140. During the sputtering process, the material of the target is deposited on the substrate.

[0046] In the sputtering process, the target material has a bias relative to the grounding area of ​​the reaction chamber, and this bias can come from the power provided by the RF source and the DC power supply. In the sputtering process, a gas is supplied to the reaction chamber from the gas source through a conduit. The gas source may contain gases that do not participate in the reaction, such as argon, krypton, helium, xenon and other gases, which can be used to strike the target material so that the material is detached from the target material to be deposited on the substrate. The plasma formed by the gas is formed between the target material and the substrate. The ions in the plasma move toward the target material with acceleration, causing the material on the target material to detach from the target material. The material detached from the target material is deposited on the substrate to form the indium-doped sulfur-based material layer 130'.

[0047] In some embodiments, the material of the target material may be the same as or similar to the material of the indium-doped sulfur-based material layer 130'. In some embodiments, the material of the target material includes arsenic, germanium, selenium, and indium. In some embodiments, the indium content of the target material is about 2 at.% to about 10 at.%, the arsenic content is about 25 at.% to about 38 at.%, the germanium content is about 8 at.% to about 20 at.%, and the selenium content is about 30 at.% to about 60 at.%.

[0048] After the indium-doped sulfur-based material layer 130' is deposited and fills the opening O1, a planarization process is performed to remove the portion of the indium-doped sulfur-based material layer 130' that protrudes beyond the dielectric layer 104, thereby obtaining the indium-doped sulfur-based selective layer 130 buried in the dielectric layer 104. In some embodiments, the thickness of the indium-doped sulfur-based selective layer 130 is approximately between 15 nanometers and 45 nanometers.

[0049] Reference Figure 2E , the second electrode 120 is formed on the indium-doped sulfur-based selective layer 130. In some embodiments, an etch stop layer 142 is formed on the indium-doped sulfur-based selective layer 130 and the dielectric layer 104, and another dielectric layer 106 is formed on the etch stop layer 142, and the dielectric layer 106 is patterned to form an opening O2 therein. The step of patterning the dielectric layer 106 includes forming a patterned photoresist layer on the dielectric layer 106. Then, the dielectric layer 106 is etched using the patterned photoresist layer as a mask, and the etching step stops when reaching the etch stop layer 142. In some embodiments, the portion of the etch stop layer 142 not covered by the patterned photoresist layer can be completely consumed or still remain on the dielectric layer 104. The patterned photoresist layer is then removed.

[0050] After the patterned photoresist layer is removed, a conductive material such as tungsten or titanium nitride is then deposited to fill the opening O2. A planarization process is then performed to remove the conductive material beyond the dielectric layer 106, thereby obtaining a second electrode 120 buried in the dielectric layer 106 and located on the indium-doped sulfur-based selective layer 130.

[0051] In some embodiments, the width of the indium-doped sulfur-based selection layer 130 is substantially the same as that of the second electrode 120, and the width of the first electrode 110 is smaller than that of the indium-doped sulfur-based selection layer 130 and the second electrode 120 thereon. In other embodiments, the widths of the first electrode 110, the indium-doped sulfur-based selection layer 130, and the second electrode 120 may be substantially the same.

[0052] Please refer to Figure 3 , which is a three-dimensional stacked view of a device 200 according to some embodiments of the present invention. The device 200 includes an array of memory cells 300 disposed on a substrate 210. The substrate 210 includes a semiconductor substrate, or a semiconductor substrate with circuits. In some embodiments, the substrate 210 can be a back end of line (BEOL) or front end of line (FEOL) substrate. Each memory cell 300 in the array includes an access device 310 and a memory 350, wherein the access device 310 and the memory 350 are in the form of semiconductor pillars. The bit line BL, which is a conductive line, connects the first group of memory cells 300, and the word line WL, which is also a conductive line and perpendicular to the bit line BL, connects the second group of memory cells 300. The access device 310 includes an indium-doped sulfur-based selection layer, and in some embodiments, the indium content of the indium-doped sulfur-based selection layer is about 2 at.% to about 10 at.%. If the indium content of the indium-doped sulfur-based selection layer is higher than 10 at.%, the leakage current will become more serious and the threshold voltage of the device will drop too much. In some embodiments, the indium content of the indium-doped sulfur-based selective layer is about 2 at.% to about 10 at.%, the arsenic content is about 25 at.% to about 38 at.%, the germanium content is about 8 at.% to about 20 at.%, and the selenium content is about 30 at.% to about 60 at.%. In some embodiments, the memory cells 300 are further vertically stacked into a stereo memory array. A dielectric layer is formed and surrounds the memory cells 300. In some embodiments, one memory cell 300 can be stacked on another memory cell 300 and isolated from each other by a dielectric layer. In some embodiments, an etch stop layer 320 is further provided between the access device 310, the memory 350, and the conductive lines (such as word lines WL, bit lines BL), and the etch stop layer 320 can be a carbon-containing layer or a silicon-doped carbon (Si:C) layer.

[0053] Reference Figure 4A and Figure 4B ,in Figure 4A and Figure 4B are cross-sectional views of the first group of memory cells 400 stacked on different planes according to some embodiments, wherein Figure 4A The cross-sectional position can be referenced Figure 3 Line segment AA in Figure 4B The cross-section position can be referenced Figure 3 Line segment BB in .

[0054] Each word line WL extends along the first direction and is connected in parallel to the second group of memory cells 400. The word line WL also serves as the first electrode 412 in each access device 410. An indium-doped sulfur-based selection layer 414 is formed on the first electrode 412 of the access device 410. The indium-doped sulfur-based selection layer 414 includes a chalcogenide compound, such as arsenic, germanium, selenium, and indium. In other words, the indium-doped sulfur-based selection layer 414 can be an indium-doped arsenic-germanium-selenium layer. In some embodiments, the indium content of the indium-doped sulfur-based selection layer 414 is about 2 at.% to about 10 at.%. If the indium content of the indium-doped sulfur-based selection layer 414 is higher than 10 at.%, the leakage current will become more serious and the threshold voltage of the device will drop too much.

[0055] In some embodiments, the indium content of the indium-doped sulfur-based selective layer 414 is about 2 at.% to about 10 at.%, the arsenic content is about 25 at.% to about 38 at.%, the germanium content is about 8 at.% to about 20 at.%, and the selenium content is about 30 at.% to about 60 at.%. In some embodiments, the thickness of the indium-doped sulfur-based selective layer 414 is about 15 nanometers to about 45 nanometers.

[0056] The second electrode 416 is formed on the indium-doped sulfur-based selective layer 414. The first electrode 412 and the second electrode 416 include a conductive material, such as tungsten or titanium nitride. In some embodiments, the indium-doped sulfur-based selective layer 414 is in direct contact with and electrically connected to the first electrode 412 and the second electrode 416. In other embodiments, additional layers, such as an etch stop layer, a thermal conductive layer, a work function layer, or other suitable layers, may be disposed between the first electrode 412, the indium-doped sulfur-based selective layer 414, and the second electrode 416. The steps of making the access device 410 may be similar to those described in the following examples. FIG. 2A to FIG. 2E The steps described.

[0057] The second electrode 416 also serves as a bottom electrode of the memory 450. The memory 450 is electrically connected to the access device 410 and can be programmed to provide two resistance states. In some embodiments, the memory 450 can include a phase change material 454 disposed on the second electrode 416. The phase change material 454 is electrically connected to the second electrode 416. The material property of the phase change material 454 can be programmed to provide a first phase with a first resistance and a second phase with a second resistance, wherein the first resistance is greater than the second resistance.

[0058] In some embodiments, the phase change material 454 may be a Germanium-Antimony-Tellurium compound (GST compound) such as Ge2Sb2Te5. Or other suitable phase change materials such as SbTe or In2Se3. In some embodiments, the array of memory cells 400 may be a multi-bit memory array. At this time, the phase change material 454 may be programmed to one of three resistance states.

[0059] Each bit line BL extends along the second direction and is connected in parallel to the first group of memory cells 400. A top electrode 456 of the memory cell 450 is disposed on the phase change material 454 and is connected to the bit line BL.

[0060] In some embodiments, an etch stop layer 420 is further provided between the conductor layer and the semiconductor layer, such as between the word line WL (first electrode 412), the indium-doped sulfur-based selection layer 414, the second electrode 416, the phase change material 454 and the top electrode 456. The etch stop layer 420 may be a carbon-containing layer or a silicon-doped carbon (Si:C) layer.

[0061] Thus, a memory cell 400 is disclosed, wherein each memory cell 400 includes a semiconductor structure of a selector and a resistor (1S1R). The 1S1R memory cell 400 allows for high-density three-dimensional stacking integration. Furthermore, by introducing an indium-doped sulfur-based selection layer 414 into the memory cell 400, the memory cell 400 can have a higher threshold voltage, a lower leakage current, and better tolerance performance in high-density cross-point applications. For example, in a memory cell 400 using an indium-doped sulfur-based selection layer 414, when the thickness of the indium-doped sulfur-based selection layer 414 is about 30 nanometers, the threshold voltage of the memory cell 400 can be greater than 3 volts, the leakage current can be less than 1 nA at an operating voltage of two volts, and the tolerance performance can be greater than 1E10 cycles. The indium-doped sulfur-based selection layer 414 helps to improve the stability of the material, adhesion, and variability in the process, so that the variation between devices becomes smaller, thereby improving the yield and reducing the periodic decay.

[0062] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor device comprising: a first electrode; a second electrode; An indium-doped sulfur-based selection layer is disposed between the first electrode and the second electrode, wherein the indium content of the indium-doped sulfur-based selection layer is about 2 at.% to about 10 at.%; in, The indium-doped sulfur-based selective layer is an indium-doped arsenic-germanium-selenium layer; the indium-doped sulfur-based selective layer has an arsenic content of about 25 at.% to about 38 at.%, a germanium content of about 8 at.% to about 20 at.%, and a selenium content of about 30 at.% to about 60 at.%. 2 . The semiconductor device of claim 1 , wherein the thickness of the indium-doped sulfur-based selective layer is about 15 nanometers to about 45 nanometers. 3 . The semiconductor device according to claim 1 , further comprising an etch stop layer disposed between the first electrode and the indium-doped sulfur-based selective layer. The semiconductor device as claimed in claim 3 , wherein the etch stop layer comprises carbon or silicon doped carbon. 5 . The semiconductor device according to claim 1 , further comprising an etch stop layer disposed between the second electrode and the indium-doped sulfur-based selective layer. The semiconductor device as claimed in claim 5 , wherein the etch stop layer comprises carbon or silicon doped carbon.

7. A memory cell comprising: An access device comprises a first electrode, a second electrode, and an indium-doped sulfur-based selection layer disposed between the first electrode and the second electrode, wherein the indium content of the indium-doped sulfur-based selection layer is about 2 at.% to about 10 at.%; and A phase change material is disposed on the access device; in, The indium-doped sulfur-based selective layer is an indium-doped arsenic-germanium-selenium layer; the indium-doped sulfur-based selective layer has an arsenic content of about 25 at.% to about 38 at.%, a germanium content of about 8 at.% to about 20 at.%, and a selenium content of about 30 at.% to about 60 at.%.

8. The memory cell of claim 7, wherein the phase change material is electrically connected to the second electrode.

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