Image sensor package and method of manufacturing the same

Abstract

The present invention discloses an image sensor package and a manufacturing method thereof. The image sensor package comprises a reconfiguration circuit structure; an image sensor chip, which is configured on the reconfiguration circuit structure and has a sensing surface, wherein a sensing area and a first conductive column are configured on the sensing surface, and the first conductive column is configured in a peripheral area next to the sensing area; a cover body, which covers the sensing area; an encapsulation body, which is configured on the reconfiguration circuit structure and encapsulates at least part of the image sensor chip and the cover body; and an upper semiconductor chip, which is configured above the image sensor chip and has a first conductor configured on the active surface of the upper semiconductor chip, wherein the first conductor overlaps the image sensor chip in a direction perpendicular to the sensing surface, wherein the first conductive column and the first conductor are aligned with each other and bonded to electrically connect the image sensor chip and the upper semiconductor chip.

Description

Technical Field

[0001] The present invention relates to a semiconductor chip package and a manufacturing method thereof, and in particular to an image sensor package and a manufacturing method thereof. Background Art

[0002] With the advent of the digital age, image sensors have gradually been applied to people's lives, such as smart phones, digital cameras, monitors, etc. In order to make image sensors both thin and light and high-performance, current packaging technology has attempted to integrate semiconductor chips into image sensor packages. However, when integrating semiconductor chips into image sensor packages, researchers will most likely face the limitation of the signal communication speed between the semiconductor chip and the image sensor chip, which results in the overall performance of the image sensor still needs to be further improved. Summary of the invention

[0003] The invention provides an image sensor package with good performance.

[0004] The present invention provides an image sensor package, comprising a reconfiguration circuit structure; an image sensor chip, which is configured on the reconfiguration circuit structure and has a sensing surface, wherein a sensing area and a first conductive column are configured on the sensing surface, and the first conductive column is configured in a surrounding area next to the sensing area; a cover body, covering the sensing area; an encapsulation body, which is configured on the reconfiguration circuit structure and encapsulates the image sensor chip and at least part of the cover body; and an upper semiconductor chip, which is configured above the image sensor chip and has a first conductor configured on the active surface of the upper semiconductor chip, wherein the first conductor overlaps with the image sensor chip in a direction perpendicular to the sensing surface, and the first conductive column and the first conductor are aligned with each other and bonded to electrically connect the image sensor chip and the upper semiconductor chip.

[0005] The present invention provides an image sensor package, comprising a reconfiguration circuit structure; a semiconductor element, arranged on the reconfiguration circuit structure, the semiconductor element comprising an image sensor chip, the image sensor chip having a sensing surface, a sensing area and a first conductive column arranged on the sensing surface, the first conductive column arranged in a peripheral area next to the sensing area; a cover body, covering the sensing area; an encapsulation body, arranged on the reconfiguration circuit structure and encapsulating at least part of the image sensor chip and the cover body; and an upper semiconductor chip, arranged above the semiconductor element and having a first conductor arranged on an active surface of the upper semiconductor chip, wherein the first conductor overlaps the semiconductor element in a direction perpendicular to the sensing surface, and the first conductive column and the first conductor are aligned with each other and bonded to electrically connect the semiconductor element and the upper semiconductor chip.

[0006] The present invention provides a method for manufacturing an image sensor package, comprising: arranging an image sensor chip on a reconfiguration circuit structure, wherein a cover body and a first conductive column are arranged on a sensing surface of the image sensor chip and the first conductive column surrounds the cover body on the sensing surface; arranging an encapsulation body on the reconfiguration circuit structure to encapsulate the image sensor chip; performing a planarization process to expose the first conductive column and the cover body from the encapsulation body; and arranging an upper semiconductor chip on the encapsulation body so that a first conductor of the upper semiconductor chip is bonded to the first conductive column, and the first conductor overlaps with the image sensor chip in a direction perpendicular to the sensing surface.

[0007] Based on the above, the image sensor package of the present invention can improve the overall performance of the image sensor package.

[0008] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0010] Figures 1A to 1H is a cross-sectional schematic diagram of the steps of manufacturing a manufacturing process of an image sensor package according to an embodiment of the present invention;

[0011] Figure 2 is a cross-sectional schematic diagram of an image sensor package according to an embodiment of the present invention;

[0012] Figure 3 FIG. 4 is a cross-sectional schematic diagram of an image sensor package according to another embodiment of the present invention.

[0013] Description of Figure Numbers

[0014] 100, 200: image sensor package;

[0015] 10: carrier;

[0016] 20: Release film;

[0017] 110: Reconfigure the circuit structure;

[0018] 112: second conductive column;

[0019] 114: dielectric layer;

[0020] 116: reconfigure the wiring layer;

[0021] 120, 230: image sensor chip;

[0022] 120A: Sensing surface;

[0023] 121: first conductive column;

[0024] 122: sensing area;

[0025] 125: Sealing structure;

[0026] 130: cover;

[0027] 140: Encapsulation body;

[0028] 150: upper semiconductor chip;

[0029] 151: first conductor;

[0030] 152: second conductor;

[0031] 160: Primer;

[0032] 170: conductive terminal;

[0033] 190: Adhesive layer;

[0034] 220: semiconductor components;

[0035] 230P: first connecting conductor;

[0036] 240P: second connecting conductor;

[0037] 240: lower semiconductor chip;

[0038] D T , D B :width;

[0039] α: angle. DETAILED DESCRIPTION

[0040] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0041] The following examples are listed and described in detail with the accompanying drawings, but the examples provided are not intended to limit the scope of the present invention. In addition, the drawings are for illustration purposes only, are not drawn according to the original size, and may enlarge or reduce different film layers or regions to be displayed in a single figure. Moreover, although the text uses "first", "second", etc. to describe different elements, regions and / or components, these elements, regions and / or components should not be limited to these terms. Instead, these terms are only used to distinguish one element, region or component from another element, region or component. Therefore, the first element, region or component discussed below can be referred to as the second element, region or component without violating the teachings of the embodiments. The same or similar element symbols represent the same or similar elements, and the following paragraphs will not be repeated one by one.

[0042] In this article, spatially relative terms such as "upper" and "lower" are defined with reference to the accompanying drawings. Therefore, it should be understood that the term "upper surface" can be used interchangeably with the term "lower surface", and when an element such as a layer or a film is described as being configured on another element, the element can be directly placed on the other element, or there can be an intermediary element between the two elements. On the other hand, when an element is described as being directly configured on another element, there is no intermediary element between the two elements. Similarly, when an element is described as being connected to another element, the element can be directly connected to the other element, or there can be an intermediary element between the two elements. On the other hand, when an element is described as being connected to another element, there is no intermediary element between the two elements.

[0043] Figures 1A to 1H FIG. 4 is a cross-sectional schematic diagram of steps of manufacturing an image sensor package according to a first embodiment of the present invention. Figure 2 FIG. 4 is a cross-sectional schematic diagram illustrating an image sensor package according to a first embodiment of the present invention.

[0044] Reference Figure 1A, a carrier 10 is provided. A release film 20 is formed on the carrier 10. The carrier 10 may be a supporting substrate used in a semiconductor chip packaging process. The material of the carrier 10 may include glass, ceramics, semiconductors, etc. Although the accompanying drawings show that only a single image sensor is packaged on the carrier 10, the carrier 10 may also be a large-sized wafer-type carrier. In other words, multiple image sensor packages may be formed on the carrier 10 at the same time. The release film 20 may be formed by an adhesive (e.g., ultraviolet (UV) glue, light-to-heat conversion (LTHC) glue, etc., or other types of adhesives). Taking the release film 20 formed by ultraviolet glue as an example, ultraviolet light may be irradiated on the release film 20 to make the release film 20 lose or reduce its viscosity, thereby enabling the carrier 10 and the release film 20 to be separated from the structure formed in subsequent steps. Taking photothermal conversion adhesive as an example, light of appropriate energy can be irradiated on the release film 20, so that the release film 20 decomposes under the thermal energy of the light and loses or reduces its viscosity, thereby allowing the carrier 10 and the release film 20 to be separated from the structure formed in subsequent steps.

[0045] Reference Figure 1B A redistribution circuit structure 110 is formed by forming a redistribution wiring layer 116 and a dielectric layer 114 on the release film 20 through thin film processes.

[0046] The reconfiguration wiring layer 116 can be formed by a build-up process. For example, the process of forming the reconfiguration wiring layer 116 includes the following steps. First, a seed layer is sputtered or deposited on the release film 20, wherein the material of the seed layer may be, for example, a conductive material such as titanium / copper. Then, a patterned photoresist layer is formed on the seed layer to expose the seed layer. A conductive material is formed on the seed layer exposed by the patterned photoresist layer through an electroplating process, and the conductive material may include copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), tungsten (W) or an alloy thereof. Then, the photoresist layer and the portion of the seed layer not covered by the conductive material are removed to form the reconfiguration wiring layer 116.

[0047] The method of forming the dielectric layer 114 may include spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), etc. The material of the dielectric layer 114 may include polyimide, epoxy resin, acrylic resin, phenolic resin, bismaleimide-trazine resin (BT resin) or any other suitable polymer dielectric material and silicon oxide layer, silicon nitride layer, silicon oxynitride layer or other suitable silicon dielectric material. The dielectric layer 114 may be a photosensitive insulating layer including a photosensitive insulating resin.

[0048] The reconfiguration circuit structure 110 may include a multi-layer or single-layer reconfiguration wiring layer 116. When the reconfiguration circuit structure 110 includes a multi-layer reconfiguration wiring layer 116, the process of forming the upper reconfiguration wiring layer 116 includes the following steps. First, an opening is formed in the dielectric layer 114 to expose the reconfiguration wiring layer 116 thereunder, wherein the method of forming the opening in the dielectric layer 114 may adopt different processes depending on the material of the dielectric layer 114. When the dielectric layer 114 is a photosensitive insulating layer including a photosensitive insulating resin, the dielectric layer 114 may be patterned by a photolithography process to form an opening. When the dielectric layer 114 is a non-photosensitive insulating layer, the dielectric layer 114 may be patterned by a photolithography / etching process, a laser drilling process, or a mechanical drilling process to form an opening. Refer to Figure 1B In the enlarged view, the upper width D of the opening formed in the dielectric layer 114 is T Can be larger than the lower width D B . That is, the angle α between the tapered sidewalls of the opening and the upper surface of the dielectric layer 114 may be greater than 90°. Then, the upper reconfiguration wiring layer 116 is formed in the same manner as the above-mentioned method of forming the reconfiguration wiring layer 116 to connect to the reconfiguration wiring layer 116 exposed through the opening of the dielectric layer 114. Although in the accompanying drawings, the reconfiguration wiring structure 110 is illustrated as including three layers of dielectric layers 114 and three layers of reconfiguration wiring layers 116, the present invention is not limited thereto, and the reconfiguration wiring structure 110 may include more or fewer layers of dielectric layers 114 and reconfiguration wiring layers 116 than those shown in the accompanying drawings.

[0049] Reference Figure 1C, a second conductive pillar 112 can be formed on the reconfiguration circuit structure 110. For example, the process of forming the second conductive pillar 112 includes the following steps. First, an opening is formed in the dielectric layer 114 of the reconfiguration circuit structure 110 to expose the reconfiguration wiring layer 116, wherein the method of forming the opening in the dielectric layer 114 may adopt different processes depending on the material of the dielectric layer 114. When the dielectric layer 114 is a photosensitive insulating layer including a photosensitive insulating resin, the dielectric layer 114 may be patterned by a photolithography process to form an opening. When the dielectric layer 114 is a non-photosensitive insulating layer, the dielectric layer 114 may be patterned by a photolithography / etching process, a laser drilling process, or a mechanical drilling process to form an opening. The upper width of the opening may be greater than the lower width. That is, the angle between the inclined sidewall of the opening and the upper surface of the dielectric layer 114 may be greater than 90°. Thereafter, a seed layer is formed on the dielectric layer 114. Then, a seed layer is formed on the surface of the reconfiguration wiring layer 116 and the dielectric layer 114. The material of the seed layer may be, for example, a conductive material such as titanium / copper. Then, a patterned photoresist layer is formed on the seed layer. The patterned photoresist layer may be formed using photolithography and / or etching processes. The opening of the patterned photoresist layer exposes the surface of the seed layer on the reconfiguration wiring layer 116. Then, a plurality of conductive columnar structures may be formed in the opening of the patterned photoresist layer. The formation method of the conductive columnar structure may be, for example, printing, electroplating, electroless plating or a combination thereof. Thereafter, the patterned photoresist layer and part of the seed layer are removed to form a second conductive column 112. The material of the second conductive column 112 may be formed using a metal or its alloy with excellent electrical properties, such as copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), tungsten (W) or its alloy.

[0050] Reference Figure 1DThe image sensor chip 120 can be attached to the reconfiguration circuit structure 110 through an adhesive layer 190 such as a chip bonding film (DAF). The image sensor chip 120 can be a complementary metal oxide semiconductor image sensor chip (CMOS image sensing chip). However, the present invention does not limit the type of the image sensor chip 120, and it can be other appropriate types of image sensor chips. The image sensor chip 120 can have a micro lens (Micro Lens) 123 on the sensing surface 120A, and the sensing area 122 of the image sensor chip 120 is below the micro lens 123. The micro lens 123 is covered with a cover 130. The cover 130 can be, for example, a transparent glass substrate. A sealing structure 125 such as a sealant is formed between the cover 130 and the micro lens 123 to separate the cover 130 and the micro lens 123 from each other. In addition, the sealing structure 125 can be used to define the space between the sealed cover 130 and the image sensor chip 120. The image sensor chip 120 has a first conductive column 121, and the first conductive column 121 is located around the sensing area 122 on the sensing surface 120A. The material of the first conductive column 121 can be formed by using a metal or an alloy thereof with excellent electrical properties, such as copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), tungsten (W) or an alloy thereof.

[0051] Reference Figure 1E and Figure 1F, forming an encapsulation body 140, wherein the encapsulation body 140 covers the image sensor chip 120 and the second conductive pillar 112. The material of the encapsulation body 140 may include a molding compound, a molding bottom filler, a resin or an epoxy molding compound (EMC), etc. If necessary, the encapsulation body 140 may be doped with an inorganic filler. The method for forming the encapsulation body 140 includes the following steps. An encapsulation material layer covering the reconfiguration circuit structure 110, the image sensor chip 120 and the second conductive pillar 112 is formed on the carrier 10 by a suitable process (such as a molding process or a deposition process), and the sealing structure 125 can prevent the encapsulation body 140 from entering the space between the cover body 130 and the image sensor chip 120. Thereafter, a planarization process (e.g., chemical mechanical polishing (CMP)) is performed to partially remove the encapsulation material layer and / or portions of the first conductive layer 121, the second conductive layer 112, and the cover 130 until the surfaces of the first conductive layer 121, the second conductive layer 112, and the cover 130 are exposed. That is, the upper surfaces of the first conductive pillars 121, the second conductive pillars 112, the cover 130, and the encapsulation body 140 may be located at the same level by the planarization process. In other words, the upper surfaces of the first conductive pillars 121, the second conductive pillars 112, the cover 130, and the encapsulation body 140 are coplanar. The first conductive pillars 121 and the second conductive pillars 112 may also slightly protrude from the upper surface of the encapsulation body 140. The first conductive pillars 121 and the second conductive pillars 112 may also be slightly recessed from the upper surface of the encapsulation body 140. When the upper surfaces of the first conductive pillars 121 and the second conductive pillars 112 are slightly recessed from the upper surface of the encapsulation body 140 , it is advantageous for the first conductive pillars 121 and the second conductive pillars 112 to be aligned and bonded to the upper semiconductor chip 150 in subsequent steps.

[0052] Herein, the height of the first conductive pillar 121 refers to the vertical distance from the sensing surface 120A of the image sensor chip 120 to the upper surface of the first conductive pillar 121, and the height of the second conductive pillar 112 refers to the vertical distance from the surface of the reconfiguration circuit structure 110 adjacent to the image sensor chip 120 to the upper surface of the second conductive pillar 112. The height of the second conductive pillar 112 may be greater than the height of the first conductive pillar 121. The width of the first conductive pillar 121 and the width of the second conductive pillar 112 may be the same as each other. Alternatively, the width of the first conductive pillar 121 and the width of the second conductive pillar 112 may be different from each other. For example, the height of the first conductive pillar 121 may be, for example, 50 micrometers to 250 micrometers, and the aspect ratio of the first conductive pillar 121 may be between 0.5 and 5. The height of the second conductive pillar 112 may be, for example, 75 micrometers to 300 micrometers, and the aspect ratio of the second conductive pillar 112 may be between 0.5 and 5.

[0053] Reference Figure 1G, providing the upper semiconductor chip 150 on the package 140 so that the first conductor 151 of the upper semiconductor chip 150 and the first conductive pillar 121 are aligned and bonded to each other, and the second conductor 152 of the upper semiconductor chip 150 and the second conductive pillar 112 are aligned and bonded to each other, thereby electrically connecting the upper semiconductor chip 150, the image sensor chip 130 and the reconfiguration circuit structure 110 to each other. In other words, the electrical connection between the first conductor 151 of the upper semiconductor chip 150 and the first conductive pillar 121 and the electrical connection between the second conductor 152 of the upper semiconductor chip 150 and the second conductive pillar 112 are not achieved through the reconfiguration circuit structure. In this case, not only the packaging process can be simplified, but also the electrical connection paths between the upper semiconductor chip 150 and the first conductive pillar 121 and the second conductive pillar 112 can be effectively shortened, thereby improving the communication performance between the upper semiconductor chip 150 and the image sensor chip 120.

[0054] The first conductor 151 of the upper semiconductor chip 150 overlaps the image sensor chip 120 in a direction perpendicular to the sensing surface 120A of the image sensor chip 120, and the second conductor 152 of the upper semiconductor chip 150 does not overlap the image sensor chip 120 in a direction perpendicular to the sensing surface 120A of the image sensor chip 120. The materials of the first conductor 151 and the second conductor 152 may include conductive materials such as copper (Cu), silver (Ag), palladium (Pd), aluminum (Al), nickel (Ni), titanium (Ti), gold (Au), platinum (Pt), tungsten (W) or alloys thereof. The shapes of the first conductor 151 and the second conductor 152 may include columnar or thumbtack-shaped bumps. The method of bonding the first conductor 151 to the first conductive pillar 121 and the bonding of the second conductor 152 to the second conductive pillar 112 may be, for example, direct bonding by heating or bonding using bonding metal. For example, a bonding metal such as solder alloy, copper, gold, silver, indium, palladium, titanium, manganese, cobalt, or an alloy thereof may be disposed between the first conductor 151 and the first conductive column 121 and between the second conductor 152 and the second conductive column 112, and heated to bond the first conductor 151 and the first conductive column 121 and the second conductor 152 and the second conductive column 112. The bonding of the first conductor 151 and the first conductive column 121 and the bonding of the second conductor 152 and the second conductive column 112 may not use solder. In other words, the bonding of the first conductor 151 and the first conductive column 121 and the bonding of the second conductor 152 and the second conductive column 112 may not use solder alloy. In other words, the bonding surface between the first conductor 151 and the first conductive column 121 may be a solder-free bonding surface, and the bonding surface between the second conductor 152 and the second conductive column 112 may also be a solder-free bonding surface. The bonding metal may be a low-temperature bonding metal having a melting point below 200°C. For example, the low temperature bonding metal may include twinned copper, twinned silver or other nano twinned materials, indium tin alloy, tin bismuth alloy, porous gold or a combination thereof. Compared to the conventional solder balls or solders which require a reflow temperature of more than or equal to 250°C, the use of low temperature bonding metals can achieve stable bonding of the connection structure at a relatively low heating temperature (e.g., at a temperature below 200°C or below 150°C) and meet the reliability requirements of the electrical connection requirements.

[0055] Figure 1G 1 and 2 , the image sensor package includes two upper semiconductor chips 150, but the present invention is not limited thereto. The upper semiconductor chip 150 may include a single upper semiconductor chip 150 or a plurality of upper semiconductor chips 150 arranged side by side on the encapsulation body 140. The plurality of upper semiconductor chips 150 may be identical to each other. Alternatively, the plurality of upper semiconductor chips 150 may be different from each other. The upper semiconductor chip 150 may include a memory chip, an application processor chip, a logic chip, an artificial intelligence (AI) chip, etc.

[0056] Continue to refer to Figure 1G , an underfill 160 may be applied on the encapsulation body 140 to encapsulate the first conductor 151 and the second conductor 152. The underfill 160 may fill the space between the upper semiconductor chip 150 and the encapsulation body 140 and encapsulate the first conductor 151 and the second conductor 152. Figure 1G As shown, the bottom filler 160 has an inclined sidewall, and the upper width of the bottom filler 160 is, for example, smaller than the lower width of the bottom filler 160. In some embodiments, the width of the bottom filler 160 is gradual, and the width of the bottom filler 160 gradually decreases from one end closer to the encapsulation body 140 toward the other end closer to the upper semiconductor chip 150.

[0057] Reference Figure 1G and Figure 1H , a release process is performed to make Figure 1H The structure shown in FIG. 1 is separated from the carrier 10 and the release film 20. When the release film 20 is formed by ultraviolet glue, the above release process can irradiate ultraviolet light on the release film 20 to make the release film 20 lose or reduce its viscosity, thereby allowing the carrier 10 and the release film 20 to be separated from each other. Figure 1H When the release film 20 is formed by the photothermal conversion adhesive, the above release process can irradiate the release film 20 with light of appropriate energy, so that the release film 20 is decomposed under the heat energy of the light and loses or reduces its viscosity, thereby allowing the carrier 10 and the release film 20 to be separated from each other. Figure 1H The structures shown in are separated.

[0058] Next, a plurality of conductive terminals 170 may be formed on the surface of the reconfigured circuit structure 110 that is separated from the carrier 10 and the release film 20 to complete the Figure 2 The image sensor package 100 of the present invention is shown. The conductive terminal 170 is, for example, a solder ball, but the present invention is not limited thereto. A plurality of image sensor packages 100 of the present invention can be formed simultaneously on a large-sized wafer, and then individual image sensor packages 100 can be separated by a process such as cutting. Therefore, the sidewall of the encapsulation body 140 in the image sensor package 100 of the present invention can be aligned with the sidewall of the reconfiguration circuit structure 110.

[0059] Reference Figure 2In the image sensor package 100 of the present invention, the image sensor chip 120 and the upper semiconductor chip 150 are connected to each other through the first conductive pillar 121 of the image sensor chip 120 and the first conductor 151 of the upper semiconductor chip 150. In other words, no circuit layer is provided between the image sensor chip 120 and the upper semiconductor chip. Since the image sensor chip 120 and the upper semiconductor chip 150 are connected not through the circuit layer but through the first conductive pillar 121 of the image sensor chip 120 and the first conductor 151 of the upper semiconductor chip 150, the transmission path of the power and / or signal between the image sensor chip 120 and the upper semiconductor chip 150 can be shortened, thereby improving the transmission speed and quality of the power and / or signal.

[0060] In the present embodiment, a plurality of upper semiconductor chips 150 arranged side by side can be connected to each other through the wiring structure inside the image sensor chip 120. Generally speaking, a plurality of semiconductor chips arranged side by side are connected to each other using a circuit layer or a welding wire. In a general circuit layer, the line width and the line spacing are both about 2 microns, the width of the via is about 5 microns, the width of the connection pad is about 7 microns, and the number of layers is generally 3. In the wiring structure inside the image sensor chip, the line width and the line spacing are both about 0.4 microns, the width of the via is about 0.4 microns, the width of the connection pad is about 0.7 microns, and the number of layers is generally 4. In other words, the wiring structure inside the image sensor chip has a higher line density and a larger number of layers. In the present embodiment, an image sensor chip 120 having a high-density and multi-layer connection capability is used for connection, so compared with the use of a general circuit layer for connection, the image sensor package 100 of the present embodiment can achieve high-bandwidth signal connection.

[0061] In the present embodiment, the reconfiguration circuit structure 110 and the upper semiconductor chip 150 can be connected to each other through the second conductive pillars 112 and the second conductors 152 of the upper semiconductor chip 150. Therefore, the aspect ratio of the second conductive pillars 112 can be adjusted to provide a transmission path for other signals and large currents (such as ground) between the reconfiguration circuit structure 110 and the upper semiconductor chip 150.

[0062] In this embodiment, the signal transmission path of the image sensor chip 120 can be connected to the external signal through the first conductive column 121, the upper semiconductor chip 150, the second conductive column 112, the reconfiguration circuit structure 110 and then through the conductive terminal 170. Therefore, the production of through silicon vias (TSV) can be omitted, thereby reducing the production cost of the image sensor package 100.

[0063] Figure 3 FIG. 4 is a cross-sectional schematic diagram illustrating an image sensor package according to another embodiment of the present invention.

[0064] Reference Figure 3 According to another embodiment of the present invention, an image sensor package 200 includes a semiconductor element 220. The semiconductor element 220 may include a plurality of chips having different functions. For example, the semiconductor element 220 may include an image sensor chip 230 and a lower semiconductor chip 240 stacked up and down. The lower semiconductor chip 240 may be a memory chip, a processor chip and / or a logic chip depending on the function of the image sensor package 200. The image sensor chip 230 and the lower semiconductor chip 240 may be connected to each other through a first connection conductor 230P of the image sensor chip 230 and a second connection conductor 240P of the lower semiconductor chip 240. Since the electrical path between the image sensor chip 230 and the lower semiconductor chip 240 is short, rapid signal transmission can be achieved.

[0065] Descriptions of configurations other than those described above and the like may overlap with the description provided above in the image sensor package 100 , and thus will not be described in detail.

[0066] In summary, the image sensor package of the present invention can shorten the transmission path of power and / or signals in the image sensor package and improve the overall performance of the image sensor package.

[0067] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An image sensor package, characterized in that: include: Reconfigure the circuit structure; An image sensor chip is arranged on the reconfigured circuit structure and has a sensing surface, wherein the sensing surface is arranged with a sensing area and a first conductive column, and the first conductive column is arranged in parallel in a surrounding area next to the sensing area; A cover body, covering the sensing area; An encapsulation body, disposed on the reconfiguration circuit structure and the image sensor chip and encapsulating the image sensor chip and at least a portion of the cover body so that the cover body exposes an upper surface; and an upper semiconductor chip adjacent to the exposed upper surface of the cover, the upper semiconductor chip being disposed on a common plane formed by the upper surfaces of the encapsulation body and the cover, and having first conductors disposed in parallel on an active surface of the upper semiconductor chip, Each of the first conductors is aligned with and joined to each of the first conductive pillars along a direction perpendicular to the sensing surface to electrically connect the image sensor chip and the upper semiconductor chip. 2 . The image sensor package according to claim 1 , wherein the upper semiconductor chip comprises a plurality of upper semiconductor chips arranged side by side with each other on the encapsulation body.

3. The image sensor package according to claim 1 , further comprising a second conductive column penetrating the encapsulation body, and A second conductor is further disposed on the active surface of the upper semiconductor chip, and the second conductor does not overlap with the image sensor chip in a direction perpendicular to the sensing surface, and The second conductive pillar is bonded to the second conductor to electrically connect the upper semiconductor chip and the reconfiguration circuit structure. The image sensor package of claim 3 , wherein a height of the second conductive pillar is greater than a height of the first conductive pillar. 5 . The image sensor package of claim 3 , wherein a joint interface between the first conductive pillar and the first conductor is a solder-free joint interface, and a joint interface between the second conductive pillar and the second conductor is a solder-free joint interface. 6 . The image sensor package according to claim 1 , wherein the first conductive pillar is bonded to the first conductor by a bonding metal having a melting point lower than 200° C. 7 . The image sensor package according to claim 1 , wherein the upper semiconductor chip comprises at least one of a logic chip, a memory chip, and an artificial intelligence chip. 8 . The image sensor package of claim 1 , wherein a sidewall of the encapsulation body is aligned with a sidewall of the reconfiguration circuit structure.

9. An image sensor package, comprising: Reconfigure the circuit structure; A semiconductor element is arranged on the reconfiguration circuit structure, wherein the semiconductor element comprises an image sensor chip, wherein the image sensor chip has a sensing surface, wherein a sensing area and a first conductive column are arranged in parallel in a surrounding area next to the sensing area; A cover body, covering the sensing area; An encapsulation body, disposed on the reconfiguration circuit structure and the image sensor chip and encapsulating the semiconductor element and at least a portion of the cover body so that the cover body exposes an upper surface; and An upper semiconductor chip is disposed on the same plane formed by the upper surfaces of the encapsulation body and the cover body, and a first conductor is disposed in parallel on the active surface of the upper semiconductor chip. Each of the first conductors is aligned with and joined to each of the first conductive pillars along a direction perpendicular to the sensing surface to electrically connect the image sensor chip and the upper semiconductor chip. 10 . The image sensor package according to claim 9 , wherein the upper semiconductor chip comprises a plurality of upper semiconductor chips arranged side by side above the semiconductor element.

11. The image sensor package according to claim 9, further comprising a second conductive column penetrating the encapsulation body, and A second conductor is further disposed on the active surface of the upper semiconductor chip, and the second conductor does not overlap with the semiconductor element in a direction perpendicular to the sensing surface, and The second conductive pillar is bonded to the second conductor to electrically connect the upper semiconductor chip and the reconfiguration circuit structure. 12 . The image sensor package of claim 11 , wherein a height of the second conductive pillar is greater than a height of the first conductive pillar. 13 . The image sensor package of claim 11 , wherein a joint between the first conductive pillar and the first conductor is a solder-free joint, and a joint between the second conductive pillar and the second conductor is a solder-free joint.

14. The image sensor package according to claim 9, wherein The semiconductor element further includes a lower semiconductor chip, which is stacked on top of the image sensor chip and is disposed between the reconfiguration circuit structure and the image sensor chip. The image sensor chip comprises a first connection conductor, which is arranged on a surface of the image sensor chip opposite to the sensing surface. The lower semiconductor chip has a second connection conductor disposed on a surface of the lower semiconductor chip facing the image sensor chip, and The first connecting conductor and the second connecting conductor are bonded to each other to electrically connect the image sensor chip and the lower semiconductor chip. 15 . The image sensor package of claim 9 , wherein a sidewall of the encapsulation body is aligned with a sidewall of the reconfiguration circuit structure. 16 . The image sensor package of claim 9 , wherein the first conductive pillar is bonded to the first conductor by a bonding metal having a melting point lower than 200° C.

17. A method for manufacturing an image sensor package, comprising: An image sensor chip is arranged on the reconfigured circuit structure, wherein a cover body and parallel first conductive pillars are arranged on a sensing surface of the image sensor chip, and the parallel first conductive pillars surround the cover body on the sensing surface; Disposing an encapsulation body on the reconfiguration circuit structure, the image sensor chip, and the cover body to encapsulate the image sensor chip and the cover body; performing a planarization process to expose the first conductive pillar and the upper surface of the cover from the encapsulant on a coplanar surface formed by the upper surfaces of the encapsulant and the cover; as well as An upper semiconductor chip is disposed on the package so that a first conductor of the upper semiconductor chip is aligned with and bonded to an upper surface of the first conductive pillar in a direction perpendicular to the sensing surface to electrically connect the image sensor chip and the upper semiconductor chip.

18. The method for manufacturing an image sensor package according to claim 17, further comprising: disposing a second conductive column on a peripheral portion of the reconfiguration circuit structure; as well as The second conductive pillar is bonded to a second conductor of the upper semiconductor chip to electrically connect the upper semiconductor chip and the reconfiguration circuit structure, wherein the second conductor does not overlap with the image sensor chip in a direction perpendicular to the sensing surface. 19 . The method of manufacturing an image sensor package according to claim 17 , wherein the first conductor is bonded to the first conductive pillar at a temperature of 200° C. or lower.

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