Microcontroller unit for display device and data communication

Abstract

The present invention provides a display device and a microcontroller unit for data communication. The present invention, which relates to data communication between a microcontroller and a source readout circuit, does not require a clock circuit of a slave device, thereby enabling reduction in the size of the slave device circuit and lowering power consumption.

Description

Technical Field

[0001] Embodiments relate to techniques for data communication between a microcontroller unit and a source readout integrated circuit (IC). Background Art

[0002] A large amount of data may be sent and received between internal circuits in a display device. This data may include image data containing information about images to be displayed on the panel, or control data for controlling the internal circuits to display these images. Thus, a protocol for sending and receiving data is also needed. For example, the protocol may include details about whether a synchronous method or an asynchronous method is used for communication, or details about the sequence of exchanging data when a synchronous method is used for communication.

[0003] Typically, data communication between internal circuits of a display device may be based on a serial peripheral interface (SPI) or an inter-integrated circuit (I2C). In the SPI or I2C scheme, if the clock is delayed by one or more cycles in the communication between the master device and the slave device, the master device cannot read the received data. Due to concerns about delays, there may be limitations in increasing the communication speed in the SPI or I2C scheme. To address this problem, the slave device may send data to the master device together with the clock.

[0004] However, in order to transmit the clock, the slave device must include a circuit for generating the clock internally. If the slave device includes a clock circuit internally, the size of the slave device circuit increases. In the SPI or I2C scheme, one master device communicates with multiple slave devices. In this case, if each of the multiple slave devices includes a clock circuit internally, the size of the display device in the entire system may increase.

[0005] In addition, since the clock circuit also consumes power, the power consumption may increase in proportion to the number of clock circuits provided.

[0006] In connection with this, the embodiment is directed to providing a data communication method of a display device improved in order to reduce the size of a circuit and lower power consumption. Summary of the invention

[0007] In this context, an object of an embodiment is to provide a technique in which a master device recovers data even if a slave device sends data to the master device without a clock.

[0008] Another object of an embodiment is to provide a technique in which a master device recovers data by sampling received data using a plurality of repetitive clocks having different phases.

[0009] Another object of the embodiment is to provide a technique in which a master device aligns data in byte or word units by adding a predetermined signal form to the data.

[0010] To this end, on one hand, the present invention provides a display device, comprising: a microcontroller unit, which is configured to send a master signal together with a clock; and a source readout integrated circuit, i.e., a source readout IC, which is configured to recover master data from the master signal according to the clock, and send a slave signal generated according to the clock to the microcontroller unit, wherein the microcontroller unit is configured to sample the slave signal according to multiple sampling clocks having the same frequency as the clock to generate multiple sampling data, and use the multiple sampling data to recover the slave data.

[0011] In the display device, the plurality of sampling clocks may have different phases, respectively.

[0012] In the display device, the source readout IC may not transmit a clock corresponding to the slave data.

[0013] In the display device, the microcontroller unit may sample the slave signal at a rising edge or a falling edge of the plurality of sampling clocks.

[0014] In the display device, the microcontroller unit may determine data accounting for a majority of the plurality of sampled data as the slave data.

[0015] In the display device, the microcontroller unit may generate N sampling clocks, where N is a natural number of 3 or more.

[0016] In the display device, N may be an odd number, and wherein the microcontroller unit may compare bit values ​​of the plurality of sampling data and determine a bit value accounting for the majority of the bit values ​​of the plurality of sampling data as a bit value of the slave data.

[0017] In the display device, the plurality of sampling clocks may have a uniform phase difference therebetween.

[0018] In the display device, the microcontroller unit and the source readout IC may transmit and receive the clock via a signal line in which a delay occurs.

[0019] In the display device, the microcontroller unit may divide the slave signal into predetermined units and sample the divided slave signal.

[0020] In the display device, the slave signal may include a pattern indicating a start time of a predetermined unit, and wherein the microcontroller unit may divide the slave signal based on the pattern.

[0021] In the display device, the microcontroller unit may transmit a read command using the master data, and wait for reception of the slave data after transmitting the read command.

[0022] In the display device, the slave data may be data in a serial form, and wherein the microcontroller unit may convert the plurality of sampling data from a serial form into a parallel form, store the plurality of sampling data in a parallel form in a storage unit, compare the data stored in the storage unit, and restore the slave data.

[0023] In the display device, one of the plurality of sampling clocks may be the clock.

[0024] On the other hand, the present invention provides a microcontroller unit for sending a master signal together with a clock to a slave device, the microcontroller unit comprising: a plurality of data alignment units configured to receive slave signals from the slave device and generate sampled data by sampling the slave signals according to a sampling clock having a frequency identical to that of the clock; and a data selection unit configured to compare the sampled data generated by the plurality of data alignment units to recover the slave data included in the slave signal.

[0025] In the microcontroller unit, the sampling clock may be the clock, or a clock having a phase different from that of the clock.

[0026] In the microcontroller unit, the data alignment unit may sample the slave signal at a rising edge or a falling edge of the sampling clock.

[0027] The microcontroller unit may further include a storage unit in which the sampled data is stored, and the sampled data is read out from the storage unit in a first-in-first-out (FIFO) manner using the data selection unit.

[0028] In the microcontroller unit, the slave data may be data in a serial form, and wherein the data alignment unit may convert the sampling data from a serial form into a parallel form and store the sampling data in the parallel form in the storage unit.

[0029] As described above, according to the embodiment, since a clock is not used when data is transmitted from a slave device to a master device, a clock circuit of the slave device is not required, and thus the size of the slave device circuit can be reduced.

[0030] In addition, according to the embodiment, since a clock circuit of the slave device is not required, the power consumption of the slave device can be reduced accordingly. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects, features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0032] Figure 1 is a diagram showing a structure of a display device according to an embodiment.

[0033] Figure 2 1 is a diagram showing the connection between a microcontroller unit, a source readout IC, and a panel in the prior art.

[0034] Figure 3 is a diagram showing the connection of a microcontroller unit, a source readout IC, and a panel according to an embodiment.

[0035] Figure 4 is a diagram showing a first example of communication between a microcontroller unit and a source readout IC according to the embodiment.

[0036] Figure 5 is a diagram showing a second example of communication between the microcontroller unit and the source readout IC according to the embodiment.

[0037] Figure 6 is a diagram showing waveforms of clocks and data transmitted and received between a microcontroller unit and a source readout IC according to an embodiment.

[0038] Figure 7 is a diagram illustrating an operation of a microcontroller unit sampling delayed slave data according to an embodiment.

[0039] Figure 8 is a diagram illustrating sampling with errors according to an embodiment.

[0040] Fig. 9 is a diagram showing sampling without errors according to an embodiment.

[0041] Fig.10 is a diagram illustrating an operation of a microcontroller unit aligning slave data according to an embodiment.

[0042] Fig.11 is a diagram showing a structure of a microcontroller unit according to an embodiment. DETAILED DESCRIPTION

[0043] Figure 1 is a diagram showing a structure of a display device according to an embodiment.

[0044] refer to Figure 1 , the display device 100 may include a panel 110 , a source readout IC (SRIC) 120 , a gate drive IC (GDIC) 130 , and a timing controller (TCON) 140 .

[0045] A plurality of data lines DL and a plurality of gate lines GL may be arranged on the panel 110, and a plurality of pixels may be arranged on the panel 110. A pixel may include a plurality of sub-pixels SP. Here, the sub-pixel may be a red sub-pixel (R), a green sub-pixel (G), a blue sub-pixel (B), or a white sub-pixel (W), etc. One pixel may be configured as an RGB sub-pixel SP, an RGBG sub-pixel SP, or an RGBW sub-pixel SP, etc. Hereinafter, for convenience, it will be assumed that one pixel is configured as an RGB sub-pixel SP for explanation.

[0046] The source readout IC 120 , the gate drive IC 130 , and the timing controller 140 are devices that generate signals for displaying an image on the panel 110 .

[0047] The gate driving IC 130 may supply a gate driving signal of a turn-on voltage or a turn-off voltage to the gate line GL. If the gate driving signal of the turn-on voltage is supplied to the sub-pixel SP, the sub-pixel SP is connected to the data line DL. In addition, if the gate driving signal of the turn-off voltage is supplied to the sub-pixel SP, the connection between the sub-pixel SP and the data line DL is released.

[0048] The source readout IC 120 may include a source driver inside. The source driver may supply a data voltage to the sub-pixel SP via the data line DL. The data voltage supplied to the data line DL may be supplied to the sub-pixel SP according to a gate driving signal.

[0049] In addition, the source readout IC 120 may include a readout IC (ROIC) inside. The readout IC may be embedded in the source readout IC 120 together with the source driver. The readout IC may sense a touch input by driving electrodes around the sub-pixel SP. The source readout IC 120 may drive the electrodes via the touch line TL and may receive an analog signal output from the electrodes.

[0050] The source readout IC 120 may be connected to a bonding pad of the panel 110 by a tape automated bonding (TAB) type or a chip on glass (COG) type, or may be directly formed on the panel 110, and according to an embodiment, the source readout IC 120 may be formed to be integrated on the panel 110. In addition, the source readout IC 120 may be implemented by a chip on film (COF) type.

[0051] The timing controller 140 may supply control signals to the gate drive IC 130 and the source readout IC 120. For example, the timing controller 140 may send a gate control signal GCS for starting scanning to the gate drive IC 130. In addition, the timing controller 140 may output image data RGB to the source readout IC 120. In addition, the timing controller 140 may send a data control signal DCS that controls the source readout IC 120 to supply a data voltage to each sub-pixel SP. In addition, the timing controller 140 may send a touch control signal TCS that controls the source readout IC 120 to drive the electrodes of each sub-pixel SP and sense a touch input.

[0052] Figure 2 1 is a diagram showing the connection between a microcontroller unit, a source readout IC, and a panel in the prior art.

[0053] refer to Figure 2 , the conventional display device 10 may further include a microcontroller unit (MCU) 15. A plurality of source readout ICs 12 may be configured to be included in the display device 100.

[0054] The microcontroller unit 15 and the source readout IC 12 can communicate with each other based on a serial peripheral interface (SPI) scheme or an inter-integrated circuit (I2C) scheme. In the SPI or I2C scheme, the communication entity can operate as a master device and a slave device, that is, the microcontroller unit 15 can operate as a master device, and a plurality of source readout ICs 12 can operate as slave devices.

[0055] The first communication line LN1 and the second communication line LN2 may be differential signal lines configured as two signal lines, or may be a single signal line operating in an open drain manner.

[0056] The microcontroller unit 15 may send a master clock CLKm to a plurality of source readout ICs 12 via a first communication line LN1. The master clock CLKm may be generated by the microcontroller unit 150. The master clock CLKm may be synchronized with the master data MDAT, and the master data MDAT may be sent according to the master clock CLKm. In addition, a plurality of source readout ICs 12 may send a slave clock CLKs to the microcontroller unit 15 via a first communication line LN1. The slave clock CLKs may be generated by the source readout IC 12. The slave clock CLKs may be synchronized with the slave data SDAT, and the slave data SDAT may be sent according to the slave clock CLKs.

[0057] The microcontroller unit 15 may transmit master data MDAT to the plurality of source readout ICs 12 via the second communication line LN2. The master data MDAT may be data transmitted from the microcontroller unit 15 as a master device to the source readout IC 12. In addition, the plurality of source readout ICs 12 may transmit slave data SDAT to the microcontroller unit 15 via the second communication line LN2. Here, the slave data SDAT may be synchronized with the slave clock CLKs of the first communication line LN1. In addition, the slave data SDAT may be data transmitted from the plurality of source readout ICs 12 as slave devices to the microcontroller unit 15.

[0058] As described above, the method of synchronizing the clock (e.g., the master clock CLKm and the slave clock CLKs) with the data (e.g., the master data MDAT and the slave data SDAT) in the bidirectional communication may require a circuit for generating the clock in the slave device. In the case of multiple slave devices, if there is a clock circuit for each slave device, the overall size of the circuit may increase due to these clock circuits.

[0059] On the other hand, a plurality of source readout ICs 12 may be connected to the panel 11. Each source readout IC 12 may be allocated to a uniformly divided area in the panel 11, and may be connected to a sub-pixel SP in the allocated area via a data line DL and a touch line TL.

[0060] Figure 3 is a diagram showing the connection of a microcontroller unit, a source readout IC, and a panel according to an embodiment.

[0061] refer to Figure 3 The display device 100 according to the embodiment may not include a clock transmitted from the plurality of source readout ICs 120 as slave devices to the microcontroller unit 150. That is, communication from the slave device to the master device may be performed without synchronization of the clock.

[0062] The microcontroller unit 150 may transmit the clock CLK to the plurality of source readout ICs 120 via the first communication line LN1. The clock CLK may be generated by the microcontroller unit 150. The clock CLK may be synchronized with the main data MDAT, and the main data MDAT may be transmitted according to the clock CLK. However, the source readout IC 120 may not transmit any clock to the microcontroller unit 150 via the first communication line LN1.

[0063] The microcontroller unit 150 may transmit the master data MDAT to the plurality of source sensing ICs 120 via the second communication line LN2. In addition, the plurality of source sensing ICs 120 may transmit the slave data SDAT to the microcontroller unit 150 via the second communication line LN2. Here, the slave data SDAT may not be synchronized with the clock.

[0064] As described above, if a clock is not used in communication from a slave device to a master device during bidirectional communication, the slave device may not need a circuit for generating a clock. Thus, since there is no clock circuit, the slave device circuit can become smaller.

[0065] Figure 4 is a diagram showing a first example of communication between a microcontroller unit and a source readout IC according to the embodiment.

[0066] refer to Figure 4 , the microcontroller unit 150 and the source readout IC 120 can communicate based on the I2C scheme. In the I2C communication, the microcontroller unit 150 can operate as a master device, and the plurality of source readout ICs 120 can operate as slave devices. Figure 3 In the embodiment, the communication between the microcontroller unit 150 and the source readout IC 120 may be performed through an I2C scheme.

[0067] The first communication line LN1 and the second communication line LN2 may connect the microcontroller unit 150 and the plurality of source readout ICs 120. The first communication line LN1 and the second communication line LN2 may be configured as a common bus.

[0068] The microcontroller unit 150 may transmit the clock CLK to the source sensing IC 120 via the SCL terminal. In addition, the microcontroller unit 150 may transmit the master data MDAT to the source sensing IC 120 via the SDA terminal. On the other hand, the source sensing IC 120 may transmit the slave data SDAT to the microcontroller unit 150 via the SDA terminal.

[0069] Figure 5 is a diagram showing a second example of communication between the microcontroller unit and the source readout IC according to the embodiment.

[0070] refer to Figure 5 The microcontroller unit 150 and the source readout IC 120 may communicate based on a serial peripheral interface (SPI) scheme. In the SPI communication, the microcontroller unit 150 may operate as a master device, and the plurality of source readout ICs 120 may operate as slave devices.

[0071] The microcontroller unit 150 may send the clock CLK to the source readout IC 120 via the CLK_P terminal. In addition, the microcontroller unit 150 may send the master data MDAT to the source readout IC 120 via the MOSI terminal. In addition, the source readout IC 120 may send the slave data SDAT to the microcontroller unit 150 via the MISO terminal. In addition, the microcontroller unit 150 may send the selection signal SEL to the source readout IC 120 via the SS terminal, thereby selecting one of the plurality of source readout ICs 120 to transmit and receive data.

[0072] Here, communication lines for transmitting the clock CLK, the master data MDAT, and the slave data SDAT may be configured as a common bus.

[0073] Figure 6 is a diagram showing waveforms of clocks and data transmitted and received between a microcontroller unit and a source readout IC according to an embodiment.

[0074] refer to Figure 6 , the microcontroller unit as a master device and the source readout IC as a slave device can use the clock CLK to perform synchronous communication.

[0075] The microcontroller unit can generate a clock CLK and master data MDAT. The clock CLK can be generated from a clock signal generated by an internal oscillator (not shown). The microcontroller unit can send the master data MDAT to the source readout IC according to the clock CLK. For example, the master data MDAT can be synchronized at the rising edge of the clock CLK from a low level to a high level. The source readout IC can read the value of the master data MDAT at the timing of the rising edge of the clock CLK. In addition, the master data MDAT can be synchronized at the falling edge of the clock CLK from a high level to a low level. The source readout IC can read the value of the master data MDAT at the timing of the falling edge of the clock CLK.

[0076] The source readout IC can receive the delayed clock CLK and the delayed master data MDAT. Here, since the clock CLK and the master data MDAT are sent from the master device to the destination slave device via the same path at the same timing, the delay time of the clock CLK and the delay time of the master data MDAT can be the same. Figure 6 In the example, the delay time can be represented as “Td”.

[0077] The source readout IC can generate slave data SDAT. Conventionally, the source readout IC can send the slave data SDAT to the microcontroller unit according to the clock CLK used by the microcontroller unit to send the master data MDAT. For example, the slave data SDAT can be synchronized at the rising edge or falling edge of the clock CLK generated by the microcontroller unit and can be sent to the microcontroller unit.

[0078] Like the source readout IC, the microcontroller unit can also receive delayed slave data SDAT. Here, if the source readout IC uses the clock CLK generated by the microcontroller unit to send the slave data SDAT to the microcontroller unit, based on the clock CLK, the slave data SDAT may be delayed again by the delay time Td of the master data MDAT. Therefore, the delay time of the slave data SDAT may be 2Td (Td+Td=2Td).

[0079] By comparing the master data MDAT with the slave data SDAT based on the clock CLK, since the master data MDAT is synchronized with the clock CLK and has the same delay, the source readout IC has no difficulty in reading the master data MDAT, but since the slave data SDAT is delayed by 2Td relative to the clock CLK, the microcontroller unit may have problems in reading the slave data SDAT. For example, the source readout IC can sample all of the first to fourth transmission bits TXD1 to TXD4 at four rising edges of the clock CLK, but the microcontroller unit can sample only the first to third reception bits RXD1 to RXD3, although the microcontroller unit must sample the first to fourth reception bits RXD1 to RXD4.

[0080] Therefore, since the microcontroller unit as the master device and the source read IC as the slave device use the clock CLK used when sending the master data MDAT to send the slave data SDAT, the microcontroller unit may not be able to correctly sample the slave data SDAT, resulting in errors when reading data.

[0081] Figure 7 is a diagram illustrating an operation of a microcontroller unit sampling delayed slave data according to an embodiment.

[0082] refer to Figure 7 , the microcontroller unit can send a clock CLK and first data synchronized with the clock CLK, and can receive second data. The source readout IC can generate second data and can send the second data to the microcontroller unit. The microcontroller unit can determine a plurality of sampling points, can sample a signal corresponding to the second data at the plurality of sampling points to generate a plurality of sampled data, and can restore the second data from the plurality of sampled data.

[0083] Here, the first data may correspond to the master data MDAT. The second data may correspond to the slave data SDAT. The recovery of the slave data SDAT may be achieved by sampling the slave signal corresponding to the slave data SDAT at multiple sampling points to generate multiple sampled data, and comparing and selecting the multiple sampled data. The result of comparing and selecting the multiple sampled data may include the same value as the value of the second data (i.e., the slave data SDAT).

[0084] Specifically, if a delayed slave signal is sent to the microcontroller unit, the slave signal may be sampled by the microcontroller unit.

[0085] The slave signal may be delayed for a specific amount of time (e.g., 2Td) and then sent to the microcontroller unit as the master device. Although the slave signal may arrive at the microcontroller unit in a delayed state relative to the clock CLK used when sending the master signal corresponding to the master data MDAT, the slave signal may have the same frequency as the frequency of the clock CLK.

[0086] In addition, the microcontroller unit can sample the slave signal and read the slave signal.In order to determine the sampling timing of the slave signal, the microcontroller unit can use a repetitive clock.

[0087] The microcontroller unit may generate at least two or more repetitive clocks. Preferably, the microcontroller unit may generate three or more repetitive clocks, and may sample the slave signal. Multiple sampled values ​​may be obtained by sampling any one bit in the slave signal using multiple repetitive clocks, and the multiple sampled values ​​may have as many 0s or 1s as the number of sampling times. The microcontroller unit is required to determine the final bit value from "0" and "1". In this case, the microcontroller unit may determine "0" or "1" that accounts for the majority of the multiple sampled values ​​(e.g., half or more of the number of sampled values) as the final bit value. Therefore, since the majority can be selected from "0" and "1" only when there are a large number of candidate groups (i.e., a large number of sampled values), the number of repetitive clocks required for sampling may be two or more. Preferably, since one of "0" and "1" is required to be more dominant or more frequent than the other, the number of repetitive clocks may be an odd number of 3 or more. Determining the final bit value from multiple sampled values ​​will be described later.

[0088] To copy the clock, if a slave signal is received, the microcontroller unit can copy the clock CLK previously generated for the master signal, thereby generating a plurality of sampling clocks CLK_1, CLK_2, and CLK_3. The microcontroller unit can use the clock CLK itself as the object of copying as one of the sampling clocks CLK_1, CLK_2, and CLK_3.

[0089] There may be phase differences between the sampling clocks CLK_1, CLK_2, and CLK_3, and these phase differences may be consistent between the sampling clocks. For example, the sampling clocks CLK_1, CLK_2, and CLK_3 may have the same phase difference θ1, and θ1 may be 120 degrees. That is, the phase difference between the first sampling clock CLK_1 and the second sampling clock CLK_2, the phase difference between the second sampling clock CLK_2 and the third sampling clock CLK_3, and the phase difference between the first sampling clock CLK_1 and the third sampling clock CLK_3 may be θ1 is 120 degrees, respectively.

[0090] The microcontroller unit can sample the slave signal using sampling clocks CLK_1, CLK_2, and CLK_3. The microcontroller unit can read the slave signal at the corresponding edges of the sampling clocks CLK_1, CLK_2, and CLK_3. The sampling time can be a rising edge or a falling edge. Here, for convenience, the description will be based on the rising edge.

[0091] For example, the microcontroller unit may sample the first reception bit RXD1 of the slave signal at the rising edges of the first to third sampling clocks CLK_1, CLK_2, and CLK_3. The microcontroller unit may read the first reception bit RXD1 at the rising edges of the respective clocks. Subsequently, the microcontroller unit may read the other reception bits RXD2 and RXD3 by sampling the other reception bits RXD2 and RXD3 at the rising edges of the respective clocks.

[0092] Figure 8 is a diagram illustrating sampling with errors according to an embodiment.

[0093] refer to Figure 8 , in order to sample the slave signal corresponding to the slave data SDAT, multiple sampling clocks CLK_1, CLK_2 and CLK_3 may have specific conditions. The condition may be that a predetermined time period of multiple sampling clocks CLK_1, CLK_2 and CLK_3 is required to overlap with the data segment of the slave signal. The data segment is an area including touch data sent from the source readout IC, and may include a bit period Tb. At the same time, the condition may be that a predetermined time period of multiple sampling clocks CLK_1, CLK_2 and CLK_3 is required to overlap with the bit period Tb of the slave signal. The predetermined time period may be defined as a valid time period for the microcontroller unit to identify the slave signal. Only when the valid time period falls within the bit period Tb can the bit value of the bit period Tb be accurately sampled. If the valid time period falls outside the bit period Tb, an error may occur when sampling the bit value of the bit period Tb.

[0094] The microcontroller unit can replicate the clock so that the multiple sampling clocks CLK_1, CLK_2 and CLK_3 have an effective time period. The effective time period can be a period of time and can include a setup time period Ts and a holding time period Th. In order for the microcontroller unit to sample at a specific sampling time (for example, at a rising edge), the setup time period Ts and the holding time period Th on both sides of the sampling time are required to fall within the bit period Tb.

[0095] The setting time period Ts and the holding time period Th are time periods in which the levels of the multiple sampling clocks CLK_1, CLK_2, and CLK_3 fluctuate and the fluctuating levels are stable, and can be effective time periods for obtaining correct sampled data. The setting time period Ts can be the minimum time that must be used to stabilize the slave signal before the rising edge of the sampling clock. The holding time period Th can be the minimum time that must be used to stabilize the slave signal after the rising edge of the sampling clock. Optionally, the setting time period Ts and the holding time period Th can be the minimum time that must be used to stabilize the slave signal before and after the falling edge. The setting time period Ts and the holding time period Th can be effective time periods for correct sampling at the rising edge or the falling edge.

[0096] If the valid time period falls outside the data segment of the slave signal, the data alignment unit of the microcontroller unit may generate a plurality of sampling data using data different from data included in the data segment.

[0097] That is, if the setup period Ts and the hold period Th of the plurality of sampling clocks CLK_1, CLK_2, and CLK_3 fall outside the bit period Tb, the sampling according to the clocks may be erroneous, and the microcontroller unit may obtain erroneous sampling values ​​accordingly. Figure 8 The first sampling clock CLK_1 falls outside the bit period Tb, so the first sampling value according to the first sampling clock CLK_1 may be erroneous. Therefore, the microcontroller unit obtains an erroneous sampling value.

[0098] If the valid time period falls within the data segment of the slave signal, the data alignment unit of the microcontroller unit may generate a plurality of sampling data using the data included in the data segment.

[0099] That is, if the setup time period Ts and the hold time period Th of the plurality of sampling clocks CLK_1, CLK_2, and CLK_3 fall within the bit period Tb, the sampling according to the clocks can be normal, and the microcontroller unit can obtain a normal sampling value accordingly. Figure 8The second sampling clock CLK_2 does not fall outside the bit period Tb, so the second sampling value according to the second sampling clock CLK_2 is normal. The microcontroller unit can obtain a normal sampling value. The third sampling value according to the third sampling clock CLK_3 is also normal.

[0100] The microcontroller unit may select one of the plurality of sample values ​​and determine the selected sample value as slave data (SDAT). The plurality of sample values ​​may have a bit value of "0" or "1", and the microcontroller unit may select a final bit value that accounts for the majority from the two bit values. The selected sample value may be any one of "0" and "1".

[0101] For example, if a slave signal is received from a source readout IC, the microcontroller unit may generate sampling clocks CLK_1, CLK_2, and CLK_3, and may sample the slave signal according to the sampling clocks CLK_1, CLK_2, and CLK_3, thereby extracting first to third sampling values. The first to third sampling values ​​may be bit values ​​"0" or "1", and may have any bit value repeated. Figure 8 In the embodiment, if the microcontroller unit samples the second reception bit RXD2 of the slave signal according to the first to third sampling clocks CLK_1, CLK_2 and CLK_3 having the same phase difference, and if the value of the second reception bit RXD2 is "0", the first sampling value after sampling according to the first sampling clock CLK_1 may be "1", the second sampling value after sampling according to the second sampling clock CLK_2 may be "0", and the third sampling value after sampling according to the third sampling clock CLK_3 may be "0".

[0102] The reason why the first sampled value is "1" (which is different from the other sampled values) is that the setup time period Ts and the holding time period Th of the first sampling clock CLK_1 fall outside the bit period Tb of the second reception bit RXD2, so the first sampled value has an error. If the setup time period Ts and the holding time period Th of the first sampling clock CLK_1 fall within the bit period Tb of the second reception bit RXD2, and if the first sampled value is normal, the first sampled value may be "0". However, since the first sampled value has an error, the first sampled value becomes "1" instead of "0".

[0103] In addition, in the above example, the microcontroller unit can obtain the first to third sampling values ​​{1,0,0} according to the first to third sampling clocks CLK_1, CLK_2 and CLK_3. However, if the timing in the first to third sampling clocks CLK_1, CLK_2 and CLK_3 is different from the timing in the above example, the microcontroller unit can obtain the first to third sampling values ​​{0,0,0}, {0,0,1} and {0,1,0}.

[0104] Therefore, if the first to third sampling values ​​are {0,0,0}, {0,0,1}, {0,1,0}, and {1,0,0}, the microcontroller unit can select the bit value "0" which is the majority from the bit values ​​"0" and "1", and can determine the bit value "0" as the bit value of the second reception bit RXD2 of the slave signal. This is due to the fact that the sampling value "1" indicates an error, which may be caused by sampling the second reception bit RXD2 in a state where the valid time period of the sampling clock from which the sampling value is derived (i.e., the setting time period Ts and the holding time period Th) falls outside the bit period Tb.

[0105] On the other hand, if the microcontroller unit samples the second reception bit RXD2 of the slave signal according to the first to third sampling clocks CLK_1, CLK_2, and CLK_3 having the same phase difference, and if the value of the second reception bit RXD2 is "1" and the first to third sampling values ​​are {0, 1, 1}, {1, 0, 1}, {1, 1, 0}, and {1, 1, 1}, the microcontroller unit can select "1" which is the majority from "0" and "1", and can determine "1" as the bit value of the second reception bit RXD2 of the slave signal. This is due to the fact that the sampling value "0" indicates an error, which may be caused by sampling the second reception bit RXD2 in a state where the valid time period (i.e., the setting time period Ts and the holding time period Th) of the sampling clock from which the sampling value is derived falls outside the bit period Tb.

[0106] As described above, since the microcontroller unit determines the final slave signal (or selects any one of the bit values ​​"0" and "1") from a plurality of sampled values, the more sampled values ​​there are, the more obvious the frequencies of "0" and "1". For example, if there are two sampled values ​​with the combinations {0,1} and {1,0}, it may be difficult to determine the second received bit RXD2 of the slave signal from the bit values ​​"0" and "1". However, if there are a plurality of sampled values, a greater number of normal sampled values ​​can be obtained compared to sampled values ​​with errors. Therefore, the microcontroller unit can determine the bit value that appears more frequently as the second received bit RXD2 of the slave data SDAT.

[0107] Fig. 9 is a diagram showing sampling without errors according to an embodiment.

[0108] refer to Fig. 9 , the condition that all the sampling clocks CLK_1 , CLK_2 , and CLK_3 sample the slave signal corresponding to the slave data SDAT (for example, the condition that the setup period Ts and the holding period Th must fall within the bit period Tb) can be satisfied.

[0109] For example, if the setup time period Ts and the hold time period Th of the plurality of sampling clocks CLK_1, CLK_2, and CLK_3 fall within the bit period Tb, the sampling according to the clocks is normal, and the microcontroller unit can obtain normal sampling values ​​accordingly. Fig. 9 In the example, since the first sampling clock CLK_1 does not fall outside the bit period Tb, the first sampling value according to the first sampling clock CLK_1 is normal. The microcontroller unit can obtain a normal sampling value. The second sampling value and the third sampling value according to the second sampling clock CLK_2 and the third sampling clock CLK_3 are also normal.

[0110] Even if a plurality of normal sampling values ​​without error are extracted, the microcontroller unit may select one of the plurality of sampling values ​​and may determine the selected sampling value as the slave data SDAT. If there is an error, the plurality of sampling values ​​may have alternating bit values ​​of "0" and "1", but if there is no error, the plurality of sampling values ​​may have bit values ​​including only one of "0" and "1". The microcontroller unit may select a bit value having only one of "0" and "1".

[0111] For example, if the microcontroller unit samples the second reception bit RXD2 of the slave signal according to the first to third sampling clocks CLK_1, CLK_2, and CLK_3 having the same phase difference, and if the value of the second reception bit RXD2 is "0" and the first to third sampling values ​​are {0, 0, 0}, the microcontroller unit can select a unique value "0" from "0" and "1", thereby determining the value "0" as the bit value of the second reception bit RXD2 of the slave signal. In this case, the first to third sampling values ​​are normal and there is no error.

[0112] Since all the setup periods Ts and the holding periods Th of the first to third sampling clocks CLK_1 , CLK_2 , and CLK_3 are synchronized within the bit period Tb of the second reception bit RXD2 , the first to third sampling values ​​have a unique value of “0”.

[0113] On the other hand, if the microcontroller unit samples the second reception bit RXD2 of the slave signal according to the first to third sampling clocks CLK_1, CLK_2, and CLK_3 having the same phase difference, and if the value of the second reception bit RXD2 is "1" and the first to third sampling values ​​are {1, 1, 1}, the microcontroller unit can select a unique value "1" from "0" and "1", and can determine the value "1" as the bit value of the second reception bit RXD2 of the slave data SDAT. In this case, the first to third sampling values ​​are normal and there is no error.

[0114] Fig.10is a diagram illustrating an operation of a microcontroller unit aligning slave data according to an embodiment.

[0115] refer to Fig.10 The microcontroller unit may align the slave data SDAT in units of data (eg, in units of bytes or words). The microcontroller unit may identify the slave data SDAT in units of bytes or words through data alignment.

[0116] In order to align the slave data SDAT, the microcontroller unit can find a specific pattern from the slave data SDAT. The pattern can be located in the area of ​​the most significant bit (MSB) of the slave data SDAT. If the microcontroller unit recognizes the pattern, a series of bits after the pattern can be divided into predetermined bit units, and the divided bits can be recognized by byte or word.

[0117] For example, the slave data SDAT may include the first to third reception bits RXD1 to RXD3 and start data before the first to third reception bits RXD1 to RXD3. The start data may be a series of bit strings. Fig.10 In the example, the start data may be represented as {1, 1, 0, 1}. If the microcontroller unit finds the start data, the microcontroller unit may align the first to third receive bits RXD1 to RXD3 after the start data by byte or word. The start data indicates when the alignment starts and may correspond to the mode used for the alignment of the slave data SDAT.

[0118] On the other hand, the microcontroller unit as the master device can predict the time when the slave data SDAT is sent from the source read IC as the slave device. Since the source read IC sends the slave data SDAT after receiving the read command from the microcontroller unit, the microcontroller unit does not always wait to receive the slave data SDAT, but waits to receive the slave data SDAT only after sending the read command.

[0119] For example, if the microcontroller unit sends a read command to the source readout IC at time T1, the microcontroller unit may wait to receive the slave data SDAT. Thereafter, the source readout IC may start to output the slave data SDAT at time T1'.

[0120] The microcontroller unit can predict the reception of the slave data SDAT. Since the microcontroller unit sends a read command before receiving, the microcontroller unit is able to predict the time when the slave data SDAT arrives. Here, SDAT' can represent the slave data predicted by the microcontroller unit.

[0121] Although the microcontroller unit predicts that the slave data SDAT' will arrive at the microcontroller unit at time T2, the slave data SDAT may actually arrive at the microcontroller unit at time T2'. The transmission of the slave data SDAT may be delayed by 2Td, and the slave data SDAT may arrive at the microcontroller unit at time T2' delayed by 2Td relative to time T2.

[0122] Fig.11 is a diagram showing a structure of a microcontroller unit according to an embodiment.

[0123] refer to Fig.11 The microcontroller unit 150 may include a clock duplication unit 151, a plurality of data alignment units 152, a plurality of storage units 153, and a data selection unit 154. The data alignment unit 152 may receive a signal corresponding to the first data, may determine a plurality of sampling points, and may sample the signal corresponding to the first data at the plurality of sampling points, thereby generating a plurality of sampled data. The data selection unit 154 may generate a second data that accounts for the majority of the plurality of sampled data, and may restore the first data from the second data.

[0124] Here, the first data may correspond to the slave data SDAT. The second data may correspond to sampling data which is one of a plurality of sampling data and occupies a majority of the plurality of sampling data, and may eventually include the same value as that of the first data (ie, the slave data SDAT).

[0125] The microcontroller unit 150 may receive a slave signal corresponding to the slave data SDAT, and the slave signal may be transmitted to each data alignment unit 152 .

[0126] The clock copy unit 151 may receive the clock CLK and may copy the clock CLK to generate a plurality of sampling clocks CLK_1 , CLK_2 , and CLK_3 . The plurality of sampling clocks CLK_1 , CLK_2 , and CLK_3 may be transmitted to the data alignment unit 152 and the storage unit 153 .

[0127] Each data alignment unit 152 can align data based on the received sampling clocks of the sampling clocks CLK_1, CLK_2, and CLK_3. First, the data alignment unit 152 can identify the starting point of the data and can divide the data. The data alignment unit 152 can use the received sampling clock to sample the data of each bit, thereby generating a sampled value. The data alignment unit 152 can generate a set of sampled values ​​by collecting the sampled values ​​of all bits. The set of sampled values ​​can have a serial form. The data alignment unit 152 can convert the set of sampled values ​​from a serial form to a parallel form.

[0128] For example, the data alignment unit 152 that receives the first sampling clock CLK_1 can find the starting data from the slave data SDAT, and can divide the slave data SDAT in units of bytes or words. In addition, the data alignment unit 152 can sample the divided data for each bit to generate a first sampling value. The data alignment unit 152 can collect the first sampling values ​​of all bits to generate a set of first sampling values. The data alignment unit 152 can convert the set of first sampling values ​​from a serial form to a parallel form.

[0129] The slave data SDAT (a set of sampled values) in parallel form may be stored in the storage unit 153, and the data selection unit 154 may read out the set of sampled values ​​from the storage unit 153. The storage and reading for the storage unit 153 may be performed in a first-in, first-out (FIFO) manner. The storage unit 153 may include a plurality of flip-flops or shift registers internally for a first-in, first-out manner. The storage unit 153 may receive an input of a clock CLK_S, thereby causing the flip-flop or shift register to operate, and may store a set of sampled values, or may output the set of sampled values ​​to the data selection unit 154.

[0130] For example, a set of first sampling values ​​in parallel form can be stored in the storage unit 153 and then shifted from the storage unit 153 to be output in a first-in-first-out manner. A set of second sampling values ​​and a set of third sampling values ​​can also be stored in corresponding storage units 153 and then can be output.

[0131] Then, the data selection unit 154 may receive a plurality of slave data SDAT (sets of sampled values) in parallel form from the storage unit 153, may compare the plurality of sets of sampled values ​​for each bit, and may select a majority of bit values ​​or a bit value whose occurrence number exceeds half of the value occurrence number for each bit. The data selection unit 154 may collect only the bit values ​​selected for each bit, and may determine these bit values ​​as the slave data SDAT to be read.

[0132] For example, Figure 7As shown, the slave data SDAT may include first to third reception bits RXD1 to RXD3, and the first to third reception bits RXD1 to RXD3 may have bit values ​​{0, 1, 0}. In addition, the data alignment unit 152 may sample the slave signal for each of the first to third reception bits RXD1 to RXD3 according to the first sampling clock CLK_1, and may generate a set of first sampling values ​​having bit values ​​{1, 1, 0}. Similarly, the data alignment unit 152 may generate a set of second sampling values ​​{0, 1, 0} based on the second sampling clock CLK_2, and may generate a set of third sampling values ​​{0, 1, 0} based on the third sampling clock CLK_3. The data alignment unit 152 may convert the set of first to third sampling values ​​into a set of first to third sampling values ​​in parallel form.

[0133] Here, the sampled value of the first reception bit RXD1 according to the first sampling clock CLK_1 is "1" instead of "0", which may indicate an error. As described above, the error may be caused by the effective time period of the first sampling clock CLK_1 being outside the bit period of the first reception bit RXD1.

[0134] In this case, the data selection unit 154 may determine the sampling values ​​of the respective received bits. The data selection unit 154 may compare the bit values ​​of the respective received bits using the set of the first sampling values ​​{1, 1, 0}, the set of the second sampling values ​​{0, 1, 0}, and the set of the third sampling values ​​{0, 1, 0}. As a result of sampling the first received bit RXD1 three times, "1" appears once and "0" appears twice, so the frequency of "0" exceeds half of the number of occurrences of the value. The data selection unit 154 may select the bit value "0" for the first received bit RXD1.

[0135] Likewise, as a result of sampling the second reception bit RXD2 three times, “1” appears three times, so the frequency of “1” exceeds half of the number of occurrences of the value. The data selection unit 154 may select the bit value “1” for the second reception bit RXD2. As a result of sampling the third reception bit RXD3 three times, “0” appears three times, so the frequency of “0” exceeds half of the number of occurrences of the value. The data selection unit 154 may select the bit value “0” for the third reception bit RXD3.

[0136] Therefore, the data selection unit 154 may determine {0, 1, 0} obtained by collecting bit values ​​selected from the first to third reception bits RXD1 to RXD3 as the slave data SDAT to be read.

[0137] As described above, even if errors exist in some of the sampling values, the data selection unit 154 can compare the sampling values ​​in which the errors exist with the other sampling values, and can select the sampling values ​​that account for the majority, thereby ensuring normal sampling.

[0138] CROSS-REFERENCE TO RELATED APPLICATIONS

[0139] This application claims priority to Korean Patent Application No. 10-2019-0132607, filed on October 24, 2019, which is hereby incorporated by reference for all purposes as if fully set forth herein.

Claims

1. A display device, comprising: a microcontroller unit configured to send a master signal along with a clock; as well as a source readout integrated circuit, namely a source readout IC, configured to recover master data from the master signal according to the clock and to send a slave signal generated according to the clock to the microcontroller unit, wherein the microcontroller unit is configured to sample the slave signal according to a plurality of sampling clocks having the same frequency as the frequency of the clock to generate a plurality of sampling data, and to restore the slave data using the plurality of sampling data, and The microcontroller unit determines data that accounts for the majority of the plurality of sampled data as the slave data.

2. The display device according to claim 1, wherein: The plurality of sampling clocks have different phases, respectively.

3. The display device according to claim 1, wherein: The source readout IC does not send a clock corresponding to the slave data.

4. The display device according to claim 2, wherein: The microcontroller unit samples the slave signal at a rising edge or a falling edge of the plurality of sampling clocks.

5. The display device according to claim 1, wherein: The microcontroller unit generates N sampling clocks, where N is a natural number of 3 or more.

6. The display device according to claim 5, wherein: N is an odd number, and wherein the microcontroller unit compares bit values ​​of the plurality of sampling data and determines a bit value that accounts for the majority of the bit values ​​of the plurality of sampling data as a bit value of the slave data.

7. The display device according to claim 1, wherein: There is a consistent phase difference between the plurality of sampling clocks.

8. The display device according to claim 1, wherein: The microcontroller unit and the source readout IC transmit and receive the clock via a signal line in which a delay occurs.

9. The display device according to claim 1, wherein: The microcontroller unit divides the slave signal into predetermined units and samples the divided slave signal.

10. The display device according to claim 9, wherein: The slave signal includes a pattern indicating a start time of a predetermined unit, and wherein the microcontroller unit divides the slave signal based on the pattern.

11. The display device according to claim 1, wherein: The microcontroller unit sends a read command using the master data, and waits for reception of the slave data after sending the read command.

12. The display device according to claim 1, wherein: The slave data is data in a serial form, and wherein the microcontroller unit converts the plurality of sampling data from a serial form into a parallel form, stores the plurality of sampling data in a parallel form in a storage unit, compares the data stored in the storage unit, and restores the slave data.

13. The display device according to claim 1, wherein: One of the plurality of sampling clocks is the clock.

14. A microcontroller unit for sending a master signal together with a clock to a slave device, the microcontroller unit comprising: a plurality of data alignment units configured to receive slave signals from the slave device and generate sampled data by sampling the slave signals according to a sampling clock having the same frequency as that of the clock; as well as a data selection unit configured to compare the sampled data generated by the plurality of data alignment units to restore slave data included in the slave signal, The microcontroller unit determines data that accounts for the majority of the plurality of sampled data as the slave data.

15. The microcontroller unit according to claim 14, wherein: The sampling clock is the clock, or a clock having a phase different from that of the clock.

16. The microcontroller unit according to claim 15, wherein: The data alignment unit samples the slave signal at a rising edge or a falling edge of the sampling clock.

17. The microcontroller unit according to claim 14, further comprising a storage unit in which the sampled data is stored and from which the sampled data is read in a first-in-first-out (FIFO) manner using the data selection unit.

18. The microcontroller unit according to claim 17, wherein: The slave data is data in a serial form, and wherein the data alignment unit converts the sampling data from a serial form into a parallel form and stores the sampling data in the parallel form in the storage unit.

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