A switch matrix circuit and irreversible data recording method thereof

By designing a switch matrix circuit combining a microcontroller, battery cell and MOS tube group, recording data using the blow-off of the snake-shaped circuit line, and restoring the data by reading the conduction of the snake-shaped circuit line, the existing technology is solved It is difficult to record and store confidential data in products that do not allow disassembly, and irreversible data recording and reading are realized.

CN112712845BActive Publication Date: 2025-02-11FUJIAN SCUD POWER TECH CO LTD
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Patent Information

Application Number
CN202011619468.0
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2020-12-30
Publication Date
2025-02-11
Estimated Expiration
2040-12-30

AI Technical Summary

Technical Problem

The prior art is difficult to record and store confidential data in products that do not allow customers to remove shells, and irreversible data recording is not possible.

Method used

A switch matrix circuit was designed, using a microcontroller, battery cell and MOS tube group to combine a snake-shaped circuit line, and the data was recorded by burning the PCB line of the intermediate part B, and the snake-shaped circuit line was read through a multimeter or a special tool. Conduct the data to restore.

Benefits of technology

It realizes irreversible data recording and reading on a microcontroller that does not have the memory to write, which is suitable for products that do not allow customers to disassemble the shell, and does not need to communicate with chips such as flash.

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Abstract

The invention discloses a switch matrix circuit and an irreversible data recording method thereof. The switch matrix circuit comprises a single chip computer, a battery cell, a MOS tube group A, a MOS tube group B, and C serpentine circuit lines. The battery cell is provided with a positive electrode and a negative electrode. The MOS tube group A is composed of X first MOS tubes, the MOS tube group B is composed of Y second MOS tubes, C is the product of X and Y, the S poles of the X first MOS tubes are connected to the D poles of the Y second MOS tubes through the serpentine circuit line, the serpentine circuit line comprises an end A1, an end A2, and a middle part B, and the widths of the PCB line of the end A1 and the PCB line of the end A2 are both greater than the PCB line of the middle part B. The middle part of the invention will burn out when controlled by the MOS tube, and after burning out, the serpentine circuit line can be read by a multimeter or a special tooling to determine whether it is conductive, thereby judging whether the PCB line of the middle part B is damaged, and thus recording the data on the PCB.
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Description

Technical Field

[0001] The invention relates to a switch matrix circuit and an irreversible data recording method thereof. Background Art

[0002] For some confidential product prototypes, or products that customers are not allowed to unpack, or some functions that need to record key abnormal data to distinguish whether the responsibility is the customer or the manufacturer, or some events in the product life cycle that need to be recorded in historical data for traceability, we often add a clock chip to the system to record the time when the event occurred, and also add a flash chip or use a flash-operable microcontroller to record data. In fact, these chip data can be read and cleared through communications or special equipment. Summary of the invention

[0003] The object of the present invention is to overcome the deficiencies in the prior art and to provide a switch matrix circuit and an irreversible data recording method thereof.

[0004] In order to achieve the above object, the present invention is achieved through the following technical solutions:

[0005] A switch matrix circuit comprises a single-chip computer, a battery cell, a MOS tube group A, a MOS tube group B, and C serpentine circuit lines, wherein the battery cell is provided with a positive electrode and a negative electrode, the MOS tube group A is composed of X first MOS tubes, the MOS tube group B is composed of Y second MOS tubes, C is the product of X and Y, the D poles of the X first MOS tubes are all connected to the positive electrode of the battery cell, the negative electrode of the battery cell is connected to a ground signal GND, the G poles of the X first MOS tubes are all connected to the single-chip computer, the G poles of the Y second MOS tubes are all connected to the single-chip computer, the S poles of the Y second MOS tubes are all connected to the ground signal GND, the S poles of the X first MOS tubes are all connected to the D poles of the Y second MOS tubes through the serpentine circuit line, and the serpentine circuit line comprises an end A1, an end A2, and a middle part B, the end A1 is fixedly connected to the end A2 through the middle part B, and the widths of the PCB line of the end A1 and the PCB line of the end A2 are both greater than the PCB line of the middle part B.

[0006] Preferably, the width of the PCB line at the end A1 and the width of the PCB line at the end A2 are both 41 mils, and the width of the PCB line at the middle portion B is 6 mils.

[0007] Preferably, the first MOS transistor and the second MOS transistor are both N-channel MOS transistors.

[0008] Preferably, the MOS tube group A is composed of three first MOS tubes, the three first MOS tubes are MOS tube Q1, MOS tube Q2, and MOS tube Q3, the C is 9, the MOS tube group B is composed of three second MOS tubes, the three second MOS tubes are MOS tube Q4, MOS tube Q5, and MOS tube Q6, the D pole of the MOS tube Q1, the D pole of the MOS tube Q2, and the D pole of the MOS tube Q3 are all connected to the positive pole of the battery cell, the negative pole of the battery cell is connected to the ground signal GND, the G pole of the MOS tube Q1, the G pole of the MOS tube Q2, and the G pole of the MOS tube Q3 are all connected to the single-chip computer, the G pole of the MOS tube Q4, The G poles of the MOS tube Q5 and the G poles of the MOS tube Q6 are connected to the single chip computer, the S poles of the MOS tube Q4, the S poles of the MOS tube Q5, and the S poles of the MOS tube Q6 are connected to the ground signal GND, the S poles of the MOS tube Q1, the S poles of the MOS tube Q2, and the S poles of the MOS tube Q2 are connected to the D pole of the MOS tube Q4 through the serpentine circuit line, the S poles of the MOS tube Q1, the S poles of the MOS tube Q2, and the S poles of the MOS tube Q2 are connected to the D pole of the MOS tube Q5 through the serpentine circuit line, and the S poles of the MOS tube Q1, the S poles of the MOS tube Q2, and the S poles of the MOS tube Q2 are connected to the D pole of the MOS tube Q6 through the serpentine circuit line.

[0009] A method for recording irreversible data in a switch matrix circuit, using C serpentine circuit lines as data bits, taking n1 of them as event records, that is, 2 to the power of n1, thereby recording 2 n1 events, take n2 bits as time record, that is, 2 n2 data, thus recording 2 n2 At a certain time, when data needs to be read, use a multimeter to measure whether the serpentine circuit line is conductive or use a special tool to read the serpentine circuit line to restore the data.

[0010] As a preferred embodiment, a method for recording irreversible data of a switch matrix circuit, wherein C is 9, 3 bits are taken as event records, that is, 2 to the power of c, thereby recording 8 events, and 6 bits are taken as time records, that is, 2 6 data, thereby recording 64 times. When it is necessary to read the data, use a multimeter to measure whether the serpentine circuit line is conductive or use a special tool to read the serpentine circuit line to restore the data.

[0011] The beneficial effects of the present invention are as follows: the widths of the PCB lines at the end A1 and the end A2 of the present invention are greater than the PCB lines at the middle part B, so the PCB lines at the end A1 and the end A2 are thick lines, and the middle part B is thin lines, so the middle part B will be burned out when controlled by the MOS tube, and after burning out, the serpentine circuit line can be read by a multimeter or a special tooling to read whether it is conductive, so as to judge whether the PCB line of the middle part B is damaged, and thus the data is recorded on the PCB. The present invention uses the damaged PCB routing as recorded data, which has an irreversible characteristic, unless the board is replaced, and the board replacement itself is also an event, and the wrong order of removing the board can also be recorded as an event in this method event; the present invention is applicable to single-chip microcomputers that do not have their own memory that can be written, such as single-chip microcomputers of a few cents; the present invention does not need to communicate with chips such as flash, and is directly driven by IO ports; the present invention is applicable to applications with a small amount of data, such as a 485 communication system with 1 master and 4 slaves, communication allocates ID, and the board coexists with the warehouse after the PCB is blown, and the ID cannot be changed by adjusting the dial switch and ID resistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is the circuit principle diagram of the present invention;

[0013] Figure 2 This is a PCB diagram of a serpentine circuit line. DETAILED DESCRIPTION

[0014] The technical solution of the present invention is further described below in conjunction with the accompanying drawings:

[0015] like Figure 1As shown, a switch matrix circuit includes a single-chip computer MCU, a battery cell CELL, a MOS tube group A, a MOS tube group B, and C serpentine circuit lines. The battery cell CELL is provided with a positive electrode and a negative electrode. The MOS tube group A is composed of three first MOS tubes, and the MOS tube group B is composed of three second MOS tubes. The C is the product of 3 and 3, so C is 9. The three first MOS tubes are MOS tubes Q1, MOS tube Q2, and MOS tube Q3. The three second MOS tubes are MOS tubes Q4, MOS tube Q5, and MOS tube Q6. The D pole of the MOS tube Q1, the D pole of the MOS tube Q2, and the D pole of the MOS tube Q3 are all connected to the positive pole of the battery cell CELL, and the negative pole of the battery cell CELL is connected to the ground signal GND. The G poles of the MOS tube Q1, the G poles of the MOS tube Q2, and the G poles of the MOS tube Q3 are all connected to the single-chip computer MCU. The G poles of the MOS tube Q4, the M The G pole of the MOS tube Q5 and the G pole of the MOS tube Q6 are connected to the single-chip computer MCU, the S pole of the MOS tube Q4, the S pole of the MOS tube Q5, and the S pole of the MOS tube Q6 are connected to the ground signal GND, the S pole of the MOS tube Q1, the S pole of the MOS tube Q2, and the S pole of the MOS tube Q2 are connected to the D pole of the MOS tube Q4 through the serpentine circuit line, the S pole of the MOS tube Q1, the S pole of the MOS tube Q2, and the S pole of the MOS tube Q5 are connected to the D pole of the MOS tube Q6 through the serpentine circuit line, and the serpentine circuit line includes an end A1, an end A2, and a middle part B, the end A1 is fixedly connected to the end A2 through the middle part B, and the width of the PCB line of the end A1 and the PCB line of the end A2 is greater than the PCB line of the middle part B.

[0016] like Figure 1 , Figure 2 As shown, the width of the PCB line at the end A1 and the PCB line at the end A2 are both 41 mils, and the width of the PCB line at the middle portion B is 6 mils.

[0017] like Figure 1 As shown, MOS transistor Q1 , MOS transistor Q2 , MOS transistor Q3 , MOS transistor Q4 , MOS transistor Q5 , and MOS transistor Q6 are all N-channel MOS transistors.

[0018] A method for recording irreversible data in a switch matrix circuit, wherein C is 9, 3 bits are taken as event records, that is, 2 to the power of c, thereby recording 8 events, and 6 bits are taken as time records, that is, 2 6 data, thereby recording 64 times. When it is necessary to read the data, use a multimeter to measure whether the serpentine circuit line is conductive or use a special tool to read the serpentine circuit line to restore the data.

[0019] An alternative scheme is a switch matrix circuit, including a single-chip computer MCU, a battery cell CELL, a MOS tube group A, a MOS tube group B, and C serpentine circuit lines, wherein the battery cell CELL is provided with a positive electrode and a negative electrode, the MOS tube group A is composed of X first MOS tubes, the MOS tube group B is composed of Y second MOS tubes, the C is the product of X and Y, the D poles of the X first MOS tubes are all connected to the positive pole of the battery cell CELL, the negative pole of the battery cell CELL is connected to the ground signal GND, and the X first MOS tubes are connected to the positive pole of the battery cell CELL. The G poles of the Y second MOS tubes are all connected to the single-chip microcomputer MCU, the G poles of the Y second MOS tubes are all connected to the single-chip microcomputer MCU, the S poles of the Y second MOS tubes are all connected to the ground signal GND, the S poles of the X first MOS tubes are all connected to the D poles of the Y second MOS tubes through a serpentine circuit line, the serpentine circuit line includes an end A1, an end A2, and a middle part B, the end A1 is fixedly connected to the end A2 through the middle part B, and the width of the PCB line of the end A1 and the PCB line of the end A2 are both greater than the PCB line of the middle part B.

[0020] A method for recording irreversible data in a switch matrix circuit, using C serpentine circuit lines as data bits, taking n1 of them as event records, that is, 2 to the power of n1, thereby recording 2 n1 events, take n2 bits as time record, that is, 2 n2 data, thus recording 2 n2 At a certain time, when data needs to be read, use a multimeter to measure whether the serpentine circuit line is conductive or use a special tool to read the serpentine circuit line to restore the data.

[0021] The width of the PCB line at the end A1 and the PCB line at the end A2 of the present invention is greater than that of the PCB line at the middle part B. Therefore, the PCB lines at the end A1 and the end A2 are thick lines, and the middle part B is thin lines. Therefore, the middle part B will be burned out when controlled by the MOS tube. After burning out, the serpentine circuit line can be read by a multimeter or a special tooling to read whether it is conductive, so as to judge whether the PCB line of the middle part B is damaged, and thus the data is recorded on the PCB. The present invention uses the damaged PCB routing as recorded data, which has an irreversible characteristic, unless the board is replaced. The board replacement itself is also an event. The wrong order of removing the board can also be recorded as an event in this method event; the present invention is applicable to single-chip microcomputers that do not have their own memory that can be written, such as single-chip microcomputers of a few cents; the present invention does not need to communicate with chips such as flash, and is directly driven by IO ports; the present invention is applicable to applications with a small amount of data, such as a 485 communication system with 1 master and 4 slaves, where the communication allocates IDs. After the PCB is blown out, the board coexists with the warehouse, and the ID cannot be changed by adjusting the dip switch and ID resistor.

[0022] It should be noted that the above is only a specific embodiment of the present invention. Obviously, the present invention is not limited to the above embodiment, and there are many variations. In short, all variations that can be directly derived or associated with the content disclosed by ordinary technicians in this field should be considered as the protection scope of the present invention.

Claims

1. A switch matrix circuit, characterized in that: It includes a single-chip computer MCU, a battery cell CELL, a MOS tube group A, a MOS tube group B, and C serpentine circuit lines, wherein the battery cell CELL is provided with a positive electrode and a negative electrode, the MOS tube group A is composed of X first MOS tubes, the MOS tube group B is composed of Y second MOS tubes, and C is the product of X and Y. The D poles of the X first MOS tubes are all connected to the positive electrode of the battery cell CELL, the negative electrode of the battery cell CELL is connected to the ground signal GND, the G poles of the X first MOS tubes are all connected to the single-chip computer MCU, the G poles of the Y second MOS tubes are all connected to the single-chip computer MCU, the S poles of the Y second MOS tubes are all connected to the ground signal GND, the S poles of the X first MOS tubes are all connected to the D poles of the Y second MOS tubes through the serpentine circuit line, and the serpentine circuit line includes an end A1, an end A2, and a middle part B, the end A1 is fixedly connected to the end A2 through the middle part B, and the widths of the PCB line of the end A1 and the PCB line of the end A2 are both greater than the PCB line of the middle part B; The first MOS tube and the second MOS tube are both N-channel MOS tubes; the MOS tube group A is composed of three first MOS tubes, which are MOS tube Q1, MOS tube Q2, and MOS tube Q3, and C is 9; the MOS tube group B is composed of three second MOS tubes, which are MOS tube Q4, MOS tube Q5, and MOS tube Q6; the D pole of the MOS tube Q1, the D pole of the MOS tube Q2, and the D pole of the MOS tube Q3 are all connected to the positive pole of the battery cell CELL, the negative pole of the battery cell CELL is connected to the ground signal GND, and the G pole of the MOS tube Q1, the G pole of the MOS tube Q2, and the G pole of the MOS tube Q3 are all connected to the single-chip microcomputer M CU, the G pole of the MOS tube Q4, the G pole of the MOS tube Q5, and the G pole of the MOS tube Q6 are all connected to the single-chip computer MCU, the S pole of the MOS tube Q4, the S pole of the MOS tube Q5, and the S pole of the MOS tube Q6 are all connected to the ground signal GND, the S pole of the MOS tube Q1, the S pole of the MOS tube Q2, and the S pole of the MOS tube Q2 are all connected to the D pole of the MOS tube Q4 through a serpentine circuit line, the S pole of the MOS tube Q1, the S pole of the MOS tube Q2, and the S pole of the MOS tube Q2 are all connected to the D pole of the MOS tube Q5 through a serpentine circuit line, and the S pole of the MOS tube Q1, the S pole of the MOS tube Q2, and the S pole of the MOS tube Q2 are all connected to the D pole of the MOS tube Q6 through a serpentine circuit line; Take C serpentine circuit lines as data bits, and take n1 of them as event record, which is 2 to the power of n1, so as to record 2 n1 events, take n2 bits as time record, that is, 2 n2 data, thus recording 2 n2 At a certain time, when data needs to be read, use a multimeter to measure whether the serpentine circuit line is conductive or use a special tool to read the serpentine circuit line to restore the data.

2. A switch matrix circuit according to claim 1, characterized in that: The width of the PCB line at the end A1 and the PCB line at the end A2 are both 41 mils, and the width of the PCB line at the middle portion B is 6 mils.

3. A switch matrix circuit according to claim 1, characterized in that: The C is 9, 3 of which are used to record events, which is 2 to the power of c, so 8 events are recorded, and 6 of which are used to record time, which is 2 6 data, thereby recording 64 times. When it is necessary to read the data, use a multimeter to measure whether the serpentine circuit line is conductive or use a special tool to read the serpentine circuit line to restore the data.

Citation Information

Patent Citations

  • Switch matrix circuit

    CN214043095U