Plasma processing system and edge ring assembly therefor

Abstract

The present invention provides a plasma processing system for processing a wafer and a preparation method thereof. The system includes: an electrostatic chuck; and an edge ring assembly surrounding the electrostatic chuck. The edge ring assembly includes: a dielectric ring having a top surface, a bottom surface opposite to the top surface, and a protrusion extending upward from the top surface; and a coil embedded in the protrusion of the dielectric ring, the coil having a plurality of loops, each of the plurality of loops having a different distance relative to the bottom surface of the dielectric ring.

Description

Technical Field

[0001] The present invention relates generally to plasma processing systems and, more particularly, to a plasma processing system having an edge ring with coils embedded therein for regulating a fringing magnetic field. Background Art

[0002] Due to the limitation of process machines, bad dies usually come from dies manufactured in the edge area of ​​the wafer. With the continuous development of semiconductor technology, the number of chips produced in the wafer continues to increase. Therefore, the number of dies produced in the edge area of ​​the wafer has also increased. Therefore, the importance of accurately performing the manufacturing process in the edge area of ​​the wafer is becoming more and more important for the manufacturing yield of the semiconductor process. Summary of the invention

[0003] In view of this, it is necessary to provide a plasma processing system and an edge ring assembly thereof to solve the above technical problems.

[0004] A plasma processing system for processing a wafer, comprising: an electrostatic chuck; and an edge ring assembly surrounding the electrostatic chuck, the edge ring assembly comprising: a dielectric ring having a top surface, a bottom surface opposite to the top surface, and a protrusion extending upward from the top surface; and a coil embedded in the protrusion of the dielectric ring, the coil having a plurality of loops, each of the plurality of loops having a different distance relative to the bottom surface of the dielectric ring.

[0005] A method for forming a dielectric ring, comprising: forming a plurality of loops, wherein the plurality of loops are configured to form a coil; forming a plurality of dielectric layers, wherein the plurality of loops are correspondingly embedded in the plurality of dielectric layers;

[0006] electrically coupling the plurality of loops to each other; forming a base dielectric layer having a surface area greater than a surface area of ​​each of the plurality of dielectric layers; and physically coupling the plurality of dielectric layers and the base dielectric layer to each other.

[0007] A plasma processing chamber, comprising: an electrostatic chuck having a step edge on its periphery, the step edge of the electrostatic chuck having a step base and a step wall that are substantially perpendicular to each other; and an edge ring assembly configured to surround the electrostatic chuck, the edge ring assembly comprising: a first quartz ring configured to surround the periphery of the electrostatic chuck, the first quartz ring having a step edge on its inner periphery, the step edge of the first quartz ring having a step base and a step wall that are substantially perpendicular to each other; a second quartz ring configured to be disposed on the first quartz ring, the second quartz ring having a step edge on its inner periphery, the step edge of the second quartz ring having a step base and a step wall that are substantially perpendicular to each other; a dielectric ring configured to be disposed on the first quartz ring The invention relates to a dielectric ring comprising: a step base of the electrostatic chuck and a step base of the first quartz ring, wherein the dielectric ring has a step edge on its inner circumference, the step edge of the dielectric ring having a step base and a step wall substantially perpendicular to each other; a coil embedded in the dielectric ring and formed along the step wall of the dielectric ring, the coil having a plurality of loops, each of the plurality of loops having a different distance corresponding to the step base of the dielectric ring; and a tuning ring disposed on the step base of the dielectric ring and the step base of the second quartz ring, the tuning ring having a top surface, a bottom surface opposite to the top surface, and a cavity defined and formed along the bottom surface, the cavity covering a portion of the dielectric ring protruding from the step base of the dielectric ring. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0009] Figure 1 A schematic cross-sectional view of a region of a plasma processing system according to some embodiments disclosed herein is shown;

[0010] Figure 2 A schematic cross-sectional view of a dielectric ring according to some embodiments disclosed herein is shown;

[0011] Figure 3 A schematic cross-sectional view of a dielectric ring according to some other embodiments disclosed in the present invention is shown;

[0012] Figure 4 An isometric schematic diagram of a coil according to some embodiments disclosed herein is shown;

[0013] Figure 5AA schematic top view of a coil according to some other embodiments disclosed in the present invention is shown;

[0014] Figure 5B An isometric schematic diagram of a coil according to some other embodiments disclosed herein is shown;

[0015] Figure 6 A flowchart showing a method of forming a plasma processing system according to some embodiments disclosed herein;

[0016] Figure 7 A flowchart showing a method of forming an edge ring according to some embodiments disclosed herein;

[0017] Figure 8 A schematic cross-sectional view of a plasma processing system according to a related embodiment is shown;

[0018] Fig. 9 A schematic diagram of a plasma processing system according to some embodiments of the present disclosure is shown.

[0019] However, it is to be noted that the accompanying drawings illustrate only exemplary embodiments of the present invention and are therefore not to be considered limiting the scope of the present invention, as the present invention may admit to other equally effective embodiments.

[0020] Main component symbols

[0021]

[0022]

[0023] The following specific implementation manner will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0024] The following description will refer to the accompanying drawings to more fully describe the present invention. Illustrated in the accompanying drawings are exemplary embodiments disclosed by the present invention. However, the present invention can be implemented in many different forms and should not be construed as being limited to the exemplary embodiments set forth herein. These exemplary embodiments are provided to make the present invention thorough and complete and to fully convey the scope of the present invention to those skilled in the art. Similar reference numerals represent identical or similar components.

[0025] The terms used herein are only used for the purpose of describing specific exemplary embodiments and are not intended to limit the present invention. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to also include the plural forms. In addition, when used herein, "include" and / or "comprise" or "include" and / or "includes" or "have" and / or "have", integers, steps, operations, components and / or components, but do not exclude the existence or addition of one or more other features, regions, integers, steps, operations, components, components and / or groups thereof.

[0026] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. In addition, unless explicitly defined herein, terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meanings in the relevant art and the present disclosure, and will not be interpreted as an idealized or overly formal meaning.

[0027] The following will describe exemplary embodiments in conjunction with the accompanying drawings. It should be noted that the components depicted in the reference drawings are not necessarily shown to scale; and the same or similar components will be given the same or similar reference numerals or similar technical terms.

[0028] Figure 8 A regional cross-sectional view of a plasma processing system 800 according to a related embodiment is shown. The plasma processing system 800 has an edge ring 801 surrounding a wafer (or die) 802. The edge ring 801 is typically a unitary member made of a single material. A first film 803 and a second film 804 are disposed on the wafer 802. The total thickness of the wafer 802, the first film 803, and the second film 804 is large enough so that the second film 804 protrudes above the surface of the edge ring 801. In the process of manufacturing a semiconductor device, a groove 805 is formed in the first film 803 and the second film 804.

[0029] This figure schematically shows a plasma etching process, in which the second film 804 is bombarded by ions in a plasma provided from above. The traveling direction of the ions is determined by Figure 8807a, 807b in FIG. Ideally, the groove 805 is generated in a direction perpendicular to the plane of the wafer 802. Near the inner and central regions surrounding the wafer 802, the traveling direction of the ions is substantially perpendicular to its upper surface (as shown by arrow 807a). However, the plasma sheath 806 (as shown by the dotted line) experiences a bending effect at the edge region of the wafer 802. Therefore, the traveling direction of the ions near the curved portion of the plasma sheath 806 becomes tilted (as shown by arrow 807b). As a result, the groove 805 formed near the edge region of the wafer 802 becomes tilted compared to the groove formed in the central region of the wafer 802. The tilted structural features generated near the edge region of the wafer often become process defects, thereby reducing the manufacturing yield during the semiconductor process. Therefore, it is necessary to find an appropriate method to prevent the tilting problem of the traveling direction of the ions in the edge region of the wafer.

[0030] Fig. 9 A plasma processing system according to some embodiments of the present disclosure is shown. The plasma processing system operates in a processing chamber 901. The processing chamber 901 can accommodate an electrode 902 to provide an electric charge for forming a plasma in the processing chamber 901, and an electrostatic chuck to hold a chip (or wafer) 104 to be processed.

[0031] Figure 1 A close-up of a portion of a plasma processing system is shown. Specifically, Figure 1 A regional cross-sectional view of a plasma processing system 100 according to some embodiments disclosed herein (e.g., at a wafer edge / seal ring region) is shown. The plasma processing system 100 includes an electrostatic chuck (ESC) 101 and an edge ring assembly 102 configured to surround the electrostatic chuck 101. The electrostatic chuck 101 includes an electrostatic chuck base 1011 and an electrostatic chuck dielectric layer 1012 disposed thereon. In some embodiments, the material of the electrostatic chuck base 1011 is made of aluminum. In the example shown, a chip (or wafer) 104 is arranged on the electrostatic chuck dielectric layer 1012. Although other layers may exist on the surface of the chip 104, the structural design of the edge ring assembly 102 according to the present invention is configured to have a top surface that is higher than the upper surfaces of many additional layers of the chip.

[0032] In an exemplary embodiment, the sinking distance of the wafer 104 relative to the top surface of the edge ring assembly 102 is about 1 mm to 2 mm. In some embodiments, the electrostatic chuck pedestal 1011 has a step edge at its periphery. The step edge of the electrostatic chuck pedestal 1011 has a step wall 1011-2 that is substantially perpendicular to the step base 1011-1. The edge ring assembly 102 may include a dielectric ring 1022 and a coil 1021 disposed within the dielectric ring 1022. In some embodiments, the dielectric ring 1022 is disposed above the step base 1011-1 of the electrostatic chuck pedestal 1011. The dielectric ring 1022 has a step edge on its inner periphery. The step edge of the dielectric ring 1022 has a step wall 1022-3 that is substantially perpendicular to the step base 1022-1. In some embodiments, the height of the step wall 1022-3 of the dielectric ring 1022 is greater than the thickness of the wafer 104 (considering all layers formed on its surface).

[0033] In some embodiments, the coil 1021 is formed along the step wall 1022-3 of the dielectric ring 1022. In some embodiments, the coil 1021 is coupled to at least one DC voltage source (Voltage Supply) and is configured to generate a magnetic field corresponding to the DC voltage source. The magnetic field is used to adjust the direction of travel of the ions. In some embodiments, the voltage terminal is set through the electrostatic chuck 101 or the electrostatic chuck base 1011 and is configured to couple the coil 1021 to the DC voltage source. The supply voltage of the at least one DC voltage source can be in the range of about -24 volts to +24 volts.

[0034] In some embodiments, the edge ring assembly 102 further includes a first quartz ring 1023 surrounding the periphery of the electrostatic chuck 101 and a second quartz ring 1024 disposed above the first quartz ring 1023. The first quartz ring 1023 has a step edge on the inner periphery. The step edge of the first quartz ring 1023 has a step wall 1023-2 substantially perpendicular to its step base 1023-1. The dielectric ring 1022 is further disposed on the step base 1023-1 of the first quartz ring 1023. The second quartz ring 1024 has a step edge on the inner periphery. The step edge of the second quartz ring 1024 has a step wall 1024-2 substantially perpendicular to its step base 1024-1. The second quartz ring 1024 is configured as a structure separated from the first quartz ring 1023, so that when the second quartz ring 1024 is damaged, it is not necessary to replace the first quartz ring 1023 together with the second quartz ring 1024. In some embodiments, the edge ring assembly 102 further includes a tuning ring 1025 for covering the protruding structure of the dielectric ring 1022. In other words, the tuning ring 1025 is configured to be coupled to the dielectric ring 1022 over its top surface.

[0035] The application of a tuning ring (e.g., ring 1025) can further mitigate the bending effect of the plasma sheath. On the one hand, the presence of the tuning ring 1025 can enhance the effect of the coil 1021, thereby further tuning the profile of the plasma sheath at the edge region of the processed workpiece (e.g., wafer). In some embodiments, the tilt angle of the direction of travel of the ions at the edge of the wafer can be adjusted to achieve further uniformity (e.g., adjusting the tilt angle of the direction of travel of the ions at the edge of the wafer relative to the direction of travel of the ions at the center region of the wafer). In some embodiments, the tilt angle of the ions at the edge region of the wafer can be adjusted to reach approximately 90 degrees. In some embodiments, the material composition for the tuning ring can substantially include silicon. In some embodiments, the tuning ring can include the same or similar material as the processed workpiece.

[0036] In some embodiments, the protrusion of the dielectric ring 1022 is designed to hold the tuning ring 1025 in place. The tuning ring 1025 can be disposed on the step base 1022-1 of the dielectric ring 1022 and the step base 1024-1 of the second quartz ring 1024. The tuning ring 1025 has a top surface and a bottom surface opposite to the top surface. A cavity is formed along the bottom surface of the tuning ring 1025. The cavity is configured to cover a portion of the dielectric ring 1022, for example, the portion of the dielectric ring 1022 can be a portion protruding from the step base 1022-1 of the dielectric ring. In some embodiments of the edge ring assembly 102 without a tuning ring (e.g., ring 1025), the top surface of the protrusion of the dielectric ring 1022 can be configured to be higher than the workpiece (e.g., the wafer 104 and all material layers on its surface). In some embodiments of the edge ring assembly 102 having the tuning ring 1025, the top surface of the tuning ring 1025 can be higher than the chip 104 (including layers disposed on the chip surface). In some embodiments, the plasma processing system 100 further includes a quartz filler 103 disposed between the edge ring assembly 102 and the electrostatic chuck 101.

[0037] Figure 21 shows a cross section of a dielectric ring 1022' according to some embodiments disclosed herein. The dielectric ring 1022' of the edge ring assembly may be formed by a plurality of dielectric layers (e.g., dielectric layers 1022A', 1022B', and 1022C' and a base dielectric layer 1022D') stacked on each other. The base dielectric layer 1022D' forms a top surface of the dielectric ring 1022' and a dielectric ring bottom surface opposite thereto. The plurality of dielectric layers 1022A', 1022B', and 1022C' form a protrusion structure extending upward from the top surface of the dielectric ring 1022'. In some embodiments, the plurality of dielectric layers 1022A', 1022B', and 1022C' and the base dielectric layer 1022D' have an annular structure. In some embodiments, the plurality of dielectric layers 1022A', 1022B', and 1022C' may have the same planar area and, when stacked on each other, be aligned with each other. The planar area of ​​the base dielectric layer 1022D' is larger than the planar area of ​​each of the plurality of dielectric layers 1022A', 1022B', and 1022C'. In some embodiments, the outer radii of the plurality of dielectric layers 1022A', 1022B', 1022C' and the base dielectric layer 1022D' are substantially the same, while the inner radii of the plurality of dielectric layers 1022A', 1022B', and 1022C' are larger than the inner radius of the base dielectric layer 1022D'. After stacking the plurality of dielectric layers 1022A', 1022B', and 1022C' on the base dielectric layer 1022D', the exposed area left on the top surface of the base dielectric layer 1022D' forms the step base of the dielectric ring 1022'.

[0038] In some embodiments, the height of the protrusion structure is configured to be greater than the thickness of the wafer. In the illustrated embodiment, the height of the protrusion structure of the dielectric ring 1022' is defined as the sum of the thicknesses of the plurality of dielectric layers 1022A', 1022B', and 1022C'. The thickness of each of the plurality of dielectric layers 1022A', 1022B', and 1022C' may be the same or different from one another. In an exemplary embodiment, when the thicknesses of the plurality of dielectric layers 1022A', 1022B', and 1022C' are different from one another, the thickness D1' of the dielectric layer 1022A' is approximately 160 μm; the thickness D2' of the dielectric layer 1022B' is approximately 100 μm; and the thickness D3' of the dielectric layer 1022C' is approximately 640 μm. In an exemplary embodiment, the thickness D4' of the base dielectric layer 1022D' is approximately 10 mm. In some embodiments, the dielectric ring is made of a ceramic material.

[0039] In some embodiments, the coil 1021' is embedded in the protrusion of the dielectric ring 1022'. The coil 1021' includes a plurality of loops 1021-1', 1021-2', and 1021-3'. Each of the plurality of loops 1021-1', 1021-2', and 1021-3' has a thickness (T1') of approximately 50 μm. In some embodiments, the plurality of loops 1021-1', 1021-2', and 1021-3' have a circular cross-sectional profile, and their thickness T1' defines the diameter of this circular cross-sectional shape. In some embodiments, the number of the plurality of loops of the coil 1021' may be greater than or equal to three.

[0040] The number of turns of the coil may correspond to the number of stacked dielectric layers (e.g., layers 1022A' / B' / C'). For example, when the number of turns is greater than three, dielectric layer 1022B' and loop 1021-2' may be repeatedly fabricated to reach the target number of turns. Each of the plurality of turns 1021-1', 1021-2', and 1021-3' is respectively embedded in the plurality of dielectric layers 1022A', 1022B', and 1022C' of the dielectric ring 1022. Each of the plurality of turns 1021-1', 1021-2', and 1021-3' is arranged at different distances relative to the bottom surface of the dielectric ring 1022'. The distance of each of the plurality of loops 1021-1', 1021-2', and 1021-3' from the bottom surface of the dielectric ring 1022' may depend on the stacking order of the plurality of dielectric layers 1022A', 1022B', and 1022C' of the dielectric ring 1022'.

[0041] In some embodiments, in the dielectric layer 1022A' farthest from the base dielectric layer 1022D', the loop 1021-1' embedded therein is arranged to be closer to the surface of the dielectric layer 1022A' close to the adjacent dielectric layer 1022B'. In some embodiments, in the dielectric layer 1022C' closest to the base dielectric layer 1022D', the loop 1021-3' embedded therein is arranged to be closer to the surface of the dielectric layer 1022C' close to the adjacent dielectric layer 1022B'. In some embodiments, the dielectric layer 1022B' has a loop 1021-2' arranged to be equidistant from two adjacent dielectric layers 1022A' and 1022C'. In some embodiments, the coil 1021' is made of molybdenum manganese.

[0042] Figure 4 FIG. 1 shows a schematic isometric view of a coil 1021 ′ according to some other embodiments disclosed herein. Figure 2 and Figure 4In some embodiments, the plurality of loops 1021-1', 1021-2', and 1021-3' of the coil 1021' are coupled to each other to form a circular metal structure of a cylindrical spiral structure. In some embodiments, the coil 1021' forms a left-handed spiral. The plurality of loops 1021-1', 1021-2', and 1021-3' shown form a spiral shape, wherein when a counterclockwise tightening motion is applied to the coil 1021' (e.g., starting from the loop 1021-1' that is farthest from the base dielectric layer 1022D'), the spiral shape extends toward the base dielectric layer (1022D).

[0043] In the current embodiment, the plurality of loops 1021-1', 1021-2', and 1021-3' have the same radius as each other and are concentric with each other. Adjacent loops 1021-1', 1021-2', and 1021-3' are coupled to each other through metal contacts Y' between corresponding adjacent dielectric layers 1022A', 1022B', and 1022C'. Each of the plurality of loops 1021-1', 1021-2', and 1021-3' has a gap X' that terminates the conductive path within each loop. In the illustrated embodiment, the gaps X' of the plurality of loops 1021-1', 1021-2', and 1021-3' are positioned in a clockwise order from each other (starting from the gap X' of the loop 1021-1' that is farthest from the base dielectric layer 1022D'). The metal contacts Y' of the subsequent layers may be positioned offset from each other by a gap distance X'. The metal contacts Y' are arranged orthogonally to the plurality of loops 1021-1', 1021-2', and 1021-3'. The pitch distance between the plurality of loops 1021-1', 1021-2', and 1021-3' of the coil 1021' may be in a range between about 100 μm and about 300 μm.

[0044] Figure 31 shows a cross section of a dielectric ring 1022'' according to some other embodiments disclosed herein. The dielectric ring 1022'' of the edge ring assembly may be formed by a plurality of dielectric layers (e.g., layers 1022A'', 1022B'', and 1022C'') and a base dielectric layer 1022D'' in a manner stacked on top of one another. The base dielectric layer 1022D'' forms a top surface of the dielectric ring 1022'' and a bottom surface of the dielectric ring 1022'' opposite to the top surface. The plurality of dielectric layers 1022A'', 1022B'', and 1022C'' form a protrusion structure of the dielectric ring 1022'' extending upward from the top surface of the dielectric ring 1022''. In some embodiments, the plurality of dielectric layers 1022A'', 1022B'', and 1022C'', and the base dielectric layer 1022D'' have a ring structure. The plurality of dielectric layers 1022A", 1022B", and 1022C" may have the same planar area and, when stacked on each other, be aligned with each other. The planar area of ​​the base dielectric layer 1022D" is greater than the planar area of ​​each of the plurality of dielectric layers 1022A", 1022B", and 1022C". In some embodiments, the outer radius of the plurality of dielectric layers 1022A", 1022B", 1022C" is substantially the same as the base dielectric layer 1022D", while the inner radius of the plurality of dielectric layers 1022A", 1022B", and 1022C" is greater than the inner radius of the base dielectric layer 1022D". After stacking the plurality of dielectric layers 1022A", 1022B", and 1022C" on the base dielectric layer 1022D", an exposed area left on the top surface of the base dielectric layer 1022D" forms a step base of the dielectric ring 1022".

[0045] In some embodiments, the height of the protruding structure is configured to be greater than the thickness of the wafer it carries. In the illustrated embodiment, the height of the protruding structure of the dielectric ring 1022'' is defined as the sum of the thickness of each of the multiple dielectric layers 1022A'', 1022B'', and 1022C''. The thicknesses of the multiple dielectric layers 1022A'', 1022B'', and 1022C'' may be the same or different from each other. In an exemplary embodiment, when the thicknesses of the multiple dielectric layers 1022A'', 1022B'', and 1022C'' are different from each other, the thickness D1'' of the dielectric layer 1022A'' is approximately 160 μm, the thickness D2'' of the dielectric layer 1022B'' is approximately 100 μm, and the thickness D3'' of the dielectric layer 1022C'' is approximately 640 μm. In an exemplary embodiment, the thickness D4'' of the base dielectric layer 1022D'' is approximately 10 mm. In some embodiments, the dielectric ring may be made of a ceramic material.

[0046] In some embodiments, the coil 1021'' is embedded in the protrusion of the dielectric ring 1022''. The coil 1021'' includes a plurality of loops 1021-1'', 1021-2'' and 1021-3''. Each of the plurality of loops 1021-1'', 1021-2'' and 1021-3'' has a thickness T1'' of approximately 50 μm. In some embodiments, the plurality of loops 1021-1'', 1021-2'' and 1021-3'' have a circular cross-sectional profile, and their thickness T1'' defines the diameter of the above-mentioned circular cross-sectional shape. In some embodiments, the number of the plurality of loops 1021-1'', 1021-2'' and 1021-3'' of the coil 1021'' may be greater than or equal to three.

[0047] The distance of each of the plurality of loops 1021-1", 1021-2", and 1021-3" from the bottom surface of the dielectric ring 1022" may depend on the stacking order of the plurality of dielectric layers 1022A", 1022B", and 1022C" of the dielectric ring 1022". In some embodiments, in the dielectric layer 1022A" farthest from the base dielectric layer 1022D", the loop 1021-1" embedded therein is arranged closer to the surface of the dielectric layer 1022A" closer to the adjacent dielectric layer 1022B". In some embodiments, in the dielectric layer 1022C" closest to the base dielectric layer 1022D", the loop 1021-3" embedded therein is arranged closer to the surface of the dielectric layer 1022C" closer to the adjacent dielectric layer 1022B". In some embodiments, the dielectric layer 1022B" has a loop 1021-2" disposed equidistant from two adjacent dielectric layers 1022A" and 1022C". In some embodiments, the coil 1021" may be made of molybdenum manganese.

[0048] Figure 5A A top view of a coil 1021 ″ according to some embodiments disclosed herein is shown. Figure 5B Schematic isometric view of a coil 1021 ″ according to some embodiments disclosed in the present invention. Figure 3 , Figure 5A and Figure 5BIn some embodiments, the plurality of loops 1021-1'', 1021-2'' and 1021-3'' of the coil 1021'' are annular metals coupled to each other to form a conical spiral structure. In some embodiments, the coil 1021'' is a left-handed spiral structure. The plurality of loops 1021-1'', 1021-2'' and 1021-3'' form a spiral shape, wherein when a counterclockwise tightening motion is applied to the coil 1021'' (for example, starting from the loop 1021-1'' farthest from the base dielectric layer 1022D''), the spiral shape structure extends toward the base dielectric layer 1022D''.

[0049] In the current embodiment, a plurality of loops 1021-1", 1021-2", and 1021-3" have different radii from each other and are concentrically arranged with each other. The loop 1021-3" having the largest radius is arranged in the dielectric layer 1022C" closest to the base dielectric layer 1022D". The loop 1021-1" having the smallest radius is arranged in the dielectric layer 1022A" farthest from the base dielectric layer 1022D". The radial distance W" between adjacent loops is approximately 100µm. By forming a metal contact Y" via corresponding adjacent dielectric layers 1022A", 1022B", and 1022C", the adjacent loops 1021-1", 1021-2", and 1021-3" are electrically coupled to each other. Each of the plurality of loops 1021-1", 1021-2", and 1021-3" has a gap X" that terminates the planar conductive path within each loop. The gaps X" of the plurality of loops 1021-1", 1021-2", and 1021-3" are positioned in a clockwise order relative to each other (starting from the gap X" of the loop 1021-1" that is farthest from the base dielectric layer 1022D".

[0050] The metal contacts Y'' of the subsequent layers may be offset in position by a gap distance X''. Since the plurality of loops 1021-1'', 1021-2'', and 1021-3'' have different radii from each other, and the metal contacts Y'' are disposed orthogonally to the plurality of loops 1021-1'', 1021-2'', and 1021-3'', a planar contact Y1'' may be formed that extends tangentially toward the center of the loops 1021-2'' and 1021-3''. The length of the planar contact Y1'' may be substantially the same as the radial distance W'' between adjacent loops. The pitch distance between the plurality of loops 1021-1'', 1021-2'', and 1021-3'' of the coil 1021'' may be in a range between about 100 μm and about 300 μm.

[0051] Figure 6A flow chart of a method for forming a plasma processing system according to some embodiments disclosed in the present invention is shown. The method includes a procedure (601): providing an electrostatic chuck in a processing chamber; a procedure (602): providing a dielectric ring on the electrostatic chuck; and a procedure (603): providing a voltage source configured to supply a DC voltage to a coil to generate a magnetic field, the magnetic field being used to adjust the tilt angle of ions in the plasma to be perpendicular to the top surface of the electrostatic chuck. In some embodiments, the method for forming a plasma processing system also includes providing a tuning ring to cover the dielectric ring. In some embodiments, the method for forming a plasma processing system also includes providing at least one quartz ring surrounding the electrostatic chuck, and providing a quartz filler between the at least one quartz ring and the electrostatic chuck. The method for providing at least one quartz ring includes providing a first quartz ring surrounding the electrostatic chuck, and providing a second quartz ring above the first quartz ring. In some embodiments, the second quartz ring can be designed to be separate from the first quartz ring.

[0052] Figure 7 A flowchart of a method for forming an edge ring according to some embodiments disclosed in the present invention is shown. The method includes a procedure (701): forming a plurality of loops; a procedure (702): forming a plurality of dielectric layers; a procedure (703): electrically coupling the plurality of loops to each other; a procedure (704): forming a base dielectric layer; and a procedure (705): physically coupling the plurality of dielectric layers and the base dielectric layer to each other. When electrically coupled to each other, the plurality of loops form a coil. In some embodiments, the plurality of loops are correspondingly embedded in the plurality of dielectric layers. The above structure can be achieved by, when forming the plurality of dielectric layers, the plurality of loops are correspondingly embedded in the plurality of dielectric layers.

[0053] The aforementioned multiple dielectric layers and the base dielectric layer can be formed by sintering ceramic powder. In its process, a mold can be used to define the shape of the dielectric layer. Specifically, in some embodiments, ceramic powder can be placed in a mold and a pre-formed loop can be buried in the ceramic powder. Heat or pressure is applied to the ceramic powder through the mold, and the ceramic powder is melted to form a solid structure as a dielectric layer. The surface area of ​​the above-mentioned base dielectric layer is set to be larger than each of the multiple dielectric layers. In addition, different molds can be used to form the base dielectric layer in the same manner as the multiple dielectric layers. In addition, embedded loops may not be provided in the base dielectric layer. In some embodiments, multiple dielectric layers and the base dielectric layer can be fused to each other using an adhesive material. In some other embodiments, multiple dielectric layers and the base dielectric layer can be fused to each other by forming multiple dielectric layers and the base dielectric layer on each other in sequence, and they are fused during the sintering process.

[0054] In some embodiments, the metal contact for interconnecting adjacent loops may be preformed together with the adjacent loops. In addition, a portion of the metal contact may protrude from the dielectric layer. In some other embodiments, the metal contact for interconnecting adjacent loops may be preformed and divided in the adjacent loops. For example, half of the metal contact may be formed on one adjacent loop, and the other half of the metal contact may be formed on another adjacent loop. When the corresponding adjacent dielectric layers are fused to each other, the two halves of the metal contact are then electrically coupled to each other. In some other embodiments, the metal contact may be formed after the dielectric layer is formed. For example, a hole may be formed in the dielectric layer to accommodate the metal contact structure. After the metal contact structure is set, if there is an unfilled gap around it, the gap may be filled and eliminated during the adhesion process of the dielectric layers to each other.

[0055] According to some embodiments, a plasma processing system includes an electrostatic chuck surrounded by an edge ring assembly. The edge ring assembly may include a dielectric ring in which a coil is embedded. The coil may be configured in a conical spiral or a cylindrical spiral. A magnetic field is generated by providing a power supply voltage to the coil. The magnetic field is used to generate a force applied to ions in the plasma. When a force is applied to ions near the plasma sheath, ions having an inclined traveling direction angle in the edge region of the wafer may be pushed to correct their inclined direction angle. Without adjustment, the inclined direction angle of the ions may be within a range of about 75° to 85°. After applying a force from the magnetic field for correction, the corrected direction angle may be within a range of about 88° to 90°. Therefore, when a plasma etching process is performed, a groove having an inclined profile formed on the edge region of the wafer during plasma etching may be reduced or avoided. Thereby, the manufacturing yield of the semiconductor process may be improved.

[0056] In view of the foregoing disclosure, one aspect of the present invention provides a plasma processing system for processing a wafer, comprising: an electrostatic chuck; and an edge ring assembly surrounding the electrostatic chuck, the edge ring assembly comprising: a dielectric ring having a top surface, a bottom surface opposite to the top surface, and a protrusion extending upward from the top surface; and a coil embedded in the protrusion of the dielectric ring, the coil having a plurality of loops, each of the plurality of loops having a different distance relative to the bottom surface of the dielectric ring.

[0057] In some embodiments, the system further includes a tuning ring that can be coupled to the top surface of the dielectric ring and covers the protrusion of the dielectric ring.

[0058] In some embodiments, a height of the protrusion of the dielectric ring is greater than or substantially equal to a thickness of the aforementioned wafer.

[0059] In some embodiments, the plurality of loops of the coil are ring-shaped metals coupled to each other to form a conical spiral shape.

[0060] In some embodiments, the plurality of loops are respectively embedded in a plurality of dielectric layers, and the plurality of dielectric layers are stacked on each other to form the dielectric ring.

[0061] In some embodiments, a pitch between the plurality of turns of the coil is in a range between about 100 μm and about 300 μm.

[0062] In some embodiments, the number of the plurality of loops of the coil is greater than or equal to three.

[0063] In some embodiments, the material of the tuning ring includes silicon.

[0064] In some embodiments, the coil is coupled to a DC voltage source, wherein a supply voltage of the DC voltage source is in the range of -24 volts to 24 volts.

[0065] In some embodiments, the system further includes: a voltage terminal passing through the electrostatic chuck and electrically coupled to the DC voltage source.

[0066] Another aspect of the present disclosure provides a method for forming a dielectric ring, comprising: forming a plurality of loops, the plurality of loops being configured to form a coil; forming a plurality of dielectric layers, the plurality of loops being correspondingly embedded in the plurality of dielectric layers; electrically coupling the plurality of loops to each other; forming a base dielectric layer, the surface area of ​​the base dielectric layer being larger than the surface area of ​​each individual one of the plurality of dielectric layers; and physically coupling the plurality of dielectric layers and the base dielectric layer to each other.

[0067] In some embodiments, the plurality of loops are ring-shaped metals coupled to each other to form a cylindrical spiral shape or a conical spiral shape.

[0068] In some embodiments, the method further includes sintering ceramic powder to form the plurality of dielectric layers and the base dielectric layer.

[0069] In some embodiments, the method further includes providing metal contacts between adjacent loops to electrically couple the plurality of loops.

[0070] Another aspect disclosed in the present invention provides a plasma processing chamber, which includes: an electrostatic chuck having a step edge on its periphery, the step edge of the electrostatic chuck having a step base and a step wall that are substantially perpendicular to each other; and an edge ring assembly configured to surround the electrostatic chuck, the edge ring assembly including: a first quartz ring configured to surround the periphery of the electrostatic chuck, the first quartz ring having a step edge on its inner periphery, the step edge of the first quartz ring having a step base and a step wall that are substantially perpendicular to each other; a second quartz ring configured to be disposed on the first quartz ring, the second quartz ring having a step edge on its inner periphery, the step edge of the second quartz ring having a step base and a step wall that are substantially perpendicular to each other; a dielectric ring, the step edge of the dielectric chuck having a step edge on its inner periphery, the step edge of the second quartz ring having a step base and a step wall that are substantially perpendicular to each other; and a dielectric ring, the step edge of the dielectric chuck having a step edge on its inner periphery. A dielectric ring is used to be arranged on the step base of the electrostatic chuck and the step base of the first quartz ring, the dielectric ring having a step edge on its inner circumference, the step edge of the dielectric ring having a step base and a step wall substantially perpendicular to each other; a coil embedded in the dielectric ring and formed along the step wall of the dielectric ring, the coil having a plurality of loops, each of the plurality of loops having a different distance corresponding to the step base of the dielectric ring; and a tuning ring, which is arranged on the step base of the dielectric ring and the step base of the second quartz ring, the tuning ring having a top surface, a bottom surface opposite to the top surface, and a cavity defined and formed along the bottom surface, the cavity covering a portion of the dielectric ring protruding from the step base of the dielectric ring.

[0071] In some embodiments, the plurality of loops of the dielectric ring are ring-shaped metals coupled to each other to form a cylindrical spiral shape or a conical spiral shape.

[0072] In some embodiments, the plurality of loops are respectively embedded in a plurality of dielectric layers, and the plurality of dielectric layers are stacked on each other to form the dielectric ring.

[0073] In some embodiments, the material of the dielectric ring includes ceramic, and the material of the coil includes molybdenum manganese.

[0074] In some embodiments, the system further comprises: a quartz filler configured to be disposed between the edge ring assembly and the electrostatic chuck.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention.

Claims

1. A plasma processing chamber, characterized in that: include: An electrostatic chuck having a stepped edge on its periphery, wherein the stepped edge of the electrostatic chuck has a stepped base and a stepped wall that are substantially perpendicular to each other; and An edge ring assembly configured to surround the electrostatic chuck, the edge ring assembly comprising: a first quartz ring configured to surround the periphery of the electrostatic chuck, the first quartz ring having a step edge on an inner periphery, the step edge of the first quartz ring having a step base and a step wall that are substantially perpendicular to each other; a second quartz ring configured to be disposed on the first quartz ring, the second quartz ring having a step edge on an inner periphery thereof, the step edge of the second quartz ring having a step base and a step wall that are substantially perpendicular to each other; a dielectric ring configured to be disposed on the step base of the electrostatic chuck and the step base of the first quartz ring, the dielectric ring having a step edge on its inner periphery, the step edge of the dielectric ring having a step base and a step wall that are substantially perpendicular to each other; a coil embedded in the dielectric ring and formed along the step wall of the dielectric ring, the coil having a plurality of loops, each of the plurality of loops having a different distance corresponding to the step base of the dielectric ring; and A tuning ring is disposed on the stepped base of the dielectric ring and the stepped base of the second quartz ring, the tuning ring having a top surface, a bottom surface opposite to the top surface, and a cavity defined along the bottom surface, the cavity covering a portion of the dielectric ring protruding from the stepped base of the dielectric ring.

2. The plasma processing chamber according to claim 1, characterized in that Also includes: A quartz packing is configured to be disposed between the edge ring assembly and the electrostatic chuck.

3. The plasma processing chamber according to claim 1, characterized in that The dielectric ring has a top surface and a bottom surface opposite to the top surface and a protrusion extending upward from the top surface; The plasma processing chamber further comprises: A tuning ring is coupled to the top surface of the dielectric ring and covers the protrusion of the dielectric ring.

4. The plasma processing chamber according to claim 3, characterized in that: The plasma processing chamber is used for processing a wafer, and the height of the protrusion of the dielectric ring is greater than or equal to the thickness of the wafer.

5. The plasma processing chamber according to claim 1, wherein: The plurality of loops of the coil are ring-shaped metals coupled to each other to form a cylindrical spiral shape.

6. The plasma processing chamber according to claim 1, wherein: The plurality of loops of the coil are ring-shaped metals coupled to each other to form a conical spiral shape.

7. The plasma processing chamber according to claim 1, wherein: A pitch between the plurality of turns of the coil ranges between 100 μm and 300 μm.

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