A low void ratio flip-chip LED chip and preparation method thereof

Abstract

The present invention discloses a flip-chip LED chip with low void ratio and a preparation method thereof. The flip-chip LED chip comprises a substrate, a light-emitting structure arranged on the substrate, an electrode arranged on the light-emitting structure, a welding layer arranged on the electrode, and a point-measurement contact layer arranged on the welding layer; the welding layer is made of Au and Sn, and the mass percentage of Au and Sn is (15% to 30%): (70% to 85%); wherein the welding layer is a laminated structure, including a multi-layer Sn / Au laminate; or, the welding layer is a laminated structure, including a multi-layer Sn / AuSn laminate; or, the welding layer is a laminated structure, including a multi-layer Au x Sn 1‑x Layer, each layer of Au x Sn 1‑x The ratio of Au to Sn is different. The flip-chip LED chip of the present invention has low void rate and high yield.

Description

Technical Field

[0001] The invention relates to the technical field of light emitting diodes, and in particular to a flip-chip LED chip with a low void ratio and a preparation method thereof. Background Art

[0002] Flip-chip LED chips are widely used in automotive lighting, household lighting, backlight display and other fields due to their outstanding features such as good heat dissipation performance, uniform current distribution, high reliability and high light efficiency.

[0003] AuSn eutectic welding technology is commonly used in the packaging application of flip-chip LED chips. There is no need for wire bonding to fix the die, which greatly reduces the packaging time and cost. However, it has high requirements for the eutectic welding process, and also has high requirements for the selection, flatness and manufacturing process of the packaging substrate. At the same time, it also puts forward higher requirements for the metal preparation process of the solder layer of AuSn eutectic welding.

[0004] In addition, the flip-chip LED chip is welded on the package substrate using AuSn eutectic welding technology, which will produce a high void rate (defective rate). The void rate refers to the welding adhesion effect between the chip pad electrode metal and the package substrate. Through X-Ray scanning of the welding adhesion area, if it is all black, the welding adhesion effect is good, the void rate is small, and the yield rate is high; if the local area of ​​the welding adhesion area appears white (such as Figure 1 As shown in the figure, the more white areas there are, the higher the void rate is and the lower the yield is. The void rate is equal to the ratio of the white area to the total solder adhesion area.

[0005] The void rate is not only affected by the chip pad electrode metal and its process, but also by the packaging process. Generally, packaging manufacturers control the chip void rate below 15%, which is considered qualified. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a flip-chip LED chip with low void ratio, which has low void ratio and high yield.

[0007] The technical problem that the present invention needs to solve is to provide a method for preparing a flip-chip LED chip with a low void ratio. The preparation method is simple and can prepare a flip-chip LED chip with a low void ratio and a high yield.

[0008] In order to solve the above technical problems, the present invention provides a low void ratio flip-chip LED chip, comprising a substrate, a light emitting structure arranged on the substrate, an electrode arranged on the light emitting structure, a welding layer arranged on the electrode, and a point measurement contact layer arranged on the welding layer; the material of the welding layer is Au and Sn, and the mass percentage of Au and Sn is (15% to 30%): (70% to 85%); wherein,

[0009] The welding layer is a laminated structure, including multiple layers of Sn / Au laminated layers; or,

[0010] The welding layer is a laminated structure, including multiple layers of Sn / AuSn laminated layers; or,

[0011] The welding layer is a laminated structure, including multiple layers of Au x Sn 1-x Layer, each layer of Au x Sn 1-x The ratio of Au and Sn is different.

[0012] As an improvement of the above scheme, in the Sn / Au stack, the thickness of Sn is a1, and the thickness of Au is b1, wherein a1:b1=(15-30):(70-85).

[0013] As an improvement of the above scheme, in the Sn / AuSn stack, the thickness of Sn is a2, and the thickness of AuSn is b2, wherein a2:b2=(10-25):(75-90);

[0014] In the Sn / AuSn stack, the thickness of Sn is 0.15 to 0.35 μm, and the thickness of AuSn is 1.05 to 1.55 μm.

[0015] As an improvement of the above solution, the mass percentage of Au and Sn in AuSn is (75% to 82%): (18% to 25%).

[0016] As an improvement of the above solution, the welding layer is from the inside to the outside, that is, from the direction close to the electrode to the direction away from the electrode, each layer of Au x Sn 1-x The content of Au in the sample gradually increases;

[0017] Among them, Au x Sn 1-x In the stack, 0.85≥x≥0.5.

[0018] As an improvement of the above solution, the material of the point-to-point contact layer is selected from gold and / or platinum, and its thickness is 30 to 70 nm.

[0019] Accordingly, the present invention also provides a method for preparing a flip-chip LED chip with a low void ratio, comprising the following steps:

[0020] S1, forming a light-emitting structure on a substrate;

[0021] S2, forming an electrode on the light-emitting structure;

[0022] S3. Form a welding layer on the electrode by electron beam evaporation, thermal evaporation or magnetron sputtering; the welding layer is made of Au and Sn, and the mass percentage of Au and Sn is (15% to 30%): (70% to 85%); wherein the welding layer is a laminated structure, including multiple layers of Sn / Au laminated layers; or, the welding layer is a laminated structure, including multiple layers of Sn / AuSn laminated layers; or, the welding layer is a laminated structure, including multiple layers of Au x Sn 1-x Layer, each layer of Au x Sn 1-x The ratio of Au and Sn is different;

[0023] S4. Form a point measurement contact layer on the welding layer.

[0024] As an improvement of the above solution, the method for preparing the welding layer includes:

[0025] S31, depositing a Sn layer by electron beam evaporation process;

[0026] S32, depositing and forming an Au layer by electron beam evaporation process;

[0027] S33, repeating steps S31 and S32 for multiple times to form a multi-layer Sn / Au stack.

[0028] As an improvement of the above solution, the method for preparing the welding layer includes:

[0029] S31, depositing a Sn layer by electron beam evaporation process;

[0030] S32, depositing and forming an AuSn layer by using an electron beam evaporation process or a thermal evaporation process;

[0031] S33, repeating steps S31 and S32 for multiple times to form a multi-layer Sn / AuSn stack.

[0032] As an improvement of the above solution, the method for preparing the welding layer includes:

[0033] S31, Au is deposited by electron beam evaporation or thermal evaporation x Sn 1-x layer;

[0034] S32, repeat step S31 at least once to form a multilayer Au x Sn 1-x layer.

[0035] The implementation of the present invention has the following beneficial effects:

[0036] The soldering layer of the present invention compounds gold and pure tin layers to form a Sn / Au laminate, and eliminates the stress of the soldering layer by compounding Au and Sn in different proportions, thereby improving the wetting performance between the soldering layer metal and the substrate, thereby reducing the packaging void rate between the soldering layer and the substrate.

[0037] The soldering layer of the present invention forms a Sn / AuSn laminate by compounding different proportions of a gold-tin alloy and a pure tin layer. The stress of the soldering layer is eliminated by compounding Au and Sn in different proportions, and the wetting performance between the soldering layer metal and the substrate is improved, thereby reducing the packaging void rate between the soldering layer and the substrate.

[0038] The soldering layer of the present invention forms Au by compounding gold-tin alloy layers of different proportions. x Sn 1-x The stacking method eliminates the stress of the welding layer by compounding Au and Sn in different proportions, improves the wetting performance between the welding layer metal and the substrate, and thus reduces the packaging void rate between the welding layer and the substrate.

[0039] The advantages of the Au-Sn eutectic soldering of the present invention include: (1) reducing thermal resistance, as both tin (Sn) and gold (Au) materials are metal materials with good thermal conductivity; (2) providing light efficiency, as the luminous efficiency of LEDs is inversely proportional to the thermal resistance; (3) improving efficiency, as LED eutectics are solidified in one step; and (4) having a stronger bonding strength than silver glue solidification, which greatly reduces the phenomenon of crystal shedding.

[0040] The present invention forms a point-testing contact layer on the welding layer, and the point-testing contact layer can be used to ensure the stability of the flip-chip LED chip test and the reliability of the solder layer, thereby further reducing the probability of void generation.

[0041] The present invention adopts electron beam evaporation process to form a single substance Sn layer and a single substance Au layer, and the formed eutectic solder compound (Sn / Au stack) has a stable ratio and a good eutectic effect ratio (low void ratio).

[0042] The present invention adopts electron beam evaporation process to form a single substance Sn layer, and adopts thermal evaporation process to prepare the AuSn layer, whose Au and Sn components are more stable, the eutectic solder compound ratio formed during packaging is more stable, the grains are finer, and the eutectic effect is better (low void rate).

[0043] The present invention adopts the thermal evaporation process to prepare Au x Sn 1-x The Au and Sn components of the layer are more stable, the eutectic solder compound ratio formed during packaging is more stable, the grains are finer, and the eutectic effect is better (low void rate). BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 This is an X-Ray scan of the soldering adhesion area between the existing flip-chip LED chip and the substrate;

[0045] Figure 2 This is a schematic structural diagram of a flip-chip LED chip according to the preferred embodiment 1 of the present invention;

[0046] Figure 3 This is an X-Ray scan of the welding adhesion area between the flip-chip LED chip and the substrate in the preferred embodiment 1 of the present invention;

[0047] Figure 4 This is a schematic diagram of the structure of a flip-chip LED chip according to the preferred embodiment 2 of the present invention;

[0048] Figure 5 This is an X-Ray scan of the welding adhesion area between the flip-chip LED chip and the substrate in the preferred embodiment 2 of the present invention;

[0049] Figure 6 This is a schematic diagram of the structure of a flip-chip LED chip according to the preferred embodiment 3 of the present invention;

[0050] Figure 7 This is an X-Ray scan of the welding adhesion area between the flip-chip LED chip and the substrate in the preferred embodiment 3 of the present invention. DETAILED DESCRIPTION

[0051] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention will be further described in detail below with reference to the accompanying drawings.

[0052] See also Figure 2 As a preferred embodiment 1 of the present invention, the present invention provides a low void ratio flip-chip LED chip, comprising a substrate 10, a light emitting structure 20 arranged on the substrate 10, an electrode 30 arranged on the light emitting structure 20, a welding layer 40 arranged on the electrode 30, and a point contact layer 50 arranged on the welding layer 40, wherein the welding layer 40 is a laminated structure, including a multi-layer Sn / Au laminate.

[0053] The soldering layer 40 of the present invention is formed by combining gold and pure tin layers to form a Sn / Au laminate. The stress of the soldering layer is eliminated by combining Au and Sn in different proportions, and the wetting performance between the soldering layer metal and the substrate is improved, thereby reducing the packaging void rate between the soldering layer and the substrate. Figure 3 , by X-Ray scanning the welding area between the electrode and the substrate of the flip-chip LED chip of this solution, the white area is significantly reduced, that is, the void rate is reduced and the yield rate is increased. Specifically, the welding void rate of the existing flip-chip LED chip is 40% to 60%. Figure 1 As shown in FIG. 1 , the void ratio of the flip-chip LED chip in this solution is 5% to 10%. Figure 3 shown.

[0054] Specifically, the flip-chip LED chip of the present invention can be directly soldered on a substrate plated with gold or silver through the soldering layer 40. Specifically, when the substrate is heated to a suitable eutectic temperature, the gold or silver element will penetrate into the soldering layer to change the composition of the soldering layer, thereby increasing the melting point of the soldering layer, solidifying the soldering layer and firmly soldering the flip-chip LED chip on the substrate. The advantages of the Au-Sn eutectic soldering of the present invention include: (1) reducing thermal resistance, as both tin (Sn) and gold (Au) materials are metal materials with good thermal conductivity; (2) providing light efficiency, as the LED luminous efficiency is inversely proportional to the thermal resistance; (3) improving efficiency, as the LED eutectic is solidified in one step; and (4) the bonding strength is greater than that of silver glue solidification, which greatly reduces the phenomenon of crystal shedding.

[0055] The thickness of Sn and the thickness of Au in the Sn / Au laminate determine the ratio of Sn to Au in the Sn / Au laminate. Since the welding layer of the present invention eliminates the stress of the welding layer by compounding AuSn in different ratios, the wetting performance between the welding layer metal and the substrate is improved, thereby reducing the packaging void rate between the welding layer and the substrate. The mass percentage of Au and Sn is in the range of (15% to 30%): (70% to 85%), and Au and Sn can form a stable eutectic compound. Therefore, the thickness of Sn and the thickness of Au in the Sn / Au laminate should not be too thick or too thin. Preferably, in the Sn / Au laminate, the thickness of Sn is a1, and the thickness of Au is b1, wherein a1:b1=(15 to 30):(70 to 85). More preferably, a1:b1=(18 to 25):(75 to 82).

[0056] Preferably, in the Sn / Au stack, the thickness of Sn is 0.2-0.4 μm, and the thickness of Au is 1-1.5 μm.

[0057] Among them, the total thickness of the welding layer 40 also plays an important role in reducing the packaging void rate between the welding layer 40 and the substrate; if the thickness of the welding layer 40 is too thin, it will not play a role in reducing the packaging void rate; if the thickness of the welding layer 40 is too thick, it will increase the preparation difficulty and production cost.

[0058] Preferably, the welding layer 40 includes 3 to 10 layers of Sn / Au laminates. More preferably, the welding layer 40 includes 3 to 5 layers of Sn / Au laminates.

[0059] Specifically, the light emitting structure 20 includes an epitaxial layer provided on the substrate 10, a transparent conductive layer 24 provided on the epitaxial layer, a reflective layer 25 provided on the transparent conductive layer 24, and a protective layer 26 provided on the reflective layer 25 and the epitaxial layer, wherein the epitaxial layer includes a first semiconductor layer 21 provided on the substrate, an active layer 22 provided on the first semiconductor layer 21, and a second semiconductor layer 23 provided on the active layer 22.

[0060] The electrode 30 includes a first electrode and a second electrode. The first electrode penetrates the protective layer 26 and is disposed on the first semiconductor layer 21 . The second electrode penetrates the protective layer 26 and the reflective layer 25 and is disposed on the transparent conductive layer 24 .

[0061] The reflective layer 25 is a metal reflective layer, which reflects the light emitted by the epitaxial layer to the substrate side, so as to improve the light extraction efficiency of the flip-chip LED chip.

[0062] Preferably, the reflective layer 25 includes an Ag layer and an Ag protective layer, wherein the Ag protective layer covers the Ag layer to prevent Ag from being oxidized when the passivation layer is deposited and to prevent Ag from being etched when the passivation layer is etched.

[0063] Preferably, the material of the Ag protective layer is selected from one or more metals of Ti, W, Al, Ni, and Pt.

[0064] The first electrode and the second electrode have the same structure, and their materials are selected from one or more of Cr, Ni, Al, Ti, Pt, and Au.

[0065] In order to ensure the soldering yield of the flip-chip LED chip, preferably, the first electrode and the second electrode are equal in size and have heights on the same level.

[0066] The present invention forms a point-test contact layer on the soldering layer, which can ensure the stability of the flip-chip LED chip test and the reliability of the solder layer, and further reduce the probability of void generation. Therefore, the material of the point-test contact layer needs to be a metal with good conductivity and not easy to oxidize.

[0067] Preferably, the material of the point-to-point contact layer is selected from gold and / or platinum.

[0068] Among them, the thickness of the point-measurement contact layer plays an important role in the test stability of the flip-chip LED chip and the reliability of the solder layer. If the thickness of the point-measurement contact layer is too thin, it will not protect the solder layer and ensure the test stability; if the thickness of the point-measurement contact layer is too thick, it will also affect the test stability of the flip-chip LED chip and increase the difficulty of preparation and production cost. Preferably, the thickness of the point-measurement contact layer is 30 to 70 nm. More preferably, the thickness of the point-measurement contact layer is 40 to 60 nm.

[0069] Accordingly, the present invention also provides a flip-chip LED chip with a low void ratio, comprising the following steps:

[0070] S1, forming a light-emitting structure on a substrate;

[0071] S2, forming an electrode on the light-emitting structure;

[0072] S3, forming a welding layer on the electrode;

[0073] The preparation method of the welding layer comprises:

[0074] S31, depositing a Sn layer on the electrode by electron beam evaporation process;

[0075] Preferably, the thickness of the Sn layer is 0.2-0.4 μm.

[0076] S32, depositing an Au layer on the Sn layer using an electron beam evaporation process;

[0077] Preferably, the Au layer has a thickness of 1 to 1.5 μm.

[0078] S33, repeating steps S31 and S32 for multiple times to form a multi-layer Sn / Au stack.

[0079] Preferably, steps S31 and S32 are repeated 3 to 10 times to form 3 to 10 Sn / Au stacked layers.

[0080] S4. Form a point measurement contact layer on the welding layer.

[0081] Specifically, the point-measurement contact layer is deposited on the welding layer by electron beam evaporation, magnetron sputtering or thermal evaporation process.

[0082] The present invention adopts electron beam evaporation process to form a single substance Sn layer and a single substance Au layer, and the formed eutectic solder compound (Sn / Au stack) has a stable ratio and a good eutectic effect ratio (low void ratio).

[0083] See also Figure 4 As the preferred solution 2 of the present invention, different from the preferred solution 1, the soldering layer 40 of this solution is a laminated structure, including multiple layers of Sn / AuSn laminated layers. The soldering layer 40 of this solution forms a Sn / AuSn laminated layer by compounding different proportions of gold-tin alloy and pure tin layer. The stress of the soldering layer is eliminated by compounding Au and Sn in different proportions, and the wetting performance between the soldering layer metal and the substrate is improved, thereby reducing the packaging void rate between the soldering layer and the substrate. See Figure 5 , by X-Ray scanning the welding area between the electrode and the substrate of the flip-chip LED chip of this solution, the white area is significantly reduced, that is, the void rate is reduced and the yield rate is increased. Specifically, the welding void rate of the existing flip-chip LED chip is 40% to 60%. Figure 1 As shown in FIG. 1 , the void ratio of the flip-chip LED chip in this solution is 5% to 10%. Figure 5 shown.

[0084] Similarly, the flip-chip LED chip of the present invention can be directly soldered to a substrate plated with gold or silver through the soldering layer 40. Specifically, when the substrate is heated to a suitable eutectic temperature, the gold or silver element will penetrate into the soldering layer to change the composition of the soldering layer, thereby increasing the melting point of the soldering layer, solidifying the soldering layer and firmly soldering the flip-chip LED chip to the substrate. The advantages of the Au-Sn eutectic soldering of the present invention include: (1) reducing thermal resistance, as both tin (Sn) and gold-tin (AuSn) materials are metal materials with good thermal conductivity; (2) providing light efficiency, as the LED luminous efficiency is inversely proportional to the thermal resistance; (3) improving efficiency, as the LED eutectic is solidified in one step; and (4) the bonding strength is greater than that of silver glue solidification, which greatly reduces the phenomenon of crystal shedding.

[0085] The thickness of Sn and the thickness of AuSn in the Sn / AuSn laminate determine the ratio of Sn to Au in the Sn / AuSn laminate. Since the welding layer of the present invention eliminates the stress of the welding layer by compounding AuSn in different proportions, the wetting performance between the welding layer metal and the substrate is improved, thereby reducing the packaging void rate between the welding layer and the substrate. The mass percentage of Au and Sn is within the range of (15% to 30%): (70% to 85%), and Au and Sn can form a stable eutectic compound. Therefore, the thickness of Sn and the thickness of AuSn in the Sn / AuSn laminate should not be too thick or too thin. Preferably, in the Sn / AuSn laminate, the thickness of Sn is a2, and the thickness of AuSn is b2, wherein a2:b2=(10-25):(75-90). More preferably, a2:b2=(15-20):(80%-85%).

[0086] Among them, the ratio of Au and Sn in AuSn will also affect the ratio of Au and Sn in the Sn / AuSn stack; in addition, the ratio of Au and Sn in AuSn will also affect the stability of the AuSn layer, the fineness of the grains and the eutectic effect. Preferably, the mass percentage of Au and Sn in AuSn is in the range of (70% to 85%): (15% to 30%), and AuSn has good stability, fine grains, and good eutectic effect. More preferably, the mass percentage of Au and Sn in AuSn is (75% to 82%): (18% to 25%).

[0087] Preferably, in the Sn / AuSn stack, the thickness of Sn is 0.15-0.35 μm, and the thickness of AuSn is 1.05-1.55 μm.

[0088] Among them, the total thickness of the welding layer 40 also plays an important role in reducing the packaging void rate between the welding layer and the substrate; if the thickness of the welding layer 40 is too thin, it will not play a role in reducing the packaging void rate; if the thickness of the welding layer 40 is too thick, it will increase the preparation difficulty and production cost.

[0089] Preferably, the welding layer 40 includes 3 to 10 layers of Sn / AuSn laminates. More preferably, the welding layer includes 3 to 5 layers of Sn / AuSn laminates.

[0090] In addition, different from the preferred embodiment 1, the method for preparing the welding layer in this embodiment includes:

[0091] S31, depositing a Sn layer on the electrode by electron beam evaporation process;

[0092] Preferably, the thickness of the Sn layer is 0.15-0.35 μm.

[0093] S32, depositing an AuSn layer on the Sn layer by using an electron beam evaporation process or a thermal evaporation process;

[0094] Among them, compared with the electron beam evaporation process, the AuSn layer prepared by the thermal evaporation process has more stable Au and Sn components, a more stable eutectic solder compound ratio formed during packaging, finer grains, and a better eutectic effect (low void rate). The AuSn layer prepared by the electron beam evaporation process is prone to imbalance in the eutectic solder compound ratio formed during packaging (low Sn content), and the eutectic effect is not as good as the AuSn layer prepared by the thermal evaporation process.

[0095] Preferably, the AuSn layer has a thickness of 1.05 to 1.55 μm.

[0096] S33, repeating steps S31 and S32 for multiple times to form a multi-layer Sn / AuSn stack.

[0097] Preferably, steps S31 and S32 are repeated 3 to 10 times to form 3 to 10 layers of Sn / AuSn stacks.

[0098] See also Figure 6 As the preferred solution 3 of the present invention, different from the preferred solution 1, the welding layer of this solution is a laminated structure, including multiple layers of Au x Sn 1-x Layer, where each layer of Au x Sn 1-x The ratio of Au to Sn is different, that is, each layer of Au x Sn 1-x The size of x is different.

[0099] Preferably, the welding layer is from the inside to the outside, that is, from the direction close to the electrode to the direction away from the electrode, each layer of Au x Sn 1-x The Au content in the solder layer gradually increases. That is, from the inside to the outside, each layer of Au x Sn 1-x The x in the middle gradually gets bigger.

[0100] The soldering layer of this scheme combines different proportions of gold-tin alloy layers to form Au x Sn 1-x The stacking method eliminates the stress of the solder layer by combining Au and Sn in different proportions, improves the wetting performance between the solder layer metal and the substrate, and thus reduces the packaging void rate between the solder layer and the substrate. Figure 7 , by X-Ray scanning the welding area between the electrode and the substrate of the flip-chip LED chip of this solution, the white area is significantly reduced, that is, the void rate is reduced and the yield rate is increased. Specifically, the welding void rate of the existing flip-chip LED chip is 40% to 60%. Figure 1 As shown in FIG. 1 , the void ratio of the flip-chip LED chip in this solution is 5% to 10%. Figure 7 shown.

[0101] Similarly, the flip-chip LED chip of the present invention can be directly soldered to a substrate plated with gold or silver through a soldering layer. Specifically, when the substrate is heated to a suitable eutectic temperature, gold or silver elements will penetrate into the soldering layer to change the composition of the soldering layer, thereby increasing the melting point of the soldering layer, solidifying the soldering layer and firmly soldering the flip-chip LED chip to the substrate. The advantages of the Au-Sn eutectic soldering of the present invention include: (1) reducing thermal resistance, as both tin (Sn) and gold (Sn) materials are metal materials with good thermal conductivity; (2) providing light efficiency, as the LED luminous efficiency is inversely proportional to the thermal resistance; (3) improving efficiency, as the LED eutectic is solidified in one step; and (4) the bonding strength is greater than that of silver glue solidification, which greatly reduces the phenomenon of crystal shedding.

[0102] Among them, Au x Sn 1-x The size of x in the stack determines the ratio of Sn to Au. Since the welding layer of the present invention eliminates the stress of the welding layer by compounding AuSn in different ratios, the wetting performance between the welding layer metal and the substrate is improved, thereby reducing the packaging void rate between the welding layer and the substrate, wherein 0.85≥x≥0.5, that is, x cannot be less than 0.5. If x is less than 0.5, the Au content is too little, In will diffuse to the surface of the welding layer, and affect the point-to-point electrical properties of the flip-chip LED chip; if x is greater than 0.85, the Au content is too large, and Au and Sn cannot form a stable eutectic compound.

[0103] Wherein, the total mass ratio of Au and Sn in the welding layer is within the range of (15% to 30%): (70% to 85%), and Au and Sn can form a stable eutectic compound. It should be noted that the total thickness of the welding layer also plays an important role in reducing the packaging void rate between the welding layer and the substrate; if the thickness of the welding layer is too thin, it will not play a role in reducing the packaging void rate; if the thickness of the welding layer is too thick, it will increase the difficulty of preparation and production cost.

[0104] Preferably, the welding layer includes 3 to 10 layers of Aux Sn 1-x More preferably, the welding layer includes 3 to 5 layers of Au x Sn 1-x Optimally, the welding layer includes 3 layers of Au x Sn 1-x Layers, where the first layer is Au 0.75 Sn 0.25 , the second layer is Au 0.8 Sn 0.2 , the third layer is Au 0.85 Sn 0.15 , the first layer Au 0.75 Sn 0.25 Set on the electrode, the second layer of Au 0.8 Sn 0.2 Set on the first layer Au 0.75 Sn 0.25 On the third layer, Au 0.85 Sn 0.15 Set on the second layer Au 0.8 Sn 0.2 superior.

[0105] In addition, different from the preferred embodiment 1, the method for preparing the welding layer in this embodiment includes:

[0106] S31, deposit Au on the electrode using electron beam evaporation or thermal evaporation x Sn 1-x layer;

[0107] S32, repeat step S31 at least once to form a multilayer Au x Sn 1-x layer.

[0108] Compared with the electron beam evaporation process, the Au prepared by thermal evaporation process x Sn 1-x The Au and Sn components of the layer are more stable, the eutectic solder compound ratio formed during packaging is more stable, the grains are finer, and the eutectic effect is better (low void rate). Au prepared by electron beam evaporation process x Sn 1-x The ratio of the eutectic solder compound formed during packaging is easily unbalanced (low Sn content), and the eutectic effect is not as good as the AuSn layer prepared by thermal evaporation process.

[0109] The present invention will be further described with specific embodiments below.

[0110] Example 1

[0111] A low void ratio flip-chip LED chip, comprising a substrate, a light emitting structure arranged on the substrate, an electrode arranged on the light emitting structure, a welding layer arranged on the electrode, and a spot contact layer arranged on the welding layer, wherein the welding layer is a laminated structure, comprising three layers of Sn / Au laminates, wherein in each Sn / Au laminate, the thickness of Sn is 0.2 μm, and the thickness of Au is 1 μm;

[0112] The Sn layer and the Au layer are formed by electron beam evaporation process.

[0113] Example 2

[0114] A low void ratio flip-chip LED chip, comprising a substrate, a light emitting structure arranged on the substrate, an electrode arranged on the light emitting structure, a welding layer arranged on the electrode, and a spot contact layer arranged on the welding layer, wherein the welding layer is a laminated structure, comprising 5 layers of Sn / Au laminated layers, wherein in each Sn / Au laminated layer, the thickness of Sn is 0.3 μm, and the thickness of Au is 1.3 μm;

[0115] The Sn layer and the Au layer are formed by electron beam evaporation process.

[0116] Example 3

[0117] A low void ratio flip-chip LED chip comprises a substrate, a light emitting structure arranged on the substrate, an electrode arranged on the light emitting structure, a welding layer arranged on the electrode, and a point contact layer arranged on the welding layer. The welding layer is a laminated structure, comprising three layers of Sn / AuSn laminates. In each Sn / AuSn laminate, the thickness of Sn is 0.15 μm, the thickness of AuSn is 1.05 μm, and the ratio of Au to Sn in AuSn is 75%:25%.

[0118] The Sn layer and the AuSn layer are formed by electron beam evaporation process.

[0119] Example 4

[0120] A low void ratio flip-chip LED chip comprises a substrate, a light emitting structure arranged on the substrate, an electrode arranged on the light emitting structure, a welding layer arranged on the electrode, and a spot contact layer arranged on the welding layer, wherein the welding layer is a laminated structure, comprising three layers of Sn / AuSn laminated layers, in each Sn / AuSn laminated layer, the thickness of Sn is 0.15 μm, the thickness of AuSn is 1.05 μm, and the ratio of Au to Sn in AuSn is 75%:25%;

[0121] The Sn layer is formed by electron beam evaporation process, and the AuSn layer is formed by thermal evaporation process.

[0122] Example 5

[0123] A low void ratio flip-chip LED chip, comprising a substrate, a light emitting structure arranged on the substrate, an electrode arranged on the light emitting structure, a welding layer arranged on the electrode, and a point measurement contact layer arranged on the welding layer, wherein the welding layer is a laminated structure, comprising three layers of Au x Sn 1-x Layers, where the first layer is Au 0.75 Sn 0.25 , the second layer is Au 0.8 Sn 0.2 , the third layer is Au 0.85 Sn 0.15 , the first layer Au 0.75 Sn 0.25 Set on the electrode, the second layer of Au 0.8 Sn 0.2 Set on the first layer Au 0.75 Sn 0.25 On the third layer, Au 0.85 Sn 0.15 Set on the second layer Au 0.8 Sn 0.2 superior;

[0124] Among them, the electron beam evaporation process is used to form 3 layers of Au x Sn 1-x layer.

[0125] Example 6

[0126] A low void ratio flip-chip LED chip, comprising a substrate, a light emitting structure arranged on the substrate, an electrode arranged on the light emitting structure, a welding layer arranged on the electrode, and a point measurement contact layer arranged on the welding layer, wherein the welding layer is a laminated structure, comprising three layers of Au x Sn 1-x Layers, where the first layer is Au 0.75 Sn 0.25 , the second layer is Au 0.8 Sn 0.2 , the third layer is Au 0.85 Sn 0.15 , the first layer Au 0.75 Sn 0.25 Set on the electrode, the second layer of Au 0.8 Sn 0.2 Set on the first layer Au 0.75 Sn 0.25 On the third layer, Au 0.85 Sn 0.15 Set on the second layer Au 0.8 Sn 0.2 superior;

[0127] Among them, three layers of Au are formed by thermal evaporation process. x Sn1-x layer.

[0128] Comparative Example 1

[0129] A flip-chip LED chip comprises a substrate, a light-emitting structure arranged on the substrate, an electrode arranged on the light-emitting structure, and a soldering layer arranged on the electrode, wherein the soldering layer is a laminated structure, comprising three layers of Sn / Au laminates, wherein in each Sn / Au laminate, the thickness of Sn is 0.2 μm and the thickness of Au is 1 μm;

[0130] The Sn layer and the Au layer are formed by electron beam evaporation process.

[0131] Comparative Example 2

[0132] A low void ratio flip-chip LED chip comprises a substrate, a light emitting structure arranged on the substrate, an electrode arranged on the light emitting structure, a welding layer arranged on the electrode, and a point contact layer arranged on the welding layer, wherein the welding layer is a Sn / Au stack, the thickness of Sn is 0.5 μm, and the thickness of Au is 0.5 μm; wherein the Sn layer and the Au layer are formed by electron beam evaporation process.

[0133] Comparative Example 3

[0134] A low void ratio flip-chip LED chip comprises a substrate, a light emitting structure arranged on the substrate, an electrode arranged on the light emitting structure, a welding layer arranged on the electrode, and a point contact layer arranged on the welding layer, wherein the welding layer is a Sn / AuSn stack, the thickness of Sn is 0.3 μm, and the thickness of AuSn is 2 μm; wherein the Sn layer and the AuSn layer are formed by electron beam evaporation process.

[0135] Comparative Example 4

[0136] A low void ratio flip-chip LED chip comprises a substrate, a light emitting structure arranged on the substrate, an electrode arranged on the light emitting structure, a welding layer arranged on the electrode, and a point contact layer arranged on the welding layer, wherein the welding layer is an AuSn layer with a thickness of 2 μm, wherein the AuSn layer is formed by an electron beam evaporation process.

[0137] The flip-chip LED chips of Examples 1 to 6 and Comparative Examples 1 to 4 were soldered on substrates of the same specifications to test their void defect rates. The number of test chips for each Example and Comparative Example was 500, and the structures were as follows:

[0138]

[0139] The above disclosure is only a preferred embodiment of the present invention, which certainly cannot be used to limit the scope of the present invention. Therefore, equivalent changes made according to the claims of the present invention are still within the scope of the present invention.

Claims

1. A low void ratio flip-chip LED chip, comprising a substrate, a light emitting structure disposed on the substrate, and an electrode disposed on the light emitting structure, characterized in that: It also includes a welding layer arranged on the electrode, and a point contact layer arranged on the welding layer; the material of the welding layer is Au and Sn, and the mass percentage of Au and Sn is (15%~30%): (70%~85%); wherein, The welding layer is a laminated structure, including multiple layers of Sn / AuSn laminates; In the Sn / AuSn stack, the thickness of Sn is a2, and the thickness of AuSn is b2, where a2:b2=(10~25):(75~90).

2. The low void ratio flip-chip LED chip according to claim 1, characterized in that: The mass percentage of Au and Sn in AuSn is (75%~82%):(18%~25%).

3. The low void ratio flip-chip LED chip according to claim 1, characterized in that: The material of the point-to-point contact layer is selected from gold and / or platinum, and the thickness thereof is 30-70 nm.

4. A method for preparing a flip-chip LED chip with low void ratio, characterized in that: The following steps are involved: S1, forming a light-emitting structure on a substrate; S2, forming an electrode on the light-emitting structure; S3, forming a welding layer on the electrode by electron beam evaporation process, thermal evaporation process or magnetron sputtering process; the material of the welding layer is Au and Sn, and the mass percentage of Au and Sn is (15%~30%): (70%~85%); wherein the welding layer is a laminated structure, including a multi-layer Sn / AuSn laminate; S4, forming a point measurement contact layer on the welding layer; The preparation method of the welding layer comprises: S31, depositing a Sn layer by electron beam evaporation process; S32, depositing and forming an AuSn layer by using an electron beam evaporation process or a thermal evaporation process; S33, repeating steps S31 and S32 for multiple times to form a multi-layer Sn / AuSn stack.

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