Display device

Abstract

The display device includes a display panel, a gate driver, a data driver, an emission controller, and a drive controller, the display panel includes pixels, the pixels include a first type of switching element and a second type of switching element different from the first type, the gate driver is used to generate a gate signal based on a gate clock signal and provide the gate signal to the display panel, the data driver is used to provide a data voltage to the display panel, the emission controller is used to provide an emission control signal to the display panel, and the drive controller is used to generate a control signal for controlling the gate driver, the data driver, and the emission controller. In a low-frequency driving mode, the display panel operates in a writing frame for writing data into the pixel and a holding frame for holding the data written into the pixel, and the drive controller provides a gate clock signal having a DC voltage to the gate driver during the holding frame.

Description

Technical Field

[0001] The present invention relates to a display device and a method for driving the display device. Background Art

[0002] Generally, a display device includes a display panel and a display panel driver. The display panel includes a plurality of pixels, a plurality of gate lines, a plurality of data lines, and a plurality of emission control lines. The display panel driver includes a gate driver configured to provide a gate signal to the gate line, a data driver configured to provide a data voltage to the data line, an emission controller configured to provide an emission control signal to the emission control line, and a drive controller configured to generate a control signal for controlling the gate driver, the data driver, and the emission controller.

[0003] Recently, when an image displayed on a display panel is a still image, or the display panel is driven in an always-on display (AOD) mode, a method for reducing power consumption through low-frequency driving has been studied. Summary of the invention

[0004] Technical issues

[0005] An object of the present invention is to provide a display device capable of reducing power consumption of a display panel.

[0006] However, the object of the present invention is not limited thereto. Therefore, the object of the present invention can be expanded without departing from the spirit and scope of the present invention.

[0007] Solutions to technical problems

[0008] According to an embodiment, a display device may include a display panel, a gate driver, a data driver, an emission controller, and a drive controller, wherein the display panel includes pixels, the pixels include a first type of switching element and a second type of switching element different from the first type, the gate driver is configured to generate a gate signal based on a gate clock signal and provide the gate signal to the display panel, the data driver is configured to provide a data voltage to the display panel, the emission controller is configured to provide an emission control signal to the display panel, and the drive controller is configured to generate a control signal for controlling the gate driver, the data driver, and the emission controller. Here, in a low-frequency driving mode, the drive controller may provide the gate clock signal swinging between a high level and a low level to the gate driver during a writing frame for writing data to the pixel, and may provide the gate clock signal having a DC voltage to the gate driver during a holding frame for holding the data written in the pixel.

[0009] In an embodiment, in the low frequency driving mode, the gate clock signal may swing between the high level and the low level during the write frame, and may be maintained at the low level during the hold frame.

[0010] In an embodiment, in the low frequency driving mode, the gate clock signal may swing between the high level and the low level during the write frame, and may be maintained at the high level during the hold frame.

[0011] In an embodiment, the first type of switching element may be a polysilicon thin film transistor. In addition, the second type of switching element may be an oxide thin film transistor.

[0012] In an embodiment, the first type of switch element may be a P-type transistor. In addition, the second type of switch element may be an N-type transistor.

[0013] In an embodiment, the pixel may include a first switching element, a second switching element, a third switching element, a fourth switching element, a fifth switching element, a sixth switching element, a seventh switching element, a storage capacitor and an organic light emitting diode, the first switching element includes a gate electrode connected to a first node, a first electrode connected to a second node and a second electrode connected to a third node, the second switching element includes a gate electrode to which a first data write gate signal is applied, a first electrode to which the data voltage is applied and a second electrode connected to the second node, the third switching element includes a gate electrode to which a second data write gate signal is applied, a first electrode connected to the first node and a second electrode connected to the third node, the fourth switching element includes a gate electrode to which a data initialization gate signal is applied, a first electrode to which an initialization voltage is applied and a second electrode connected to the third node. The first electrode and the second electrode connected to the first node, the fifth switching element includes a gate electrode applied with the emission control signal, a first electrode applied with a high power supply voltage, and a second electrode connected to the second node, the sixth switching element includes a gate electrode applied with the emission control signal, a first electrode connected to the third node, and a second electrode connected to the anode of the organic light emitting diode, the seventh switching element includes a gate electrode applied with an organic light emitting diode initialization gate signal, a first electrode applied with the initialization voltage, and a second electrode connected to the anode of the organic light emitting diode, the storage capacitor includes a first electrode applied with the high power supply voltage and a second electrode connected to the first node, and the organic light emitting diode includes the anode and a cathode applied with a low power supply voltage.

[0014] In an embodiment, the first switching element, the second switching element, the fifth switching element, and the sixth switching element may be the polysilicon thin film transistor. In addition, the third switching element, the fourth switching element, and the seventh switching element may be the oxide thin film transistor.

[0015] In an embodiment, in the low-frequency driving mode, the second switching element, the fifth switching element, and the sixth switching element may be driven at a first driving frequency, and the third switching element may be driven at a second driving frequency lower than the first driving frequency.

[0016] In an embodiment, the driving controller may include a gate controller configured to generate the gate clock signal.

[0017] According to an embodiment, a display device may include a display panel, a gate driver, a data driver, an emission controller, and a drive controller, wherein the display panel includes pixels, the pixels include a first type of switching element and a second type of switching element different from the first type, the gate driver is configured to provide a gate signal to the display panel, the data driver is configured to provide a data voltage to the display panel, the emission controller is configured to provide an emission control signal to the display panel, and the drive controller is configured to generate a control signal for controlling the gate driver, the data driver, and the emission controller. Here, in a low-frequency driving mode, the drive controller may provide an analog driving voltage for operating the data driver to the data driver during a writing frame for writing data to the pixel, and may provide the analog driving voltage for not operating the data driver to the data driver during a holding frame for holding the data written in the pixel.

[0018] In an embodiment, in the low-frequency driving mode, the driving controller may provide the analog driving voltage having a first voltage level to the data driver during the write frame, and may provide the analog driving voltage having a second voltage level lower than the first voltage level to the data driver during the hold frame.

[0019] In an embodiment, the first type of switching element may be a polysilicon thin film transistor. In addition, the second type of switching element may be an oxide thin film transistor.

[0020] In an embodiment, the first type of switch element may be a P-type transistor. In addition, the second type of switch element may be an N-type transistor.

[0021] In an embodiment, the pixel may include a first switching element, a second switching element, a third switching element, a fourth switching element, a fifth switching element, a sixth switching element, a seventh switching element, a storage capacitor and an organic light emitting diode, the first switching element includes a gate electrode connected to a first node, a first electrode connected to a second node and a second electrode connected to a third node, the second switching element includes a gate electrode to which a first data write gate signal is applied, a first electrode to which the data voltage is applied and a second electrode connected to the second node, the third switching element includes a gate electrode to which a second data write gate signal is applied, a first electrode connected to the first node and a second electrode connected to the third node, the fourth switching element includes a gate electrode to which a data initialization gate signal is applied, a first electrode to which an initialization voltage is applied and a second electrode connected to the third node. The first electrode and the second electrode connected to the first node, the fifth switching element includes a gate electrode applied with the emission control signal, a first electrode applied with a high power supply voltage, and a second electrode connected to the second node, the sixth switching element includes a gate electrode applied with the emission control signal, a first electrode connected to the third node, and a second electrode connected to the anode of the organic light emitting diode, the seventh switching element includes a gate electrode applied with an organic light emitting diode initialization gate signal, a first electrode applied with the initialization voltage, and a second electrode connected to the anode of the organic light emitting diode, the storage capacitor includes a first electrode applied with the high power supply voltage and a second electrode connected to the first node, and the organic light emitting diode includes the anode and a cathode applied with a low power supply voltage.

[0022] In an embodiment, the first switching element, the second switching element, the fifth switching element, and the sixth switching element may be the polysilicon thin film transistor. In addition, the third switching element, the fourth switching element, and the seventh switching element may be the oxide thin film transistor.

[0023] In an embodiment, in the low-frequency driving mode, the second switching element, the fifth switching element, and the sixth switching element may be driven at a first driving frequency, and the third switching element may be driven at a second driving frequency lower than the first driving frequency.

[0024] In an embodiment, the pixel may further include an eighth switching element including a gate electrode to which a hold voltage enable signal is applied, a first electrode to which a hold voltage is applied, and a second electrode connected to the first electrode of the second switching element.

[0025] In an embodiment, in the low frequency driving mode, the driving controller may provide the analog driving voltage to the data driver during the writing frame, and may provide the holding voltage to the pixel during the holding frame.

[0026] In an embodiment, the eighth switching element may be the polysilicon thin film transistor.

[0027] In an embodiment, the driving controller may include a voltage generator configured to generate a voltage provided to the data driver and the pixel.

[0028] Effects of the Invention

[0029] According to an embodiment of the present invention, in a low-frequency driving mode of a display device including pixels having a first type of switching element and a second type of switching element, the display device provides a gate clock signal having a DC voltage to a gate driver during a holding frame, so that power consumption can be reduced.

[0030] According to an embodiment of the present invention, in a low frequency driving mode of a display device including pixels having first and second type switching elements, the display device does not operate a data driver during a holding frame, so that power consumption can be reduced.

[0031] In addition, according to an embodiment of the present invention, in a low-frequency driving mode of a display device including pixels having a first type of switching element and a second type of switching element, the display device supplies a holding voltage to the pixel during a holding frame, so that leakage current can be prevented from being generated and the brightness of the pixel can be constantly maintained. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a block diagram showing a display device according to an embodiment of the present invention.

[0033] Figure 2 It is shown that the Figure 1 A circuit diagram of an example of a pixel in a display device.

[0034] Figure 3 is shown applied to Figure 2 Timing diagram of the pixel input signal.

[0035] Figure 4 is shown in low frequency drive mode applied to Figure 2 A timing diagram of an example of a pixel signal.

[0036] Figure 5 is shown in low frequency drive mode applied to Figure 2 FIG. 1 is a timing diagram of another example of a signal of a pixel.

[0037] Figure 6 It is shown that the Figure 1 A circuit diagram of another example of a pixel in a display device.

[0038] Figure 7 is shown in low frequency drive mode applied to Figure 6 A timing diagram of an example of a pixel signal.

[0039] Figure 8 It is shown that Figure 1 A block diagram of an electronic device of a display device.

[0040] Fig. 9 It is shown Figure 8 The electronic device is implemented as an example of a smart phone. DETAILED DESCRIPTION

[0041] Hereinafter, embodiments of the present invention will be explained in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used to indicate the same components, and repeated description of the same components will be omitted.

[0042] Figure 1 is a block diagram showing a display device according to an embodiment of the present invention.

[0043] Reference Figure 1 The display device 100 may include a display panel 110 and a display panel driver. The display panel driver may include a gate driver 120, a data driver 130, an emission controller 140, and a driving controller 150.

[0044] The display panel 110 may include a plurality of gate lines GWPL, GWNL, GIL, and GBL, a plurality of data lines DL, a plurality of emission control lines EML, a sustaining voltage supply line VsusL, and a plurality of pixels PX electrically connected to the gate lines GWPL, GWNL, GIL, and GBL, the data lines DL, the emission control lines EML, and the sustaining voltage supply line VsusL. The gate lines GWPL, GWNL, GIL, and GBL, the emission control lines EML, and the sustaining voltage supply line VsusL may extend in a first direction D1, and may be arranged in a second direction D2 perpendicular to the first direction D1. The data lines DL may extend in a second direction D2, and may be arranged in the first direction D1. The first direction D1 may be parallel to the long side of the display panel 110, and the second direction D2 may be parallel to the short side of the display panel 110. Each of the pixels PX may be formed in a region where a gate line intersects with a data line DL.

[0045] The driving controller 150 may receive input image data IMG and an input control signal CON from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may include white image data. The input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CON may include a main clock signal and a data enable signal. The input control signal CON may also include a vertical synchronization signal and a horizontal synchronization signal.

[0046] The driving controller 150 may generate control signals CTL1 , CTL2 , and CTL3 for controlling the gate driver 120 , the data driver 130 , and the emission controller 140 based on the input image data IMG and the input control signal CON.

[0047] The driving controller 150 may generate a first control signal CTL1 for controlling the operation of the gate driver 120 based on the input control signal CON. The driving controller 150 may output the first control signal CTL1 to the gate driver 120. For example, the first control signal CTL1 may include a vertical start signal and a gate clock signal. In one embodiment, in the low-frequency driving mode, the driving controller 150 may provide a gate clock signal swinging between a high level and a low level to the gate driver 120 during a write frame for writing data to the pixel PX, and provide a gate clock signal having a DC voltage to the gate driver 120 during a hold frame for holding the data written in the pixel PX. For example, the driving controller 150 may include a gate controller configured to generate a gate clock signal.

[0048] The driving controller 150 may generate a second control signal CTL2 for controlling the operation of the data driver 130 based on the input control signal CON. The driving controller 150 may output the second control signal CTL2 to the data driver 130. For example, the second control signal CTL2 may include a horizontal start signal and a load signal.

[0049] The driving controller 150 may generate a data signal DATA based on the input image data IMG. For example, the driving controller 150 may convert the input image data IMG into the data signal DATA by applying an algorithm for compensating the image quality of the input image data IMG. The driving controller 150 may output the data signal DATA to the data driver 130.

[0050] In addition, the driving controller 150 may generate an analog driving voltage AVDD for operating the data driver 130. The driving controller 150 may output the analog driving voltage AVDD to the data driver 130. In addition, the driving controller 150 may generate a holding voltage Vsus for constantly holding the driving current of the pixel PX. The driving controller 150 may provide the holding voltage Vsus to the pixel PX. For example, the driving controller 150 may include a voltage generator configured to generate a voltage provided to the data driver 130 and the pixel PX. In one embodiment, in the low-frequency driving mode, the driving controller 150 may provide the analog driving voltage AVDD having a first voltage level to the data driver 130 during the writing frame, and provide the analog driving voltage AVDD having a second voltage level (e.g., 0V) to the data driver 130 during the holding frame. In another embodiment, in the low-frequency driving mode, the driving controller 150 may provide the analog driving voltage AVDD having a first voltage level to the data driver 130 during the writing frame, and provide the holding voltage Vsus having a third voltage level to the pixel PX during the holding frame. For example, the third voltage level may be equal to or different from the first voltage level.

[0051] The driving controller 150 may generate a third control signal CTL3 for controlling the operation of the emission controller 140 based on the input control signal CON. The driving controller 150 may output the third control signal CTL3 to the emission controller 140.

[0052] The gate driver 120 may generate gate signals GWP, GWN, GI, and GB in response to the first control signal CTL1 supplied from the driving controller 150. The gate driver 120 may output the gate signals GWP, GWN, GI, and GB to the gate lines GWPL, GWNL, GIL, and GBL.

[0053] The data driver 130 may generate a data voltage Vd based on a second control signal CTL2, an analog driving voltage AVDD, and a data signal DATA supplied from the driving controller 150. The data driver 130 may generate a gamma reference voltage based on the second control signal CTL2 and the analog driving voltage AVDD received from the driving controller 150. The gamma reference voltage may have a value corresponding to each data signal DATA. For example, the data driver 130 may generate a gamma reference voltage by allocating the analog driving voltage AVDD supplied from the driving controller 150. The data driver 130 may convert the data signal DATA into an analog data voltage Vd by using the gamma reference voltage. The data driver 130 may output the data voltage Vd to the data line DL.

[0054] The emission controller 140 may generate an emission control signal EM in response to the third control signal CTL3 supplied from the driving controller 150. The emission controller 140 may output the emission control signal EM to the emission control line EML.

[0055] Figure 2 It is shown that the Figure 1 A circuit diagram of an example of a pixel in a display device, and Figure 3 is shown applied to Figure 2 Timing diagram of the pixel input signal.

[0056] Reference Figures 1 to 3 , the display panel 110 may include a plurality of pixels PX, and each of the pixels PX may include an organic light emitting diode OLED.

[0057] The pixel PX receives the data writing gate signals GWP and GWN, the data initialization gate signal GI, the organic light emitting diode initialization gate signal GB, and the emission control signal EM to emit light from the organic light emitting diode OLED according to the level of the data voltage Vd so that an image can be displayed.

[0058] According to an embodiment of the present invention, each of the pixels PX may include a first type of switching element and a second type of switching element different from the first type. For example, the first type of switching element may be a polysilicon thin film transistor. For example, the first type of switching element may be a low temperature polysilicon (LTPS) thin film transistor. For example, the second type of switching element may be an oxide thin film transistor. For example, the first type of switching element may be a P-type transistor, and the second type of switching element may be an N-type transistor.

[0059] For example, the data write gate signals GWP and GWN may include a first data write gate signal GWP and a second data write gate signal GWN. The first data write gate signal GWP may be applied to a P-type transistor and may have a low-level activation signal at a data write timing. The second data write gate signal GWN may be applied to an N-type transistor and may have a high-level activation signal at a data write timing.

[0060] According to an embodiment of the present invention, each of the pixels PX may include first, second, third, fourth, fifth, sixth and seventh switching elements T1, T2, T3, T4, T5, T6 and T7, a storage capacitor CST and an organic light emitting diode OLED.

[0061] The first switching element T1 may include a gate electrode connected to the first node N1, a first electrode connected to the second node N2, and a second electrode connected to the third node N3. For example, the first switching element T1 may be a polysilicon thin film transistor. The first switching element T1 may be a P-type thin film transistor. The first electrode of the first switching element T1 may be a source electrode, and the second electrode of the first switching element T1 may be a drain electrode.

[0062] The second switching element T2 may include a gate electrode to which a first data write gate signal GWP is applied, a first electrode to which a data voltage Vd is applied, and a second electrode connected to the second node N2. For example, the second switching element T2 may be a polysilicon thin film transistor. The second switching element T2 may be a P-type thin film transistor. The first electrode of the second switching element T2 may be a source electrode, and the second electrode of the second switching element T2 may be a drain electrode.

[0063] The third switching element T3 may include a gate electrode to which the second data write gate signal GWN is applied, a first electrode connected to the first node N1, and a second electrode connected to the third node N3. For example, the third switching element T3 may be an oxide thin film transistor. The third switching element T3 may be an N-type thin film transistor. The first electrode of the third switching element T3 may be a source electrode, and the second electrode of the third switching element T3 may be a drain electrode.

[0064] The fourth switching element T4 may include a gate electrode to which a data initialization gate signal GI is applied, a first electrode to which an initialization voltage VI is applied, and a second electrode connected to the first node N1. For example, the fourth switching element T4 may be an oxide thin film transistor. The fourth switching element T4 may be an N-type thin film transistor. The first electrode of the fourth switching element T4 may be a source electrode, and the second electrode of the fourth switching element T4 may be a drain electrode.

[0065] The fifth switching element T5 may include a gate electrode to which an emission control signal EM is applied, a first electrode to which a high power supply voltage ELVDD is applied, and a second electrode connected to the second node N2. For example, the fifth switching element T5 may be a polysilicon thin film transistor. The fifth switching element T5 may be a P-type thin film transistor. The first electrode of the fifth switching element T5 may be a source electrode, and the second electrode of the fifth switching element T5 may be a drain electrode.

[0066] The sixth switching element T6 may include a gate electrode to which an emission control signal EM is applied, a first electrode connected to the third node N3, and a second electrode connected to the anode of the organic light emitting diode OLED. For example, the sixth switching element T6 may be a polysilicon thin film transistor. The sixth switching element T6 may be a P-type thin film transistor. The first electrode of the sixth switching element T6 may be a source electrode, and the second electrode of the sixth switching element T6 may be a drain electrode.

[0067] The seventh switching element T7 may include a gate electrode to which an organic light emitting diode initialization gate signal GB is applied, a first electrode to which an initialization voltage V1 is applied, and a second electrode connected to an anode of the organic light emitting diode OLED. For example, the seventh switching element T7 may be an oxide thin film transistor. The seventh switching element T7 may be an N-type thin film transistor. The first electrode of the seventh switching element T7 may be a source electrode, and the second electrode of the seventh switching element T7 may be a drain electrode.

[0068] The storage capacitor CST may include a first electrode to which the high power voltage ELVDD is applied and a second electrode connected to the first node N1.

[0069] The organic light emitting diode OLED may include an anode and a cathode to which a low power voltage ELVSS is applied.

[0070] Reference Figure 3 , the pixel PX may be operated in the first period P1 to the fourth period P4. During the first period P1, the fourth switching element T4 may be turned on in response to the data initialization gate signal GI, so that the first node N1 and the storage capacitor CST may be initialized. During the second period P2, the second switching element T2 and the third switching element T3 may be turned on in response to the first data write gate signal GWP and the second data write gate signal GWN, respectively, so that the threshold voltage of the first switching element T1 may be compensated, and the data voltage Vd for which the threshold voltage is compensated may be written into the first node N1. During the third period P3, the seventh switching element T7 may be turned on in response to the organic light emitting diode initialization gate signal GB, so that the anode of the organic light emitting diode OLED may be initialized. During the fourth period P4, the fifth switching element T5 and the sixth switching element T6 may be turned on in response to the emission control signal EM, so that the organic light emitting diode OLED may emit light.

[0071] During the first period P1, the data initialization gate signal GI may have an activation level. For example, the activation level of the data initialization gate signal GI may be a high level. When the data initialization gate signal GI having an activation level is supplied, the fourth switching element T4 may be turned on so that the initialization voltage VI may be applied to the first node N1.

[0072] During the second period P2, each of the first data write gate signal GWP and the second data write gate signal GWN may have an activation level. For example, the activation level of the first data write gate signal GWP may be a low level, and the activation level of the second data write gate signal GWN may be a high level. When the first data write gate signal GWP and the second data write gate signal GWN having the activation level are supplied, the second switching element T2 and the third switching element T3 may be turned on. In addition, the first switching element T1 may be turned on by the initialization voltage VI. Along the path formed as the first switching element T1, the second switching element T2, and the third switching element T3 are turned on, the data voltage Vd supplied to the first electrode of the second switching element T2 may be set to the first node N1. In this case, since the third switching element T3 is turned on, the first switching element T1 is diode-connected, so that the data voltage Vd (i.e., the voltage obtained by subtracting the threshold voltage from the data voltage Vd) to which the threshold voltage of the first switching element T1 is compensated may be set to the first node N1.

[0073] During the third period P3, the organic light emitting diode initialization gate signal GB may have an activation level. For example, the activation level of the organic light emitting diode initialization gate signal GB may be a high level. When the organic light emitting diode initialization gate signal GB having the activation level is supplied, the seventh switching element T7 may be turned on so that the initialization voltage V1 may be applied to the anode of the organic light emitting diode OLED.

[0074] During the fourth period P4, the emission control signal EM may have an activation level. For example, the activation level of the emission control signal EM may be a low level. When the emission control signal EM having a low level is supplied, the fifth switching element T5 and the sixth switching element T6 may be turned on. In addition, the first switching element T1 may be turned on by the data voltage Vd. The first switching element T1 may generate a driving current based on the data voltage Vd. The driving current may be supplied to the anode of the organic light emitting diode OLED through the sixth switching element T6, so that the organic light emitting diode OLED may emit light.

[0075] Figure 4 is shown in low frequency drive mode applied to Figure 2 A timing diagram of an example of a pixel signal.

[0076] Reference Figures 1 to 4, the display device may be driven in a normal driving mode operating at a normal driving frequency, and may be driven in a low-frequency driving mode operating at a frequency lower than the normal driving frequency. For example, when the input image data is a moving image, the display panel may be operated in the normal driving mode. For example, when the input image data is a still image, the display panel may be operated in the low-frequency driving mode. For example, when the display device is driven in an always-on display (AOD) mode, the display panel may be operated in the low-frequency driving mode.

[0077] The display panel can be driven in frames and can be refreshed once per frame in a normal driving mode. Therefore, the normal driving mode may only include a writing frame WRITING FRAME for writing data to pixels. In a low-frequency driving mode, the display panel can be refreshed at the frequency of the low-frequency driving mode. Therefore, the low-frequency driving mode may include a writing frame WRITING FRAME for writing data to pixels and a holding frame HOLDING FRAME for holding the data written in the pixels. For example, when the frequency of the normal driving mode is 60Hz and the frequency of the low-frequency driving mode is 1Hz, the low-frequency driving mode may include one writing frame WRITING FRAME and 59 holding frames HOLDING FRAME during 1 second. When the frequency of the normal driving mode is 60Hz and the frequency of the low-frequency driving mode is 1Hz, 59 consecutive holding frames HOLDING FRAME may be arranged between two adjacent writing frames WRITING FRAME. In this case, in Figure 2 In the pixel, the second switching element T2, the fifth switching element T5 and the sixth switching element T6 can be operated at 60 Hz, and the third switching element T3 can be operated at 1 Hz. For example, when the frequency of the normal driving mode is 60 Hz and the frequency of the low-frequency driving mode is 10 Hz, the low-frequency driving mode may include 10 writing frames WRITING FRAME and 50 holding frames HOLDING FRAME during 1 second. When the frequency of the normal driving mode is 60 Hz and the frequency of the low-frequency driving mode is 10 Hz, five consecutive holding frames HOLDING FRAME may be arranged between two adjacent writing frames WRITING FRAME. In this case, in Figure 2 In the pixel of FIG. 5 , the second switching element T2 , the fifth switching element T5 , and the sixth switching element T6 may be operated at 60 Hz, and the third switching element T3 may be operated at 10 Hz.

[0078] Reference Figure 4, the gate clock signals CLK1 and CLK2 may include a first gate clock signal CLK1 and a second gate clock signal CLK2. For example, the second gate clock signal CLK2 may be a signal obtained by allowing the first gate clock signal CLK1 to be delayed. For example, the second gate clock signal CLK2 may be an inverted signal of the first gate clock signal CLK1. Although Figure 4 , the first gate clock signal CLK1 and the second gate clock signal CLK2 are shown, but the gate clock signal is not limited thereto. For example, the gate driver may also receive the gate clock signal according to the configuration of the stage generating the gate signal.

[0079] The driving controller of the display device according to the embodiment of the present invention may provide a gate clock signal having a DC voltage to a gate driver during the holding frame HOLDING FRAME. In one embodiment, in the low-frequency driving mode, the gate clock signals CLK1 and CLK2 may swing between a high level and a low level during the writing frame WRITING FRAME, and may be maintained at a low level during the holding frame HOLDING FRAME. In another embodiment, in the low-frequency driving mode, the gate clock signals CLK1 and CLK2 may swing between a high level and a low level during the writing frame WRITING FRAME, and may be maintained at a high level during the holding frame HOLDING FRAME. For example, the high level may have a gate-on voltage level, and the low level may have a gate-off voltage level.

[0080] Reference Figure 4 , the first gate clock signal CLK1 may swing between a high level and a low level during the writing frame WRITING FRAME, and may be maintained at a low level during the holding frame HOLDING FRAME. In addition, the second gate clock signal CLK2 may swing between a high level and a low level during the writing frame WRITING FRAME, and may be maintained at a high level during the holding frame HOLDING FRAME. In the display device according to an embodiment of the present invention, during the holding frame HOLDING FRAME in the low-frequency driving mode, the gate clock signals CLK1 and CLK2 may be maintained as a DC voltage having a high level or a low level without swinging, so that power consumption can be reduced.

[0081] Figure 5 is shown in low frequency drive mode applied to Figure 2 FIG. 1 is a timing diagram of another example of a signal of a pixel.

[0082] Reference Figure 1 , Figure 2 , Figure 3 and Figure 5, the display device can be driven in a normal driving mode operating at a normal driving frequency, and can be driven in a low-frequency driving mode operating at a frequency lower than the normal driving frequency. For example, when the input image data is a moving image, the display panel can be operated in the normal driving mode. For example, when the input image data is a still image, the display panel can be operated in the low-frequency driving mode. For example, when the display device is driven in the AOD mode, the display panel can be operated in the low-frequency driving mode.

[0083] The display panel may be driven in units of frames and may be refreshed once per frame in a normal driving mode. Therefore, the normal driving mode may include only a writing frame WRITING FRAME for writing data into a pixel. In a low-frequency driving mode, the display panel may be refreshed at the frequency of the low-frequency driving mode. Therefore, the low-frequency driving mode may include a writing frame WRITING FRAME for writing data into a pixel and a holding frame HOLDING FRAME for holding the data written into the pixel. During the holding frame HOLDING FRAME, the driving controller of the display device may not operate the data driver.

[0084] Reference Figure 5 In the low-frequency driving mode, the driving controller of the display device may provide an analog driving voltage AVDD having a first voltage level LV1 to the data driver during the writing frame WRITING FRAME, and provide an analog driving voltage AVDD having a second voltage level LV2 lower than the first voltage level LV1 to the data driver during the holding frame HOLDING FRAME. The second voltage level may have a voltage level (e.g., 0V) at which the data driver is not operated. The data driver may generate a gamma reference voltage based on the analog driving voltage AVDD having the first voltage level LV1 during the writing frame WRITING FRAME. The data driver may convert the data signal supplied from the driving controller into an analog data voltage Vd by using the gamma reference voltage, and output the data voltage Vd to the data line. During the holding frame HOLDING FRAME, the data driver may receive an analog driving voltage AVDD having a second voltage level LV2. Based on the analog driving voltage AVDD having the second voltage level LV2, the data driver may not operate during the holding frame HOLDING FRAME. Therefore, in the display device according to the embodiment of the present invention, the data driver may not operate during the holding frame HOLDING FRAME in the low frequency driving mode, so that power consumption can be reduced.

[0085] Figure 6 It is shown that the Figure 1 A circuit diagram of another example of a pixel in a display device, and Figure 7 is shown in low frequency drive mode applied to Figure 6 A timing diagram of an example of a pixel signal.

[0086] Reference Figure 6 According to an embodiment of the present invention, each of the pixels PX may include a first switching element T1, a second switching element T2, a third switching element T3, a fourth switching element T4, a fifth switching element T5, a sixth switching element T6, a seventh switching element T7, and an eighth switching element T8, a storage capacitor CST, and an organic light emitting diode OLED. Figure 6 In addition to the pixel PX including the eighth switching element T8, according to the embodiment of the present invention Figure 6 The pixel PX may have Figure 2 The pixels PX have substantially the same structure.

[0087] The eighth switching element T8 may include a gate electrode to which a hold voltage enable signal Vsus_en is applied, a first electrode to which a hold voltage Vsus is applied, and a second electrode connected to the first electrode of the second switching element T2. For example, the eighth switching element T8 may be a polysilicon transistor. The eighth switching element T8 may be a P-type thin film transistor. The first electrode of the eighth switching element T8 may be a source electrode, and the second electrode of the eighth switching element T8 may be a drain electrode.

[0088] Reference Figure 7 In the low-frequency driving mode, the driving controller of the display device may provide the analog driving voltage AVDD to the data driver during the writing frame WRITING FRAME, and provide the holding voltage Vsus to the pixel PX during the holding frame HOLDING FRAME. For example, the driving controller may include a voltage generator configured to generate the analog driving voltage AVDD and the holding voltage Vsus.

[0089] The driving controller may generate a voltage having a first voltage level during a writing frame WRITING FRAME and provide the generated voltage to the data driver as an analog driving voltage AVDD, and may generate a voltage having a voltage level equal to or different from the first voltage level during a holding frame HOLDING FRAME and provide the generated voltage to the pixel as a holding voltage Vsus. Since the voltage is not supplied to the data driver during the holding frame HOLDING FRAME, the data driver may not operate.

[0090] In addition, the driving controller may provide a sustain voltage enable signal Vsus_en to the pixel. Figure 6 and Figure 7, the holding voltage enable signal Vsus_en may be activated during the holding frame HOLDING FRAME and supplied to the gate electrode of the eighth switching element T8. During the holding frame HOLDING FRAME, the eighth switching element T8 may be turned on in response to the holding voltage enable signal Vsus_en. Therefore, during the holding frame HOLDING FRAME, the holding voltage Vsus may be supplied to the first electrode of the second switching element T2 through the eighth switching element T8.

[0091] exist Figure 6 In the pixel of the display device according to the embodiment of the present invention, during the holding frame HOLDING FRAME, a leakage current may be generated by the second switching element T2 connected to the first switching element T1. When the voltage of the first electrode of the first switching element T1 is changed by the leakage current generated by the second switching element T2, the driving current may be changed so that the brightness of the pixel PX may be changed. Since the pixel PX of the display device according to the embodiment of the present invention supplies the holding voltage Vsus to the first electrode of the second switching element T2 through the eighth switching element T8 during the holding frame HOLDING FRAME, the leakage current generated by the second switching element T2 can be prevented. Therefore, the pixel PX can emit light with constant brightness.

[0092] As described above, since the driving controller of the display device according to the embodiment of the present invention provides the analog driving voltage AVDD to the data driver during the writing frame WRITING FRAME, and does not provide the analog driving voltage AVDD to the data driver during the holding frame HOLDING FRAME, the data driver can be prevented from operating during the holding frame HOLDING FRAME. Therefore, the power consumption of the display device can be reduced during the holding frame HOLDING FRAME. In addition, since the driving controller of the display device according to the embodiment of the present invention provides the holding voltage Vsus to the pixel PX during the holding frame HOLDING FRAME, the driving current can be prevented from being changed due to the leakage current.

[0093] Figure 8 It is shown that Figure 1 A block diagram of an electronic device of a display device, and Fig. 9 It is shown Figure 8 The electronic device is implemented as an example of a smart phone.

[0094] Reference Figure 8 and Fig. 9 , the electronic device 200 may include a processor 210, a storage device 220, a storage device 230, an input / output (I / O) device 240, a power supply 250, and a display device 260. Here, the display device 260 may be Figure 1In addition, the electronic device 200 may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, etc. In an embodiment, as Fig. 9 As shown in FIG. 3 , the electronic device 200 may be implemented as a smart phone 300. However, the electronic device 200 is not limited thereto.

[0095] The processor 210 may perform various computing functions. The processor 210 may be a microprocessor, a central processing unit (CPU), etc. The processor 210 may be connected to other components via an address bus, a control bus, a data bus, etc. In addition, the processor 210 may be connected to an expansion bus such as a peripheral component interconnect (PCI) bus. The storage device 220 may store data for the operation of the electronic device 200. For example, the storage device 220 may include a non-volatile storage device and / or a volatile storage device, and the non-volatile storage device has an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistance random access memory (RRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc., and the volatile storage device has a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, etc. The storage device 230 may include a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc.

[0096] The I / O device 240 may include input devices such as a keyboard, a keypad, a mouse device, a touch pad, a touch screen, etc., and output devices such as a printer, a speaker, etc. In some embodiments, a display device 260 may be included in the I / O device 240. The power supply 250 may provide power for the operation of the electronic device 200. The display device 260 may be coupled to other components via a bus or other communication link.

[0097] As described above, the display device 260 may include a display panel, a gate driver, a data driver, an emission controller, and a drive controller. The display panel may include a plurality of pixels. The drive controller may generate a control signal for controlling the gate driver, the data driver, and the emission controller based on input image data and an input control signal. The gate driver may generate a gate signal based on a first control signal supplied from the drive controller, and output the gate signal to a gate line of the display panel. The data driver may generate a data signal based on a second control signal supplied from the drive controller, and output the data signal to a data line of the display panel. The emission controller may generate an emission control signal based on a third control signal supplied from the drive controller, and output the emission control signal to an emission control line of the display panel.

[0098] The drive controller may generate a first control signal for controlling the operation of the gate driver based on the input control signal. For example, the first control signal may include a vertical start signal and a gate clock signal. According to an embodiment of the present invention, in a low-frequency drive mode, the display panel may operate in a write frame for writing data into a pixel and a hold frame for maintaining the data written into the pixel. In one embodiment, the drive controller may provide a gate clock signal having a DC voltage to the gate driver during the hold frame, so that the power consumption of the display device 260 can be reduced.

[0099] The drive controller may generate a second control signal for controlling the operation of the data driver based on the input control signal. The drive controller may generate an analog drive voltage for operating the data driver. In one embodiment, the drive controller of the display device 260 according to the embodiment of the present invention may not operate the data driver during the holding frame. For example, the drive controller may provide an analog drive voltage having a first voltage level to the data driver during the write frame, and provide an analog drive voltage having a second voltage level (e.g., 0V) to the data driver during the holding frame. Since the data driver does not operate during the holding frame, the power consumption of the display device 260 can be reduced. In another embodiment, the drive controller of the display device 260 according to the embodiment of the present invention may provide an analog drive voltage having a first voltage level to the data driver during the write frame, and provide a holding voltage having a third voltage level to the pixel during the holding frame. Since the data driver does not receive the analog drive voltage during the holding frame, the data driver may not operate. In addition, since the pixel receives the holding voltage during the holding frame, the leakage current of the driving transistor (first switching element) can be prevented from being generated. Therefore, the power consumption of the display device 260 can be reduced, and the display quality can be improved.

[0100] Industrial Availability

[0101] The present invention can be applied to electronic devices including display devices. For example, the present invention can be applied to televisions, computer monitors, laptop computers, digital cameras, smart phones, cellular phones, smart boards, tablet PCs, personal digital assistants (PDAs), portable multimedia players (PMPs), MP3 players, car navigation systems, video phones, head mounted display (HMD) devices, etc.

[0102] The foregoing is illustrative of embodiments and should not be construed as limiting thereof. Although a few embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without materially departing from the novel teachings and advantages of this invention.

[0103] Description of Reference Numerals

[0104] 100: Display device 110: Display panel

[0105] 120: Gate driver 130: Data driver

[0106] 140: Transmitting controller 150: Driving controller

[0107] 200: electronic device 300: smart phone

Claims

1. A display device, comprising: a display panel comprising pixels, the pixels comprising switching elements of a first type and switching elements of a second type different from the first type; a gate driver configured to generate a gate signal based on a gate clock signal and provide the gate signal to the display panel; a data driver configured to provide a data voltage to the display panel; an emission controller configured to provide an emission control signal to the display panel; as well as a driving controller configured to generate control signals for controlling the gate driver, the data driver, and the emission controller, Wherein, in the low-frequency driving mode, the driving controller is configured to provide the gate clock signal swinging between a high level and a low level to the gate driver during a writing frame for writing data into the pixel, and to provide the gate clock signal having a DC voltage to the gate driver during a holding frame for holding the data written into the pixel, wherein the driving controller comprises a voltage generator configured to generate an analog voltage for operating the data driver and a holding voltage for constantly holding a driving current of the pixel, and Wherein, in the low-frequency driving mode, the driving controller provides the analog voltage to the data driver during the writing frame and provides the holding voltage to the pixel during the holding frame.

2. The display device according to claim 1, wherein: In the low-frequency driving mode, the gate clock signal swings between the high level and the low level during the write frame, and remains at the low level during the hold frame.

3. The display device according to claim 1, wherein: In the low-frequency driving mode, the gate clock signal swings between the high level and the low level during the write frame, and remains at the high level during the hold frame.

4. The display device according to claim 1, wherein: The switching element of the first type is a polysilicon thin film transistor, and Wherein, the second type of switching element is an oxide thin film transistor.

5. The display device according to claim 4, wherein: The switching element of the first type is a P-type transistor, and Wherein, the second type of switch element is an N-type transistor.

6. The display device according to claim 4, wherein: The pixels include: a first switching element including a gate electrode connected to the first node, a first electrode connected to the second node, and a second electrode connected to the third node; a second switching element, the second switching element including a gate electrode to which a first data write gate signal is applied, a first electrode to which the data voltage is applied, and a second electrode connected to the second node; a third switching element, the third switching element comprising a gate electrode to which a second data write gate signal is applied, a first electrode connected to the first node, and a second electrode connected to the third node; a fourth switching element, the fourth switching element comprising a gate electrode to which a data initialization gate signal is applied, a first electrode to which an initialization voltage is applied, and a second electrode connected to the first node; a fifth switching element including a gate electrode to which the emission control signal is applied, a first electrode to which a high power supply voltage is applied, and a second electrode connected to the second node; a sixth switching element, the sixth switching element comprising a gate electrode to which the emission control signal is applied, a first electrode connected to the third node, and a second electrode connected to an anode of an organic light emitting diode; a seventh switching element, the seventh switching element comprising a gate electrode to which an organic light emitting diode initialization gate signal is applied, a first electrode to which the initialization voltage is applied, and a second electrode connected to the anode of the organic light emitting diode; a storage capacitor including a first electrode to which the high power supply voltage is applied and a second electrode connected to the first node; and IPC2102KR0313.OA2 The organic light emitting diode includes the anode and a cathode to which a low power supply voltage is applied.

7. The display device according to claim 6, wherein: The first switch element, the second switch element, the fifth switch element and the sixth switch element are polysilicon thin film transistors, and Wherein, the third switch element, the fourth switch element and the seventh switch element are oxide thin film transistors.

8. The display device according to claim 6, wherein: In the low-frequency driving mode, the second switching element, the fifth switching element, and the sixth switching element are driven at a first driving frequency, and the third switching element is driven at a second driving frequency lower than the first driving frequency.

9. The display device according to claim 1, wherein: The driving controller includes a gate controller configured to generate the gate clock signal.

10. A display device, comprising: a display panel comprising pixels, the pixels comprising switching elements of a first type and switching elements of a second type different from the first type; a gate driver configured to provide a gate signal to the display panel; a data driver configured to provide a data voltage to the display panel; an emission controller configured to provide an emission control signal to the display panel; as well as a driving controller configured to generate control signals for controlling the gate driver, the data driver, and the emission controller, wherein the driving controller comprises a voltage generator configured to generate an analog driving voltage provided to the data driver and a holding voltage for constantly holding a driving current of the pixel, and Wherein, in the low frequency driving mode, the driving controller is configured to provide the analog driving voltage for operating the data driver to IPC2102KR0313.OA2 during a writing frame for writing data to the pixel The data driver and supplies the analog driving voltage which does not operate the data driver to the data driver during a holding frame for holding the data written in the pixel.

11. The display device according to claim 10, wherein: In the low-frequency driving mode, the driving controller is configured to provide the analog driving voltage having a first voltage level to the data driver during the write frame, and to provide the analog driving voltage having a second voltage level lower than the first voltage level to the data driver during the hold frame.

12. The display device according to claim 10, wherein: The switching element of the first type is a polysilicon thin film transistor, and Wherein, the second type of switching element is an oxide thin film transistor.

13. The display device according to claim 12, wherein: The switching element of the first type is a P-type transistor, and Wherein, the second type of switch element is an N-type transistor.

14. The display device according to claim 12, wherein: The pixels include: a first switching element including a gate electrode connected to the first node, a first electrode connected to the second node, and a second electrode connected to the third node; a second switching element, the second switching element including a gate electrode to which a first data write gate signal is applied, a first electrode to which the data voltage is applied, and a second electrode connected to the second node; a third switching element, the third switching element comprising a gate electrode to which a second data write gate signal is applied, a first electrode connected to the first node, and a second electrode connected to the third node; a fourth switching element, the fourth switching element comprising a gate electrode to which a data initialization gate signal is applied, a first electrode to which an initialization voltage is applied, and a second electrode connected to the first node; a fifth switching element including a gate electrode to which the emission control signal is applied, a first electrode to which a high power supply voltage is applied, and a second electrode connected to the second node; A sixth switching element, the sixth switching element comprising a gate electrode IPC2102KR0313.OA2 to which the emission control signal is applied an anode of the organic light emitting diode, a first electrode connected to the third node, and a second electrode connected to the anode of the organic light emitting diode; a seventh switching element, the seventh switching element comprising a gate electrode to which an organic light emitting diode initialization gate signal is applied, a first electrode to which the initialization voltage is applied, and a second electrode connected to the anode of the organic light emitting diode; a storage capacitor including a first electrode to which the high power supply voltage is applied and a second electrode connected to the first node; and The organic light emitting diode includes the anode and a cathode to which a low power supply voltage is applied.

15. The display device according to claim 14, wherein: The first switch element, the second switch element, the fifth switch element and the sixth switch element are polysilicon thin film transistors, and Wherein, the third switch element, the fourth switch element and the seventh switch element are oxide thin film transistors.

16. The display device according to claim 14, wherein: In the low-frequency driving mode, the second switching element, the fifth switching element, and the sixth switching element are driven at a first driving frequency, and the third switching element is driven at a second driving frequency lower than the first driving frequency.

17. The display device according to claim 14, wherein: The pixel also includes: An eighth switching element includes a gate electrode to which a hold voltage enable signal is applied, a first electrode to which a hold voltage is applied, and a second electrode connected to the first electrode of the second switching element.

18. The display device according to claim 17, wherein: In the low frequency driving mode, the driving controller is configured to provide the analog driving voltage to the data driver during the writing frame, and to provide the holding voltage to the pixel during the holding frame.

19. The display device according to claim 18, wherein: The eighth switching element is the polysilicon thin film transistor.

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