Integrated circuit device

Abstract

An integrated circuit (IC) device includes a first fin-type active region and a second fin-type active region on a substrate. A plurality of first semiconductor patterns is disposed stacked on the first fin-type active region as a plurality of spaced-apart first channel regions of a first FINFET. A plurality of second semiconductor patterns is disposed stacked on the second fin-type active region as a plurality of spaced-apart second channel regions of a second FINFET. A first gate structure is disposed on the plurality of first semiconductor patterns. The first gate structure includes a first material region at least partially filling spaces between the plurality of spaced-apart first channel regions. Further, a second gate structure is disposed on the plurality of second semiconductor patterns. The second gate structure includes a second material region and a third material region at least partially filling spaces between the plurality of spaced-apart second channel regions.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0146961, filed on November 15, 2019, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to integrated circuit (IC) devices and methods of manufacturing the same, and more particularly, to IC devices including transistors having a multi-gate structure and methods of manufacturing the same. Background Technology

[0004] Due to advancements in electronic technology, the demand for increased integration density in IC devices has grown, and miniaturization of IC devices has been underway. With the miniaturization of IC devices, undesirable short-channel effects (SCEs) may occur in transistors, thereby reducing the reliability of the IC devices. To reduce the occurrence of SCEs, IC devices with multi-gate structures, such as nanosheet transistors, have been proposed. Summary of the Invention

[0005] The present invention provides an integrated circuit (IC) device with a precisely adjustable threshold voltage and improved performance.

[0006] The present invention also provides a method for manufacturing an IC device that can provide a precisely regulated threshold voltage and improved performance.

[0007] According to an embodiment of the present invention, an integrated circuit device is provided, comprising a first fin active region and a second fin active region located on a substrate. A plurality of first semiconductor patterns are disposed, stacked on the first fin active regions as a plurality of spaced-apart first channel regions of a first FINFET. A plurality of second semiconductor patterns are disposed, stacked on the second fin active regions as a plurality of spaced-apart second channel regions of a second FINFET. Furthermore, a first gate structure is disposed on the plurality of first semiconductor patterns. The first gate structure includes a first material region that at least partially fills the space between the plurality of spaced-apart first channel regions. Furthermore, a second gate structure is disposed on the plurality of second semiconductor patterns. The second gate structure includes a second material region and a third material region that at least partially fill the space between the plurality of spaced-apart second channel regions.

[0008] In some embodiments of these embodiments conceived according to the present invention, the oxygen content percentage in the second material region exceeds the oxygen content percentage in the first material region. According to other embodiments of the present invention, the first material region extends on the sidewalls of the plurality of first semiconductor patterns and on the top surface of the uppermost of the plurality of first semiconductor patterns. The first gate structure may further include a fourth material region and a fifth material region extending on the sidewalls and top surface of the first material region. Furthermore, the oxygen content percentage in the fourth material region may exceed the oxygen content percentage in the first material region.

[0009] In other embodiments of the present invention, the first material region includes at least one selected from a metal nitride containing a first metal, a metal carbide containing the first metal, and a metal carbonitride containing the first metal. Furthermore, the second material region includes at least one selected from a metal oxide containing a second metal, a metal nitride containing the second metal, a metal carbon oxide containing the second metal, and a metal carbonitride containing the second metal. The first metal may be selected from the group consisting of titanium, niobium, tantalum, molybdenum, and tungsten, and the second metal may be selected from the group consisting of titanium, niobium, tantalum, molybdenum, and tungsten. According to a preferred aspect of these embodiments, the second material region includes M... x O y N z Where M is a metal, O is oxygen, N is nitrogen, x>0.0, z>0.0, 0.2≤y≤0.7, 0.3≤x+z≤0.8. The first material region can be electrically insulated from the plurality of first semiconductor patterns, and the second material region can be electrically insulated from the plurality of second semiconductor patterns.

[0010] An integrated circuit device according to another embodiment of the present invention includes: a first fin active region and a second fin active region located on a substrate; a plurality of first semiconductor patterns stacked on the first fin active regions as a plurality of spaced-apart first channel regions of a first FINFET; and a plurality of second semiconductor patterns stacked on the second fin active regions as a plurality of spaced-apart second channel regions of a second FINFET. A first gate structure is disposed on the plurality of first semiconductor patterns. The first gate structure includes a first material region surrounding and at least partially filling the space between the plurality of spaced-apart first channel regions. A second gate structure is disposed on the plurality of second semiconductor patterns. The second gate structure includes a second material region surrounding and at least partially filling the space between the plurality of spaced-apart second channel regions. The oxygen content percentage in the second material region may exceed the oxygen content percentage in the first material region, and the second material region may be M x O y N z Where M is a metal, O is oxygen, N is nitrogen, x>0.0, z>0.0, 0.2≤y≤0.7, 0.3≤x+z≤0.8.

[0011] According to another aspect of the present invention, an IC device is provided, comprising a first finned active region and a second finned active region protruding from a substrate and extending along a first direction. A plurality of first semiconductor patterns are spaced apart from the top surface of the first finned active regions. Each first semiconductor pattern has a channel region. A plurality of second semiconductor patterns are spaced apart from the top surface of the second finned active regions. Each second semiconductor pattern has a channel region. A first gate structure extends over the first finned active regions along a second direction and includes a first material layer filling a first sub-gate space between the respective first semiconductor patterns. Here, the second direction is perpendicular to the first direction. A second gate structure extends over the second finned active regions along the second direction and includes a second material layer and a third material layer, the second material layer and the third material layer being sequentially located in a second sub-gate space between the respective second semiconductor patterns.

[0012] According to another aspect of the present invention, an IC device is provided, comprising a first finned active region protruding from a substrate and extending along a first direction. A second finned active region protruding from the substrate and spaced apart from the first finned active region. The second finned active region extends along the first direction. A plurality of first semiconductor patterns are spaced apart from the top surface of the first finned active region. Each first semiconductor pattern has a channel region. A plurality of second semiconductor patterns are spaced apart from the top surface of the second finned active region. Each second semiconductor pattern has a channel region. A first gate structure extends over the first finned active region along a second direction and includes a first material layer surrounding the top and bottom surfaces of each of the plurality of first semiconductor patterns. Here, the second direction is perpendicular to the first direction. A second gate structure extends over the second finned active region along the second direction and includes a second material layer surrounding the top and bottom surfaces of each of the plurality of second semiconductor patterns. The second material layer contains a higher oxygen content than the first material layer.

[0013] According to another aspect of the present invention, an IC device is provided, comprising a first finned active region protruding from a substrate and extending along a first direction. A second finned active region protruding from the substrate and spaced apart from the first finned active region. The second finned active region extends along the first direction. A plurality of first semiconductor patterns are spaced apart from the top surface of the first finned active region. Each first semiconductor pattern has a channel region. A plurality of second semiconductor patterns are spaced apart from the top surface of the second finned active region. Each second semiconductor pattern has a channel region. A first gate structure extends over the first finned active region along a second direction and includes a first material layer surrounding the top and bottom surfaces of the plurality of first semiconductor patterns. Here, the second direction is perpendicular to the first direction. A second gate structure extends over the second finned active region along the second direction and includes a second material layer surrounding the top and bottom surfaces of each of the plurality of second semiconductor patterns. The second material layer contains a higher oxygen content than the first material layer. The first material layer has a first thickness, and the second material layer has a second thickness less than the first thickness. Attached Figure Description

[0014] Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0015] Figure 1 The layout of an integrated circuit (IC) device according to an example embodiment is shown;

[0016] Figure 2A Show along Figure 1 The cross-sectional views taken by lines A1-A1' and A2-A2';

[0017] Figure 2B Show along Figure 1 The cross-sectional views taken by lines B1-B1' and B2-B2';

[0018] Figure 3A and Figure 3B This is a cross-sectional view of an IC device according to an example embodiment;

[0019] Figure 4A and Figure 4B This is a cross-sectional view of an IC device according to an example embodiment;

[0020] Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7 , Figure 8 , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A and Figure 17B This is a cross-sectional view illustrating a method of manufacturing an IC device according to an example embodiment;

[0021] Figure 18 This is a graph showing the equivalent oxide thickness and leakage current of an IC device according to an example embodiment. Detailed Implementation

[0022] In the following description, exemplary embodiments will be described in detail with reference to the accompanying drawings.

[0023] Figure 1 The layout of an integrated circuit (IC) device 100 according to an example embodiment is shown. Figure 2A Show along Figure 1 A cross-sectional view of IC device 100 taken by lines A1-A1' and A2-A2'; Figure 2B Show along Figure 1 The cross-sectional view of IC device 100 taken by lines B1-B1' and B2-B2'.

[0024] Reference Figures 1 to 2B The substrate 110 may include a first fin-type active region FA1 and a second fin-type active region FA2. The first fin-type active region FA1 and the second fin-type active region FA2 may respectively constitute a first transistor TR1 and a second transistor TR2 with different threshold voltages. In an example embodiment, the first transistor TR1 may include a PMOS transistor, and the second transistor TR2 may include an NMOS transistor. In other embodiments, the first transistor TR1 may include an NMOS transistor having a first threshold voltage, and the second transistor TR2 may include an NMOS transistor having a second threshold voltage different from the first threshold voltage. In other embodiments, the first transistor TR1 may include a PMOS transistor having a first threshold voltage, and the second transistor TR2 may include a PMOS transistor having a second threshold voltage different from the first threshold voltage.

[0025] Substrate 110 may comprise a semiconductor material such as silicon (Si) or germanium (Ge), or a compound semiconductor such as silicon-germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). In some embodiments, substrate 110 may comprise at least one of group III-V materials and group IV materials. Group III-V materials may be binary, ternary, or quaternary compounds comprising at least one group III element and at least one group V element. Group III-V materials may be compounds comprising at least one group III element and at least one group V element. At least one group III element may be at least one element selected from indium (In), gallium (Ga), and aluminum (Al), and at least one group V element may be at least one element selected from arsenic (As), phosphorus (P), and antimony (Sb). For example, group III-V materials may be selected from InP, In... z Ga 1-z As (0≤z≤1) and Al z Ga 1-z As (0≤z≤1). Binary compounds can be, for example, any one of indium phosphide (InP), gallium arsenide (GaAs), indium arsenide (InAs), indium antimonide (InSb), and gallium antimonide (GaSb). Ternary compounds can be any one of indium gallium phosphide (InGaP), indium gallium arsenide (InGaAs), aluminum indium arsenide (AlInAs), indium gallium antimonide (InGaSb), gallium antimonide arsenide (GaAsSb), and gallium phosphide arsenide (GaAsP). Group IV materials can be silicon or germanium. However, the Group III-V and Group IV materials that can be used in the IC device according to the embodiments are not limited to the examples described herein.

[0026] Group III-V and Group IV materials (e.g., germanium) can be used as materials for forming channels in low-power, high-speed transistors. Highly efficient complementary CMOS devices can be formed by using semiconductor substrates comprising Group III-V materials (e.g., GaAs) having higher electron mobility than silicon substrates and semiconductor substrates comprising semiconductor materials (e.g., Ge) having higher hole mobility than silicon substrates. In some embodiments, when an NMOS transistor is formed on substrate 110, substrate 110 may comprise any of the aforementioned Group III-V materials. In some other embodiments, when a PMOS transistor is formed on substrate 110, at least a portion of substrate 110 may comprise Ge.

[0027] In an example embodiment, substrate 110 may have a semiconductor-on-insulator (SOI) structure, such as a silicon-on-insulator structure. Substrate 110 may include conductive regions, such as doped wells or doped structures.

[0028] Both the first fin-shaped active region FA1 and the second fin-shaped active region FA2 can extend on the substrate 110 along a first direction (X direction) and protrude from the top surface of the substrate 110 along a vertical direction (Z direction). The second fin-shaped active region FA2 can be spaced apart from the first fin-shaped active region FA1 in a second direction (Y direction) perpendicular to the first direction (X direction).

[0029] Device isolation trench 112T can be formed in substrate 110 to define a first fin active region FA1 and a second fin active region FA2, and deep trench 114T can be formed in substrate 110 to define device region DR. Device isolation film 112 can be located inside device isolation trench 112T, and deep trench insulating film 114 can be located inside deep trench 114T.

[0030] For example, the device isolation film 112 may be located on the two sidewalls of the first fin-type active region FA1 and the two sidewalls of the second fin-type active region FA2. In addition, the device isolation liner 112L may be conformally formed and extended between the device isolation film 112 and the inner wall of the device isolation trench 112T. Figure 2B An example is shown where the top surface of the device isolation film 112 is at the same horizontal height as the top surfaces of the first fin active region FA1 and the second fin active region FA2. However, in another embodiment, the top surface of the device isolation film 112 may be at a lower horizontal height than the top surfaces of the first fin active region FA1 and the second fin active region FA2. Therefore, only the lower portions of the sidewalls of the first fin active region FA1 and the second fin active region FA2 may be surrounded by the device isolation film 112. The deep trench insulating film 114 may comprise silicon oxide, silicon nitride, or a combination thereof.

[0031] Multiple first semiconductor patterns NS1 may be spaced apart from the top surface of the first fin active region FA1 along a vertical direction (Z direction). In some embodiments, the multiple first semiconductor patterns NS1 may comprise the same material as the substrate 110. For example, the multiple first semiconductor patterns NS1 may comprise semiconductors such as silicon or germanium, or compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. Each of the multiple first semiconductor patterns NS1 may comprise a channel region.

[0032] Each of the multiple first semiconductor patterns NS1 can have a relatively large width in the second direction (Y direction) and a relatively small thickness in the vertical direction (Z direction) (see reference). Figure 5B (t22 in the example). For example, multiple first semiconductor patterns NS1 may each have a nanosheet shape. In an example embodiment, multiple first semiconductor patterns NS1 may each have a width of about 5 nm to about 100 nm in the second direction (Y direction) and a thickness t22 of about 1 nm to about 10 nm in the vertical direction (Z direction), but are not limited thereto.

[0033] like Figure 2B As shown, multiple first semiconductor patterns NS1 can be spaced equally between each other. For example, the first distance d21 between the bottommost first semiconductor pattern NS1 and the top surface of the first fin active region FA1 can be substantially equal to the second distance d22 between the bottommost first semiconductor pattern NS1 and its adjacent first semiconductor pattern NS1. However, the inventive concept is not limited thereto, and the distance between the individual first semiconductor patterns NS1 can be modified to suit other embodiments. Furthermore, the number of first semiconductor patterns NS1 is not limited to [specific number]. Figure 2A and Figure 2B The quantity shown.

[0034] Multiple second semiconductor patterns NS2 may be spaced apart from the top surface of the second fin active region FA2 along a vertical direction (Z direction). The multiple second semiconductor patterns NS2 may include the same material as the substrate 110, and each of the multiple second semiconductor patterns NS2 may include a channel region.

[0035] Each of the plurality of second semiconductor patterns NS2 may have a relatively large width in the second direction (Y direction) and a relatively small thickness in the vertical direction (Z direction). For example, each of the plurality of second semiconductor patterns NS2 may have a nanosheet shape. In an example embodiment, the width of each of the plurality of second semiconductor patterns NS2 may be equal to or different from the width of each of the plurality of first semiconductor patterns NS1. Furthermore, the thickness of each of the plurality of second semiconductor patterns NS2 may be equal to the thickness t22 of each of the plurality of first semiconductor patterns NS1, but the inventive concept is not limited thereto.

[0036] The first gate structure 120G1 may surround a plurality of first semiconductor patterns NS1 located on the first finned active region FA1 and extend along a second direction (Y direction). The first gate structure 120G1 may include a first main gate portion 120M1 and a plurality of first sub-gate portions 120S1. The first main gate portion 120M1 covers the top surface of the uppermost first semiconductor pattern NS1, and the plurality of first sub-gate portions 120S1 are formed in the space between the first finned active region FA1 and the lowermost first semiconductor pattern NS1, as well as in the space between adjacent first semiconductor patterns NS1. The first gate structure 120G1 may include a first material layer 122G1, a fourth material layer 124G1, a fifth material layer 126G1, and a first buried conductive layer 128G1.

[0037] The second gate structure 120G2 may surround a plurality of second semiconductor patterns NS2 located on the second fin active region FA2 and extend along the second direction (Y direction). Figure 1 An example is shown where the second gate structure 120G2 is positioned collinearly with the first gate structure 120G1, and the end of the second gate structure 120G2 is connected to the end of the first gate structure 120G1. However, with Figure 1 In different embodiments, the second gate structure 120G2 may be spaced apart from the end of the first gate structure 120G1.

[0038] The second gate structure 120G2 may include a second main gate portion 120M2 and a plurality of second sub-gate portions 120S2. The second main gate portion 120M2 covers the top surface of the uppermost second semiconductor pattern NS2. The plurality of second sub-gate portions 120S2 are formed in the space between the second fin active region FA2 and the lowermost second semiconductor pattern NS2, and in the space between adjacent second semiconductor patterns NS2. The second gate structure 120G2 may include a second material layer 124G2, a third material layer 126G2, and a second buried conductive layer 128G2.

[0039] A first gate insulating layer GI1 may be located on the top surface of the first fin-type active region FA1 and extend over the device isolation film 112 and the deep trench insulating film 114. Furthermore, the first gate insulating layer GI1 may surround a first semiconductor pattern NS1 within a plurality of first sub-gate portions 120S1. A second gate insulating layer GI2 may be located on the top surface of the second fin-type active region FA2 and extend over the device isolation film 112 and the deep trench insulating film 114. Furthermore, the second gate insulating layer GI2 may surround a second semiconductor pattern NS2 within a plurality of second sub-gate portions 120S2.

[0040] In the first gate structure 120G1, a first material layer 122G1 may surround a plurality of first semiconductor patterns NS1 and extend on the device isolation film 112 and the deep trench insulating film 114. The first material layer 122G1 may fill the internal space of a plurality of first sub-gate portions 120S1 on the first gate insulating layer GI1. The first material layer 122G1 may surround first sidewalls NSS1 of the plurality of first semiconductor patterns NS1 that are spaced apart from each other in a second direction (Y direction), and may be located on the top surface of the uppermost first semiconductor pattern NS1.

[0041] In the second gate structure 120G2, a second material layer 124G2 and a third material layer 126G2 may surround a plurality of second semiconductor patterns NS2 and extend on the device isolation film 112 and the deep trench insulating film 114. The second material layer 124G2 and the third material layer 126G2 may fill the internal space of a plurality of second sub-gate portions 120S2 on the second gate insulating layer GI2. The second material layer 124G2 and the third material layer 126G2 may surround second sidewalls NSS2 of the plurality of second semiconductor patterns NS2 that are spaced apart from each other in the second direction (Y direction) and are located on the upper surface of the uppermost second semiconductor pattern NS2.

[0042] In an example embodiment, the first material layer 122G1 may include at least one of a metal nitride containing a first metal, a metal carbide containing a first metal, and a metal carbonitride containing a first metal, wherein the first metal may include at least one of titanium, tantalum, niobium, molybdenum, and tungsten. In some examples, the first material layer 122G1 may include titanium nitride. The first material layer 122G1 may be used as a work function adjustment layer for adjusting the threshold voltage of the first transistor TR1.

[0043] In an example embodiment, the second material layer 124G2 may include at least one of a metal oxide containing a second metal, a metal nitride containing a second metal, a metal carbon oxide containing a second metal, and a metal carbonitride containing a second metal, and the second metal may include at least one of titanium, tantalum, niobium, molybdenum, and tungsten. In some examples, the second material layer 124G2 may be of formula M x O y N z It is represented as follows, where M is the second metal, O is oxygen, and N is nitrogen, and where: 0.2≤y≤0.7, 0.3≤x+z≤0.8, and 0≤z≤0.5.

[0044] The oxygen content percentage of the material included in the second material layer 124G2 can be higher than the oxygen content percentage of the material included in the first material layer 122G1. Here, the oxygen content percentage of the material included in the first material layer 122G1 can be approximately zero. Alternatively, the oxygen content percentage of the material included in the first material layer 122G1 can be greater than zero, but lower than the oxygen content percentage of the material included in the second material layer 124G2. For example, the first material layer 122G1 may include titanium nitride, and the second material layer 124G2 may include titanium oxide. Alternatively, the first material layer 122G1 may include titanium nitride, and the second material layer 124G2 may include titanium oxynitride.

[0045] The third material layer 126G2 may include, but is not limited to, aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), titanium nitride (TiN), tungsten nitride (WN), titanium aluminide (TiAl), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), or combinations thereof. In some examples, the third material layer 126G2 may include a material having a smaller work function than the first material layer 122G1 and the second material layer 124G2. In some examples, the third material layer 126G2 may include a material having a higher aluminum (Al) content than the first material layer 122G1 and the second material layer 124G2.

[0046] The second material layer 124G2 and the third material layer 126G2 can be used as work function adjustment layers for regulating the threshold voltage of the second transistor TR2. Furthermore, the second material layer 124G2 can serve as a barrier layer configured to prevent oxygen consumption or deficiency in the high-k dielectric layer 130H of the second gate insulating layer GI2 during the formation of the third material layer 126G2. Because the second material layer 124G2 regulates the threshold voltage of the second transistor TR2 and simultaneously prevents oxygen consumption or deficiency in the high-k dielectric layer 130H, the second transistor TR2 can have reduced leakage current.

[0047] In the first gate structure 120G1, the fourth material layer 124G1 and the fifth material layer 126G1 may be located on the first material layer 122G1. The fourth material layer 124G1 and the fifth material layer 126G1 may be located in the first main gate portion 120M1, and may also be located on the uppermost first semiconductor pattern NS1 and the first sidewalls NSS1 of the plurality of first semiconductor patterns NS1. The fourth material layer 124G1 and the fifth material layer 126G1 may not be located in the sub-gate portion 120S1 between the plurality of first semiconductor patterns NS1. In some embodiments, the fourth material layer 124G1 may include at least one of a metal oxide containing a second metal, a metal nitride containing a second metal, a metal carbon oxide containing a second metal, and a metal carbonitride containing a second metal, and the second metal may include at least one of titanium, tantalum, niobium, molybdenum, and tungsten.

[0048] In some other embodiments, the fourth material layer 124G1 may be composed of chemical formula M x O y N z The formula is defined as follows: M is the second metal, O is oxygen, N is nitrogen, 0.2 ≤ y ≤ 0.7, 0.3 ≤ x + z ≤ 0.8, and 0 ≤ z ≤ 0.5. The fourth material layer 124G1 can be formed simultaneously with the second material layer 124G2, or it can be formed using a process performed under the same formation conditions as the process for forming the second material layer 124G2. Therefore, the oxygen content in the fourth material layer 124G1 can be higher than the oxygen content in the first material layer 122G1.

[0049] The fifth material layer 126G1 may comprise aluminum, copper, titanium, tantalum, tungsten, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, titanium nitride, tungsten nitride, titanium aluminide, titanium aluminum carbide, titanium aluminum nitride, tantalum carbonitride, tantalum carbide, tantalum silicon nitride, or combinations thereof, but is not limited thereto. The fifth material layer 126G1 may be formed simultaneously with the third material layer 126G2, or may be formed using a process performed under the same formation conditions as the process for forming the third material layer 126G2.

[0050] The first buried conductive layer 128G1 and the second buried conductive layer 128G2 may include, but are not limited to, aluminum, copper, titanium, tantalum, tungsten, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, titanium nitride, tungsten nitride, titanium aluminide, titanium aluminum carbide, titanium aluminum nitride, tantalum carbonitride, tantalum carbide, silicon tantalum nitride, or combinations thereof. The first buried conductive layer 128G1 may surround the fifth material layer 126G1 and fill the first main gate portion 120M1 extending along the second direction (Y direction). The second buried conductive layer 128G2 may surround the third material layer 126G2 and fill the second main gate portion 120M2 extending along the second direction (Y direction).

[0051] like Figure 2B As shown, the first material layer 122G1 may have a first thickness t11 on the top surface of the uppermost first semiconductor pattern NS1 or on the device isolation film 112. The first thickness t11 may be in the range of approximately 1 nm to approximately 10 nm, but is not limited thereto. The first thickness t11 may be greater than half (1 / 2) of the thickness of each of the plurality of first sub-gate portions 120S1. Here, the thickness of each of the plurality of first sub-gate portions 120S1 may correspond to the distance between the surface of the first gate insulating layer GI1 on one first semiconductor pattern NS1 and the surface of the first gate insulating layer GI1 on another adjacent first semiconductor pattern NS1. Therefore, the first material layer 122G1 may fill each of the plurality of first sub-gate portions 120S1.

[0052] The second material layer 124G2 may have a second thickness t12 on the top surface of the uppermost second semiconductor pattern NS2 or on the device isolation film 112. The second thickness t12 may be less than the first thickness t11. The second thickness t12 may be less than half the thickness of each of the plurality of second sub-gate portions 120S2. Here, the thickness of each of the plurality of second sub-gate portions 120S2 may correspond to the distance between the surface of the second gate insulating layer GI2 on one second semiconductor pattern NS2 and the surface of the second gate insulating layer GI2 on another adjacent second semiconductor pattern NS2. Therefore, the second material layer 124G2 may not completely fill each of the plurality of second sub-gate portions 120S2. In some examples, the second thickness t12 may be about 2 nm or less, but is not limited thereto.

[0053] The fourth material layer 124G1 may have a third thickness t13 on the top surface of the uppermost first semiconductor pattern NS1 or on the device isolation film 112. The third thickness t13 may be less than the first thickness t11 of the first material layer 122G1. The fourth material layer 124G1 may be formed simultaneously with the second material layer 124G2, or alternatively, it may be formed using a process performed under similar formation conditions to that used to form the second material layer 124G2.

[0054] In an exemplary manufacturing process, a mask layer (refer to...) Figure 14B 240 in the first fin active region FA1 can be formed on the first fin active region FA1 to cover the first material layer 122G1. The formation of the first material layer 122G1 in the second sub-gate space (see reference) can be removed. Figure 14B The portion of GSS2 in the first material layer 120S1 is then filled with the first material layer 122G1, and then the second material layer 124G2 can be formed. In this case, since the first material layer 122G1 is filled with the plurality of first sub-gate portions 120S1, the first material layer 122G1 located in the plurality of first sub-gate portions 120S1 can be prevented from being undesirably oxidized and having a relatively high oxygen content during the formation of the second material layer 124G2. Therefore, the threshold voltage of each of the first transistor TR1 and the second transistor TR2 can be precisely controlled.

[0055] like Figure 2B As shown, both the first gate insulating layer GI1 and the second gate insulating layer GI2 can have a stacked structure of an interface layer 130I and a high-k dielectric layer 130H. The interface layer 130I can mitigate interface defects between the top surface of the first fin active region FA1 and the top surface of the second fin active region FA2 and the high-k dielectric layer 130H, as well as interface defects between the surfaces of the plurality of first semiconductor patterns NS1 and the surfaces of the plurality of second semiconductor patterns NS2 and the high-k dielectric layer 130H.

[0056] In one embodiment, interface layer 130I may comprise a low-k material layer with a dielectric constant of about 9 or lower, such as a silicon oxide film, a silicon oxynitride film, a gallium oxide (Ga) film, a germanium oxide (Ge) film, or a combination thereof. In one embodiment, interface layer 130I may comprise a silicate, a combination of a silicate and a silicon oxide film, or a combination of a silicate and a silicon oxynitride film. In one embodiment, interface layer 130I may be omitted.

[0057] The high-k dielectric layer 130H may include a material having a dielectric constant higher than that of the silicon oxide film. For example, the high-k dielectric layer 130H may have a dielectric constant of about 10 to about 25. The high-k dielectric layer 130H may include materials selected from the group consisting of hafnium oxide, hafnium oxynitride, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof, but the materials included in the high-k dielectric layer 130H are not limited thereto. The high-k dielectric layer 130H may be formed using atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD) processes. The high-k dielectric layer 130H may have a dielectric constant of about 10 to about 25. up to approximately The thickness, but not limited to this.

[0058] Gate spacers 132 may be located on two sidewalls of the first gate structure 120G1 and two sidewalls of the second gate structure 120G2. Gate spacers 132 may comprise silicon nitride or silicon oxynitride. Although not shown, gate spacers 132 may have a multilayer structure comprising multiple material layers sequentially formed on two sidewalls of the first gate structure 120G1 and two sidewalls of the second gate structure 120G2.

[0059] A first recess RS1 can be formed in a first fin active region FA1 on both sides of a plurality of first semiconductor patterns NS1, and a first semiconductor layer 140S1 can fill the first recess RS1. The first semiconductor layer 140S1 can be connected to one end of each of the plurality of first semiconductor patterns NS1. The first semiconductor layer 140S1 can be grown from the first fin active region FA1 and the plurality of first semiconductor patterns NS1 using a selective epitaxial growth (SEG) process. Furthermore, a second recess RS2 can be formed in a second fin active region FA2 on both sides of a plurality of second semiconductor patterns NS2, and the second semiconductor layer 140S2 can fill the second recess RS2. Both the first semiconductor layer 140S1 and the second semiconductor layer 140S2 can include an epitaxially grown silicon (Si) layer, an epitaxially grown silicon carbide (SiC) layer, or an embedded SiGe structure including a plurality of epitaxially grown silicon germanium (SiGe) layers.

[0060] An inter-gate dielectric layer 152 may be located on the two sidewalls of the gate spacer 132, the first semiconductor layer 140S1, and the second semiconductor layer 140S2. An upper insulating layer 154 may be located on the first gate structure 120G1, the second gate structure 120G2, and the inter-gate dielectric layer 152. A first contact plug 160C1 may be located inside a first contact hole 160H1, which passes through the upper insulating layer 154 and the inter-gate dielectric layer 152 and exposes the upper surface of the first semiconductor layer 140S1. Furthermore, a second contact plug 160C2 may be located inside a second contact hole 160H2, which passes through the upper insulating layer 154 and the inter-gate dielectric layer 152 and exposes the top surface of the second semiconductor layer 140S2. As shown, a metal silicide layer 162 may be further formed between the first contact plug 160C1 and the first semiconductor layer 140S1, and between the second contact plug 160C2 and the second semiconductor layer 140S2. In some embodiments, the metal silicide layer 162 may include titanium silicide or cobalt silicide, but is not limited thereto.

[0061] According to the above example embodiment, the second gate structure 120G2 may include a second material layer 124G2 containing oxygen as a work function material layer, thereby improving the electrical performance of the IC device 100. Referring below... Figure 18 Describe the electrical properties related to the second material layer 124G2.

[0062] Figure 18 This is a graph showing the equivalent oxide thickness and leakage current of an IC device according to an example embodiment. (Refer to...) Figure 18 The equivalent oxide thickness and leakage current of the second gate structure 120G2, which has a stacked structure with a second material layer 124G2 and a third material layer 126G2, were measured. In Example EX1, titanium oxide (TiO2) x Titanium nitride (TiN) was used as the second material layer 124G2. In Comparative Example CO1, titanium nitride (TiN) was used as the second material layer 124G2. (See reference...) Figure 18 As can be seen, in Example EX1, a significantly lower leakage current was measured at an equivalent oxide thickness level equal to that of Comparative Example CO1. Therefore, it can be seen that when a metal oxide with a higher oxygen content is used as the work function adjustment layer of the second gate structure 120G, the electrical performance of the IC device 100 can be improved.

[0063] Typically, the same material can be used to form the work function modulation layer of the first gate structure and the work function modulation layer of the second gate structure to different thicknesses, so that the first transistor and the second transistor can have different threshold voltages. For example, the first work function modulation material layer can be formed in both the first transistor formation region and the second transistor formation region. The first work function modulation material layer can be removed from the second transistor formation region, and then the second work function modulation material layer can be formed in the second transistor formation region. However, in IC devices comprising multiple nanosheet semiconductor patterns, the process of selectively removing or forming work function modulation material layers located in the spaces between the multiple semiconductor patterns can be relatively difficult.

[0064] However, according to the reference Figures 1 to 2B The described IC device 100 has a first material layer 122G1 with a relatively low oxygen content (or approximately 0 oxygen content) formed in a first gate structure 120G1, and a second material layer 124G2 with a relatively high oxygen content formed in a second gate structure 120G2. Therefore, the IC device 100 can have reduced leakage current.

[0065] Furthermore, during the formation of the second material layer 124G2 with a relatively high oxygen content, the undesirable oxidation of the first material layer 122G1 located in the plurality of first sub-gate portions 120S1 can be prevented. Therefore, the threshold voltage of each of the first transistor TR1 and the second transistor TR2 can be precisely controlled. Consequently, the IC device 100 can have improved performance.

[0066] Figure 3A and Figure 3B This is a cross-sectional view of IC device 100A according to an example embodiment. Figure 3A It shows the relationship with along Figure 1 The cross-sectional diagrams corresponding to the sections intercepted by lines A1-A1' and A2-A2'. Figure 3B It shows the relationship with along Figure 1 The cross-sectional diagrams corresponding to the sections intercepted by lines B1-B1' and B2-B2'. Figure 3A and 3B In the figures, the same reference numerals are used to indicate the same as those in the figures below. Figures 1 to 2B The same components.

[0067] Reference Figure 3A and Figure 3BThe first internal spacer 142S1 may be located between the first semiconductor layer 140S1 and the first gate structure 120G1, and the second internal spacer 142S2 may be located between the second semiconductor layer 140S2 and the second gate structure 120G2. The first internal spacer 142S1 may be located between the first semiconductor layer 140S1 and the first gate insulating layer GI1 of the plurality of first sub-gate portions 120S1. The second internal spacer 142S2 may be located between the second semiconductor layer 140S2 and the second gate insulating layer GI2 of the plurality of second sub-gate portions 120S2.

[0068] For example, the first internal spacer 142S1 and the second internal spacer 142S2 may comprise silicon nitride or silicon oxynitride. In an exemplary manufacturing process, the first recess RS1 and the second recess RS2 may be formed prior to the formation of the first semiconductor layer 140S1 and the second semiconductor layer 140S2. The portion of the sacrificial layer exposed on the inner walls of the first recess RS1 and the second recess RS2 may be removed in the lateral direction (see reference). Figure 7 (210 in the middle), so that a first internal spacer 142S1 and a second internal spacer 142S2 can be formed in the space formed in the removed part.

[0069] although Figure 3A An example is shown where the width of each first internal spacer 142S1 is equal to the width of each second internal spacer 142S2, but the inventive concept is not limited thereto. In other example embodiments, the width of each first internal spacer 142S1 may be different from the width of each second internal spacer 142S2.

[0070] Figure 3A An example is shown where the sidewalls of the first internal spacer 142S1 and the second internal spacer 142S2 extend vertically, but the inventive concept is not limited thereto. In other exemplary embodiments, the sidewall of each first internal spacer 142S1 may have a curved shape protruding in the direction toward the first semiconductor pattern NS1, and the sidewall of each second internal spacer 142S2 may have a curved shape protruding in the direction toward the second semiconductor pattern NS2. In other exemplary embodiments, one of the first internal spacer 142S1 and the second internal spacer 142S2 may be omitted. For example, only the second internal spacer 142S2 may be formed without forming the first internal spacer 142S1.

[0071] Figure 4A and Figure 4B This is a cross-sectional view of the IC device 100B according to an example embodiment. Figure 4A It shows the relationship with along Figure 1 The cross-sectional diagrams corresponding to the sections intercepted by lines A1-A1' and A2-A2'. Figure 4B It shows the relationship with along Figure 1 The cross-sectional diagrams corresponding to the sections intercepted by lines B1-B1' and B2-B2'. Figure 4A and Figure 4B In the figures, the same reference numerals are used to indicate the same as those in the figures below. Figures 1 to 3B The same components.

[0072] Reference Figure 4A and Figure 4B The first distance d21b between the bottommost first semiconductor pattern NS1 and the top surface of the first fin active region FA1 can be greater than the second distance d22b between the bottommost first semiconductor pattern NS1 and the adjacent first semiconductor pattern NS1.

[0073] The first material layer 122G1 may have a first thickness t11a on the top surface of the uppermost first semiconductor pattern NS1 or on the device isolation film 112. In some embodiments, the first thickness t11a may range from about 1 nm to about 15 nm, but is not limited thereto. The first thickness t11a may be greater than half the thickness of the lowermost first sub-gate portion 120S1. The thickness of the lowermost first sub-gate portion 120S1 may correspond to the distance between the surface of the first gate insulating layer GI1 on the lowermost first semiconductor pattern NS1 and the surface of the first gate insulating layer GI1 on the first fin active region FA1. Therefore, the first material layer 122G1 may fill each of the plurality of first sub-gate portions 120S1.

[0074] Figure 4B The illustration shows a scenario where the first distance d21b between the bottommost first semiconductor pattern NS1 and the top surface of the first fin active region FA1 is equal to the distance between the bottommost second semiconductor pattern NS2 and the top surface of the second fin active region FA2. However, the inventive concept is not limited thereto. In other embodiments, the first distance d21b between the bottommost first semiconductor pattern NS1 and the top surface of the first fin active region FA1 may differ from the distance between the bottommost second semiconductor pattern NS2 and the top surface of the second fin active region FA2.

[0075] Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7 , Figure 8 , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A and Figure 17B This is a cross-sectional view illustrating a method for manufacturing an IC device according to an example embodiment. Figure 5A , Figure 6A , Figure 7 , Figure 8 , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A and Figure 17A Is along Figure 1 The cross-sectional diagrams corresponding to the process sequence of the sections intercepted by lines A1-A1' and A2-A2'. In comparison, Figure 5B , Figure 6B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B and Figure 17B Is along Figure 1 The cross-sectional diagrams of the process sequence corresponding to the sections cut by lines B1-B1' and B2-B2'.

[0076] Now refer to Figure 5A and Figure 5B The sacrificial layer 210 and the first channel semiconductor layer PNS1 can be alternately and sequentially formed on the top surface 110M of the substrate 110, and the sacrificial layer 210 and the second channel semiconductor layer PNS2 can be alternately and sequentially formed on the top surface 110M of the substrate 110. The sacrificial layer 210, the first channel semiconductor layer PNS1, and the second channel semiconductor layer PNS2 can be formed using an epitaxial process.

[0077] The first transistor can be formed on the substrate 110 (see reference). Figure 1 A first channel semiconductor layer PNS1 is formed in the region of TR1, and a second transistor (see reference) can be formed on the substrate 110. Figure 1A second channel semiconductor layer PNS2 is formed in the region of TR2. In some embodiments, the first channel semiconductor layer PNS1 and the second channel semiconductor layer PNS2 can be formed using the same process and are connected to each other to form a material layer. In other embodiments, the second channel semiconductor layer PNS2 can be formed after the first channel semiconductor layer PNS1 is formed first.

[0078] In an example embodiment, the sacrificial layer 210 and the first channel semiconductor layer PNS1 and the second channel semiconductor layer PNS2 may comprise materials that are etch-selective relative to each other. For example, each of the sacrificial layer 210 and the first channel semiconductor layer PNS1 and the second channel semiconductor layer PNS2 may comprise a single crystal layer of a group III-V compound semiconductor, a group IV-IV compound semiconductor, or a group IV semiconductor. The sacrificial layer 210 and the first channel semiconductor layer PNS1 and the second channel semiconductor layer PNS2 may comprise different materials. In an example embodiment, the sacrificial layer 210 may comprise silicon germanium, and the first channel semiconductor layer PNS1 and the second channel semiconductor layer PNS2 may comprise single crystal silicon.

[0079] In other example embodiments, the epitaxial process may include vapor phase epitaxy (VPE), CVD processes such as ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), or combinations thereof. During the epitaxial process, liquid or gaseous precursors may be used as precursors required to form the sacrificial layer 210 and the first channel semiconductor layer PNS1 and the second channel semiconductor layer PNS2.

[0080] like Figure 5B As shown, the bottommost sacrificial layer 210 may have a first thickness t21, the bottommost first channel semiconductor layer PNS1 may have a second thickness t22, and the sacrificial layer 210 located on the bottommost first channel semiconductor layer PNS1 may have a third thickness t23. In an example embodiment, the first thickness t21 may be equal to the third thickness t23, and the second thickness t22 may be less than the first thickness t21. However, the inventive concept is not limited thereto. Figure 5B As shown, the second thickness t22 can be equal to the first thickness t21. In other embodiments, the first thickness t21 can be greater than the third thickness t23. In this case, a reference can be manufactured. Figure 4A and Figure 4B The IC device 100B is described.

[0081] Subsequently, a lower layer 222 and a hard mask pattern 224 extending a predetermined length in the first direction (X direction) can be formed on the first channel semiconductor layer PNS1 and the second channel semiconductor layer PNS2. The lower layer 222 and the hard mask pattern 224 can be used as etching masks to etch the sacrificial layer 210, the first channel semiconductor layer PNS1 and the second channel semiconductor layer PNS2, and the substrate 110, thereby forming a sacrificial layer pattern (not shown) and a device isolation trench 112T.

[0082] Subsequently, a device isolation liner 112L can be conformally formed inside the device isolation trench 112T. The interior of the device isolation trench 112T can be filled on the device isolation liner 112L with a device isolation film 112, and the upper part of the device isolation film 112 can be planarized. A portion of the device isolation film 112 and the substrate 110 can be etched to form a deep trench 114T defining a device region (DR), and a deep trench insulating film 114 can be formed inside the deep trench 114T.

[0083] Subsequently, the lower layer 222 and hard mask pattern 224 retained on the sacrificial layer pattern can be removed, and a recess process can be performed to remove the upper portion of the device isolation film 112 and the upper portion of the deep trench insulating film 114 of a certain thickness.

[0084] Reference Figure 6A and Figure 6B A dummy gate structure DG can be formed on the sacrificial layer pattern and the device isolation film 112. Each dummy gate structure DG may include a dummy gate insulating layer 232, a dummy gate line 234, a dummy gate capping layer 236, and a gate spacer 132. For example, the dummy gate line 234 may include polysilicon, and the dummy gate capping layer 236 may include a silicon nitride film. The dummy gate insulating layer 232 may include a material with etch selectivity relative to the dummy gate line 234. For example, the dummy gate insulating layer 232 may include a film comprising at least one of thermal oxide, silicon oxide, and silicon nitride. The gate spacer 132 may include, but is not limited to, silicon oxide, silicon oxynitride, or silicon nitride.

[0085] Reference Figure 7 The sacrificial layer pattern and portions of the substrate 110 located on both sides of the dummy gate structure DG can be etched to form a first recess RS1 and a second recess RS2 on both sides of the dummy gate structure DG. The sidewalls of the sacrificial layer 210 and the first channel semiconductor layer PNS1 and the second channel semiconductor layer PNS2 can be exposed at the inner walls of the first recess RS1 and the second recess RS2.

[0086] Optionally, recessed regions (not shown) can be formed by removing the portion of the sacrificial layer 210 exposed at the inner walls of the first recess RS1 and the second recess RS2 in the lateral direction using an isotropic etching process. For example, the process of removing a portion of the sacrificial layer 210 may include a wet etching process, and the sacrificial layer 210 comprising SiGe can be etched faster than the first channel semiconductor layer PNS1 and the second channel semiconductor layer PNS2 comprising, for example, silicon. Therefore, recessed regions can be formed. Subsequently, insulating layers (not shown) can be formed on the inner walls of the first recess RS1 and the second recess RS2 to fill the recessed regions. By retaining only the portion of the insulating layer located in the recessed regions and removing the remaining unnecessary insulating layer, internal spacers 142S1 and 142S2 can be formed. In this case, a reference can be manufactured. Figure 3A and Figure 3B The IC device 100A is described.

[0087] Reference Figure 8 The first semiconductor layer 140S1 and the second semiconductor layer 140S2 can be formed inside the first recess RS1 and the second recess RS2, respectively. For example, the first semiconductor layer 140S1 can be formed by epitaxially growing semiconductor material from the surface of the first channel semiconductor layer PNS1 and the substrate 110 exposed at the inner wall of the first recess RS1.

[0088] also, Figure 7 and Figure 8 An exemplary method is illustrated below: After simultaneously forming a first recess RS1 and a second recess RS2 on a first finned active region FA1 and a second finned active region FA2, a first semiconductor layer 140S1 and a second semiconductor layer 140S2 are simultaneously formed. However, for example, when the first finned active region FA1 is a PMOS transistor formation region and the second finned active region FA2 is an NMOS transistor formation region, a protective film (not shown) can be formed on the second finned active region FA2, and then the first recess RS1 and the first semiconductor layer 140S1 can be formed. Thereafter, a protective film (not shown) can be formed on the first finned active region FA1, and then the second recess RS2 and the second semiconductor layer 140S2 can be formed. In this case, the material included in the first semiconductor layer 140S1 may be different from the material included in the second semiconductor layer 140S2. Thereafter, an inter-gate dielectric layer 152 can be formed on the sidewalls of the dummy gate structure DG, the first semiconductor layer 140S1, and the second semiconductor layer 140S2.

[0089] Reference Figure 9A and Figure 9B This can planarize the upper part of the dummy gate structure DG and the upper part of the inter-gate dielectric layer 152, thereby removing the dummy gate capping layer of the dummy gate structure DG (see reference). Figure 8 In section 236), the top surface of the dummy gate line 234 is exposed. Subsequently, the dummy gate line 234 and the dummy gate insulating layer 232 exposed by the inter-gate dielectric layer 152 can be removed to define the gate space GS. During the removal process, the gate spacer 132 can be retained, and the gate space GS can be defined by the two sidewalls of the gate spacer 132.

[0090] Reference Figure 10A and Figure 10B Multiple sacrificial layers 210 retained on the first fin active region FA1 and the second fin active region FA2 can be removed through the gate space GS. Therefore, the top surfaces of the first channel semiconductor layer PNS1 and the second channel semiconductor layer PNS2, as well as the top surfaces of the first fin active region FA1 and the second fin active region FA2, can be partially exposed through the gate space GS.

[0091] The first channel semiconductor layer PNS1 retained on the first fin active region FA1 can be referred to as a plurality of first semiconductor patterns NS1, and the second channel semiconductor layer PNS2 retained on the second fin active region FA2 can be referred to as a plurality of second semiconductor patterns NS2. A first sub-gate space GSS1 can be formed between the plurality of first semiconductor patterns NS1, and a second sub-gate space GSS2 can be formed between the plurality of second semiconductor patterns NS2. The removal of the plurality of sacrificial layers 210 can be performed using a wet etching process that utilizes the difference in etching rate between the sacrificial layers 210 and the first channel semiconductor layers PNS1 and the second channel semiconductor layers PNS2.

[0092] Reference Figure 11A and Figure 11B A first gate insulating layer GI1 and a second gate insulating layer GI2 can be formed on the exposed surfaces of the gate space GS, the first sub-gate space GSS1, and the second sub-gate space GSS2. The first gate insulating layer GI1 can be formed as a sidewall NSS1 surrounding a plurality of first semiconductor patterns NS1, and can also be formed on the top surface of the first fin active region FA1, as well as on the device isolation film 112 and the deep trench insulating film 114. The second gate insulating layer GI2 can be formed as a sidewall NSS2 surrounding a plurality of second semiconductor patterns NS2, and can also be formed on the top surface of the second fin active region FA2, as well as on the device isolation film 112 and the deep trench insulating film 114.

[0093] Reference Figure 12A and Figure 12BA first material layer 122G1 can be conformally formed on the first gate insulating layer GI1 and the second gate insulating layer GI2. The first material layer 122G1 can be formed not only on the first fin active region FA1 and the second fin active region FA2, but also on the device isolation film 112 and the deep trench insulating film 114. In an example embodiment, the first material layer 122G1 can completely fill the first sub-gate space GSS1 between a plurality of first semiconductor patterns NS1, and can completely fill the second sub-gate space GSS2 between a plurality of second semiconductor patterns NS2.

[0094] In an example embodiment, the first material layer 122Gl may include at least one of a metal nitride containing a first metal, a metal carbide containing a first metal, and a metal carbonitride containing a first metal, and the first metal may include at least one of titanium, tantalum, niobium, molybdenum, and tungsten.

[0095] Reference Figure 13A and Figure 13B A mask material layer can be formed on the first material layer 122G1 to fill the gate space GS, and a mask pattern can be formed on the mask material layer to overlap with the first fin active region FA1. The mask material layer can be etched using the mask pattern to form a mask layer 240. The mask layer 240 can cover multiple first semiconductor patterns NS1 and the first fin active region FA1. Furthermore, since the first sub-gate space GSS1 between the multiple first semiconductor patterns NS1 is filled with the first material layer 122G1, the first sub-gate space GSS1 may not be filled with the material included in the mask layer 240.

[0096] In an example embodiment, mask layer 240 may include a carbon-based insulating material. For example, mask layer 240 may include materials with a relatively high carbon content, such as, but not limited to, SiC:H, SiCN, SiCN:H, SiOCN, SiOCN:H, silicon oxycarbide (SiOC), spin-on hard mask (SOH), silicon-containing antireflective coating (ARC) layer, spin-on glass (SOG), advanced planarization layer (APL) and / or organic dielectric layer (ODL).

[0097] Reference Figure 14A and Figure 14B The mask layer 240 can be used as an etching mask to remove the first material layer 122G1 exposed on the second fin active region FA2, the device isolation film 112, and the deep trench insulating film 114. In an example embodiment, a wet etching process can be used to perform the removal of the first material layer 122G1 using the mask layer 240. During the wet etching process, the first material layer 122G1 located on the sidewalls of the gate space GS and in the plurality of second sub-gate spaces GSS2 can be removed.

[0098] Reference Figure 15A and Figure 15B This can remove the mask layer (see reference). Figure 14A (240 in the text). Subsequently, an etch-back process can be used to partially remove the upper portion of the first material layer 122G1 located in the gate space GS on the first finned active region FA1. The top surface of the first material layer 122G1 can be at a lower horizontal level than the top surfaces of the inter-gate dielectric layer 152 and the gate spacer 132. Furthermore, during the etch-back process, portions of the first material layer 122G1 located in the plurality of first sub-gate spaces GSS1 can be removed without damage or removal.

[0099] Reference Figure 16A and Figure 16B A second material layer 124G2 can be formed on multiple second semiconductor patterns NS2 located on the second fin active region FA2, and a fourth material layer 124G1 can be formed on the first material layer 122G1 located on the first fin active region FA1.

[0100] In example embodiments, the second material layer 124G2 and the fourth material layer 124G1 may include at least one of a metal oxide containing a second metal, a metal nitride containing a second metal, a metal carbon oxide containing a second metal, and a metal carbonitride containing a second metal. The second metal may include at least one of titanium, tantalum, niobium, molybdenum, and tungsten. In some examples, the second material layer 124G2 may be represented by the following formula: M x O y N z Where M is the second metal, O is oxygen, N is nitrogen, 0.2≤y≤0.7, 0.3≤x+z≤0.8, and 0≤z≤0.5.

[0101] In an example embodiment, the processes for forming the second material layer 124G2 and the fourth material layer 124G1 can be performed in an oxygen-containing atmosphere or using a formation process that uses oxygen as a reactant. In other embodiments, to form the second material layer 124G2 and the fourth material layer 124G1, an initial material layer can first be formed in an oxygen-free atmosphere, followed by an oxidation process (or a process that exposes the initial material layer to an oxygen-containing atmosphere). In other embodiments, the processes for forming the second material layer 124G2 and the fourth material layer 124G1 can be performed in an oxygen-containing atmosphere or using a formation process that uses oxygen as a reactant, followed by a further process that exposes the formed material layers to an oxygen-containing atmosphere.

[0102] The fourth material layer 124G1 may not be formed inside the plurality of first sub-gate spaces GSS1, but may instead be located on the first material layer 122G1 within the gate space GS1. Furthermore, during the processes of forming the second material layer 124G2 and the fourth material layer 124G1, the first material layer 122G1 located within the first sub-gate spaces GSS1 will not be oxidized or damaged. Therefore, the second material layer 124G2 and the fourth material layer 124G1 may contain a relatively high oxygen content, while the first material layer 122G1 may contain substantially no oxygen.

[0103] Subsequently, a third material layer 126G2 and a fifth material layer 126G1 can be formed on the second material layer 124G2 and the fourth material layer 124G1, respectively. The third material layer 126G2 and the fifth material layer 126G1 may contain aluminum, copper, titanium, tantalum, tungsten, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, titanium nitride, tungsten nitride, titanium aluminide, titanium aluminum carbide, titanium aluminum nitride, tantalum carbonitride, tantalum carbide, silicon tantalum nitride, or combinations thereof, but are not limited thereto.

[0104] Return to reference Figure 2A and Figure 2B A first buried conductive layer 128G1 and a second buried conductive layer 128G2 can be formed on the fifth material layer 126G1 and the third material layer 126G2 to fill the gate space GS. The upper portion of the first buried conductive layer 128G1 and the upper portion of the second buried conductive layer 128G2 can be planarized, exposing the top surface of the inter-gate dielectric layer 152. Therefore, a first gate structure 120G1 and a second gate structure 120G2 can be formed.

[0105] According to the above-described method for manufacturing the IC device 100, a first material layer 122G1 can be formed to fill the first sub-gate space GSS1 and the second sub-gate space GSS2, and the first material layer 122G1 can be removed from the second sub-gate space GSS2. Subsequently, a fourth material layer 124G1 and a second material layer 124G2 can be formed on the first material layer 122G1 and in the second sub-gate space GSS2 using a material with a relatively high oxygen content. During the formation of the second material layer 124G2 with a relatively high oxygen content, the first material layer 122G1 located in the plurality of first sub-gate portions 120S1 can be prevented from being undesirably oxidized. Therefore, advantageously, the second transistor TR2 can have a reduced leakage current, and more precise control of the threshold voltage of each of the first transistor TR1 and the second transistor TR2 can be achieved. Therefore, the IC device 100 can have improved performance.

[0106] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit device, comprising: The first finned semiconductor active region and the second finned semiconductor active region are located on the substrate; Multiple first semiconductor patterns are stacked on the first fin active region to form multiple spaced first channel regions of a first fin field-effect transistor having a first threshold voltage. Multiple second semiconductor patterns are stacked on the second fin active region to serve as multiple spaced second channel regions of a second fin field-effect transistor having a second threshold voltage different from the first threshold voltage. A first gate structure is located on the plurality of first semiconductor patterns. The first gate structure includes a first conductive material region that at least partially fills the space between the plurality of spaced-apart first channel regions and surrounds each of the plurality of spaced-apart first channel regions. as well as A second gate structure is located on the plurality of second semiconductor patterns. The second gate structure includes a second conductive material region and a third conductive material region, the second conductive material region and the third conductive material region at least partially filling the space between the plurality of spaced-apart second channel regions. Wherein, the second conductive material region surrounds each of the plurality of spaced-apart second channel regions; The third conductive material region surrounds each of the plurality of spaced-apart second channel regions and surrounds the second conductive material region; Wherein, the work function of the third conductive material region is less than the work function of the first conductive material region and less than the work function of the second conductive material region; and Wherein, the oxygen content percentage in the second conductive material region exceeds the oxygen content percentage in the first conductive material region.

2. The integrated circuit device according to claim 1, wherein, The first conductive material region extends on the sidewalls of the plurality of first semiconductor patterns and on the top surface of the uppermost first semiconductor pattern among the plurality of first semiconductor patterns; wherein the first gate structure further includes a combination of a fourth material region and a fifth material region, the fourth material region and the fifth material region extending on the sidewalls and top surface of the first conductive material region.

3. The integrated circuit device according to claim 2, wherein, The oxygen content percentage in the fourth material region exceeds the oxygen content percentage in the first conductive material region.

4. The integrated circuit device according to claim 1, wherein, The first conductive material region includes at least one of a metal nitride containing a first metal, a metal carbide containing the first metal, and a metal carbonitride containing the first metal; wherein the second conductive material region includes at least one of a metal oxide containing a second metal, a metal nitride containing the second metal, a metal carbon oxide containing the second metal, and a metal carbonitride containing the second metal.

5. The integrated circuit device according to claim 4, wherein, The first metal is selected from the group consisting of titanium, niobium, tantalum, molybdenum and tungsten; wherein the second metal is selected from the group consisting of titanium, niobium, tantalum, molybdenum and tungsten.

6. The integrated circuit device according to claim 4, wherein, The second conductive material region includes M x O y N z Where M is a metal, O is oxygen, N is nitrogen, x>0.0, z>0.0, 0.2≤y≤0.7, 0.3≤x+z≤0.

8.

7. The integrated circuit device according to claim 1, wherein, The first conductive material region is electrically insulated from the plurality of first semiconductor patterns; wherein the second conductive material region is electrically insulated from the plurality of second semiconductor patterns.

8. An integrated circuit device, comprising: The first finned semiconductor active region and the second finned semiconductor active region are located on the substrate; Multiple first semiconductor patterns are stacked on the first fin active region to form multiple spaced first channel regions of the first fin field-effect transistor. Multiple second semiconductor patterns are stacked on the second fin active region to serve as multiple spaced second channel regions of the second fin field-effect transistor. A first gate structure is located on the plurality of first semiconductor patterns, the first gate structure including a first material region surrounding and at least partially filling the space between the plurality of spaced-apart first channel regions; as well as A second gate structure is located on the plurality of second semiconductor patterns. The second gate structure includes a second material region and a third material region. The second material region surrounds and at least partially fills the space between the plurality of spaced-apart second channel regions. The third material region surrounds the second material region. The work function of the third material region is lower than that of the second material region. The oxygen content percentage in the second material region exceeds the oxygen content percentage in the first material region.

9. The integrated circuit device according to claim 8, wherein, The second material region includes M x O y N z Where M is a metal, O is oxygen, N is nitrogen, x>0.0, z>0.0, 0.2≤y≤0.7, 0.3≤x+z≤0.

8.

10. An integrated circuit device, comprising: The first fin-shaped active region and the second fin-shaped active region protrude from the substrate and extend along the first direction; A plurality of first semiconductor patterns, the plurality of first semiconductor patterns being spaced apart from the top surface of the first fin active region, each first semiconductor pattern having a channel region; A plurality of second semiconductor patterns, the plurality of second semiconductor patterns being spaced apart from the top surface of the second fin active region, each second semiconductor pattern having a channel region; A first gate structure, extending along a second direction over the first finned active region and including a first material layer, the first material layer filling first sub-gate spaces between respective first semiconductor patterns, wherein the second direction is perpendicular to the first direction; and A second gate structure extends along the second direction over the second fin active region and includes a second material layer and a third material layer, the second material layer and the third material layer being sequentially located in a second sub-gate space between respective second semiconductor patterns. The third material layer surrounds the second material layer, and the work function of the third material layer is lower than the work function of both the first and second material layers. The oxygen content of the material included in the second material layer is higher than that of the material included in the first material layer.

11. The integrated circuit device according to claim 10, wherein, The first material layer is located on the sidewalls of the plurality of first semiconductor patterns in the second direction and on the top surface of the uppermost first semiconductor pattern. The first gate structure further includes: A fourth material layer, located on the first material layer and surrounding the sidewalls of the plurality of first semiconductor patterns in the second direction; and A fifth material layer, which is located on the fourth material layer and surrounds the sidewalls of the plurality of first semiconductor patterns in the second direction.

12. The integrated circuit device according to claim 11, wherein, The oxygen content of the materials included in the fourth material layer is higher than that of the materials included in the first material layer.

13. The integrated circuit device according to claim 11, wherein, The first material layer has a first thickness, and the second material layer has a second thickness that is less than the first thickness. The second thickness is approximately 2 nm or less, and The thickness of the fourth material layer is equal to the second thickness of the second material layer.

14. The integrated circuit device according to claim 11, wherein, The first gate structure also includes a first buried conductive layer surrounding the fifth material layer. The second material layer is located on the sidewalls of the plurality of second semiconductor patterns in the second direction and on the top surface of the uppermost second semiconductor pattern, and The second gate structure also includes a second buried conductive layer surrounding the third material layer.

15. The integrated circuit device according to claim 10, wherein, The first material layer includes at least one of a metal nitride containing a first metal, a metal carbide containing the first metal, and a metal carbonitride containing the first metal. The second material layer includes at least one of a metal oxide containing a second metal, a metal nitride containing the second metal, a metal carbon oxide containing the second metal, and a metal carbonitride containing the second metal.

16. The integrated circuit device according to claim 15, wherein, The first metal includes at least one of titanium, tantalum, niobium, molybdenum, and tungsten, and The second metal includes at least one of titanium, tantalum, niobium, molybdenum, and tungsten.

17. The integrated circuit device according to claim 15, wherein, The second material layer is composed of formula M x O y N z To indicate, Where M is the second metal, 0.2≤y≤0.7, 0.3≤x+z≤0.

8.

18. The integrated circuit device of claim 10, further comprising: A first gate insulating layer is located between the plurality of first semiconductor patterns and the first material layer; as well as A second gate insulating layer is located between the plurality of second semiconductor patterns and the second material layer.

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