Comparator

Abstract

The present invention relates to a comparator, comprising: a first-stage operational amplifier circuit, a second-stage operational amplifier circuit, a bias circuit and a clamp circuit; the first-stage operational amplifier circuit comprises two voltage input terminals and a voltage output terminal; the second-stage operational amplifier circuit is connected to the bias circuit and the voltage output terminal of the first-stage operational amplifier circuit; the clamp circuit is connected to the voltage output terminal of the first-stage operational amplifier circuit. In the above-mentioned comparator, by adding a clamp circuit, the highest voltage of the voltage output terminal of the first-stage operational amplifier circuit can be clamped to a preset voltage, and the voltage variation amplitude of the voltage output terminal of the first-stage operational amplifier circuit is small during the operation of the comparator, which can reduce the discharge delay of the voltage output terminal of the first-stage operational amplifier circuit, thereby improving the flipping speed of the comparator.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a comparator. Background Art

[0002] Existing comparators are widely used in various fields. One requirement of comparators is to be able to quickly obtain the comparison result so as to quickly carry out the next step of processing. For example, when an overcurrent abnormality is detected, it is hoped that the abnormal situation will be processed as soon as possible. However, due to the inherent delay of the comparator itself, the processing speed is often delayed, and the flipping speed of the comparator is slow. This delay is mainly caused by the delay of charging and discharging of the nodes at the output end of the first-stage operational amplifier circuit and the output end of the second-stage operational amplifier circuit in the comparator. For example, when the first voltage to be compared VP is greater than the second voltage to be compared VN, the circuit pull-down of the output end of the first-stage operational amplifier circuit will be pulled down from a higher potential to the ground potential. When the first voltage to be compared VP is less than the second voltage to be compared VN, the potential of the output end of the first-stage operational amplifier circuit will be pulled up to a high potential again. In addition, the rapid change of the output signal of the first-stage operational amplifier circuit in the comparator will be coupled to the first voltage to be compared VP, forming a kickback noise, which will not only interfere with the voltage to be compared, but also may cause output error flipping. Summary of the invention

[0003] Based on this, it is necessary to improve the comparator in the prior art, which has problems such as delayed processing speed and slow flipping speed of the comparator due to the delay in charging and discharging at the output end, and the formation of kick-back noise, which interferes with the compared voltage and causes output erroneous flipping.

[0004] In order to achieve the above object, on the one hand, the present invention provides a comparator, comprising:

[0005] The first stage operational amplifier circuit, the second stage operational amplifier circuit, the bias circuit and the clamp circuit; wherein,

[0006] The first-stage operational amplifier circuit comprises two voltage input terminals and a voltage output terminal; the two voltage input terminals of the first-stage operational amplifier circuit are used to input the voltage to be compared;

[0007] The second stage operational amplifier circuit is connected to the bias circuit and the voltage output terminal of the first stage operational amplifier circuit;

[0008] The clamping circuit is connected to the voltage output terminal of the first-stage operational amplifier circuit, and is used to clamp the highest voltage of the voltage output terminal of the first-stage operational amplifier circuit to a preset voltage.

[0009] By adding a clamping circuit in the above-mentioned comparator, the maximum voltage of the voltage output terminal of the first-stage operational amplifier circuit can be clamped to a preset voltage. During the operation of the comparator, the voltage change amplitude of the voltage output terminal of the first-stage operational amplifier circuit is small, which can reduce the discharge delay of the voltage output terminal of the first-stage operational amplifier circuit, thereby improving the flipping speed of the comparator; in addition, since the voltage change amplitude of the voltage output terminal of the first-stage operational amplifier circuit is small, the coupling effect of the voltage change of the voltage output terminal of the first-stage operational amplifier circuit on the input voltage to be compared is also reduced accordingly, which can reduce the kick-back noise of the input voltage to be compared, avoid interference with the voltage to be compared, and ensure the correctness of the output; at the same time, the above-mentioned comparator also has the advantages of simple structure, low cost and easy implementation.

[0010] In one embodiment, the first stage operational amplifier circuit includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor and a second NMOS transistor; wherein,

[0011] The gate of the first PMOS tube is connected to a first voltage to be compared;

[0012] The gate of the second PMOS tube is connected to the second voltage to be compared;

[0013] The gate of the third PMOS tube is connected to the bias circuit, and the drain of the third PMOS tube is connected to the source of the first PMOS tube and the source of the second PMOS tube;

[0014] The gate and drain of the first NMOS tube are short-circuited and connected to the drain of the first PMOS tube, and the source of the first NMOS tube is grounded;

[0015] The gate of the second NMOS tube is connected to the gate of the first NMOS tube, the drain of the second NMOS tube is connected to the drain of the second PMOS tube as the voltage output terminal of the first stage operational amplifier circuit, and the source of the second NMOS tube is grounded.

[0016] In one embodiment, the clamping circuit includes a first switch tube, the control end and the current input end of the first switch tube are connected to the voltage output end of the first-stage operational amplifier circuit, and the current output end of the first switch tube is connected to the gate of the second NMOS.

[0017] In one embodiment, the first switch tube includes an NMOS tube.

[0018] In one embodiment, the clamping circuit further includes a second switch tube, the control end and the current input end of the second switch tube are connected to the voltage output end of the first-stage operational amplifier, and the current output end of the second switch tube is connected to the voltage output end of the second-stage operational amplifier.

[0019] In one example, the second-stage operational amplifier circuit includes: a fourth PMOS transistor and a third NMOS transistor; wherein,

[0020] The gate of the fourth PMOS tube is connected to the bias circuit;

[0021] The gate of the third NMOS tube is connected to the voltage output end of the first-stage operational amplifier circuit, the drain of the third NMOS tube is connected to the drain of the fourth PMOS tube and serves as the voltage output end of the second-stage operational amplifier circuit, and the source of the third NMOS tube is grounded.

[0022] In one example, the bias circuit includes: a fifth PMOS tube and a current source; wherein,

[0023] The gate of the fifth PMOS tube is connected to the first-stage operational amplifier circuit and the second-stage operational amplifier circuit, and the drain of the fifth PMOS tube is connected to the current source.

[0024] In one embodiment, the clamping circuit includes a switch tube, the control end and the current input end of the switch tube are connected to the voltage output end of the first-stage operational amplifier circuit, and the current output end of the switch tube is connected to the output end of the second-stage operational amplifier circuit.

[0025] In one embodiment, the switch tube includes an NMOS tube.

[0026] In one embodiment, the clamping circuit includes a switch tube, a current input end of the switch tube is connected to a voltage output end of the first-stage operational amplifier circuit, a control end of the switch tube is connected to a bias voltage, and a current output end of the switch tube is grounded.

[0027] In one embodiment, the switch tube includes a PMOS tube or a PNP transistor.

[0028] In one embodiment, the clamping circuit includes: a first switch tube, a second switch tube and a third switch tube; wherein,

[0029] The current input terminal of the first switch tube is connected to the voltage output terminal of the first-stage operational amplifier circuit, and the control terminal of the first switch tube is connected to the current output terminal of the second switch tube and the current input terminal of the third switch tube;

[0030] The control terminal of the second switch tube is connected to the bias circuit;

[0031] The control end of the third switch tube is short-circuited with the current input end of the third switch tube, and the circuit output end of the third switch tube is grounded.

[0032] In one embodiment, the first switch tube includes a PMOS tube or a PNP transistor, the second switch tube includes a PMOS tube, and the third switch tube includes an NMOS tube. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figures 1 to 5 4 is a circuit diagram of a comparator in different embodiments of the present invention.

[0034] Description of reference numerals:

[0035] 10 First stage op amp circuit

[0036] 11 Second stage op amp circuit

[0037] 12 Bias Circuit

[0038] 13 Clamping circuit DETAILED DESCRIPTION

[0039] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0040] It should be noted that when an element is considered to be "connected" to another element, it may be directly connected to another element and integrated therewith, or there may be an intermediate element at the same time. The terms "installed", "one end", "the other end" and similar expressions used herein are for illustrative purposes only.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0042] In one embodiment, Figures 1 to 5As shown, a comparator of the present invention includes: a first-stage operational amplifier circuit 10, a second-stage operational amplifier circuit 11, a bias circuit 12 and a clamping circuit 13; wherein the first-stage operational amplifier circuit 10 includes two voltage input terminals and a voltage output terminal; the two voltage input terminals of the first-stage operational amplifier circuit 10 are used to input a voltage to be compared; the second-stage operational amplifier circuit 11 is connected to the bias circuit 12 and the voltage output terminal of the first-stage operational amplifier circuit 10; the clamping circuit 13 is connected to the voltage output terminal of the first-stage operational amplifier circuit 10, and the clamping circuit 13 is used to clamp the highest voltage of the voltage output terminal of the first-stage operational amplifier circuit 10 to a preset voltage.

[0043] Specifically, one input terminal of the first operational amplifier circuit 10 is used to input the first voltage to be compared VN, and the other input terminal of the first operational amplifier circuit 10 is used to input the second voltage to be compared VP.

[0044] For an example, see Figures 1 to 5 The first stage operational amplifier circuit 10 includes: a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first NMOS transistor MN1 and a second NMOS transistor MN2; wherein, the gate of the first PMOS transistor MP1 is connected to the first voltage to be compared VN; the gate of the second PMOS transistor MP2 is connected to the second voltage to be compared VP; the gate of the third PMOS transistor MP3 is connected to the bias circuit 12, and the drain of the third PMOS transistor MP3 is connected to the source of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2; the gate and the drain of the first NMOS transistor MN1 are short-circuited and connected to the drain of the first PMOS transistor MP1, and the source of the first NMOS transistor MN1 is grounded; the gate of the second NMOS transistor MN2 is connected to the gate of the first NMOS transistor MN1, and the drain of the second NMOS transistor MN2 is connected to the drain of the second PMOS transistor MP2 as the voltage output terminal of the first stage operational amplifier circuit 10, which is used to output the first output signal VOUT1, and the source of the second NMOS transistor MN2 is grounded.

[0045] In one example, the second-stage operational amplifier circuit 11 includes: a fourth PMOS transistor MP4 and a third NMOS transistor MN3; wherein the gate of the fourth PMOS transistor MP4 is connected to the bias circuit 12; the gate of the third NMOS transistor MN3 is connected to the voltage output end of the first-stage operational amplifier circuit 10, and the drain of the third NMOS transistor MN3 is connected to the drain of the fourth PMOS transistor MP4 as the voltage output end of the second-stage operational amplifier circuit 11, which is used to output the second output signal VOUT2, and the source of the third NMOS transistor MN3 is grounded.

[0046] In one example, the bias circuit 12 includes: a fifth PMOS transistor MP5 and a current source IBIAS; wherein the gate of the fifth PMOS transistor MP5 is connected to the first-stage operational amplifier circuit 10 and the second-stage operational amplifier circuit 11, and the gate and drain of the fifth PMOS transistor MP5 are connected to the current source IBIAS. Specifically, the gate of the fifth PMOS transistor MP5 is connected to the gate of the third PMOS transistor MP3 and the gate of the fourth PMOS transistor MP4.

[0047] In an alternative example, Figure 1 As shown, the clamping circuit 13 may include a first switch tube M, the control end and the current input end of the first switch tube M are connected to the voltage output end of the first-stage operational amplifier circuit 10, and the current output end of the first switch tube M is connected to the gate of the second NMOS tube MN2. In this example, the clamping circuit 13 can clamp the output end of the first-stage operational amplifier circuit 10, and can clamp the highest voltage of the output end of the first-stage operational amplifier circuit 10 to Vgs (gate-source voltage of the first switch tube M) + Vgsn1 (gate-source voltage of the first NMOS tube MN1). In this way, when the second voltage to be compared VP is greater than the first voltage to be compared VN, the voltage VOUT1 at the output end of the first-stage operational amplifier circuit 10 will no longer need to be increased from a high potential (VDD-Vonp3-Vonp2, Vonp3 and Vonp2 are MP3 and MP4 tubes respectively). 2) to the ground potential, but is pulled downward from a voltage of approximately Vgs+Vgsn1 (Vgs+Vgsn1 is less than VDD-Vonp3-Vonp2), so that the discharge delay of the first-stage operational amplifier circuit 10 is reduced, thereby increasing the flip voltage of the comparator; at the same time, the change amplitude of the first-stage operational amplifier circuit 10 is smaller, so the coupling effect of the change of the first-stage operational amplifier circuit 10 on the first voltage to be compared VN and the second voltage to be compared VP is also reduced accordingly, and the first voltage to be compared VN and the second voltage to be compared VP are less disturbed by the kick-back noise.

[0048] In an example, the first switch tube M may include an NMOS tube.

[0049] In another alternative example, Figure 3 As shown, the clamping circuit 13 may include a first switch tube M1, the control end and the current input end of the first switch tube M1 are connected to the voltage output end of the first-stage operational amplifier circuit 10, and the current output end of the first switch tube M1 is connected to the gate of the second NMOS tube MN2; the control end and the current input end of the second switch tube M2 are connected to the voltage output end of the first-stage operational amplifier circuit 10, and the current output end of the second switch tube M2 is connected to the voltage output end of the second-stage operational amplifier circuit 11.

[0050] In an example, the first switch tube M1 may include an NMOS tube, and the second switch tube M2 may include an NMOS tube.

[0051] In yet another alternative example, Figure 2 As shown, the clamping circuit may include a switch tube M, the control end and the current input end of the switch tube M are connected to the voltage output end of the first-stage operational amplifier circuit 10, and the current output end of the switch tube M is connected to the output end of the second-stage operational amplifier circuit 11. In this example, the clamping circuit 13 can clamp the output end of the first-stage operational amplifier circuit 10, and can clamp the highest voltage of the output end of the first-stage operational amplifier circuit 10 to Vgs (gate-source voltage of the switch tube M) + Vdsn3 (drain-source voltage of the third NMOS tube MN3). In this way, when the second voltage to be compared VP is greater than the first voltage to be compared VN, the voltage VOUT1 at the output end of the first-stage operational amplifier circuit 10 will no longer need to be increased from a high potential (VDD-Vonp3-Vonp2, Vonp3 and Vo). np2 is the turn-on voltage value of MP3 tube and MP2 tube respectively) to the ground potential, but is pulled down from a voltage of approximately Vgs+Vdsn3, so that the discharge delay of the first-stage operational amplifier circuit 10 is reduced, thereby increasing the flip voltage of the comparator; at the same time, the change amplitude of the first-stage operational amplifier circuit 10 is smaller, so the coupling effect of the change of the first-stage operational amplifier circuit 10 on the first voltage to be compared VN and the second voltage to be compared VP is also reduced accordingly, and the first voltage to be compared VN and the second voltage to be compared VP are less disturbed by the kick-back noise.

[0052] Back to Figure 3 structure, combined with Figure 1 and Figure 2 From the analysis, it can be seen that the voltage VOUT1 at the output end of the first-stage operational amplifier circuit 10 is clamped to the smaller value between Vgsm1+Vgsn1 (Vgsm1 is the gate-source voltage of the M1 tube, Vgsn1 is the gate-source voltage of the MN1 tube) and Vgsm2+Vdsn3 (Vgsm2 is the gate-source voltage of the M2 tube, Vdsn3 is the drain-source voltage of the MN3 tube), which further reduces the variation amplitude of the voltage VOUT1 at the output end of the first-stage operational amplifier circuit 10, thereby further improving the flipping speed of the comparator and reducing the kick-back noise.

[0053] In an example, the switch tube M may include an NMOS tube.

[0054] In yet another optional example, Figure 4As shown, the clamping circuit 13 may include a switch tube M, the current input terminal of the switch tube M is connected to the voltage output terminal of the first-stage operational amplifier circuit 10, the control terminal of the switch tube is connected to the bias voltage VBIAS, and the current output terminal of the switch tube M is grounded. In this example, the clamping circuit 13 can clamp the output terminal of the first-stage operational amplifier circuit 10, and can clamp the highest voltage of the output terminal of the first-stage operational amplifier circuit 10 to Vgs1 (gate-source voltage of the switch tube M) + VBIAS. In this way, when the second voltage to be compared VP is greater than the first voltage to be compared VN, the voltage VOUT1 at the output terminal of the first-stage operational amplifier circuit 10 will no longer need to be pulled from a high potential (VDD-Vonp3-Vonp2, Vonp3 and Vonp2 are the turn-on voltage values ​​of the MP3 tube and the MP2 tube respectively) to the ground potential, but from about Vgs1+VBIAS. The voltage of AS is pulled down (Vgs1+VBIAS is less than VDD-Vonp3-Vonp2), and the voltage to which the output end of the first-stage operational amplifier circuit 10 is clamped can be changed by adjusting VBIAS, so that the discharge delay of the first-stage operational amplifier circuit 10 is reduced, thereby improving the flipping speed of the comparator; at the same time, the change amplitude of the first-stage operational amplifier voltage 10 is smaller, so the coupling effect of the change of the first-stage operational amplifier circuit 10 on the first voltage to be compared VN and the second voltage to be compared VP is also reduced accordingly, and the first voltage to be compared VN and the second voltage to be compared VP are less disturbed by the kick-back noise.

[0055] In an example, the switch tube M may include a PMOS tube or a PNP transistor.

[0056] In yet another optional example, Figure 5As shown, the clamp circuit 13 may include: a first switch tube M1, a second switch tube M2 and a third switch tube M3; wherein the current input terminal of the first switch tube M1 is connected to the voltage output terminal of the first stage operational amplifier circuit 10, and the control terminal of the first switch tube M1 is connected to the current output terminal of the second switch tube M2 and the current input terminal of the third switch tube M3; the control terminal of the second switch tube M2 is connected to the bias circuit 12, specifically, the control terminal of the second switch tube M2 is connected to the gate of the fifth PMOS tube; the control terminal of the third switch tube M3 is short-circuited with the current input terminal of the third switch tube M3, and the circuit output terminal of the third switch tube M3 is grounded. In this example, the bias voltage VBIAS connected to the gate of the first switch tube M1 is the gate-source voltage of the third switch tube M3. By selecting the first switch tube M1, the second switch tube M2 or the third switch tube M3 with different channel width-to-length ratios, the clamping circuit 13 can be adjusted to clamp the voltage output end of the first-stage operational amplifier circuit 10 to a preset clamping voltage; for example, increasing the width-to-length ratio of the first switch tube M1, the second switch M2 or the third switch M3 can reduce the bias voltage VBIAS, thereby reducing the clamping voltage; reducing the width-to-length ratio of the first switch tube M1, the second switch M2 or the third switch M3 can increase the bias voltage VBIAS, thereby increasing the clamping voltage.

[0057] In an example, the first switch tube M1 includes a PMOS tube or a PNP transistor, the second switch tube M2 includes a PMOS tube, and the third switch tube M3 includes an NMOS tube.

[0058] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0059] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A comparator, characterized in that: include: The first stage operational amplifier circuit, the second stage operational amplifier circuit, the bias circuit and the clamping circuit; wherein, The first-stage operational amplifier circuit comprises two voltage input terminals and a voltage output terminal; the two voltage input terminals of the first-stage operational amplifier circuit are used to input the voltage to be compared; The second stage operational amplifier circuit is connected to the bias circuit and the voltage output terminal of the first stage operational amplifier circuit; The clamping circuit is connected to the voltage output terminal of the first-stage operational amplifier circuit, and is used to clamp the highest voltage of the voltage output terminal of the first-stage operational amplifier circuit to a preset voltage; The clamp circuit includes: a first switch tube, a second switch tube and a third switch tube; wherein, The current input terminal of the first switch tube is connected to the voltage output terminal of the first-stage operational amplifier circuit, and the control terminal of the first switch tube is connected to the current output terminal of the second switch tube and the current input terminal of the third switch tube; The control terminal of the second switch tube is connected to the bias circuit; The control end of the third switch tube is short-circuited with the current input end of the third switch tube, and the circuit output end of the third switch tube is grounded.

2. The comparator according to claim 1, characterized in that: The first-stage operational amplifier circuit includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor and a second NMOS transistor; wherein, The gate of the first PMOS tube is connected to a first voltage to be compared; The gate of the second PMOS tube is connected to the second voltage to be compared; The gate of the third PMOS tube is connected to the bias circuit, and the drain of the third PMOS tube is connected to the source of the first PMOS tube and the source of the second PMOS tube; The gate and drain of the first NMOS tube are short-circuited and connected to the drain of the first PMOS tube, and the source of the first NMOS tube is grounded; The gate of the second NMOS tube is connected to the gate of the first NMOS tube, the drain of the second NMOS tube is connected to the drain of the second PMOS tube as the voltage output terminal of the first stage operational amplifier circuit, and the source of the second NMOS tube is grounded.

3. The comparator according to claim 1, characterized in that: The second-stage operational amplifier circuit includes: a fourth PMOS tube and a third NMOS tube; wherein, The gate of the fourth PMOS tube is connected to the bias circuit; The gate of the third NMOS tube is connected to the voltage output end of the first-stage operational amplifier circuit, the drain of the third NMOS tube is connected to the drain of the fourth PMOS tube and serves as the voltage output end of the second-stage operational amplifier circuit, and the source of the third NMOS tube is grounded.

4. The comparator according to claim 1, characterized in that: The bias circuit includes: a fifth PMOS tube and a current source; wherein, The gate of the fifth PMOS tube is connected to the first-stage operational amplifier circuit and the second-stage operational amplifier circuit, and the drain of the fifth PMOS tube is connected to the current source.

5. The comparator according to claim 1, characterized in that: The first switch tube includes a PMOS tube or a PNP transistor, the second switch tube includes a PMOS tube, and the third switch tube includes an NMOS tube.

Images