Semiconductor structure and method for manufacturing the same

Abstract

The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises: a substrate, comprising an active region and a shallow trench isolation region arranged at intervals from each other; a plurality of isolation structures, located on the surface of the substrate; a plurality of grooves, located between the plurality of isolation structures, the bottom of the groove having a first inclined surface, the first inclined surface being formed in the active region; and a conductive plug, located in the groove. The embodiments of the present disclosure can avoid the formation of an air gap inside polysilicon during the manufacturing process of a storage contact plug structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure capable of avoiding the generation of air gaps and a manufacturing method thereof. Background Art

[0002] The storage node contact (SNC) is a contact structure used to connect the transistor and the storage capacitor in the DRAM structure, usually made of polysilicon. The SNC is usually connected to the substrate and STI (Shallow Trench Isolation) at the bottom, connected to metal at the top, and has sidewalls of an isolation structure, such as a bit line structure or a dielectric layer structure.

[0003] In the related art, since the bit line structure is made in advance, a dielectric layer structure is needed to be made as an isolation structure to make the other two sidewalls of the SNC trench, and polysilicon is filled in the trench to make the SNC. Since the dielectric layer sidewalls are hard and can only be made by deposition, the trenches between the dielectric layer sidewalls formed by deposition are usually trapezoidal structures (see the specification). Figure 3 ), narrow at the top and wide at the bottom, it is difficult to control the uniformity of deposition during the polysilicon deposition process, and air gaps are often formed inside the SNC, causing changes in the electrical properties of the SNC, resulting in component failures and reducing the yield rate.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The purpose of the present disclosure is to provide a semiconductor structure and a method for manufacturing the same, which are used to overcome, at least to a certain extent, the problem of air gaps inside polysilicon during the manufacturing process of a storage contact plug structure due to limitations of related technologies.

[0006] According to a first aspect of the present disclosure, there is provided a semiconductor structure, comprising:

[0007] A substrate, comprising an active region and a shallow trench isolation region that are spaced apart from each other;

[0008] A plurality of isolation structures are located on the surface of the substrate;

[0009] A plurality of grooves are located between the plurality of isolation structures, the bottom of the grooves having a first inclined surface, and the first inclined surface is formed in the active area;

[0010] A conductive plug is located in the groove.

[0011] In an exemplary embodiment of the present disclosure, the top area of ​​the groove is smaller than the bottom area.

[0012] In an exemplary embodiment of the present disclosure, the inclination angle of the first inclined surface is 30° to 40°.

[0013] In an exemplary embodiment of the present disclosure, the bottom of the groove further has a second inclined surface, and the second inclined surface is formed in the shallow trench isolation region.

[0014] In an exemplary embodiment of the present disclosure, the inclination angle of the second inclined surface is 20° to 60°.

[0015] In an exemplary embodiment of the present disclosure, the isolation structure includes a bit line structure and a dielectric layer structure.

[0016] In an exemplary embodiment of the present disclosure, the cross-section of the groove is one or more of square, polygonal, circular or elliptical.

[0017] In an exemplary embodiment of the present disclosure, the plurality of grooves are arranged in an array.

[0018] In an exemplary embodiment of the present disclosure, the first inclined surface is a curved surface.

[0019] According to one aspect of the present disclosure, there is provided a method for manufacturing a semiconductor structure, comprising:

[0020] Providing a substrate, the substrate comprising an active area and a shallow trench isolation area that are spaced apart from each other;

[0021] forming a sacrificial layer material on the surface of the substrate;

[0022] etching a portion of the sacrificial layer material to form a plurality of first grooves;

[0023] After depositing the dielectric layer on the first groove, removing the remaining sacrificial layer material to form a plurality of second grooves;

[0024] Etching downwards the exposed active region portion at the bottom of the second groove to form a first inclined surface;

[0025] Taking the first inclined surface as a base, an epitaxial silicon growth process is performed in the second groove to fill the second groove.

[0026] In an exemplary embodiment of the present disclosure, the inclination angle of the first inclined surface is 30° to 40°.

[0027] In an exemplary embodiment of the present disclosure, after etching the first inclined surface, a natural oxide removal process and / or a carbon-based residue removal process is performed on the first inclined surface.

[0028] In an exemplary embodiment of the present disclosure, etching downward a first inclined surface on the exposed portion of the bottom active area of ​​the second groove further comprises:

[0029] At the same time, the exposed portion of the shallow trench isolation structure adjacent to the exposed portion of the active area is etched to form a second inclined surface.

[0030] In an exemplary embodiment of the present disclosure, an etching selection ratio between the exposed portion of the active area and the exposed portion of the shallow trench isolation structure is 1:1.

[0031] In an exemplary embodiment of the present disclosure, sulfur hexafluoride gas is used to etch the inclined surface.

[0032] In an exemplary embodiment of the present disclosure, the epitaxial silicon growth process in the second groove includes:

[0033] The hydrochloric acid flow rate was set to 150 sccm ± 30%.

[0034] In an exemplary embodiment of the present disclosure, the epitaxial silicon growth process in the second groove includes:

[0035] After the second trench is filled, the polysilicon is removed using a wet process to leave only the single crystal silicon, and the top of the filled silicon is adjusted to be flat.

[0036] In an exemplary embodiment of the present disclosure, after filling the second groove, the method further includes:

[0037] Metal is deposited on the filled silicon surface.

[0038] The disclosed embodiment provides a slope at the exposed active area at the bottom of the groove accommodating the SNC structure, and uses the slope as a base to grow polysilicon inside the groove, so as to quickly form a storage contact plug structure without air gaps, reduce component failure rate, and improve yield rate.

[0039] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians of the skill, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0041] Figure 1 It is a schematic diagram of an arrangement of the SNC structure in an exemplary embodiment of the present disclosure.

[0042] Figure 2 is a schematic diagram of another arrangement of the SNC structure in an exemplary embodiment of the present disclosure.

[0043] Figure 3 It is a schematic diagram of the manufacturing process of the SNC structure in the related art.

[0044] Figure 4 It is a schematic diagram of a semiconductor structure in an embodiment of the present disclosure.

[0045] Figure 5 It is a flow chart of the SNC structure manufacturing method in an embodiment of the present disclosure.

[0046] Figure 6A to Figure 6D yes Figure 5 Schematic diagram of the process showing the steps.

[0047] Fig. 7A and Figure 7B It is a schematic diagram of the inclined surface morphology of the SNC structure in the embodiment of the present disclosure.

[0048] Fig. 8A and Figure 8B It is a schematic diagram of the inclined surface morphology of the cross section at another angle of the SNC structure in the embodiment of the present disclosure.

[0049] Fig.9A This is one of the schematic diagrams of the unsatisfactory effects of polysilicon growth.

[0050] Fig. 9B This is the second schematic diagram of the unsatisfactory effect of polysilicon growth.

[0051] Fig.10 is a schematic diagram of the SNC structure after the etch-back process. DETAILED DESCRIPTION

[0052] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided so that the present disclosure will be more comprehensive and complete, and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0053] In addition, the accompanying drawings are only schematic diagrams of the present disclosure, and the same reference numerals in the drawings represent the same or similar parts, so their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities, which do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0054] The exemplary embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0055] Figure 1 It is a schematic diagram of an arrangement of the SNC structure in an exemplary embodiment of the present disclosure.

[0056] Figure 1 The structure on the right is along Figure 1 The cross-sectional view of the AA position of the structure shown on the left. In the DRAM structure, the AA position is perpendicular to the bit line (BL) and parallel to the word line (WL). Figure 1 In the embodiment, a storage contact plug structure (SNC) 11 is located between the sidewalls of two bit line structures 12 at corresponding positions in two adjacent rows of word lines, and the bottom is connected to an active region 14 and a shallow trench isolation structure (STI) 13 .

[0057] Figure 2 is a schematic diagram of another arrangement of the SNC structure in an exemplary embodiment of the present disclosure.

[0058] Figure 2 The structure on the right is along Figure 2 The cross-sectional view of the BB position of the structure shown on the left. In the DRAM structure, the BB position is perpendicular to the word line (Word Line, WL) and parallel to the bit line (Bit Line, BL). The adjacent SNC structures are isolated by the isolation structure 15, and the isolation structure 15 includes a dielectric layer structure. It can be understood that Figure 2 The storage contact plug structure (SNC) 11 is still the same as Figure 1 The bottom of the active area 14 and the shallow trench isolation structure 13 are connected. It can be understood that the BB line is moved to make the cross-section position different, and the proportions of the active area 14 and the shallow trench isolation structure 13 in the cross section are different. For the sake of simplicity, the embodiment of the present disclosure only uses the following example. Figure 2 The region positions and proportions are shown, but the present disclosure is not limited thereto.

[0059] Figure 3 It is a schematic diagram of the manufacturing process of the SNC structure in the related art.

[0060] refer to Figure 3Since the isolation structure between SNCs includes a bit line structure and a dielectric layer sidewall, the dielectric layer sidewall needs to be formed when manufacturing the groove to accommodate the SNC structure. However, since the dielectric layer sidewall is usually hard and difficult to form by etching, the related technology is often Figure 2 In the BB direction shown in the figure, a trench is made by etching a sacrificial layer material 31 (usually an oxide, such as silicon dioxide, BPSG, BSG, etc.) (as shown in a), and a dielectric layer structure 15 is made by deposition technology (as shown in b); then, the remaining sacrificial layer material 31 is removed (as shown in c), and polysilicon is deposited between the dielectric layer structures 15 to make the SNC structure 11 (as shown in d). It can be understood that there are isolation structures including bit line structures in front and behind the viewing direction in the figure (as shown in Figure 1 The isolation structure 12 on the right side, including the bit line structure, is usually formed before the dielectric layer structure 15 is formed. In this technology, since the sacrificial layer material is etched in step a, the cross section of the remaining sacrificial layer material is a trapezoid, that is, the SNC structure finally manufactured is also a trapezoidal cross section that is narrow at the top and wide at the bottom, making it difficult to complete good polysilicon deposition, and often resulting in air gaps in the SNC structure (such as d).

[0061] To this end, the embodiments of the present disclosure provide a semiconductor structure capable of avoiding the generation of air gaps in the SNC structure.

[0062] Figure 4 is a schematic diagram of a semiconductor structure in an embodiment of the present disclosure.

[0063] It should be noted that Figure 4 It is along Figure 2 The cross-sectional view of the structure at the BB position shown on the left side shows that there are isolation structures including bit line structures in front and behind the viewing direction of the figure (such as Figure 1 Isolation structure 12 on the right).

[0064] refer to Figure 4 , the semiconductor structure 400 may include:

[0065] The substrate 41 includes an active region 14 and a shallow trench isolation region 13 which are arranged in an interval manner.

[0066] An isolation structure 15, located on the surface of the substrate 41;

[0067] A plurality of grooves 42 are located in the isolation structure 15 , and the bottom of the grooves 42 has a first inclined surface 43 , and the first inclined surface 43 is formed in the active area 14 ;

[0068] The conductive plug 11 is located in the groove 42 .

[0069] Among them, due to Figure 4 yes Figure 2 The cross-sectional view along the BB direction, Figure 4 The isolation structure 15 marked in the figure is actually a dielectric layer structure, that is, Figure 2 The isolation structure 15 on the right side, but those skilled in the art can understand that the isolation structure 15 of the embodiment of the present disclosure also includes Figure 1 The bit line structure 12 shown in FIG. Figure 4 That is, the isolation structure 15 of the embodiment of the present disclosure includes four sidewall structures such as two adjacent bit line structures and two adjacent dielectric layer structures to achieve surrounding and isolation of the groove 42 .

[0070] exist Figure 4 In the illustrated embodiment, the top area of ​​the groove 42 is smaller than the bottom area, and the cross section is one or more of square, polygonal, circular or elliptical. The plurality of grooves 42 are arranged in an array, and the array may be an aligned or misaligned dot array. It is understood that, since two of the opposite sidewalls of the groove 42 are formed by an isolation structure including a bit line structure, and the bit line structure is perpendicular to the substrate, the length of the top surface of the groove 42 may be equal to the length of the bottom surface, or the width of the top surface of the groove 42 may be equal to the width of the bottom surface, and the present disclosure does not impose any special restrictions on this.

[0071] In one embodiment of the present disclosure, the inclination angle of the first inclined surface 43 may be, for example, 30° to 40°. Of course, there may be another region on the active area 14, the slope of the other region is different from the slope of the first inclined surface, for example, a horizontal region (e.g. Figure 1 The bottom shape of the SNC structure 11 in the right structure), in another embodiment of the present disclosure, the first inclined surface 43 may also be a curved surface formed by an etching process, and the present disclosure does not make any special limitation on this.

[0072] Figure 5 yes Figure 4 A flow chart of a method for manufacturing a semiconductor structure is shown.

[0073] refer to Figure 5 , a method 500 for manufacturing a semiconductor structure may include:

[0074] Step S1, providing a substrate, wherein the substrate includes an active area and a shallow trench isolation area arranged at intervals from each other, and forming a sacrificial layer material on the surface of the substrate;

[0075] Step S2, etching a portion of the sacrificial layer material to form a plurality of first grooves;

[0076] Step S3, after depositing the dielectric layer in the first groove, removing the remaining sacrificial layer material to form a plurality of second grooves;

[0077] Step S4, etching downward the exposed active area portion at the bottom of the second groove to form a first inclined surface;

[0078] Step S5, using the first inclined surface as a base, performing an epitaxial silicon growth process in the second groove to fill the second groove.

[0079] Among them, in the embodiment of the present disclosure, the sacrificial layer is, for example, an oxide layer, including but not limited to oxide (such as silicon dioxide), BPSG, BSG and other materials. The first groove is, for example, an inverted trapezoidal groove that is wide at the top and narrow at the bottom, and the second groove is, for example, a trapezoidal groove that is narrow at the bottom and wide at the top. It should be understood by those skilled in the art that a non-inverted trapezoidal first groove can also be formed here, and the specific shape is determined by factors such as the process means and process conditions adopted; the second groove can also be a non-trapezoidal groove, and the specific shape formed is related to the shape of the first groove.

[0080] Figure 6A to Figure 6D yes Figure 5 Schematic diagram of the process showing the steps.

[0081] and Figure 2 and Figure 4 To simplify the description, Figure 6A to Figure 6D The positions and proportions of the active area and shallow trench isolation area in the figure are for illustration only and are not used to limit the positions and proportions of the active area and shallow trench isolation area in the actual process.

[0082] refer to Fig. 6A ,and Figure 3 The same as step (a) in the above embodiment, the first groove 45 is also etched on the sacrificial layer 44 to prepare for the subsequent manufacturing of the isolation structure. The bottom of the first groove 45 exposes the active area 14 and the shallow trench isolation area 13 at the same time. Since the bit line structure located in the front or rear of the viewing direction of the figure is usually formed at this time, Fig. 6A The steps shown are actually to fill a sacrificial layer between the bit line structures and then etch a first groove 45 in the sacrificial layer, that is, the front and rear side walls of the first groove 45 in the viewing direction are vertical and are formed by an isolation structure including the bit line structure.

[0083] refer to Figure 6B ,and Figure 3 The same as step (b) in the above embodiment, the isolation structure 15 is also manufactured by depositing a dielectric layer, and the material of the dielectric layer is, for example, silicon nitride.

[0084] refer to Figure 6C ,and Figure 3 The same as step (c) in the embodiment of the present disclosure is that the sacrificial layer 44 is also removed to create space for the manufacture of the SNC, forming a second groove 42, and the bottom of the second groove 42 exposes both the active area 14 and the shallow trench isolation area 13. It should be noted that Figure 2It can be seen that the ratio of the active area and the shallow trench isolation area exposed at the bottom of the second groove 42 is actually different when the cross-section position is different (i.e., the BB line moves horizontally). Therefore, although the embodiment of the present disclosure only shows one exposure state of the active area and the shallow trench isolation area, in actual applications, the exposure state of the active area and the shallow trench isolation area can also be multiple.

[0085] refer to Fig.6D The embodiment of the present disclosure is to manufacture SNC by epitaxial silicon growth process. Therefore, in order to smoothly carry out the epitaxial silicon growth process, the bottom of the second groove 42 is processed, that is, a first inclined surface 43 is manufactured at the bottom of the second groove 42 by dry etching or wet etching. In order to manufacture SNC, the bottom of the second groove 42 exposes both the active area and the shallow trench isolation area (refer to Figure 2 The material of the active area is usually single crystal silicon, and the material of the shallow trench isolation area is usually oxide (for example, silicon dioxide). The two provide completely different environments for the growth of epitaxial silicon. In the embodiment of the present disclosure, during this process, single crystal silicon usually grows only on one side of the single crystal silicon, and it is difficult to grow on the silicon dioxide side, or it grows at a very slow speed. Therefore, in order to provide more crystal directions for the growth of single crystal silicon and make the growth of single crystal silicon more uniform and faster, the first bevel 43 is manufactured in the embodiment of the present disclosure before the epitaxial silicon growth process.

[0086] In an exemplary embodiment of the present disclosure, the gas used to etch the first inclined surface 43 may be, for example, sulfur hexafluoride (SF6), and the first inclined surface 43 with an inclination angle of 30° to 40° may be etched by controlling the parameters such as the bias voltage (Bias) and the flow (Flow) of the etching gas. It should be noted that the etching process often cannot guarantee the etching of a perfect plane, so in the actual process, the first inclined surface 43 may also be a curved surface formed by the etching process, and the shape of the curved surface may refer to Fig. 7A In addition, in some embodiments, the active area may also have other regions, such as a plane, that is, the end point of the first inclined surface 43 formed by etching does not coincide with the edge of the active area. At this time, the state of the active area can refer to Figure 7B shown.

[0087] In addition, since the shallow trench isolation area is connected to the active area, when etching the bevel on the exposed part of the active area, it is easy to etch the exposed part of the shallow trench isolation area at the same time. At this time, the etching selectivity can be controlled to a value such as 1:1 to form a second bevel 46, and the inclination angle of the second bevel 46 is, for example, 20° to 60°. Of course, relevant technical personnel in this field should understand that due to process deviations or the selectivity ratio is not 1:1, there will be a difference in the height of the shallow trench isolation area and the active area after etching, but in order to prevent the height of the shallow trench isolation area and the active area from differing too much, the etching selectivity ratio should not differ too much, so as to avoid the generation of air gaps during the epitaxial silicon growth process. Similar to the formation of the first bevel 43, the second bevel 46 can also be a curved surface, or the edge of the second bevel 46 does not overlap with the edge of the shallow trench isolation area. These two states can be respectively referred to. Fig. 7A and Figure 7B .

[0088] It can be understood that the etching process is performed on the entire exposed portion of the active area and the entire exposed portion of the shallow trench isolation area. Therefore, the slope at the bottom of the second groove 42 is actually similar to an upright bowl. Figure 1 From the cross section in the AA direction, Figure 2 From the cross section along the BB direction, the bottom of the second groove 42 has an inclined surface.

[0089] You can refer to Figure 8A to Figure 8B ,from Figure 1 From the cross section along the AA direction on the left side, the ratio of the active area 14 and the shallow trench isolation area 13 may be different, and the slopes may be different.

[0090] To avoid residual impurities (natural oxide layer, etching residue) ( Fig.6D 43 or 46 in the figure) affects the electrical properties of the bevel and may even cause the failure of single crystal silicon growth. In some embodiments of the present disclosure, the first bevel 43 can also be cleaned in situ by dry cleaning of oxides, dry cleaning to remove carbon-based residues, etc., to ensure the purity of the single crystal silicon interface and obtain high-quality growth effects.

[0091] After the in-situ cleaning, single crystal silicon can be grown with the inclined surface as the base until the epitaxial silicon is controlled to fill the entire second groove 42 to form a Figure 4 The conductive plug 11 is shown. In some embodiments, the conductive plug 11 is a storage contact plug structure (SNC). Figure 1 On the right, from the AA position section, Figure 1 The lower portion of the conductive plug 11 (ie, the SNC structure 11 ) shown on the right side also has an inclined surface.

[0092] It should be noted that since the appearance of the grown single crystal silicon is often not ideal (as shown in Figure 7), in another embodiment of the present disclosure, the selectivity of polysilicon growth can be reduced in step S4 while increasing the growth rate. For example, the growth selectivity can be reduced by setting a suitable hydrochloric acid flow rate. The preferred hydrochloric acid concentration is, for example, 150sccm±30%. An increase in the hydrochloric acid flow rate will inhibit the growth of polycrystalline and tend to grow on the surface of the single crystal; a decrease in the hydrochloric acid flow rate will increase the growth rate of polycrystalline silicon and increase production. Therefore, in order to ensure the quality of the single crystal and increase production, it is necessary to find the most suitable hydrochloric acid flow rate range, so the above range is set in the embodiment of the present disclosure.

[0093] In addition, since single crystal silicon and polycrystalline silicon may grow simultaneously, the shape is not easy to control, such as Fig.9A or Fig. 9B At this point, the polysilicon can be removed by a wet process such as a Recess Etch method to leave only the single crystal silicon, and the shape of the top of the single crystal silicon is trimmed to a roughly flat surface (such as Fig.10 As shown), adjust the length of the conductive plug for subsequent metal connection process.

[0094] In one embodiment, the conductive plug is a storage contact plug. After forming the storage contact plug, a metal capacitor landing pad can be formed on the storage contact plug for subsequent manufacturing of capacitors on the interface platform. Since connecting a metal landing pad on the storage contact plug belongs to the manufacture of a metal-semiconductor contact structure, in another embodiment of the present disclosure, after filling the second groove, metal can also be deposited on the surface of the conductive plug 11.

[0095] At this time, the landing pad is in contact with the single crystal silicon, which is the same as the contact between the source and drain of the transistor in the peripheral circuit area, that is, metal is in contact with the single crystal silicon. The metallization process is implemented at the same time, and the optimal process conditions can be achieved at the same time, which can make the process conditions requirements simpler, improve the performance of the contact structure, and make the contact resistance between the metal and the single crystal silicon smaller under the condition of lower manufacturing cost.

[0096] In summary, the embodiments of the present disclosure grow single crystal silicon at the bottom of the groove to manufacture a storage contact plug structure (SNC structure) that fills the groove, thereby avoiding the appearance of air gaps and reduced electrical performance in the SNC structure caused by the deposition of polycrystalline silicon in the related technology; in addition, by manufacturing a single crystal silicon bevel at the bottom of the groove and growing single crystal silicon on the single crystal silicon bevel, the problems of uneven growth and low growth rate caused by the single crystal silicon growth process can be avoided, thereby effectively improving the manufacturing efficiency while improving the yield rate.

[0097] It should be noted that, although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into multiple modules or units to be embodied.

[0098] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are to be considered exemplary only, and the true scope and concept of the present disclosure are indicated by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, comprising an active region and a shallow trench isolation region that are spaced apart from each other; A plurality of isolation structures are located on the surface of the substrate; A plurality of grooves are located between the plurality of isolation structures, the bottom of the grooves having a first inclined surface, the first inclined surface is formed in the active area, wherein the top area of ​​the grooves is smaller than the bottom area; The conductive plug is located in the groove, and the conductive plug is formed by filling the groove through an epitaxial silicon growth process.

2. The semiconductor structure according to claim 1, wherein: The inclination angle of the first inclined surface is 30°~40°.

3. The semiconductor structure according to claim 1, wherein: The bottom of the groove also has a second inclined surface, and the second inclined surface is formed in the shallow trench isolation region.

4. The semiconductor structure according to claim 3, characterized in that The inclination angle of the second inclined surface is 20°~60°.

5. The semiconductor structure according to claim 1, wherein: The isolation structure includes a bit line structure and a dielectric layer structure.

6. The semiconductor structure according to claim 1, wherein: The cross section of the groove is one or more of square, polygonal, circular or elliptical.

7. The semiconductor structure according to claim 6, wherein: The plurality of grooves are arranged in an array.

8. The semiconductor structure according to claim 1, wherein: The first inclined surface is a curved surface.

9. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising an active area and a shallow trench isolation area that are spaced apart from each other; forming a sacrificial layer material on the surface of the substrate; etching a portion of the sacrificial layer material to form a plurality of first grooves; After depositing the dielectric layer on the first groove, removing the remaining sacrificial layer material to form a plurality of second grooves; Etching downwards the exposed active region portion at the bottom of the second groove to form a first inclined surface; Taking the first inclined surface as a base, an epitaxial silicon growth process is performed in the second groove to fill the second groove, and the top area of ​​the second groove is smaller than the bottom area.

10. The manufacturing method according to claim 9, characterized in that: The inclination angle of the first inclined surface is 30°~40°.

11. The manufacturing method according to claim 9, characterized in that: The step of etching downward the first inclined surface of the exposed portion of the bottom active area of ​​the second groove further comprises: At the same time, the exposed portion of the shallow trench isolation structure adjacent to the exposed portion of the active area is etched to form a second inclined surface.

12. The manufacturing method according to claim 11, characterized in that: The etching selection ratio of the exposed portion of the active area and the exposed portion of the shallow trench isolation structure is 1:

1.

13. The manufacturing method according to claim 9, characterized in that: The epitaxial silicon growth process in the second groove includes: Set the hydrochloric acid flow rate to 150 sccm ± 30%.

14. The manufacturing method according to claim 9, characterized in that: The epitaxial silicon growth process in the second groove includes: After the second trench is filled, the polysilicon is removed using a wet process to leave only the single crystal silicon, and the top of the filled silicon is adjusted to be flat.

15. The manufacturing method according to claim 9, characterized in that: After filling the second groove, the method further comprises: Metal is deposited on the filled silicon surface.

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