Electronic component embedded substrate

Abstract

The present invention provides an electronic component embedded substrate, which includes a core substrate, an electronic component, a first insulating material and a third wiring layer, wherein the core substrate includes: an insulating body having a first surface and a second surface opposite to the first surface; a first wiring layer embedded in the insulating body so that one surface of the first wiring layer is exposed from the first surface; and a second wiring layer arranged on the insulating body to protrude on the second surface, the core substrate having a cavity, the cavity penetrating a portion of the insulating body from the first surface toward the second surface, and the cavity having a barrier layer as its bottom surface, the electronic component being arranged on the barrier layer in the cavity, the first insulating material covering at least a portion of each of the core substrate and the electronic component, and the third wiring layer being arranged on the first insulating material.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2019-0164454 filed on December 11, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to an electronic component embedded substrate. Background Art

[0003] With the advent of the fifth generation (5G) era, the number of components to be mounted on the main board of a smartphone is increasing. In addition, while maintaining compatibility with 4G LTE communications, it may be necessary to secure space in which components such as antennas, baseband modems, etc. for 5G communications are mounted. Therefore, in addition to the miniaturization of each component, miniaturization by modularizing the current components in the form of a system-in-package (SiP) will also be considered. Summary of the invention

[0004] An aspect of the present disclosure is to provide an electronic component embedded substrate capable of reducing warpage even in an asymmetric structure.

[0005] Another aspect of the present disclosure is to provide an electronic component embedded substrate that can be modularized and miniaturized in the form of a SiP.

[0006] According to an aspect of the present disclosure, an electronic component embedded substrate using a coreless substrate having a vertical inverted form as a core substrate is implemented.

[0007] According to another aspect of the present disclosure, a modular structure is introduced by mounting components on an electronic component embedded substrate.

[0008] For example, according to one aspect of the present disclosure, an electronic component embedded substrate may include a core substrate, an electronic component, a first insulating material and a third wiring layer, the core substrate including: an insulating body having a first surface and a second surface opposite to the first surface; a first wiring layer embedded in the insulating body so that one surface of the first wiring layer is exposed from the first surface; and a second wiring layer arranged on the insulating body to protrude on the second surface, the core substrate having a cavity, the cavity penetrating a portion of the insulating body from the first surface toward the second surface, and the cavity having a barrier layer as its bottom surface, the electronic component being arranged on the barrier layer in the cavity, the first insulating material covering at least a portion of each of the core substrate and the electronic component, and the third wiring layer being arranged on the first insulating material.

[0009] For example, a substrate according to one aspect of the present disclosure may include: a first insulating layer; a first wiring layer embedded in the first insulating layer and exposed from the upper surface of the first insulating layer; a second insulating layer having a thickness smaller than that of the first insulating layer and disposed on the lower surface of the first insulating layer; a second wiring layer embedded in the second insulating layer and in contact with the first insulating layer; a barrier layer including a first portion and a second portion, the first portion being in contact with the first insulating layer and the second insulating layer, the second portion extending from the first portion and exposed from the first insulating layer through a cavity; an electronic component disposed on the barrier layer in the cavity; an insulating material covering a portion of each of the first insulating layer and the electronic component; and a first connection via disposed in the first insulating layer and connecting the first wiring layer and the second wiring layer to each other. The width of the cross section of the first connection via may be gradually narrowed in a direction from the second insulating layer to the first insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a schematic block diagram illustrating an example of an electronic device system;

[0012] Figure 2 is a schematic perspective view showing an example of an electronic device;

[0013] Figure 3 is a schematic cross-sectional view showing an example of an electronic component embedded substrate;

[0014] Figure 4 is along Figure 3 A schematic cross-sectional view of an electronic component embedded substrate taken along line II′;

[0015] Figures 5 to 8 It shows the manufacturing Figure 3 Schematic process diagram of an example of an electronic component embedded substrate. DETAILED DESCRIPTION

[0016] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the accompanying drawings, the shapes, sizes, etc. of elements may be exaggerated or simplified for clear description.

[0017] Figure 1 is a schematic block diagram illustrating an example of an electronic device system.

[0018] Reference Figure 1, the electronic device 1000 may house a mainboard 1010 therein. The mainboard 1010 may include chip-related components 1020, network-related components 1030, other components 1040, etc., which are physically or electrically connected thereto. These components may be connected to other components to be described below through various signal lines 1090.

[0019] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, etc.; application processor chips, such as central processing units (e.g., central processing units (CPU)), graphics processors (e.g., graphics processing units (GPU)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, the chip-related components 1020 are not limited thereto, but may also include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other.

[0020] The network-related components 1030 may include components operating based on protocols such as Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 family, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution Data Only (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Enhanced Data GSM Environment (EDGE), Global System for Mobile Communications (GSM), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, 3G protocols, 4G protocols, and 5G protocols, as well as any other wireless protocols and wired protocols specified after the above protocols. However, the network-related components 1030 are not limited thereto, but may also include components operating based on various other wireless standards or protocols or wired standards or protocols. Furthermore, the network-related component 1030 may be combined with the above-mentioned chip-related component 1020 .

[0021] The other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramics (LTCC), electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, the other components 1040 are not limited thereto, but may also include passive components for various other purposes, etc. In addition, the other components 1040 may be combined with each other together with the above-mentioned chip-related components 1020 or the network-related components 1030.

[0022] Depending on the type of the electronic device 1000, the electronic device 1000 may include other components that may or may not be physically or electrically connected to the main board 1010. For example, these other components may include a camera 1050, an antenna 1060, a display 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown), a compass (not shown), an accelerometer (not shown), a gyroscope (not shown), a speaker (not shown), a mass storage unit (e.g., a hard disk drive) (not shown), a compact disk (CD) drive (not shown), a digital versatile disk (DVD) drive (not shown), etc. However, these other components are not limited thereto, but may also include other components for various purposes, etc., according to the type of the electronic device 1000, etc.

[0023] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automotive component, etc. However, the electronic device 1000 is not limited thereto and may be any other electronic device that processes data.

[0024] Figure 2 is a schematic perspective view showing an example of an electronic device.

[0025] Reference Figure 2 , the electronic device may be, for example, a smart phone 1100. A mainboard 1110 may be housed in the smart phone 1100, and various electronic components 1120 may be physically and / or electrically connected to the mainboard 1110. In addition, other components (such as a camera module 1130 and / or a speaker 1140) that may or may not be physically or electrically connected to the mainboard 1110 may be housed in the mainboard 1110. A portion of the electronic component 1120 may be a chip-related component, such as a semiconductor package 1121, but is not limited thereto. The semiconductor package 1121 may be a surface-mounted type, such as a semiconductor chip or a passive component on a package board of a multi-layer printed circuit board, but is not limited thereto. In addition, the electronic device is not necessarily limited to the smart phone 1100, but may be other electronic devices as described above.

[0026] Figure 3 is a schematic cross-sectional view showing an example of an electronic component embedded substrate.

[0027] Figure 4 is along Figure 3 Schematic cross-sectional view of the electronic component embedded substrate taken along line II′.

[0028] Reference Figure 3 and Figure 4 , the electronic component embedded substrate 100 according to an example may include a core substrate 110 , an electronic component 120 , insulating materials 130 and 140 , wiring layers 132 and 142 , connection via layers 133 and 143 , passivation layers 150 and 160 , and electrical connection metal bumps 170 . The core substrate 110 may include: a first insulating layer 111a; a first wiring layer 112a embedded in the first insulating layer 111a so that the upper surface of the first wiring layer 112a is exposed from the upper surface of the first insulating layer 111a; a second wiring layer 112b arranged to protrude on the lower surface of the first insulating layer 111a; a first connection via layer 113a penetrating the first insulating layer 111a and connecting the first wiring layer 112a and the second wiring layer 112b; a second insulating layer 111b arranged on the lower surface of the first insulating layer 111a and burying the second wiring layer 112b; a third wiring layer 112c arranged to protrude on the lower surface of the second insulating layer 111b; and a second connection via layer 113b penetrating the second insulating layer 111b and connecting the second wiring layer 112b and the third wiring layer 112c. The core substrate 110 may have a cavity 110H penetrating the first insulating layer 111a without penetrating the second insulating layer 111b. The cavity 110H may have a barrier layer 115 as a bottom surface thereof. The first insulating layer 111 a and the second insulating layer 111 b may be provided as an insulating body of the core substrate 110 .

[0029] The electronic component 120 may be disposed on the barrier layer 115 in the cavity 110H. The first insulating material 130 may cover at least a portion of each of the core substrate 110 and the electronic component 120. The fourth wiring layer 132 may be disposed on the first insulating material 130. The second insulating material 140 may be disposed on the first insulating material 130 to bury the fourth wiring layer 132. The fifth wiring layer 142 may be disposed on the second insulating material 140. The first passivation layer 150 may be disposed on the lower surface of the second insulating layer 111b and have a plurality of first openings that expose a portion of the third wiring layer 112c. The second passivation layer 160 may be disposed on the upper surface of the second insulating material 140 and may have a plurality of second openings that expose a portion of the fifth wiring layer 142. The electrical connection metal bumps 170 may be respectively disposed on the first openings of the first passivation layer 150 and may be respectively connected to the exposed third wiring layer 112c (i.e., connected to the exposed portion of the third wiring layer 112c).

[0030] As described above, with the advent of the 5G era, the number of components to be installed on the motherboard of a smartphone increases. In addition, while maintaining compatibility with the current 4G LTE communication, it is necessary to ensure space for installing additional components such as antennas and baseband modems for 5G communication to the motherboard. Therefore, in addition to the miniaturization of each component, miniaturization by modularizing the current components in the form of SiP is also considered. As a structure for SiP modularization, for example, it is possible to consider manufacturing a single module by mounting passive components on a substrate with an IC embedded therein. In this case, as a structure for embedding the IC into the substrate, for example, the following structure can be considered: manufacturing a four-layer core substrate, forming a non-penetrating cavity in a portion of the layer of the four-layer core substrate, and forming an insulating layer and a circuit layer only after the IC is embedded.

[0031] However, when manufacturing an electronic component embedded substrate through a core substrate having such a non-penetrating cavity, an insulating layer may be formed only on one side of the core substrate, and stress may be continuously accumulated only on the upper part of the substrate due to the solidification shrinkage of the raw material itself. In this case, a carrier used as a reinforcing material may be attached to the lower part of the core substrate to suppress the warpage generated during the process to a certain extent, but when the carrier is desorbed during the completion of the manufacturing process, stress may occur, resulting in smiley-face-shaped warpage.

[0032] On the other hand, the electronic component embedded substrate 100 according to the example may use a coreless substrate having a vertical inverted form as the core substrate 110. For example, the core substrate 110 may have a multilayer substrate form in which the second insulating layer 111b is formed on the first insulating layer 111a for stacking, and in this case, the core substrate 110 may be arranged so that the first wiring layer 112a having the embedded pattern faces upward. In this case, warping may occur in the opposite direction to the direction in which the first wiring layer 112a is embedded. When the core substrate 110 is used to embed the electronic component 120, even if the insulating layer is formed only on one side after the electronic component 120 is embedded, the stress can be offset as a result, and the warping can be reduced in terms of the finished product. Stress offset will be described with reference to the manufacturing process described later.

[0033] Hereinafter, each configuration included in the electronic component embedded substrate 100 according to examples will be described in more detail with reference to the accompanying drawings.

[0034] The core substrate 110 can also improve the rigidity of the electronic component embedded substrate 100 according to the specific material, and can be used to ensure the thickness uniformity of the first insulating material 130. In addition, since the core substrate 110 includes a first wiring layer 112a, a second wiring layer 112b, and a third wiring layer 112c, as well as a first connection via layer 113a and a second connection via layer 113b, various circuit designs are feasible, and upper and lower electrical connection paths can also be provided. In addition, the core substrate 110 may include a third wiring layer 112c disposed at a height lower than the ineffective surface of the electronic component 120, thereby easily providing a backside wiring layer. The core substrate 110 can be formed into a multilayer structure other than that shown in the accompanying drawings. For example, the required number of layers of insulating layers, wiring layers, and connection via layers can also be set below the second insulating layer 111b.

[0035] The core substrate 110 may have a cavity 110H, wherein the barrier layer 115 is disposed on the bottom surface of the cavity 110H. The cavity 110H may be formed to penetrate the first insulating layer 111a from the upper surface of the first insulating layer 111a toward the lower surface of the first insulating layer 111a. The depth of the cavity 110H may vary according to the position of the barrier layer 115. For example, in the example, the cavity 110H may not penetrate the second insulating layer 111b. The cavity 110H may have a tapered profile in which the width of the cross section of the cavity 110H narrows from the upper side to the lower side thereof, but is not limited thereto.

[0036] Insulating materials may be used as materials for the first insulating layers 111a and 111b, respectively. In this case, an insulating material of copper-clad resin (RCC) may be used as the insulating material. However, the present disclosure is not limited thereto, and in addition thereto, for example, a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as a polyimide resin), an insulating material in which a thermosetting resin or a thermoplastic resin is impregnated with an inorganic filler and / or glass fiber (or glass cloth or glass fabric) in a core material (such as a prepreg, ABF (Ajinomoto build-up film), FR-4, bismaleimide triazine (BT), etc.) may be used. When a material having high rigidity (such as a prepreg including glass fiber) is used, warping may be effectively controlled. The first insulating layer 111a may be thicker than the second insulating layer 111b. The first insulating layer 111a and the second insulating layer 111b may include the same material, or may include different materials. The boundary of the first insulating layer 111 a and the second insulating layer 111 b may be clear, or the first insulating layer 111 a and the second insulating layer 111 b may be integrated so that it is difficult to distinguish the boundary therebetween.

[0037] The first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c may include a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c may perform various functions according to the design. For example, the first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. Here, the signal (S) pattern may include various signal patterns (such as data signal patterns, etc.) in addition to the ground (GND) pattern, the power (PWR) pattern, etc. These patterns may have a line shape, a surface shape, or a pad shape. The first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c may be formed by a plating process such as an additive process (AP), a semi-AP (SAP), a modified SAP (MSAP), a TT (tenting) process, etc. Therefore, the first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c may include a seed layer (non-electroplating layer) and an electroplating layer formed based on the seed layer, respectively. The upper surface of the first wiring layer 112a may have a step h2 relative to the upper surface of the first insulating layer 111a. For example, the upper surface of the first wiring layer 112a may be located at a height lower than the upper surface of the first insulating layer 111a.

[0038] The first connection via layer 113a and the second connection via layer 113b may penetrate the first insulating layer 111a and the second insulating layer 111b, respectively, and connect the first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c. The first connection via layer 113a and the second connection via layer 113b may also include a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The first connection via layer 113a and the second connection via layer 113b may include a signal connection via, a ground connection via, a power connection via, etc., respectively, according to the design. The connection vias of the first connection via layer 113a and the second connection via layer 113b may be completely filled with a metal material, respectively, or the metal material may be formed along the wall surface of the via hole. In the first connection via layer 113a, since a portion of the first wiring layer 112a is used as a barrier for forming a via hole, each of the connection vias in the first connection via layer 113a may have a tapered profile in which the width of its cross section widens from its upper surface to its lower surface. In the second connection via layer 113b, since a portion of the second wiring layer 112b is used as a barrier for forming a via hole, each of the connection vias in the second connection via layer 113b may have a tapered profile in which the width of its cross section widens from its upper surface to its lower surface. The first connection via layer 113a and the second connection via layer 113b may also be formed by a plating process, for example, a process such as AP, SAP, MSAP, TT, etc., and therefore, the first connection via layer 113a and the second connection via layer 113b may include a seed layer (non-electroplating layer) and an electroplating layer formed based on the seed layer. The first connection via layer 113a may be simultaneously formed by the same plating process as the second wiring layer 112b, and may be integrated with the second wiring layer 112b without a boundary. The second connection via layer 113b may be simultaneously formed by the same plating process as the third wiring layer 112c, and may be integrated with the third wiring layer 112c without a boundary.

[0039] The barrier layer 115 may be disposed on the lower surface of the first insulating layer 111a and may be covered by the second insulating layer 111b. The barrier layer 115 may be formed by a plating process, for example, a process such as AP, SAP, MSAP, TT, etc., and therefore, the barrier layer 115 may include a seed layer (electroless plating layer) and an electroplating layer formed based on the seed layer. The barrier layer 115 may be formed simultaneously by a plating process that is the same as the plating process of the second wiring layer 112b, and therefore may be disposed at the same height as the second wiring layer 112b, and may include the same metal material as the second wiring layer 122b, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, etc. The barrier layer 115 may have a central region exposed from the first insulating layer 111a through the cavity 110H and an edge region surrounding the central region and covered by the first insulating layer 111a. For example, the edge region contacts the first insulating layer 111a and the second insulating layer 111b, and the central region extends from the edge region and is exposed from the first insulating layer 111a through the cavity 110H. The central region may be partially removed in the process of forming the cavity 110H, so the central region may be thinner than the edge region. That is, the central region may have a step h1 relative to the edge region.

[0040] The electronic component 120 may be disposed in the cavity 110H. The back of the electronic component 120 may be attached to the barrier layer 115 by a known adhesive 125, such as a die attach film (DAF). The electronic component 120 may be constructed as an IC in which hundreds to millions or more devices are integrated in a single chip. For example, the electronic component 120 may be implemented by a processor chip such as a central processing unit (CPU), a graphics processor (GPU), a field programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, etc., and specifically, may be implemented by an application processor (AP), but its embodiments are not limited thereto. The electronic component 120 may also be implemented by a memory such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), a flash memory, etc., or a logic chip such as an application specific IC (ASIC). In addition, the electronic component 120 may also be constructed as a chip-type passive component.

[0041] The electronic component 120 may be formed based on an effective wafer. Silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. may be used as the base material of the main body of the electronic component 120. Various circuits may be formed in the main body. The connection pad 120P may be arranged on the effective surface of the main body. The connection pad 120P may be configured to electrically connect the electronic component 120 to other components, and conductive materials such as copper (Cu), aluminum (Al), etc. may be used as materials for forming the connection pad 120P of the electronic component 120 without specific restrictions. A passivation film for covering at least a portion of the connection pad 120P and exposing at least a portion of the connection pad 120P may be arranged on the effective surface of the main body. The passivation film may be configured as an oxide film or a nitride film, or may be configured as a double layer including an oxide film and a nitride film. An insulating film, etc. may also be arranged at a desired position. The electronic component 120 may be configured as a bare chip, but its embodiment is not limited thereto. The electronic component 120 may also be configured as a packaged bare chip.

[0042] The first insulating material 130 and the second insulating material 140 may be sequentially laminated on the core substrate 110 and the electronic component 120. The first insulating material 130 may cover at least a portion of each of the core substrate 110 and the electronic component 120. In addition, the first insulating material 130 may fill at least a portion of the cavity 110H. The materials of the first insulating material 130 and the second insulating material 140 are not specifically limited. For example, an insulating material may be used, in which case, for example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, an insulating material in which a thermosetting resin or a thermoplastic resin is mixed with an inorganic filler or impregnated with an inorganic filler and / or glass fiber (or glass cloth or glass fabric) in a core material (such as a prepreg, ABF (Ajinomoto build-up film), FR-4, bismaleimide triazine (BT), etc.) may be used as the insulating material. If desired, a photosensitive encapsulant (PIE) resin may be used as the first insulating material 130 and the second insulating material 140. The first insulating material 130 and the second insulating material 140 may include the same material as each other, or may include different materials. The boundary between the first insulating material 130 and the second insulating material 140 may be clear, or the first insulating material 130 and the second insulating material 140 may be integrated so that it is difficult to distinguish the boundary between them. If necessary, an insulating material may also be formed on the second insulating material 140, in which case a wiring layer and a connection via layer (described later) may be further formed according to the number of additional insulating materials formed. If necessary, the second insulating material 140 may be omitted, and in this case, the fifth wiring layer 142 and the fourth connection via layer 143 (described later) may also be omitted.

[0043] The fourth wiring layer 132 and the fifth wiring layer 142 may include metal materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or alloys thereof. The fourth wiring layer 132 and the fifth wiring layer 142 may perform various functions according to the design. For example, the fourth wiring layer 132 and the fifth wiring layer 142 may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. Here, the signal (S) pattern may include various signal patterns (e.g., data signal patterns, etc.) in addition to the ground (GND) pattern, the power (PWR) pattern, etc. These patterns may have a line shape, a surface shape, or a pad shape. The fourth wiring layer 132 and the fifth wiring layer 142 may also be formed by a plating process such as AP, SAP, MSAP, TT, etc., and therefore, the fourth wiring layer 132 and the fifth wiring layer 142 may include a seed layer (electroless plating layer) and an electroplating layer formed based on the seed layer.

[0044] The third connection via layer 133 and the fourth connection via layer 143 may penetrate the first insulating material and the second insulating material, respectively. The third connection via layer 133 may connect the fourth wiring layer 132 to the connection pad 120P of the electronic component 120. In addition, the third connection via layer 133 may connect the first wiring layer 112a and the fourth wiring layer 132. The fourth connection via layer 143 may connect the fourth wiring layer 132 and the fifth wiring layer 142. The third connection via layer 133 and the fourth connection via layer 143 may also include metal materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), their alloys, etc. The third connection via layer 133 and the fourth connection via layer 143 may also include signal connection vias, ground connection vias, power connection vias, etc. according to the design. The third connection via layer 133 and the fourth connection via layer 143 may be completely filled with metal materials, or the metal materials may be formed along the wall surface of the via hole. In the third connection via layer 133, since the connection pad 120P and / or a portion of the first wiring layer 112a can be used as a barrier for forming a via hole, each of the connection vias in the third connection via layer 133 can have a tapered profile opposite to the first connection via layer 113a and the second connection via layer 113b, and the width of the cross section of the tapered profile narrows from its upper surface to its lower surface. In the fourth connection via layer 143, since a portion of the fourth wiring layer 132 can be used as a barrier for forming a via hole, each of the connection vias in the fourth connection via layer 143 can have a tapered profile opposite to the first connection via layer 113a and the second connection via layer 113b, and the width of the cross section of the tapered profile narrows in a direction from its upper surface to its lower surface. The third connection via layer 133 and the fourth connection via layer 143 may also be formed by a plating process, for example, a process of AP, SAP, MSAP, TT, etc. Therefore, the third connection via layer 133 and the fourth connection via layer 143 may include a seed layer (no electroplating layer) and an electroplating layer formed based on the seed layer. The third connection via layer 133 may be formed simultaneously by the same plating process as the plating process of the fourth wiring layer 132, and may be integrated without a boundary. The fourth connection via layer 143 may be formed simultaneously by the same plating process as the plating process of the fifth wiring layer 142, and may be integrated without a boundary.

[0045] The first passivation layer 150 may be an additional structure, and may protect the third wiring layer 112c from external physical damage and chemical damage. The first passivation layer 150 may be disposed on the lower surface of the second insulating layer 111b and may cover at least a portion of the third wiring layer 112c, and may have a plurality of first openings for exposing a portion of the third wiring layer 112c, respectively. The material of the first passivation layer 150 may not be limited to any specific material. For example, an insulating material may be used, and a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, an insulating material in which a thermosetting resin or a thermoplastic resin is mixed with an inorganic filler or impregnated with an inorganic filler and / or glass fiber in a core material (such as a prepreg, ABF (Ajinomoto build-up film), FR-4, bismaleimide triazine (BT), etc.) may be used as the insulating material. Alternatively, a solder resist (SR) may be used.

[0046] The second passivation layer 160 may be an additional structure, and may protect the fifth wiring layer 142 from external physical damage and chemical damage. The second passivation layer 160 may be disposed on the upper surface of the second insulating material 140 and may cover at least a portion of the fifth wiring layer 142, and may have a plurality of second openings for exposing a portion of the fifth wiring layer 142, respectively. The material of the second passivation layer 160 may not be limited to any specific material. For example, an insulating material may be used, and a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, an insulating material in which a thermosetting resin or a thermoplastic resin is mixed with an inorganic filler or impregnated with an inorganic filler and / or glass fiber in a core material (such as a prepreg, ABF (Ajinomoto build-up film), FR-4, bismaleimide triazine (BT), etc.) may be used as the insulating material. Alternatively, a solder resist (SR) may be used.

[0047] The electrically connected metal bumps 170 may be respectively disposed on the plurality of first openings of the first passivation layer 150. The electrically connected metal bumps 170 may be respectively connected to the exposed third wiring layer 112c. The electrically connected metal bumps 170 may physically connect and / or electrically connect the electronic component embedded substrate 100 to an external entity. For example, the electronic component embedded substrate 100 may be mounted on a main board, a ball grid array (BGA) substrate, etc. of an electronic device through the electrically connected metal bumps 170. The electrically connected metal bumps 170 may be formed using tin (Sn) or an alloy containing tin (Sn), such as solder, but this is merely an example, and embodiments thereof are not limited thereto. The electrically connected metal bumps 170 may be configured as pads, solder balls, pins, etc. The electrically connected metal bumps 170 may include multiple layers or a single layer. When the electrically connected metal bumps 170 include multiple layers, the electrically connected metal bumps 170 may include copper pillars or solder, and when the electrically connected metal bumps 170 include a single layer, the electrically connected metal bumps 170 may include tin-silver solder or copper. However, this is only an example, and embodiments are not limited thereto. The number of electrical connection metal bumps 170 , the spacing between the electrical connection metal bumps 170 , and the arrangement form of the electrical connection metal bumps 170 may not be limited to any specific example and may vary according to embodiments.

[0048] The component 210 may be further disposed on the second passivation layer 160 and may be connected to the exposed portion of the fifth wiring layer 142. The component 210 may be disposed on the second passivation layer 160 in a surface-mounted form through the connecting member 220, respectively. The component 210 may be an active component and / or a passive component. An example of an active component may be the above-mentioned IC described with reference to the electronic component 120. An example of a passive component may be a chip capacitor such as a multilayer ceramic capacitor (MLCC) and a chip inductor such as a power inductor (PI). The connecting member 220 may include tin (Sn) or an alloy containing tin (Sn), for example, solder, etc., respectively. If necessary, a molding material 230 covering the component 210 may be further disposed on the second passivation layer 160, and the molding material 230 may be a known epoxy molding compound (EMC), but is not limited thereto. When the component 210 is further disposed, the electronic component embedded substrate 100 may be used as a SiP.

[0049] In addition, the electronic component embedded substrate 100 may have a plurality of cavities 110H, and in this case, the above-mentioned barrier layer 115 may be applied to each cavity 110H. The same or different electronic components may be disposed in each cavity 110H.

[0050] Figures 5 to 8 It shows the manufacturing Figure 3 Schematic process diagram of an example of an electronic component embedded substrate in FIG.

[0051] Reference Figure 5, first, prepare the core substrate 110. The core substrate 110 can be manufactured by a coreless process. For example, a first wiring layer 112a can be formed on a separate carrier in a plating process, a first insulating layer 111a can be laminated using RCC, etc., and then a barrier layer 115, a second wiring layer 112b, and a first connection via layer 113a can be formed after processing the via hole, and a second insulating layer 111b can be laminated on the first insulating layer 111a using RCC, etc., and then a third wiring layer 112c and a second connection via layer 113b can be formed in a plating process after processing the via hole. In this case, when the second insulating layer 111b is formed, stress S1 may occur due to the curing shrinkage of the second insulating layer 111b. In the example, the core substrate 110 manufactured so that stress S1 is offset by stresses S2 to S4 (described later) can be used by separating from the separate carrier and then by vertical inversion. Next, the core substrate 110 can be attached to a carrier 300 for warpage control. In this case, a first passivation layer 150 formed using ABF or the like may be disposed between the core substrate 110 and the carrier 300. Thereafter, the cavity 110H may be formed through a process such as sand blasting or the like.

[0052] Reference Figure 6 , next, the electronic component 120 may be disposed in the cavity 110H. The electronic component 120 may be disposed in a face-up form. For example, the back side of the electronic component 120 may be attached to the barrier layer 115 using an adhesive 125 such as DAF or the like. Next, after laminating the first insulating material 130 on the core substrate 110 and the electronic component 120 using a prepreg, ABF, or the like, a fourth wiring layer 132 and a third connection via layer 133 may be formed by a plating process after processing the via hole. In this case, the stress S2 generated by the curing shrinkage of the first insulating material 130 may appear on its upper portion, but the warping may be suppressed by the carrier 300.

[0053] Reference Figure 7 , next, the second insulating material 140 may be formed on the first insulating material 130 by laminating a prepreg or ABF, and the fifth wiring layer 142 and the fourth connection via layer 143 may be formed by a plating process after processing the via hole. In this case, the stress S3 generated by the curing shrinkage of the second insulating material 140 may appear on its upper portion. The warpage caused by the stress S3 may also be suppressed by the carrier 300. Next, the second passivation layer 160 may be formed on the insulating material 140 by a method such as laminating ABF. In this case, the stress S4 generated by the curing shrinkage of the second insulating material 140 may appear on its upper portion. The warpage caused by the stress S4 may also be suppressed by the carrier 300.

[0054] Reference Figure 8, next, the carrier 300 is separated. In this case, warping may occur due to the stored stresses S1 to S4, but in the example, the lower stress S1 and the upper stresses S2 to S4 may be offset to some extent, thereby reducing the resulting warping. Next, a first opening and a second opening may be formed in the first passivation layer 150 and the second passivation layer 160, respectively. If necessary, an electrically connected metal bump 170 may be further formed. If necessary, the component 210 may be further mounted by the connecting member 220 and covered with the molding material 230. The electronic component embedded substrate 100 according to the above example may be manufactured by a series of processes.

[0055] In the example embodiments, for ease of description, with reference to the cross-section in the diagram, the terms "side region", "side surface", etc. may be used to indicate a surface formed by intercepting in the left / right direction, the terms "lower side", "lower part", "lower surface", etc. may be used to indicate a direction facing downward, and the terms "upper side", "upper part", "upper surface", etc. may be used to indicate a direction opposite to the above directions. The concept that an element is disposed on the side region, upper side, upper region, or lower region may include a configuration in which the element is in direct contact with an element configured as a reference in the corresponding direction and a configuration in which the element is not in direct contact with the reference element. For ease of description, the terms may be defined as above, and the scope of rights of the example embodiments is not specifically limited to the above terms.

[0056] In example embodiments, the term "connection" may indicate not only "direct connection" but also "indirect connection" by means of an adhesive layer or the like. In addition, the term "electrical connection" may include both a case where an element is "physically connected" and a case where an element is "non-physically connected". In addition, the terms "first", "second", etc. may be used to distinguish one element from another, and may not limit the order and / or importance associated with the elements, etc. In some cases, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of rights of example embodiments.

[0057] In the example embodiments, the term "example embodiment" may not indicate one and the same example embodiment, but may be provided to describe and emphasize different unique features of each example embodiment. The example embodiments suggested above may be implemented without excluding the possibility of combining features of other example embodiments. For example, unless otherwise noted, even if a feature described in one example embodiment is not described in another example embodiment, the description may be understood to be related to another example embodiment.

[0058] The terms used in the exemplary embodiments are used to simply describe the exemplary embodiments and are not intended to limit the present disclosure. Unless otherwise specified, singular terms also include plural forms.

[0059] As described above, according to the present disclosure, an electronic component embedded substrate capable of reducing warpage even in an asymmetric structure can be provided.

[0060] According to the present disclosure, an electronic component embedded substrate that can be modularized and miniaturized in the form of a SiP can be provided.

[0061] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the invention as defined by the appended claims.

Claims

1. An electronic component embedded substrate, comprising: A core substrate, comprising: an insulating body having a first surface and a second surface opposite to the first surface; a first wiring layer embedded in the insulating body so that one surface of the first wiring layer is exposed from the first surface; and a second wiring layer provided on the insulating body to protrude on the second surface, the core substrate having a cavity penetrating a portion of the insulating body from the first surface toward the second surface, and the cavity having a barrier layer as a bottom surface thereof; an electronic component disposed on the barrier layer in the cavity; a first insulating material covering at least a portion of each of the core substrate and the electronic component; and A third wiring layer is provided on the first insulating material, The first wiring layer, the second wiring layer, and the third wiring layer are connected to each other through a plurality of connecting via layers. An upper layer connection via of the plurality of connection via layers connecting the first wiring layer and the third wiring layer has a tapered profile in a direction opposite to that of a lower layer connection via of the plurality of connection via layers located below the upper layer connection via.

2. The electronic component embedded substrate according to claim 1, wherein: The core substrate includes: a first insulating layer having the first surface; a fourth wiring layer provided on the first insulating layer to protrude on a surface of the first insulating layer opposite to the first surface of the first insulating layer; and a second insulating layer provided on the surface of the first insulating layer opposite to the first surface of the first insulating layer and having the second surface opposite to a surface facing the first insulating layer, The insulating body comprises the first insulating layer and the second insulating layer, The first wiring layer is embedded in the first insulating layer, and The fourth wiring layer is embedded in the second insulating layer.

3. The electronic component embedded substrate according to claim 2, wherein: The plurality of connection via layers include: a first connection via layer that penetrates the first insulating layer and connects the first wiring layer and the fourth wiring layer; and a second connection via layer that penetrates the second insulating layer and connects the second wiring layer and the fourth wiring layer, and The connection vias of each of the first connection via layer and the second connection via layer have a tapered profile whose width of a cross section widens in a direction from the first surface toward the second surface.

4. The electronic component embedded substrate according to claim 3, wherein: The plurality of connection via layers further include a third connection via layer that penetrates the first insulating material and connects the third wiring layer to the electronic component and the first wiring layer, respectively. Wherein, the connection vias of the third connection via layer have a tapered profile in a direction opposite to a direction of the connection vias of each of the first connection via layer and the second connection via layer.

5. The electronic component embedded substrate according to claim 2, wherein: The cavity penetrates the first insulating layer but does not penetrate the second insulating layer.

6. The electronic component embedded substrate according to claim 2, wherein: The barrier layer is provided at the same height as the fourth wiring layer, and The barrier layer includes the same metal material as the fourth wiring layer.

7. The electronic component embedded substrate according to claim 6, wherein: The barrier layer has a first region exposed from the first insulating layer through the cavity and a second region surrounding the first region and covered by the first insulating layer, and The first region is thinner than the second region.

8. The electronic component embedded substrate according to claim 6, wherein: The second wiring layer is disposed at a lower height than the barrier layer.

9. The electronic component embedded substrate according to claim 1, wherein: The electronic component has an active surface provided with connection pads and an inactive surface opposite to the active surface, the inactive surface facing the barrier layer.

10. The electronic component embedded substrate according to claim 9, wherein: The inactive surface of the electronic component is attached to the barrier layer by an adhesive.

11. The electronic component embedded substrate according to claim 1, further comprising: a second insulating material disposed on the first insulating material and covering at least a portion of the third wiring layer; as well as A fifth wiring layer is arranged on the second insulating material.

12. The electronic component embedded substrate according to claim 11, further comprising: a first passivation layer disposed on the second surface of the insulating body and having a first opening for exposing a portion of the second wiring layer; as well as The second passivation layer is disposed on the second insulating material and has a second opening for exposing a portion of the fifth wiring layer.

13. The electronic component embedded substrate according to claim 12, further comprising: An electrical connection metal bump is disposed on the first opening and connected to the exposed portion of the second wiring layer.

14. The electronic component embedded substrate according to claim 12, further comprising: a component disposed on the second passivation layer and connected to the exposed portion of the fifth wiring layer, Wherein, the component includes at least one of an active component and a passive component.

15. The electronic component embedded substrate according to claim 1, wherein: The first surface of the insulating body has a step relative to an exposed one surface of the first wiring layer.

16. A substrate, comprising: a first insulating layer; a first wiring layer embedded in the first insulating layer and exposed from an upper surface of the first insulating layer; a second insulating layer having a thickness smaller than that of the first insulating layer and disposed on a lower surface of the first insulating layer; a second wiring layer embedded in the second insulating layer and in contact with the first insulating layer; a barrier layer comprising a first portion and a second portion, the first portion being in contact with the first insulating layer and the second insulating layer, the second portion extending from the first portion and exposed from the first insulating layer through the cavity, the second portion being thinner than the first portion; an electronic component disposed on the barrier layer in the cavity; an insulating material covering a portion of each of the first insulating layer and the electronic component; as well as a first connection via provided in the first insulating layer and connecting the first wiring layer and the second wiring layer to each other, The width of the cross section of the first connecting via gradually narrows in a direction from the second insulating layer to the first insulating layer.

17. The substrate according to claim 16, wherein The electronic component has an active surface provided with connection pads and an inactive surface opposite to the active surface, the inactive surface facing the barrier layer.

18. The substrate according to claim 17, further comprising: a third wiring layer, disposed on the lower surface of the second insulating layer; A fourth wiring layer is disposed on the upper surface of the insulating material; a second connection via that penetrates the second insulating layer and connects the second wiring layer and the third wiring layer to each other; as well as a third connecting via that penetrates the insulating material and connects the fourth wiring layer to the connection pad of the electronic component and the first wiring layer, respectively; The width of the cross section of the second connection via gradually narrows in the direction from the second insulation layer to the first insulation layer, and the width of the cross section of each of the third connection vias gradually narrows in the direction from the first insulation layer to the second insulation layer.

19. The substrate according to claim 16, wherein The barrier layer is provided at the same height as the second wiring layer, and The barrier layer includes the same metal material as the second wiring layer.

20. The substrate according to claim 16, wherein The upper surface of the first insulating layer has a step with respect to a surface of the first wiring layer exposed from the first insulating layer.

21. An electronic component embedded substrate, comprising: A core substrate, comprising: an insulating body having a first surface and a second surface opposite to the first surface; a first wiring layer embedded in the insulating body so that one surface of the first wiring layer is exposed from the first surface; and a second wiring layer provided on the insulating body to protrude on the second surface, the core substrate having a cavity penetrating a portion of the insulating body from the first surface toward the second surface, and the cavity having a barrier layer as a bottom surface thereof; an electronic component disposed on the barrier layer in the cavity; a first insulating material covering at least a portion of each of the core substrate and the electronic component; and A third wiring layer is provided on the first insulating material, The insulating body includes: a first insulating layer having the first surface; and a second insulating layer disposed on a surface of the first insulating layer opposite to the first surface of the first insulating layer and having the second surface. wherein the barrier layer has a first region exposed from the first insulating layer through the cavity and a second region surrounding the first region and covered by the first insulating layer, and The first region is thinner than the second region.

22. A substrate, comprising: a first insulating layer; a first wiring layer embedded in the first insulating layer and exposed from an upper surface of the first insulating layer; a second insulating layer having a thickness smaller than that of the first insulating layer and disposed on a lower surface of the first insulating layer; a second wiring layer embedded in the second insulating layer and in contact with the first insulating layer; a barrier layer including a first portion and a second portion, the first portion being in contact with the first insulating layer and the second insulating layer, the second portion extending from the first portion and exposed from the first insulating layer through the cavity; an electronic component disposed on the barrier layer in the cavity; an insulating material covering a portion of each of the first insulating layer and the electronic component; as well as a first connection via provided in the first insulating layer and connecting the first wiring layer and the second wiring layer to each other, The width of the cross section of the first connecting via gradually narrows in a direction from the second insulating layer to the first insulating layer. The substrate further comprises: a third wiring layer, disposed on the lower surface of the second insulating layer; A fourth wiring layer is disposed on the upper surface of the insulating material; a second connection via that penetrates the second insulating layer and connects the second wiring layer and the third wiring layer to each other; and a third connecting via that penetrates the insulating material and connects the fourth wiring layer to the connection pad of the electronic component and the first wiring layer, respectively; The width of the cross section of the second connection via gradually narrows in the direction from the second insulation layer to the first insulation layer, and the width of the cross section of each of the third connection vias gradually narrows in the direction from the first insulation layer to the second insulation layer.

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