Encapsulation substrate and multi-chip package including the same

Abstract

Provided are a packaging substrate and a multi-chip package including the packaging substrate. The packaging substrate includes: a substrate; a first structure disposed on the substrate and having a first through-hole; a first wiring layer disposed on the substrate and located in the first through-hole; a first insulating layer disposed on the substrate, located in the first through-hole, and covering at least a portion of the first wiring layer; and a second wiring layer disposed on the first insulating layer.

Description

[0001] This application claims the benefit of priority of Korean Patent Application No. 10-2019-0163279, filed with the Korean Intellectual Property Office on December 10, 2019, the entire disclosure of which is incorporated herein by reference for all purposes. Technical Field

[0002] The present disclosure relates to a package substrate and a multi-chip package including the package substrate. Background Art

[0003] Compared with the case of manufacturing an entire system-on-chip using a single silicon die, in the case of dividing a die into chiplets, the manufacturing cost of the chips can be further reduced and the disposal cost due to low yield can also be reduced. With the latest trend of chipletization, interconnection technologies between chiplets have emerged. For example, substrates including silicon interposers, substrates including silicon-based interconnect bridges capable of realizing electrical connections between dies, etc. have been developed. However, such technologies require the manufacture of expensive silicon interconnect dies. In addition, in the case of silicon-based interconnect bridges, reliability problems occur due to the mismatch in the coefficient of thermal expansion (CTE) between the silicon material of the bridge and the organic material of the substrate. Summary of the Invention

[0004] One aspect of the present disclosure is to provide a package substrate capable of providing relatively inexpensive multi-chip interconnection and a multi-chip package including the package substrate.

[0005] Another aspect of the present disclosure is to provide a package substrate capable of reducing the risk of yield reduction and a multi-chip package including the package substrate.

[0006] Another aspect of the present disclosure is to provide a package substrate with a high degree of freedom in wiring design and a multi-chip package including the package substrate.

[0007] Another aspect of the present disclosure is to provide a package substrate having improved reliability (advantageous for bending control) and a multi-chip package including the package substrate.

[0008] Another aspect of the present disclosure is to provide a package substrate capable of forming a thin structure and a multi-chip package including the package substrate.

[0009] According to one aspect of the present disclosure, a fine circuit is realized by forming a dam-like structure on a substrate and sequentially forming a wiring layer, an insulating layer, etc. in a through-hole formed through the structure.

[0010] For example, a packaging substrate includes: a substrate; a first structure disposed on the substrate and having a first through-hole; a first wiring layer disposed on the substrate and located in the first through-hole; a first insulating layer disposed on the substrate, located in the first through-hole, and covering at least a portion of the first wiring layer; and a second wiring layer disposed on the first insulating layer.

[0011] For example, a multi-chip package includes: a packaging substrate including a substrate, a first structure, a first wiring layer, a first insulating layer, and a second wiring layer, the first structure being disposed on the substrate and having a first through-hole, the first wiring layer being disposed on the substrate and located in the first through-hole, the first insulating layer being disposed on the substrate and located in the first through-hole and covering at least a portion of the first wiring layer, the second wiring layer being disposed on the first insulating layer; a first semiconductor chip disposed on the packaging substrate and having a first connection pad; and a second semiconductor chip disposed on the packaging substrate near the first semiconductor chip and having a second connection pad. At least one of the first connection pads is electrically connected to at least one of the second connection pads through the first wiring layer.

[0012] For example, a packaging substrate includes: a substrate; a dam-like structure disposed on the substrate; a first pattern disposed inside the dam-like structure and on the substrate; a second pattern disposed outside the dam-like structure and on the substrate; an insulating layer covering only the first pattern of the first pattern and the second pattern; a wiring layer disposed on the insulating layer; and a via layer disposed in the insulating layer and connecting the first pattern to the wiring layer. Description of the Drawings

[0013] Through the following detailed description in conjunction with the drawings, the above and other aspects, features, and advantages of the present disclosure will be more clearly understood, wherein:

[0014] Figure 1 is a schematic block diagram showing an example of an electronic device system;

[0015] Figure 2 is a schematic perspective view showing an example of an electronic device;

[0016] Figure 3 is a schematic cross-sectional view of a multi-chip package according to an example;

[0017] Figure 4 is when viewed from above and applied to Figure 3 a schematic plan view of a packaging substrate according to an example of the multi-chip package in; and

[0018] Figure 5 and Figure 6 is a schematic process diagram showing an example of a package substrate according to an example for manufacturing a multi-chip package applied to Figure 3 in. Detailed implementation manners

[0019] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings as follows.

[0020] Figure 1 is a schematic block diagram showing an example of an electronic device system.

[0021] Referring to Figure 1 , the electronic device 1000 houses a main board 1010. The main board 1010 may include chip-related components 1020, network-related components 1030, other components 1040, etc. physically or electrically connected thereto. These components may be connected to other components to be described below through various signal lines 1090.

[0022] The chip-related components 1020 may include: memory chips, such as volatile memories (e.g., dynamic random access memories (DRAMs)), non-volatile memories (e.g., read-only memories (ROMs)), flash memories, etc.; application processor chips, such as central processors (e.g., central processing units (CPUs)), graphics processors (e.g., graphics processing units (GPUs)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, the chip-related components 1020 are not limited thereto, but may also include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of packages including the above chips or electronic components.

[0023] The network-related components 1030 may include components operating according to protocols such as: Wi-Fi (Institute of Electrical and Electronics Engineers (IEEE) 802.11 family, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Only (Ev-DO), High Speed Packet Access+ (HSPA+), High Speed Downlink Packet Access+ (HSDPA+), High Speed Uplink Packet Access+ (HSUPA+), Enhanced Data rates for GSM Evolution (EDGE), Global System for Mobile Communications (GSM), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, 3G, 4G, and 5G protocols, and any other wireless and wired protocols specified after the above-mentioned protocols. However, the network-related components 1030 are not limited thereto, but may also include components operating according to various other wireless standards or protocols or wired standards or protocols. In addition, the network-related components 1030 may be combined with each other together with the above-mentioned chip-related components 1020.

[0024] The other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, Low Temperature Co-fired Ceramic (LTCC), Electromagnetic Interference (EMI) filters, Multi-Layer Ceramic Capacitors (MLCC), etc. However, the other components 1040 are not limited thereto, but may also include passive components for various other purposes. In addition, the other components 1040 may be combined with each other together with the above-mentioned chip-related components 1020 or network-related components 1030.

[0025] Depending on the type of the electronic device 1000, the electronic device 1000 may include other components that may or may not be physically or electrically connected to the main board 1010. These other components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown), a compass (not shown), an accelerometer (not shown), a gyroscope (not shown), a speaker (not shown), a mass storage unit (e.g., a hard disk drive) (not shown), a Compact Disc (CD) drive (not shown), a Digital Versatile Disc (DVD) drive (not shown), etc. However, these other components are not limited thereto, but may also include other components for various purposes depending on the type of the electronic device 1000, etc.

[0026] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automotive component, etc. However, the electronic device 1000 is not limited thereto, and may be any other electronic device that processes data.

[0027] Figure 2 is a schematic perspective view showing an example of an electronic device.

[0028] Referring to the accompanying drawings, the electronic device may be, for example, a smart phone 1100. The main board 1110 may be accommodated in the smart phone 1100, and various electronic components 1120 may be physically and / or electrically connected to the main board 1110. In addition, other electronic components (such as a camera module 1130 and / or a speaker 1140) that may or may not be physically and / or electrically connected to the main board 1110 may be accommodated in the main board 1110. A part of the electronic components 1120 may be the above-described chip-related components, for example, a semiconductor package 1121, but is not limited thereto. The semiconductor package 1121 may be a surface-mount type package in the form of a package substrate on which a semiconductor chip or a passive component is mounted, but is not limited thereto. The electronic device is not necessarily limited to the smart phone 1100, and may be other electronic devices as described above.

[0029] Referring to Figure 2 , the electronic device may be, for example, a smart phone 1100. The main board 1110 may be accommodated in the smart phone 1100, and various electronic components 1120 may be physically and / or electrically connected to the main board 1110. In addition, other electronic components (such as a camera module 1130 and / or a speaker 1140) that may or may not be physically and / or electrically connected to the main board 1110 may be accommodated in the main board 1110. A part of the electronic components 1120 may be the above-described chip-related components, for example, a semiconductor package 1121, but is not limited thereto. The semiconductor package 1121 may be a surface-mount type package in the form of a package substrate on which a plurality of chips are mounted, but is not limited thereto. The electronic device is not necessarily limited to the smart phone 1100, and may be other electronic devices as described above.

[0030] Figure 3 is a schematic cross-sectional view of a multi-chip package according to an example.

[0031] Figure 4 is when viewed from above, applied to Figure 3 is a schematic plan view of a package substrate of a multi-chip package according to an example in

[0032] Referring toFigure 3 and Figure 4 , the multi-chip package 500 according to the example includes: a package substrate 100; a first semiconductor chip 310 disposed on the package substrate 100; and a second semiconductor chip 320 disposed on the package substrate 100 near the first semiconductor chip 310. The package substrate 100 includes a substrate 110, a structure 120 disposed on the substrate 110 and having a through-hole 120H, and an insulating layer 130, a wiring layer 140, and a wiring via layer 150 disposed in the through-hole 120H of the substrate 110. The first semiconductor chip 310 and the second semiconductor chip 320 can both be electrically connected to the wiring layer 140 of the package substrate 100 and can be electrically connected to each other through the wiring layer 140.

[0033] As described above, with the latest trend of chipletization, an interconnection technology between chiplets has emerged. For example, substrates including a silicon interposer, substrates including a silicon-based interconnection bridge capable of achieving electrical connection between dies, etc. have been developed. However, such technologies require the manufacture of expensive silicon interconnection dies. In addition, in the case of a silicon-based interconnection bridge, reliability problems occur due to the mismatch in the coefficient of thermal expansion (CTE) between the silicon material of the bridge and the organic material of the substrate.

[0034] On the other hand, the multi-chip package 500 according to the example can provide an interconnection between multiple chips by providing a package substrate 100 with an organic bridging circuit. For example, the package substrate 100 according to the example can be manufactured by forming a dam-like structure 120 on the substrate 110 and sequentially forming a wiring layer 140, an insulating layer 130, etc. in the through-hole 120H passing through the structure 120. In this case, an organic-based process can be mainly performed instead of a silicon-based process to reduce costs and lower the process difficulty level. In addition, since there is no need to insert an additional bridge die, the risk of reducing the yield can be reduced. In addition, the material of the insulating layer 130 can be a liquid photosensitive material, so that a fine circuit can be realized and the design freedom can be made variable high. Therefore, a local fine circuit for interconnection between multiple chips can be easily provided when needed. In addition, heterogeneous materials can be applied only locally, and there is no cavity process for inserting an additional bridge die, etc., which is advantageous for bending control. In addition, an additional interposer substrate can be omitted, which is advantageous for the thin structure of the product. In addition, since the wiring layer 140, etc. are integrated with the substrate 110, the circuit wiring in the substrate 110 can be easily connected to the wiring layer 140, thereby reducing signal loss.

[0035] In the packaged substrate 100 according to the example, each of the structure 120, the insulating layer 130, the wiring layer 140, and the wiring via layer 150 may include a plurality of layers. For example, the packaged substrate 100 according to the example may include: a first structure 121 disposed on the substrate 110 and having a first through-hole 121H; a second structure 122 disposed on the first structure 121 and having a second through-hole 122H; a first wiring layer 141 disposed on the substrate 110 and located in the first through-hole 121H; a first insulating layer 131 disposed on the substrate 110, located in the first through-hole 121H, and covering at least a portion of the first wiring layer 141; a second wiring layer 142 disposed on the first insulating layer 131 and located in the second through-hole 122H; a first wiring via layer 151 passing through the first insulating layer 131 in the first through-hole 121H and connecting the first wiring layer 141 and the second wiring layer 142 to each other; a second insulating layer 132 disposed on the first insulating layer 131, located in the second through-hole 122H, and covering at least a portion of the second wiring layer 142; a third wiring layer 143 disposed on the second insulating layer 132; and a second wiring via layer 152 passing through the second insulating layer 132 in the second through-hole 122H and connecting the second wiring layer 142 and the third wiring layer 143 to each other. As described, the number of layers in the fine circuit can be adjusted as needed. The first structure 121 may include a dam structure, and the first insulating layer 131 is disposed inside the dam structure and spaced apart from the region outside the dam structure.

[0036] In addition, the encapsulation substrate 100 according to the example may further include a fourth wiring layer 145. The fourth wiring layer 145 is disposed on the substrate 110 and is located on the outer side of the structure 120, for example, on the outer side of the first structure 121. The fourth wiring layer 145 may be disposed at a height corresponding to the height of the first wiring layer 141. The fourth wiring layer 145 may be an additional circuit rather than a bridging circuit. At least a part of the fourth wiring layer 145 may be electrically connected to at least a part of the first wiring layer 141. Each of the first semiconductor chip 310 and the second semiconductor chip 320 may be electrically connected to at least a part of the fourth wiring layer 145. As described above, due to the high degree of design freedom, a normal wiring circuit can be designed on the substrate 110 independently of the bridging circuit. In this case, as a non-limiting example, the third wiring layer 143 (the uppermost wiring layer of the wiring layer 140) may include a plurality of first pads 143P having a first pitch P1, the fourth wiring layer 145 may include a plurality of second pads 145P having a second pitch P2, and the first pitch P1 may be smaller than the second pitch P2. For example, the plurality of first pads 143P may be fine circuits having a finer pitch compared to the plurality of second pads 145P. Such a relationship may also be applied to other wiring layers in the wiring layer 140. The encapsulation substrate 100 may include: a first pattern (for example, including the first wiring layer 141), disposed inside the dam-like structure and on the substrate; a second pattern (for example, including the fourth wiring layer 145), disposed outside the dam-like structure and on the substrate; and an insulating layer (for example, including the first insulating layer 131), covering only the first pattern among the first pattern and the second pattern.

[0037] Hereinafter, a multi-chip package according to an example and an encapsulation substrate according to an example included in the multi-chip package will be described in detail with reference to the drawings.

[0038] The substrate 110 may be a multilayer printed circuit board (PCB). The printed circuit board (PCB) may be a cored PCB or a coreless PCB. As a non-limiting example, the substrate 110 may be a ball grid array (BGA) type PCB. The substrate 110 may include a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers. The number of insulating layers, wiring layers, and via layers is not necessarily limited, and each of the insulating layers, wiring layers, and via layers may include a plurality of layers or a single layer according to the design.

[0039] The material of the insulating layer can be an insulating material. In this case, the insulating material can be a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material containing a reinforcing material (such as glass fiber, glass cloth, glass fabric) and / or an inorganic filler together with a thermosetting resin or a thermoplastic resin, such as copper-clad laminate (CCL), flexible copper-clad laminate (FCCL), prepreg, ABF (Ajinomoto Build-up Film), photosensitive dielectric (PID), etc. However, the insulating material is not limited thereto, and a glass plate or a ceramic plate can be used as the material of a specific insulating layer (for example, the core layer). If necessary, a liquid crystal polymer (LCP) with low dielectric loss can be used. When multiple insulating layers are used, the materials of each of the insulating layers can be the same as or different from each other.

[0040] The material of the wiring layer can be a metal material. In this case, the metal material can be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), their alloys, etc. The wiring layer can be used to perform various functions according to the design of the relevant layer. For example, the wiring layer can include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. In this case, the signal (S) pattern can include various signal patterns other than the ground (GND) pattern, the power (PWR) pattern, etc., for example, a data signal pattern, etc. These patterns can all include line patterns, plane patterns, and / or pad patterns.

[0041] The material of the via layer can also be a metal material. In this case, the metal material can be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), their alloys, etc. Each of the wiring vias in the via layer can be completely filled with the metal material, or the metal material can be formed along the wall of the via hole. In addition, known shapes such as a conical shape, an hourglass shape, a cylindrical shape, etc. can all be applied to the wiring via. The via layer can be used to perform various functions according to the design of the relevant layer. For example, each of the wiring vias can include a wiring via for signal connection, a wiring via for ground connection, a wiring via for power connection, etc.

[0042] The structure 120 may include a first structure 121 and a second structure 122. The first structure 121 and the second structure 122 may respectively have a first through-hole 121H and a second through-hole 122H. The first through-hole 121H and the second through-hole 122H may be connected to each other to form a through-hole 120H. The materials of the first structure 121 and the second structure 122 are not necessarily limited and may be any material as long as it is used as a dam. As a non-limiting example, each of the first structure 121 and the second structure 122 may include a solder resist. In this case, since each of the first structure 121 and the second structure 122 can be easily patterned into a desired shape, the first through-hole 121H and the second through-hole 122H can be more easily realized. However, the present disclosure is not limited thereto, and the first structure 121 and the second structure 122 may include other known insulating materials. If necessary, the first structure 121 and the second structure 122 may include a metal material or a ceramic material.

[0043] When the structure 120 includes a plurality of layers, it may have a stepped shape. For example, the second structure 122 may have a smaller planar area than the planar area of the first structure 121. Accordingly, the inner wall surfaces of the first through-hole 121H and the second through-hole 122H may have a step with respect to each other. In addition, the outer side surfaces of the first structure 121 and the second structure 122 may also have a step with respect to each other. In this regard, the second through-hole 122H may have a larger planar area than the planar area of the first through-hole 121H. When the structure 120 is implemented to include a plurality of layers by such a stepped implementation, alignment can be more easily performed, and the multi-layer insulating layer 130, the wiring layer 140, and the wiring via layer 150 can be more easily formed in sequence.

[0044] The insulating layer 130 may include a first insulating layer 131 and a second insulating layer 132. The first insulating layer 131 and the second insulating layer 132 may include an insulating material, for example, a photosensitive dielectric (PID) (photosensitive insulating material). The photosensitive dielectric (PID) may be provided in a liquid state to be cured, which makes it easy to realize a fine circuit. The boundary between the first insulating layer 131 and the second insulating layer 132 may be distinct or may not be distinct.

[0045] The wiring layer 140 may include a first wiring layer 141, a second wiring layer 142, and a third wiring layer 143. The first wiring layer 141, the second wiring layer 142, and the third wiring layer 143 may include a metallic material. The metallic material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), their alloys, etc. The first wiring layer 141, the second wiring layer 142, and the third wiring layer 143 may be designed according to the relevant layer to perform various functions. For example, the first wiring layer 141, the second wiring layer 142, and the third wiring layer 143 may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. In this case, the signal (S) pattern may include various signal patterns other than the ground (GND) pattern, the power (PWR) pattern, etc., for example, a data signal pattern, etc. These patterns may all include a line pattern, a plane pattern, and / or a pad pattern. The fourth wiring layer 145 may also include the above-mentioned metallic material, and may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. In addition, the fourth wiring layer 145 may include a line pattern, a plane pattern, and / or a pad pattern. The patterns of the first wiring layer 141, the second wiring layer 142, and the third wiring layer 143 may be respectively formed into fine circuits having a density higher than that of the pattern of the fourth wiring layer 145.

[0046] The wiring via layer 150 may include a first wiring via layer 151 and a second wiring via layer 152. The first wiring via layer 151 and the second wiring via layer 152 may include a metallic material. The metallic material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), their alloys, etc. The wiring vias of each of the first wiring via layer 151 and the second wiring via layer 152 may be completely filled with the metallic material, or the metallic material may be formed along the wall surface of the via hole. In addition, known shapes such as a conical shape, an hourglass shape, a cylindrical shape, etc. may be applied to the wiring vias. The first wiring via layer 151 and the second wiring via layer 152 may also be designed according to the relevant layer to perform various functions. For example, each of the first wiring via layer 151 and the second wiring via layer 152 may include a wiring via for signal connection, a wiring via for ground connection, a wiring via for power connection, etc.

[0047] The first semiconductor chip 310 may be a die in the form of an integrated circuit (IC), in which hundreds to millions or more of devices are integrated in a single chip. In this case, the substrate material constituting the main body may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. Various circuits may be formed in the main body. The first connection pad 310P of the first semiconductor chip 310 is provided to electrically connect the first semiconductor chip 310 to another component, and the material forming the first connection pad 310P may be a metallic material such as copper (Cu), aluminum (Al), etc., but is not limited thereto. A passivation layer may be formed on the main body to expose the first connection pad 310P. The passivation layer may be an oxide layer, a nitride layer, etc., or may be a double layer of an oxide layer and a nitride layer. An insulating layer, etc. may be further provided at other necessary positions. If necessary, the first semiconductor chip 310 may be a chip-scale packaged die, in which a redistribution layer is formed on the main body to redistribute the first connection pad 310P.

[0048] The second semiconductor chip 320 may also be a die in the form of an integrated circuit (IC), in which hundreds to millions or more of devices are integrated in a single chip. If necessary, the second semiconductor chip 320 may have a structure in which multiple integrated circuits (ICs) are stacked. The stacked integrated circuits IC may be electrically connected to each other through through-silicon vias (TSVs). The second semiconductor chip 320 may also have a second connection pad 320P to be electrically connected to another component, and may be further provided with a passivation layer, an insulating layer, etc. If necessary, the second semiconductor chip 320 may also be a chip-scale packaged die. In addition, at least one of the first connection pads 310P and at least one of the second connection pads 320P may be electrically connected to each other through the first wiring layer 141.

[0049] As a non-limiting example, the first semiconductor chip 310 may be an application specific integrated circuit (ASIC). Optionally, the first semiconductor chip 310 may be a field programmable gate array (FPGA). Optionally, the first semiconductor chip 310 may be a chipset of an application specific integrated circuit (ASIC) and a field programmable gate array (FPGA). Optionally, the first semiconductor chip 310 may be a graphics processing unit (GPU). Optionally, the first semiconductor chip 310 may be a chipset of an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), and a graphics processing unit (GPU). Further, the second semiconductor chip 320 may be a stacked memory, such as a high bandwidth memory (HBM). Each of the first semiconductor chip 310 and the second semiconductor chip 320 may be a relatively expensive chip having dozens to millions or more I / Os, but is not limited thereto. Each of the first semiconductor chip 310 and the second semiconductor chip 320 may include a plurality of semiconductor chips. In this case, in the fine circuit region provided by the structure 120, the insulating layer 130, the wiring layer 140, and the wiring via layer 150 of the package substrate 100, the plurality of semiconductor chips may be locally and independently formed of each other.

[0050] When viewed from above, at least a part of the first semiconductor chip 310 may be arranged to overlap at least a part of the wiring layer 140 (e.g., the first wiring layer 141, the second wiring layer 142, and the third wiring layer 143). Further, when viewed from above, at least a part of the first semiconductor chip 310 may be arranged to overlap at least a part of the fourth wiring layer 145. In this case, at least one of the plurality of first connection pads 310P of the first semiconductor chip 310 may be connected to at least one of the plurality of first pads 143P of the third wiring layer 143 through the first connection members 311 and 313. Further, at least one of the plurality of first connection pads 310P of the first semiconductor chip 310 may be connected to at least one of the plurality of second pads 145P of the fourth wiring layer 145 through the second connection members 312 and 314.

[0051] When viewed from above, at least a part of the second semiconductor chip 320 may be disposed to overlap at least a part of the wiring layers 140 (e.g., the first wiring layer 141, the second wiring layer 142, and the third wiring layer 143). In addition, when viewed from above, at least a part of the second semiconductor chip 320 may be disposed to overlap at least a part of the fourth wiring layer 145. In this case, at least one of the plurality of second connection pads 320P of the second semiconductor chip 320 may be connected to at least one of the plurality of first pads 143P of the third wiring layer 143 through the third connection members 321 and 323. In addition, at least one of the plurality of second connection pads 320P of the second semiconductor chip 320 may be connected to at least one of the plurality of second pads 145P of the fourth wiring layer 145 through the fourth connection members 322 and 324.

[0052] The first connection members 311 and 313 may include at least one of the first metal bumps 311 and the first electrical connection metals 313, the second connection members 312 and 314 may include at least one of the second metal bumps 312 and the second electrical connection metals 314, the third connection members 321 and 323 may include at least one of the third metal bumps 321 and the third electrical connection metals 323, and the fourth connection members 322 and 324 may include at least one of the fourth metal bumps 322 and the fourth electrical connection metals 324. Each of the first to fourth connection members 311, 312, 313, 314, 321, 322, 323, and 324 may include a plurality of connection members, and the pitch between the plurality of connection members may correspond to the pitch between the plurality of pads 143P and 145P to be connected. Each of the first metal bump 311, the second metal bump 312, the third metal bump 321, and the fourth metal bump 322 may be a metal pillar including copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof, but the materials are not limited thereto. Each of the first electrical connection metal 313, the second electrical connection metal 314, the third electrical connection metal 323, and the fourth electrical connection metal 324 may be formed of solder and be an alloy including a metal having a low melting point lower than the melting point of copper (Cu) (e.g., tin (Sn)) (e.g., an alloy including tin (Sn)), but this is merely an example, and the materials are not limited thereto.

[0053] Figure 5 and Figure 6 is a schematic process diagram showing an example of a package substrate according to an example for manufacturing a multi-chip package applied to Figure 3 in.

[0054] Refer to Figure 5, a substrate 110 is prepared. A first wiring layer 141 is formed on the substrate 110 using a plating process (such as an additive process (AP), a semi-additive process (SAP), a modified SAP (MSAP), a through-hole technology (TT), etc.). If necessary, a fourth wiring layer 145 is also formed using the same plating process. In this case, the first wiring layer 141 and the fourth wiring layer 145 may have the same or substantially the same thickness and may be made of the same material. In addition, patterning performed through a photolithography process of a solder mask film or patterning performed through sandblasting, etching, or laser processing of an ABF forms a structure 120 on the substrate 110. The structure 120 may be formed of multiple layers according to the design and may be formed to include, for example, a first structure 121 and a second structure 122. The order of forming the first wiring layer 141, the fourth wiring layer 145, and the structure 120 is not necessarily limited. The first wiring layer 141 and the fourth wiring layer 145 may be formed first, or the structure 120 may be formed first. Next, a photosensitive insulating material or the like in a liquid state is applied to the first through-hole 121H of the first structure 121 and then cured to form a first insulating layer 131. Various types of coating processes may be used to perform the application of the photosensitive insulating material. Next, a via hole 151v for forming a wiring via layer is formed in the first insulating layer 131 using a photolithography process or the like.

[0055] Referring to Figure 6 , a second wiring layer 142 is formed on the first insulating layer 131 through the above plating process. In this case, a first wiring via layer 151 is also formed by filling the via hole 151v. Next, a photosensitive insulating material or the like in a liquid state is applied to the second through-hole 122H of the second structure 122 and then cured to form a second insulating layer 132. Various types of coating processes may also be used to perform the application of the photosensitive insulating material. Next, a via hole for forming a second wiring via layer 152 is formed in the second insulating layer 132 using a photolithography process or the like. Then, a third wiring layer 143 is formed on the second insulating layer 132 through the above plating process. In this case, a second wiring via layer 152 is also formed by filling the via hole. Depending on the number of layers of the structure 120, a series of processes may be further repeated so that a fine circuit region is formed with more multi-layers. Thus, the above-described package substrate 100 according to the example can be manufactured.

[0056] As described above, a package substrate capable of providing relatively inexpensive multi-chip interconnection and a multi-chip package including the package substrate can be provided.

[0057] In addition, a package substrate capable of reducing the risk of yield reduction and a multi-chip package including the package substrate can be provided.

[0058] In addition, a package substrate with a high degree of freedom in wiring design and a multi-chip package including the package substrate can be provided.

[0059] In addition, a package substrate with improved reliability (advantageous for bending control) and a multi-chip package including the package substrate can be provided.

[0060] In addition, a package substrate capable of forming a thin structure and a multi-chip package including the package substrate can be provided.

[0061] In the present disclosure, terms such as "lower side", "lower part", "lower surface", etc. have been used to indicate the direction of the cross-section relative to the drawing towards the mounting surface of the electronic component package, and terms such as "upper side", "upper part", "upper surface", etc. have been used to indicate the direction opposite to the direction indicated by terms such as "lower side", "lower part", "lower surface", etc. However, these directions are defined only for the purpose of convenience of explanation, and the claims are not particularly limited by the directions defined as above.

[0062] In the specification, the meaning of "connection" between a component and another component includes indirect connection through an adhesive layer and direct connection between two components. In addition, "electrical connection" means including physical connection and physical disconnection. It can be understood that when an element is referred to as "first" and "second", the element is not limited thereto. These terms can be used only for the purpose of distinguishing an element from other elements, and may not limit the order or importance of the element. In some cases, without departing from the scope of the claims set forth herein, the first element may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0063] The term "example embodiment" used herein does not always refer to the same example embodiment, but is provided to emphasize specific features or characteristics different from those of another example embodiment. However, the example embodiments provided herein are considered to be capable of being implemented by combining all or part of each other. For example, unless otherwise provided with a contrary or conflicting description, an element described in a specific example embodiment can be understood as being related to the description in another example embodiment even if it is not described in the other example embodiment.

[0064] The terms used herein are for describing example embodiments only and are not intended to limit the present disclosure. In this case, unless otherwise necessarily interpreted based on a specific context, the singular form includes the plural form.

[0065] Although the example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the present disclosure defined by the appended claims.

Claims

1. An encapsulation substrate, comprising: a substrate; a first structure disposed on the substrate and having a first through-hole; a first wiring layer disposed on the substrate and located in the first through-hole; a first insulating layer disposed on the substrate, located in the first through-hole, and covering at least a portion of the first wiring layer; a second wiring layer disposed on the first insulating layer; and a fourth wiring layer disposed on the substrate and located on the outer side of the first structure, wherein the first wiring layer and the fourth wiring layer are disposed at corresponding heights with respect to each other.

2. The encapsulation substrate according to claim 1, further comprising: a second structure disposed on the first structure and having a second through-hole; a second insulating layer disposed on the first insulating layer and located in the second through-hole; and a third wiring layer disposed on the second insulating layer, wherein the second wiring layer is disposed in the second through-hole on the first insulating layer, and the second insulating layer covers at least a portion of the second wiring layer.

3. The encapsulated substrate according to claim 2, wherein Each of the first structure and the second structure includes a solder mask.

4. The encapsulated substrate according to claim 2, wherein, The second structure has a planar area smaller than that of the first structure.

5. The encapsulation substrate according to claim 2, wherein, The inner wall surfaces of the first through-hole and the second through-hole have a step with respect to each other.

6. The encapsulation substrate according to claim 4, wherein, The second through-hole has a planar area larger than that of the first through-hole.

7. The encapsulation substrate according to claim 2, further comprising: a first wiring via layer penetrating the first insulating layer in the first through-hole and connecting the first wiring layer and the second wiring layer to each other; and a second wiring via layer penetrating the second insulating layer in the second through-hole and connecting the second wiring layer and the third wiring layer to each other.

8. The encapsulation substrate according to claim 2, wherein, The third wiring layer includes a plurality of first pads having a first pitch, the fourth wiring layer includes a plurality of second pads having a second pitch, and the first pitch is smaller than the second pitch.

9. The encapsulated substrate according to claim 1, wherein, The first structure includes a dam structure, and the first insulating layer is disposed inside the dam structure and is spaced apart from the region outside the dam structure.

10. A multi-chip package, comprising: an encapsulation substrate, the encapsulation substrate including a substrate, a first structure, a first wiring layer, a first insulating layer, a second wiring layer, and a fourth wiring layer, the first structure being disposed on the substrate and having a first through-hole, the first wiring layer being disposed on the substrate and located in the first through-hole, the first insulating layer being disposed on the substrate and located in the first through-hole and covering at least a portion of the first wiring layer, the second wiring layer being disposed on the first insulating layer, the fourth wiring layer being disposed on the substrate and located on the outer side of the first structure, wherein the first wiring layer and the fourth wiring layer are disposed at corresponding heights with respect to each other; a first semiconductor chip disposed on the encapsulation substrate and having a first connection pad; and a second semiconductor chip disposed on the encapsulation substrate near the first semiconductor chip and having a second connection pad, At least one of the first connection pads is electrically connected to at least one of the second connection pads through the first wiring layer.

11. The multi-chip package according to claim 10, wherein, In a plan view of the multi-chip package, at least a part of each of the first semiconductor chip and the second semiconductor chip overlaps at least a part of the first wiring layer.

12. The multi-chip package according to claim 10, wherein, The package substrate further includes: a second structure provided on the first structure and having a second through-hole; a second insulating layer provided on the first insulating layer and located in the second through-hole; and a third wiring layer provided on the second insulating layer, The second wiring layer is provided in the second through-hole on the first insulating layer, and The second insulating layer covers at least a part of the second wiring layer.

13. The multi-chip package according to claim 10, wherein, In a plan view of the multi-chip package, at least a part of each of the first semiconductor chip and the second semiconductor chip overlaps at least a part of the fourth wiring layer.

14. The multi-chip package according to claim 12, wherein, The third wiring layer includes a plurality of first pads having a first pitch, The fourth wiring layer includes a plurality of second pads having a second pitch, and The first pitch is smaller than the second pitch.

15. The multi-chip package according to claim 14, wherein, At least one of the first connection pads is connected to at least one of the first pads through a first connection member, and at least one of the first connection pads is connected to at least one of the second pads through a second connection member, At least one of the second connection pads is connected to at least one of the first pads through a third connection member, and at least one of the second connection pads is connected to at least one of the second pads through a fourth connection member, and Each of the first connection member, the second connection member, the third connection member, and the fourth connection member includes at least one of a metal bump and an electrically conductive metal.

16. The multi-chip package according to claim 10, wherein, The first structure includes a dam-like structure, and The first insulating layer is provided inside the dam-like structure and is spaced apart from an area outside the dam-like structure.

17. A package substrate, comprising: A substrate; A dam-like structure provided on the substrate; A first pattern provided inside the dam-like structure and on the substrate; A second pattern provided outside the dam-like structure and on the substrate; An insulating layer covering only the first pattern of the first pattern and the second pattern; A wiring layer provided on the insulating layer; And A via layer provided in the insulating layer and connecting the first pattern to the wiring layer, Wherein, the first pattern and the second pattern are provided at corresponding heights.

18. The encapsulated substrate according to claim 17, wherein, The insulating layer includes a photosensitive insulating material.

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