Directional deposition in etch chambers

Abstract

A method for forming a vertical growth mask for etching applications is described. The disclosed embodiment involves introducing a tungsten-containing deposition precursor and one or more carrier gases while igniting a plasma to selectively deposit tungsten on the fields of positive features of a patterned etch mask without substantially depositing tungsten on the sidewalls of the positive features or on exposed surfaces of a target layer beneath the patterned etch mask.

Description

[0001] Incorporated by Reference

[0002] The PCT application form is filed concurrently with this specification as a part of this application. Each application to which this application claims the benefit of or priority as identified in the concurrently filed PCT application form is incorporated herein by reference in its entirety and for all purposes. Background Art

[0003] The manufacture of semiconductor devices includes the fabrication of microprocessors, logic, and memory devices. Such devices can be manufactured using a variety of techniques, including patterning techniques that implement various types of masks. Some processes involve forming structures that include silicon oxides and silicon nitrides. Some techniques for forming such structures may be limited to patterning techniques that include both etching and deposition.

[0004] The background description provided here is for the purpose of generally presenting the context of the present disclosure. No admission is made, either explicitly or implicitly, that the work of the presently designated inventors is prior art to the present disclosure to the extent that it is described in this background section and in aspects of the specification that were not determined to be prior art at the time the application was filed. Summary of the Invention

[0005] Methods and apparatus for processing semiconductor substrates are provided herein. One aspect relates to a method that includes providing a semiconductor substrate having a patterned etch mask located above a target layer, the patterned etch mask comprising spaced positive features, each spaced positive feature having a field and a sidewall; and depositing a vertical growth mask selectively on the field of the spaced positive features relative to the target layer.

[0006] In various implementations, the vertical growth mask includes at least one feature; and a critical dimension of the at least one feature of the vertical growth mask is substantially the same as a critical dimension of a corresponding spaced-apart positive feature of the patterned etch mask.

[0007] In some implementations, depositing the vertical growth mask on the field is performed at a substrate temperature between about 0°C and about 160°C.

[0008] The method further includes etching the target layer using both the patterned etch mask and the vertical growth mask as masks. In some embodiments, depositing the vertical growth mask and etching the target layer are performed simultaneously. In some embodiments, the depositing and etching are performed simultaneously by exposing the semiconductor substrate to a fluorocarbon gas and a tungsten-containing gas and igniting a plasma. The fluorocarbon gas and the tungsten-containing gas can be delivered at a ratio of the fluorocarbon gas flow rate to the tungsten-containing gas flow rate between about 10:1 and about 1:1. In some embodiments, the fluorocarbon gas is delivered at a flow rate of less than about 80% of the total volume of the fluorocarbon gas and the tungsten-containing gas.

[0009] In some embodiments, the target layer comprises amorphous carbon, and the depositing and the etching are performed simultaneously by exposing the semiconductor substrate to an oxygen plasma and a tungsten-containing plasma simultaneously.

[0010] In some embodiments, the method further comprises cyclically alternating selectively depositing the vertical growth mask and etching the target layer. In some embodiments, the target layer comprises amorphous carbon, and the etching is performed by exposing the target layer to oxygen plasma.

[0011] In various embodiments, the dimensions of the spaces between the spaced positive features of the vertical growth mask are substantially the same as the dimensions of the spaces between the spaced positive features of the patterned etch mask. In some embodiments, the dimensions of the spaces between the spaced positive features of the patterned etch mask are within about 100% of the dimensions of the spaces between the spaced positive features of the vertical growth mask.

[0012] In various embodiments, the spaces between the spaced-apart positive features have an aspect ratio of between about 50:1 and about 100:1.

[0013] In various embodiments, the size of the space between two adjacent spaced-apart positive features is between about 10 nm and about 200 nm.

[0014] In various embodiments, selectively depositing the vertical growth mask on the field includes exposing the field to a tungsten-containing gas. In some embodiments, the tungsten-containing gas is delivered with a dilution gas. The dilution gas can be one or more of argon, hydrogen, and mixtures thereof. The tungsten-containing gas can be a tungsten halide. In some embodiments, the tungsten halide is selected from the group consisting of tungsten hexafluoride and tungsten hexachloride. In some embodiments, selectively depositing the vertical growth mask on the field further includes igniting a plasma in an environment containing the tungsten-containing gas. The plasma is generated at a plasma power between approximately 100 W and approximately 500 W.

[0015] In various embodiments, selectively depositing the vertical growth mask on the fields is performed in a processing chamber having a chamber pressure between about 10 mTorr and about 100 mTorr.

[0016] In various embodiments, selectively depositing the vertical growth mask on the fields is performed by adjusting process conditions such as plasma power, chamber pressure, or substrate temperature.

[0017] In various embodiments, the patterned etch mask has a thickness between about 5 nm and about 200 nm.

[0018] In various implementations, the patterned etch mask comprises a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

[0019] In various embodiments, the patterned etch mask comprises a photoresist. The target layer can be an antireflective coating. In various embodiments, the target layer has a thickness between about 500 nm and about 5000 nm.

[0020] Another aspect relates to a method comprising providing a semiconductor substrate having a patterned etch mask over a target layer, the patterned etch mask comprising spaced-apart positive features, each spaced-apart positive feature having a field and a sidewall; and depositing a vertically grown tungsten-containing mask selectively on the field of the spaced-apart positive features relative to the target layer.

[0021] Another aspect relates to a method comprising: providing a semiconductor substrate comprising a carbon-containing target layer, an antireflective layer, and a patterned photoresist; patterning the antireflective layer to form a patterned antireflective mask; exposing the semiconductor substrate to a tungsten-containing precursor and igniting a plasma under conditions to selectively deposit a tungsten-containing mask to form a patterned tungsten-containing mask on fields of the patterned antireflective mask; and patterning the carbon-containing target layer using the patterned antireflective mask and the patterned tungsten-containing mask.

[0022] Another aspect relates to a method comprising: providing a semiconductor substrate comprising a target layer and a patterned etch mask having a first critical dimension; and exposing the semiconductor substrate to a plasma to form a tungsten material having a second critical dimension on the patterned etch mask, the plasma being generated from a mixture of argon and hydrogen gases and a tungsten-containing precursor using a plasma power between about 100 W and about 500 W at a substrate temperature below about 160° C., such that the second critical dimension is within about 150% of the first critical dimension.

[0023] Another aspect relates to an apparatus comprising: a reaction chamber comprising a susceptor for holding a substrate; a plasma source coupled to the reaction chamber and configured to generate a plasma; one or more first gas inlets coupled to the reaction chamber; a second gas inlet coupled to the reaction chamber; and a controller comprising instructions for: introducing a mixture of argon and hydrogen and a tungsten-containing precursor; generating the plasma using a plasma power between about 100 W and about 500 W; and setting a temperature of the susceptor below about 160° C.

[0024] These and other aspects will be further described below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 are process flow diagrams illustrating operations performed according to certain disclosed embodiments.

[0026] Figure 2 are process flow diagrams illustrating operations performed according to certain disclosed embodiments.

[0027] Figure 3 、 4 , 5, 6A-6B, 7A-7B, and 8A-8C are schematic diagrams of substrates undergoing operation in certain disclosed embodiments.

[0028] Figure 9 is a schematic diagram of an exemplary processing chamber for performing certain disclosed embodiments.

[0029] Figure 10is a schematic diagram of an exemplary processing apparatus for performing certain disclosed embodiments. DETAILED DESCRIPTION

[0030] In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments presented. The disclosed embodiments may be practiced without some or all of these specific details. In other cases, well-known processing operations are not described in detail to avoid unnecessarily obscuring the disclosed embodiments. Although the disclosed embodiments will be described in conjunction with specific embodiments, it should be understood that they are not intended to limit the disclosed embodiments.

[0031] In semiconductor device manufacturing, masking methods are used to pattern and etch substrates. As the aspect ratio of substrates increases, the demand for highly selective hard masks increases. Various patterning schemes involve forming positive features, such as dielectric spacers, which serve as masks for etching target layers. However, some dielectric spacers may be susceptible to corrosion, especially when the aspect ratio of the gaps between the dielectric spacers is large and the gap depth may therefore be large, which may result in longer etching durations to etch the target layer below the dielectric spacers. As a result, some dielectric spacers may be corroded during the etching of the target layer.

[0032] There are methods to prevent corrosion of the etch mask during etching, but these methods involve a plasma-enhanced chemical vapor deposition (PECVD) process that can cause breadcrumb-like growth on the etch mask, reducing the critical dimensions of negative features between masks and altering feature profiles. This is a particular concern for features with very high aspect ratios and long etch runs.

[0033] For the formation of these masks, techniques involve alternating between etching the underlying layer (e.g., the target layer) and depositing additional mask material to address the issue of mask corrosion during the etching process. The operations involve different process gases and sometimes different tools, which extend the processing time as the wafer is transferred from one station to another, or even from one tool to another.

[0034] Provided herein are methods for depositing a mask over fields of a patterned substrate while substantially preserving critical dimensions of the mask. In various embodiments, deposition of the mask can be performed while selectively etching a target layer in negative features of the mask.

[0035] Deposition of the vertical growth mask described herein results in little or no horizontal deposition as the mask is deposited. That is, deposition on the fields of the positive substrate results in the sidewalls of the vertical growth mask being mostly vertical without changing the size of the spaces between the positive features of the patterned mask. Deposition occurs with essentially no deposition on the sidewalls of the positive substrate, and most or all of the deposition occurs only on the fields. As the mask grows vertically, additional deposited mask material is deposited in large quantities over the existing mask material, and the growth is essentially vertical. That is, little or no mask material is deposited on the sidewalls of the deposited mask, and the vertical growth mask can be grown to a variety of thicknesses suitable for specific applications. Deposition is selective in that it preferentially forms new material on the positive features, particularly on top of those features. Selective deposition can be performed in such a way that new material forms vertically on top of the positive features, without extending substantially horizontally. Thus, a particular advantage of certain disclosed embodiments is the ability to preserve the critical dimensions of features (i.e., the width of the space between positive features on which the vertical growth mask is deposited) such that the width of the deposited vertical growth mask is substantially the same as the underlying etch mask on which it is deposited. For clarity, the material on which the vertical growth mask is deposited will be referred to as the "underlying etch mask" or "etch mask," but it will be understood that a variety of materials, including polymeric materials, dielectrics, and semiconductor materials, can be used for the etch mask. It will be understood that the etch mask can be a patterned photoresist. It will also be understood that the etch mask can be a patterned antireflective coating, such as a bottom antireflective coating (BARC) or a dielectric antireflective coating (DARC). The term "vertical growth mask" is used to refer to a material deposited above the underlying etch mask that results in the preservation of the critical dimensions of the features as well as the width of the mask. An advantage of certain disclosed embodiments is the ability to avoid trimming or thinning the formed mask structure. Thinning or trimming is defined as a reduction in a critical dimension of more than 2% of the critical dimension, or a reduction in any concavity or roughness in the sidewalls.

[0036] The vertical growth mask can be a tungsten-containing material, such as tungsten metal. In many embodiments, the tungsten-containing material is not pure tungsten metal and may contain some impurities. Although tungsten is described herein as an example material, it should be understood that other metal-containing materials, or even metal-free materials, can be used to achieve vertical growth by employing appropriate reactants and process conditions.

[0037] Also disclosed herein is a method for depositing a vertical growth mask while etching an underlying layer during the same operation. The process conditions used to deposit the vertical growth mask can also be used to etch an underlying target material (e.g., an antireflective layer or an amorphous carbon layer) such that each exposure of the substrate to the process conditions (including but not limited to precursor gases, plasma conditions, temperature, and pressure) simultaneously causes the formation of the vertical growth mask over the underlying etch mask and the etching of the underlying target material below the underlying etch mask. In other words, a single process can simultaneously form the vertical mask over the field and etch the target material in the feature.

[0038] Disclosed embodiments include selecting a process window and the geometry of an underlying mask pattern to enable vertical growth of a vertical growth mask, etching of an underlying target material, or both.

[0039] Without being bound by a particular theory, it is believed that geometric selectivity, material selectivity, or both contribute to the ability of certain disclosed embodiments to achieve selective vertical growth and, in some cases, simultaneously etch the underlying target material. Geometric selectivity refers to selectivity achieved by depositing more material in one region of a substrate having a first geometric characteristic relative to another region of the substrate having a second geometric characteristic, where the region is defined as a location on the substrate based on the geometry or topography of the exposed substrate. This form of selectivity is based solely on geometry, without the need to use different materials to selectively enhance or inhibit deposition. The thicker deposition in one region relative to another region depends on the deposition rate (the thickness deposited in a time unit) in each region. Geometric selectivity can be achieved due to the aspect ratio of the negative features on the substrate and can result in a deposition rate on a field of the substrate (i.e., on either side of the feature opening of the negative feature) that is greater than the deposition rate on the sidewall or bottom region of the negative feature. It is believed that vertical growth can be achieved in certain disclosed embodiments due to the high aspect ratio of the negative features between the positive features defined by the underlying etch mask.

[0040] Material selectivity refers to the selectivity achieved by depositing more material on one material of a substrate relative to another material on the substrate due to differences in the chemistry, physics, morphology, etc. (composition, lattice structure, or any other properties) of the materials; that is, for example, the deposition rate on a dielectric material may be greater than the deposition rate on a conductive material. It is believed that vertical growth can be achieved in certain disclosed embodiments due to material selectivity between the surface of the underlying etch mask (or the surface of the deposited material of the vertical growth mask) and the surface of the target material below the underlying etch mask. In addition, when depositing a vertical growth mask, it is believed that vertical growth can be achieved in certain disclosed embodiments due to material selectivity between the surface of the deposited material of the vertical growth mask and the surfaces of both the underlying etch mask and the target material below the underlying etch mask. This form of selectivity is based solely on material differences, without the need for different surface geometries to selectively enhance or inhibit deposition. Of course, in some cases, selectivity can be imparted by a combination of geometric and compositional differences on the exposed surface.

[0041] Figure 1 is a process flow diagram illustrating operations performed according to certain disclosed embodiments.

[0042] In operation 120 , a patterned semiconductor substrate having a patterned etch mask over a target layer is provided.

[0043] The semiconductor substrate can be a silicon wafer, such as a 200 mm wafer, a 300 mm wafer, or a 450 mm wafer, including a wafer having one or more material layers (e.g., dielectric, conductive, or semiconductive materials) deposited thereon. Non-limiting examples of underlying layers include dielectric layers and conductive layers, such as silicon oxide, silicon nitride, silicon carbide, metal oxides, metal nitrides, metal carbides, and metal layers (e.g., copper, aluminum, tungsten, cobalt, ruthenium, molybdenum, tantalum, etc.).

[0044] The patterned etch mask is sometimes referred to herein as a "underlying etch mask". The patterned etch mask can include spaced positive features (as opposed to recesses). During etching, the spaced features are transferred to a target layer of the substrate directly above or on an intermediate layer above the target layer. The size of the positive feature can be characterized as a critical dimension, which is the width measured horizontally across the entire positive feature at the shortest distance from one side wall to the other side wall in a cross-section of the positive feature. Each positive feature includes a sidewall and an exposed field. The exposed field is the top horizontal area of the feature. The field can be defined by a mask previously used to pattern the patterned etch mask (e.g., a patterned photoresist); during etching, the mask used to pattern the patterned etch mask is removed, leaving the exposed field of the patterned etch mask features. In various embodiments, the average critical dimension of the positive features on the substrate is between about 10 nm and about 200 nm.

[0045] The distance separating adjacent features is the spacing of the features, which is measured from the center of the first space between the positive features of the mask to the center of the adjacent space on the other side of the positive feature. The distance between the positive features may be referred to herein as a "negative feature" having a "negative feature opening" measured horizontally across the space between the two positive features, as measured from the sidewall of the positive feature to the sidewall of the adjacent positive feature. In certain embodiments, the average aspect ratio of the negative features is at least about 1:1, or between about 50:1 and about 100:1. It should be understood that in some embodiments, there may be various feature sizes and / or aspect ratios across the entire surface of the substrate. It should also be understood that in some embodiments, there may be identical and / or similar feature sizes across the entire surface of the substrate.

[0046] In certain embodiments, the patterned etch mask has an average thickness of about 5 nm to about 3000 nm. The average thickness of the patterned etch mask is measured by taking the average of the thickness measured vertically from the field of the positive feature of each feature to the top of the layer immediately below the mask.

[0047] In certain embodiments, the patterned etch mask is a dielectric material, silicon, carbon, or a polymer material.

[0048] In some embodiments, the dielectric material comprises silicon oxide, silicon nitride, silicon oxynitride (SiON), or a combination thereof. The dielectric material can be deposited using a thermal technique or a plasma-assisted technique using a silicon-containing precursor and one or more oxygen-containing and / or nitrogen-containing reactants. As an example, the dielectric material can be etched using a fluorocarbon-containing chemistry and optionally a plasma.

[0049] "Silicon oxide" herein refers to x O yAny and all stoichiometric possibilities, including integer values of x and y and non-integer values of x and y. For example, "silicon oxides" include compounds having the formula SiO n where 1 < n < 2, where n can be an integer value or a non-integer value. "Silicon oxides" can include, for example, substoichiometric compounds such as SiO 1.8 . "Silicon oxides" also include silicon dioxide (SiO2) and silicon monoxide (SiO). "Silicon oxides" also include natural and synthetic variants and also include any and all crystal and molecular structures, including tetrahedral coordination of oxygen atoms around a central silicon atom. "Silicon oxides" also include amorphous silicon oxides and silicates.

[0050] "Silicon nitrides" as used herein refer to any and all stoichiometric possibilities including integer values of x and y and non-integer values of x and y, such as x = 3 and y = 4. For example, "silicon nitrides" include compounds having the formula SiN x N y where 1 < n < 2, where n can be an integer value or a non-integer value. "Silicon nitrides" can include, for example, substoichiometric compounds such as SiN n . "Silicon nitrides" also include Si3N4 and silicon nitrides with trace and / or interstitial hydrogen (SiNH) and silicon nitrides with trace and / or interstitial oxygen (SiON). "Silicon nitrides" also include natural and synthetic variants and also include any and all lattice, crystal and molecular structures, including trigonal alpha-silicon nitride, hexagonal beta-silicon nitride, and cubic gamma-silicon nitride. "Silicon nitrides" also include amorphous silicon nitrides and can include silicon nitrides with trace impurities.

[0051] In some embodiments, the polymeric material has the chemical formula C x H y [[ID=2,6]]O z and can be pre-deposited by spin coating and patterned using an etch chemistry including oxygen and fluorocarbon gas and / or plasma. In some embodiments, the polymeric material is a photoresist patterned by exposure to radiation and developed using a lithography technique such as EUV lithography.

[0052] In some embodiments, the patterned etch mask is a patterned photoresist.

[0053] ​​In some embodiments, the patterned etch mask can be patterned in advance using a developed photoresist as a mask. In some embodiments, the patterned etch mask can be or include an antireflective layer. For example, the patterned etch mask can be a BARC layer, or can be a DARC layer.

[0054] In operation 140, a vertical growth mask is deposited over the exposed areas of the patterned etch mask. The vertical growth mask is deposited using precursors and process conditions that increase the deposited thickness of the mask over time, but substantially does not deposit on the sidewalls of the patterned etch mask or the sidewalls of the vertical growth mask as the mask is deposited. This behavior may be referred to as "vertical growth," but it should be understood that "vertical" is only used as a term to describe the phenomenon when the substrate is positioned horizontally with its active surface. In some embodiments, the precursors and process conditions may be selected to adjust the profile of the material deposited in the vertical growth mask. In some embodiments, the vertical growth mask is a patterned tungsten-containing mask.

[0055] The vertical growth mask may be a metal-containing material or a non-metallic material. Examples of materials for the vertical growth mask include silicon-containing materials such as silicon, carbon-containing materials, boron-containing materials, titanium-containing materials, ruthenium-containing materials, and tungsten-containing materials such as tungsten metal or tungsten-doped metals.

[0056] The vertical growth mask can be deposited by introducing one or more process gases and igniting a plasma. The one or more process gases used depend on the material to be deposited on the vertical growth mask. In various embodiments, the one or more process gases include a metal-containing gas. In some embodiments, the metal-containing gas is a metal halide. In some embodiments, the metal-containing gas is a metal carbonyl gas. The metal-containing gas may include a tungsten-containing gas. Examples of tungsten-containing gases include tungsten halides, such as tungsten pentachloride, tungsten hexachloride, tungsten pentafluoride, and tungsten pentachloride. In some embodiments, the metal-containing gas includes a titanium-containing gas, such as titanium chloride (TiCl4). In some embodiments, the metal-containing gas includes a ruthenium-containing gas, such as triruthenium dodecacarbonate (Ru3(CO) 12 ). In various embodiments, the one or more process gases include a carbon-containing gas or a boron-containing gas. Examples of carbon-containing gases include methane (CH4), acetylene (C2H2), and propylene (C3H6). Exemplary boron-containing gases include diborane (B2H6). In various embodiments, a tungsten-containing gas is used to deposit a tungsten-containing vertical growth mask. In various embodiments, a carbon-containing gas is used to deposit a carbon-containing vertical growth mask. In various embodiments, a boron-containing gas is used to deposit a boron-containing vertical growth mask. In various embodiments, a titanium-containing gas is used to deposit a titanium-containing vertical growth mask. In various embodiments, a ruthenium-containing gas is used to deposit a ruthenium-containing vertical growth mask.

[0057] In some embodiments, the plasma is ignited in an environment with one or more process gases. For example, in some embodiments, the plasma can be ignited in a tungsten-containing gas environment. Although plasma-based deposition processes are described herein, in some embodiments, plasma-free thermal processes can be used by selecting process conditions (e.g., chamber pressure, gas flow rates, temperature, etc.).

[0058] In some embodiments, the one or more process gases include a non-metallic gas, such as a silicon-containing gas or a carbon-containing gas, depending on the material of the vertical growth mask.

[0059] The one or more process gases used to deposit the vertical growth mask can be delivered along with one or more carrier gases and / or diluent gases. In some embodiments, the carrier gas can be transferred prior to delivery to the processing chamber housing the substrate. In some embodiments, the carrier gas is delivered to the processing chamber along with the one or more process gases. Exemplary carrier gases include argon, hydrogen, helium, and combinations thereof.

[0060] A dilution gas, which can be composed of the same composition as the carrier gas, can be used with the process gas used to deposit the vertical growth mask or introduced as a separate operation. The dilution gas can be used to limit etching or trimming by halogen species that can be deposited by decomposing metal halides. The dilution gas can be ignited with a plasma to facilitate the removal of halogen species.

[0061] The composition of the gases delivered to deposit the vertical growth mask can affect the deposition profile of the deposited vertical growth mask. Specifically, the ratio of the process gases can be used to adjust the directionality and growth rate of the vertical growth mask. For example, in some embodiments, the ratio of tungsten hexafluoride to hydrogen is between about 1:0 and about 1:5 to achieve a critical dimension of the vertically deposited vertical growth mask within about 150% of the critical dimension of the patterned etch mask.

[0062] Specifically, in some embodiments, the vertical growth mask can be deposited by introducing a mixture of tungsten hexafluoride with argon and hydrogen and igniting the plasma.

[0063] The plasma is ignited using process conditions including, but not limited to, plasma power and frequency, the conditions being selected such that, over time, exposure of fields of the patterned mask to the plasma in the process gas environment results in an increase in thickness of the vertical growth mask, wherein a critical dimension of the vertical growth mask is substantially the same as a critical dimension of the patterned etch mask, e.g., within about 10% or within about 5%.

[0064] In some embodiments, plasma is ignited, and the treatment gas reacts with the field of the patterned etch mask to perform a deposition process. In some embodiments, the treatment gas reacts with the substrate or is adsorbed onto the surface of the field of the patterned etch mask. In various embodiments, deposition is preferential or selective so that deposition occurs faster on the field of the patterned etch mask than on the sidewalls of the patterned etch mask. In some embodiments, there is substantially no deposition on the sidewalls of the patterned etch mask. In various embodiments, the treatment gas is introduced into the chamber in a gaseous form and may optionally be accompanied by a carrier gas such as argon, helium, hydrogen, or a combination thereof. The substances produced by the treatment gas plasma can be directly produced by forming a plasma in a processing chamber that accommodates the substrate, or they can be remotely produced in a processing chamber that does not accommodate the substrate and can be supplied to the processing chamber that accommodates the substrate.

[0065] In some embodiments, the plasma is formed in situ such that the plasma is formed directly on the surface of the substrate in the chamber. In various embodiments, the plasma is an inductively coupled plasma or a capacitively coupled plasma. In some embodiments, a bias voltage between about 0 V and about 500 V is applied to a pedestal supporting the substrate to cause the charged plasma species to travel directionally toward the substrate.

[0066] In various embodiments, the plasma power for a single wafer is between about 100 W and about 500 W. The plasma can be generated using high frequency and / or low frequency plasma.

[0067] During operation 140, the substrate temperature may be set to a temperature between about 20° C. and about 80° C. It should be understood that the substrate temperature is the temperature set for the pedestal supporting the semiconductor substrate in order to heat or cool the substrate itself, and is not necessarily the exact temperature of the substrate itself at any given time.

[0068] Operation 140 can be performed in a process chamber set to a chamber pressure between about 10 mTorr and about 100 mTorr. It will be appreciated that the pressure can be adjusted as needed to achieve a deposition rate and a particular deposition profile. In some embodiments, the pressure is adjusted to achieve substantial vertical growth such that the critical dimension of the vertical growth mask is within about 150% of the critical dimension of the patterned etch mask.

[0069] In various embodiments, to deposit the vertical growth mask, the deposition rate, deposition profile, and directionality of the deposition (i.e., achieving certain shapes of the deposited vertical growth mask) are achieved by adjusting process conditions such as plasma power, chamber pressure, substrate temperature, and / or gas flow composition and / or flow rate and / or ratio of flow rates of the flowing gases. The selectivity of the deposition also depends on the material on which the vertical growth mask is deposited and other exposed areas of the substrate.

[0070] For example, a tungsten vertical growth mask can be deposited on a DARC material relative to an exposed carbon-containing material. Specifically, a tungsten vertical growth mask can be deposited on a silicon oxynitride material relative to an exposed amorphous carbide material. In some embodiments, a vertical growth mask can be deposited on a polymer BARC material relative to a DARC material.

[0071] Selective deposition can also be achieved using specific feature geometries. For example, the aspect ratio of the spaces between the positive features of the patterned etch mask before deposition can be in the range of about 50:1 to about 200:1. Selective deposition of the vertical growth mask can be achieved when the width of the negative features between the positive features of the patterned etch mask before deposition is between about 10 nm and about 200 nm. Selective deposition of the vertical growth mask can be achieved when the depth of the negative features between the positive features of the patterned etch mask is at least about 20 nm.

[0072] Operation 140 may be performed by simultaneously introducing one or more process gases and one or more carrier gases and igniting a plasma in a plasma enhanced chemical vapor deposition type process.

[0073] In a plasma enhanced atomic layer deposition (PEALD) type process, operation 140 may be performed by introducing one or more process gases and one or more carrier gases in alternating pulses and igniting a plasma during the introduction of at least one of the process gases or the carrier gases or both.

[0074] Alternating pulse deposition is performed by repeating cycles. A cycle may include a pulse of a first gas and a pulse of a second, different gas, wherein the second gas does not flow during the pulse of the first gas and the first gas does not flow during the pulse of the second gas.

[0075] In one example, the deposition cycle performed during operation 140 is a pulse of tungsten hexafluoride and a pulse of an argon / hydrogen mixture.

[0076] Each pulse in a deposition cycle can be of a specific duration. The pulses of the first gas and the pulses of the second gas can have different durations. The pulses of the first gas and the second gas can have the same duration. In one example, the pulses of tungsten hexafluoride can be between about 100 milliseconds and about 10 seconds, while the pulses of the argon / hydrogen mixture can be between about 100 milliseconds and about 10 seconds.

[0077] In some embodiments, the second gas is used to clean or treat the substrate. For example, in some embodiments, prolonged exposure of a particular patterned etch mask to tungsten hexafluoride can cause degradation of the patterned etch mask, and / or prolonged exposure of an underlying target layer can cause degradation of the target layer. Alternating the introduction of tungsten hexafluoride with the introduction of a carrier gas or carrier gas mixture that can clean the substrate surface can prevent unwanted etching or trimming of the patterned etch mask and target layer. During the carrier gas pulses, a plasma can be ignited.

[0078] In various embodiments of cyclic deposition, multiple cycles of alternating pulses of process gas and carrier gas are performed, for example, at least about 2 cycles, or between about 3 cycles and about 20 cycles. Additionally, because the duration of each pulse can vary, the number of cycles can depend on the duration of each pulse and the desired thickness of the vertical growth mask.

[0079] In some embodiments, process conditions may vary from cycle to cycle, depending on the desired deposition profile.

[0080] Back to Figure 1 In operation 160, the target layer located below the patterned etch mask is etched using the patterned etch mask and the deposited vertical growth mask as masks. The patterned etch mask and the deposited vertical growth mask have similar critical dimensions, while the spacing remains the same, and the space between the features of the mask is substantially flanked by sidewalls comprising the patterned etch mask material and the vertical growth mask material. Etching is performed using these features as masks, and using a chemical that is selective for etching the target layer so that the etch rate of the target layer is substantially greater than the etch rate of the vertical growth mask. The etch rate depends on the composition of the etching gas used and the process conditions. The etching gas depends on the material of the target layer and the depth to which the target layer may be etched.

[0081] In one example, the target layer is an amorphous carbon layer, and the etching gas used includes a gas having a chemical formula of C x F y H z wherein x is 1-4, y is 1-8, and z is 1-6. A plasma may be ignited during etching. For a single wafer, the plasma may be ignited using a plasma power between about 50 W and about 3000 W. The etch rate of amorphous carbon etched using CF4 plasma ignited using a plasma power of 300 W may be at least about 1.5 times the etch rate of a tungsten vertical growth mask.

[0082] Although the etching can be selective, such that the target layer is etched faster than the mask, it should be understood that in some embodiments, the vertical growth mask may degrade with prolonged exposure to the etching chemistry used for the target layer. In various embodiments, the etching of the target layer can be temporarily stopped by repeating operation 140 to deposit additional vertical growth mask before continuing etching in operation 160.

[0083] In some embodiments, operations 140 and 160 are performed simultaneously. That is, in some embodiments, deposition of the vertical growth mask can occur while etching the target layer by introducing a selection of process gases and adjusting process conditions including temperature and plasma power to reduce consumption of the vertical growth mask while etching the target layer. Specific examples are further described below.

[0084] There are several advantages to simultaneously etching the target layer and depositing the vertical growth mask. First, the gas used to deposit the vertical growth mask can be delivered to the same chamber used to etch the target layer, flowing simultaneously with the etching gas used to etch the target layer, thereby improving efficiency and avoiding the need to move the wafer between chambers, between workstations, or even between tools used to form the mask and etch the target layer. Second, because the vertical growth mask deposition gas chemistry is introduced continuously, there is little or no risk of mask degradation while etching the target layer. This allows for the etching of very thick materials, which involves prolonged exposure to etching chemicals during the etching of very thick materials, without degrading the mask. For example, the thickness of the target layer to be etched can be between about 500 nm and about 5000 nm. Third, the process conditions are carefully adjusted so that the deposited vertical growth mask has a critical dimension that is substantially the same as the critical dimension of the patterned etch mask. Therefore, even if the target layer is exposed to the deposition gas of the vertical growth mask, the vertical growth mask is only deposited on the field of the patterned etch mask or on the field of the deposited vertical growth mask, and rarely or never deposited on the sidewalls of the space between the patterned etch mask or the vertical growth mask.

[0085] Simultaneously etching and depositing a vertical growth mask involves adjusting process conditions and gas flows to achieve a tolerable etching rate for the target layer while maintaining the thickness of the vertical growth mask to prevent degradation during etching of the target layer. In some embodiments, performing operations 140 and 160 simultaneously involves introducing one or more gases suitable for etching the target layer and one or more gases suitable for depositing the vertical growth mask together. The one or more gases suitable for etching the target layer have been described above with respect to operation 160. The one or more gases suitable for depositing the vertical growth mask have been described above with respect to operation 140. In some embodiments, the one or more gases suitable for etching the target layer include fluorocarbon gases. In some embodiments, the one or more gases suitable for depositing the vertical growth mask include tungsten-containing gases. In various embodiments, the ratio of the fluorocarbon gas flow rate to the tungsten-containing gas flow rate affects the etching rate of the target layer and the deposition rate of the vertical growth mask. In various embodiments, where the target layer is amorphous carbon and the vertical growth mask is a tungsten mask deposited on a SiON patterned etch mask, the ratio of the carbon tetrafluoride gas flow rate to the tungsten hexafluoride gas flow rate is between about 20:1 and about 1:1. In some embodiments, the fluorocarbon gas is delivered at a flow rate less than about 80% of the total flow rate of all delivered gases. In various embodiments, simultaneous etching and deposition can result in a net etch rate of 1 nm / sec for the target layer with a net deposition rate of 0.5 nm / sec for the vertical growth mask.

[0086] In one example, the target layer is amorphous carbon, and the vertical growth mask is a tungsten mask deposited on a SiON patterned etch mask (having a critical dimension of 50 nm). The vertical growth mask is deposited by performing three cycles at a substrate temperature of 60° C. and a chamber pressure of 20 mTorr. Each cycle includes a pulse of tungsten hexafluoride (at a flow rate of 30 sccm and a duration of 10 seconds) and a pulse of argon / hydrogen plasma (wherein the argon flow rate is 200 sccm and the hydrogen flow rate is 200 sccm). The plasma is ignited at a plasma power of 300 W at a substrate temperature of 60° C. and a chamber pressure of 20 mTorr. The deposited vertical growth mask has a critical dimension of 50 nm and a thickness of 50 nm, and is not deposited on the sidewalls of the SiON patterned etch mask.

[0087] In another example, the target layer is amorphous carbon, and the vertical growth mask is a tungsten mask deposited on a SiON patterned etch mask (having a critical dimension of 50 nm). The amorphous carbon layer is etched while the vertical growth mask is being deposited by introducing tungsten hexafluoride at a flow rate of approximately 10 sccm, introducing a fluorocarbon gas (e.g., CH2F2 and SF6) at a flow rate of 50 sccm, and igniting a helium plasma, wherein the helium flow rate is 300 sccm, the plasma power is 300 W, the substrate temperature is 40° C., and the chamber pressure is 10 mTorr. The deposited vertical growth mask has a critical dimension of 50 nm and a thickness of 50 nm, is not deposited on the sidewalls of the SiON patterned etch mask, and the amount of the etched amorphous carbon layer is less than about 10 nm. .

[0088] In some embodiments, operations 140 and 160 may be performed alternately, sequentially, or by repeating a cycle comprising operation 140 followed by operation 160 multiple times. In some embodiments, operation 140 is performed after operation 160 is performed for a duration such that operation 140 acts to compensate for the vertical growth mask that has degraded during operation 160.

[0089] Specific examples are described further below.

[0090] Figure 2 are process flow diagrams illustrating operations performed according to certain disclosed embodiments. Figure 2 An exemplary process flow is provided for transferring a pattern of a patterned photoresist to an antireflective layer and selectively depositing a vertical mask on the patterned antireflective mask to form a multilayer mask including both the antireflective layer and the vertical mask, and etching a target layer using the multilayer mask.

[0091] In operation 220, a patterned semiconductor substrate having a patterned photoresist on an antireflective layer over a target layer is provided. It should be understood that in some embodiments, there may be more than one antireflective layer and other layers such as capping layers, barrier layers, etc. on the substrate.

[0092] Figure 3 is a schematic diagram of an exemplary semiconductor substrate that may be provided in operation 220. Although specific materials are described herein and Figure 3 A specific stack is depicted in FIG, but it should be understood that the stack may be Figure 2 In operation 220 , another semiconductor substrate is provided.

[0093] Figure 3The target layer 300 includes a target layer 300, which can be any suitable material. In some embodiments, the target layer 300 can be an amorphous carbon layer. Above the target layer 300 is a DARC layer 302, which in some embodiments can be a silicon-containing material, such as any one or more of silicon oxide, silicon nitride, and silicon oxynitride. Above the DARC layer 302 is a BARC layer 305, which can be a polymer material deposited by spin coating. The top surface of the BARC layer 305 includes a patterned photoresist 307, which can be photolithographically patterned and contain silicon, carbon, or both.

[0094] Back to Figure 2 In operation 230, the anti-reflective layer is etched to form a patterned etch mask. Operation 230 may involve providing one or more etching gases suitable for etching the anti-reflective layer, depending on the material of the layer, and optionally igniting a plasma and applying a bias. The etch is selective to the underlying layer of the anti-reflective layer to prevent etching of the underlying layer.

[0095] Figure 4 and Figure 5 A schematic diagram of an exemplary semiconductor substrate after etching the anti-reflective layer in operation 230 is shown. Figure 4 A substrate having a target layer 300 and a DARC layer 302 is shown, wherein Figure 3 The BARC layer 305 is etched to form a patterned BARC layer 405. This forms a patterned etch mask including the patterned BARC layer 405, which can then be used to etch underlying layers such as the DARC layer 302.

[0096] In some embodiments, operation 230 further includes etching the DARC layer 302 . Figure 5 The substrate with the target layer 300 is shown after etching the BARC layer 305 to form the patterned BARC layer 405 and etching the DARC layer 302 to form the patterned DARC layer 502. The patterned photoresist 307 is removed and / or degraded by etching the different anti-reflective layers. This forms a patterned etch mask that includes both the patterned BARC layer 405 and the patterned DARC layer 502.

[0097] return Figure 2 In operation 240, a vertical growth mask is deposited on the exposed areas of the patterned etch mask formed in operation 230. Operation 240 may be performed using any suitable process gas, process conditions, and methods consistent with those described above. Figure 1 For example, the vertical growth mask may be deposited using one or more cycles of alternating pulses of a tungsten-containing precursor and an argon and hydrogen mixture while the plasma is ignited.

[0098] Figure 6A and 6B An example is shown in which a vertical mask for deposition is selectively formed without depositing on the target layer 300 and without etching the target layer 300 . Figure 6A Shows the successor Figure 5 The substrate is then formed so that the substrate includes the target layer 300, the patterned BARC layer 405, and the patterned DARC layer 502. A vertical growth mask 600, which may be tungsten, is deposited over the field of the patterned BARC layer 405, with little or no deposition on the sidewalls of the patterned BARC layer 405 or the patterned DARC layer 502, or on the exposed surface of the target layer 300.

[0099] Figure 6B Shown in Figure 2 Operation 240 is performed for a period of time sufficient to form a thicker vertical growth mask 620. Figure 6B As shown, the substrate can be exposed to processing gases and process conditions to achieve selective vertical deposition of the vertical mask 620, but not deposition on the sidewalls of the patterned BARC layer 405 or the patterned DARC layer 502 or on the exposed surface of the target layer 300. The critical dimensions of the thicker vertical growth mask 620 are approximately the same as the critical dimensions of the patterned DARC layer 502 and the patterned BARC layer 405.

[0100] Back to Figure 2 In operation 260, the target layer 300 is etched using the patterned etching mask and the vertical mask as masks. Figure 1 Operation 260 may be performed using any suitable process gases, process conditions, and other characteristics as described with respect to operation 160 .

[0101] as Figure 1 Like the deposition and etching operations in FIG, operations 240 and 260 may also be performed simultaneously, or may be performed in separate operations and may be repeated for multiple cycles. The variations of simultaneous, sequential, and repeated operations of operations 140 and 160 described above may also be applied to operations 240 and 260.

[0102] Figure 7A and 7B An example is shown in which, while etching a target layer, a deposited vertical mask is selectively formed and is not deposited on the target layer, nor is the target layer etched.

[0103] Figure 7A Display Figure 5The substrate is then formed so that the substrate includes the target layer 300, the patterned BARC layer 405, and the patterned DARC layer 502. A vertical growth mask 700 (which may be tungsten) is deposited over the field of the patterned BARC layer 405, with little or no deposition on the sidewalls of the patterned BARC layer 405 or the patterned DARC layer 502, or on the exposed surface of the target layer 300.

[0104] Figure 7B A substrate is shown, wherein Figure 2 Operations 240 and 260 are performed simultaneously for a duration sufficient to substantially etch the target layer 300 to form negative features 702 in the target layer 300, thereby forming an etch target layer 307, while maintaining and / or increasing the thickness of the vertical growth mask 700. Continuous exposure to both the gas used to deposit the vertical growth mask 700 and the gas used to etch the target layer 300 can be used to achieve this result. Figure 7B The thickness of the vertical growth mask 700 is depicted as being approximately the same as Figure 7A , but it should be understood that in some embodiments, the thickness will be different after continued exposure to both the etching gas used to etch the target layer 300 and the gas used to deposit the vertical growth mask 700.

[0105] Figure 8A and 8B An example is shown in which deposition of a vertical mask and etching of a target layer are performed in a cyclic process in an alternating pulse manner. The vertical mask is selectively formed and is neither deposited on the target layer nor etches the target layer.

[0106] Figure 8A Shows the following Figure 5 The substrate after performing operation 260 is exposed to an etchant used to etch the target layer 300 using the patterned BARC layer 405 and the patterned DARC layer 502 as a mask, thereby forming a partially etched target layer 308. In this operation, the amount of target layer 300 etched is indicated by arrow 801, while some material of the vertical growth mask 800 may be etched, resulting in an etched vertical growth mask 810. This situation may occur where the etch rate of the vertical growth mask 800 is much slower than the etch rate of the target layer 300, but the exposure duration is long enough to etch some of the vertical growth mask 800.

[0107] Figure 8B Shows the following Figure 8AAnd on the substrate after repeatedly performing operation 240, operation 240 is performed to supplement the vertical growth mask 820 without etching the portion of the etch target layer 308 or depositing a vertical growth mask material such as tungsten on the sidewalls of the patterned BARC layer 405, the patterned DARC layer 502, or on the surface of the portion of the etch target layer 308.

[0108] Figure 8C Shows the following Figure 8B And after repeating operation 260, the substrate is further etched by repeating operation 260 to form an additionally etched target layer 318, so that additional thickness is removed, as shown by arrow 802. The etching can also further remove some of the supplementary vertical growth mask 820 to form a further etched vertical growth mask 821. Operations 240 and 260 can be repeated in an alternating cycle to continue etching the target layer and replenishing the vertical growth mask at the same time. In some embodiments, the vertical growth mask is deposited to a sufficient thickness so that redeposition of the vertical growth mask does not need to be performed. In some embodiments, the vertical growth mask is deposited to a certain thickness so that redeposition of the vertical growth mask is performed only once for each thickness of the etched target layer, and each thickness of the etched target layer can vary depending on the composition and thickness of the deposited vertical growth mask. In some embodiments, it is possible to deposit a thick vertical growth mask and then etch the target layer without having to deposit an additional vertical growth mask, especially if the etch chemistry is highly selective for etching the target layer relative to the vertical growth mask.

[0109] The various embodiments described herein can be used in a variety of applications, including extreme ultraviolet (EUV) patterning, 3D NAND mask etching (e.g., etching of carbon-containing materials or doped carbon-containing materials), and stamping applications. An example of a stamping application is a process for etching high aspect ratio hole and trench patterns to "stamp" the target film at the bottom of the hole or trench and minimize film loss at the top of the feature. Some of the examples provided herein for etching carbon-containing layers on stacks having BARC and DARC layers may be relevant to EUV patterning processes.

[0110] Device

[0111] In certain embodiments, an inductively coupled plasma (ICP) reactor may be suitable for performing certain disclosed embodiments, including deposition with a vertical mask and etching of a target layer using the vertical mask. Such an ICP reactor is also described in U.S. Patent Application Publication No. 2014 / 0170853, filed December 10, 2013, entitled "IMAGEREVERSAL WITH AHM GAP FILL FOR MULTIPLEPATTERNING," which is incorporated herein by reference in its entirety and for all purposes. Although an ICP reactor is described herein, it should be understood that a capacitively coupled plasma reactor may also be used in some embodiments.

[0112] Figure 9 A cross-sectional view of an inductively coupled plasma integrated etching and deposition apparatus 900 suitable for practicing certain embodiments herein is schematically shown, exemplified by a Kiyo TM The inductively coupled plasma apparatus 900 includes a main processing chamber 901 structurally defined by chamber walls 901 and a window 911. The chamber walls 901 may be made of stainless steel or aluminum. The window 911 may be made of quartz or other dielectric materials. An optional internal plasma grid 950 divides the main processing chamber 901 into an upper sub-chamber 902 and a lower sub-chamber 903. In most embodiments, the plasma grid 950 may be removed, thereby utilizing the chamber space formed by the sub-chambers 902 and 903. A chuck 917 is positioned in the lower sub-chamber 903 near the bottom inner surface. The chuck 917 is configured to receive and hold a semiconductor wafer 919 on which etching and deposition processes are performed. The chuck 917 may be an electrostatic chuck for supporting the wafer 919 when the wafer 919 is present. In some embodiments, an edge ring (not shown) surrounds the chuck 917 and has an upper surface that is approximately coplanar with the top surface of the wafer 919 (when the wafer is present on the chuck 917). The chuck 917 also includes electrostatic electrodes for clamping and releasing the wafer. A filter and a DC clamp power source (not shown in the figure) can be provided for this purpose. Other control systems can also be provided for lifting the wafer 919 off the chuck 917. The chuck 917 can be charged with an RF power supply 923. The RF power supply 923 is connected to the matching circuit 921 via a connector 927. The matching circuit 921 is connected to the chuck 917 via a connector 925. In this manner, the RF power supply 923 is connected to the chuck 917.

[0113] Elements for plasma generation include a coil 933 located above the window 911. In some embodiments, no coil is used in the disclosed embodiments. The coil 933 is made of a conductive material and includes at least one full turn. Figure 9The example of coil 933 shown in FIG includes three turns. A cross-section of coil 933 is shown symbolically, with coils having an "X" symbol indicating that the coil extends rotationally into the page, and conversely, coils having a "●" symbol indicating that the coil extends rotationally out of the page. Elements for plasma generation also include an RF power supply 941 configured to provide RF power to coil 933. Generally, RF power supply 941 is connected to matching circuit 939 via connector 945. Matching circuit 939 is connected to coil 933 via connector 943. In this manner, RF power supply 941 is connected to coil 933. An optional Faraday shield 949 is positioned between coil 933 and window 911. Faraday shield 949 is maintained in a spaced relationship relative to coil 933. Faraday shield 949 is positioned directly above window 911. Coil 933, Faraday shield 949, and window 911 are each configured to be substantially parallel to one another. The Faraday shield can prevent metal or other substances from being deposited on the dielectric window of the plasma chamber 901 .

[0114] Processing gases (e.g., metal halides such as tungsten hexafluoride, argon, hydrogen, fluorocarbons, etc.) can be introduced into the processing chamber 901 through one or more main gas inlets 960 and / or through one or more side gas inlets 970 located in the upper chamber 902. Similarly, although not explicitly shown, similar gas inlets can be used to supply processing gases to the capacitively coupled plasma processing chamber. A vacuum pump, such as a single-stage or two-stage dry mechanical pump and / or turbomolecular pump 940, can be used to pump processing gases from the processing chamber 901 and maintain the pressure within the processing chamber 901. For example, during a purge operation, the same pump that may be used to purge the chamber can be used to evacuate the chamber 901 to prevent halogen species from trimming or etching the mask. A valve-controlled conduit can be used to fluidically connect the vacuum pump to the processing chamber 901 to selectively control the application of the vacuum environment provided by the vacuum pump. During the operation of the plasma process, this can be achieved using a closed-loop controlled flow restriction device, such as a throttle valve (not shown) or a pendulum valve (not shown). Similarly, a vacuum pump and valve that are controlled and fluidically connected to the capacitively coupled plasma processing chamber can also be used.

[0115] During operation of the device, one or more process gases may be supplied through the gas inlet 960 and / or 970. In certain embodiments, the process gas may be supplied only through the main gas inlet 960, or only through the side gas inlet 970. In some cases, the gas inlet shown in the figure may be replaced by a more complex gas inlet, for example, by one or more nozzles. The Faraday shield 949 and / or the optional grid 950 may include internal channels and holes that enable the process gas to be delivered to the chamber 901. One or both of the Faraday shield 949 and the optional grid 950 may serve as a nozzle for delivering the process gas. In some embodiments, the liquid evaporation and delivery system may be located upstream of the chamber 901 so that once the liquid reactant or precursor is evaporated, the evaporated reactant or precursor is introduced into the chamber 901 through the gas inlet 960 and / or 970.

[0116] RF power is supplied to the coil 933 from the RF power supply 941, causing RF current to flow through the coil 933. The RF current flowing through the coil 933 generates an electromagnetic field surrounding the coil 933. This electromagnetic field generates an induced current within the upper sub-chamber 902. The generated ions and radicals interact physically and chemically with the wafer 919, selectively etching features of the wafer and depositing layers on the wafer.

[0117] If a plasma grid is used so that both an upper sub-chamber 902 and a lower sub-chamber 903 exist, an induced current acts on the gas present in the upper sub-chamber 902 to generate an electron-ion plasma in the upper sub-chamber 902. An optional internal plasma grid 950 limits the amount of hot electrons in the lower sub-chamber 903. In some embodiments, the apparatus is designed and operated so that the plasma present in the lower sub-chamber 903 is an ion-ion plasma.

[0118] Both the upper electron-ion plasma and the lower ion-ion plasma may contain cations and anions, but the ion-ion plasma will have a greater ratio of anions to cations. Volatile etching and / or deposition byproducts may be removed from the lower sub-chamber 903 via port 922. The chuck 917 disclosed herein may operate within an elevated temperature range between about 10° C. and about 250° C. This temperature will depend on the process operation and the specific recipe.

[0119] When installed in a clean room or manufacturing facility, chamber 901 can be coupled to a facility (not shown). The facility includes piping that provides process gases, vacuum, temperature control, and environmental particle control. These facilities are coupled to chamber 901 when installed in the target manufacturing facility. In addition, chamber 901 can be coupled to a transfer chamber, allowing semiconductor wafers to be transferred in and out of chamber 901 by a robot using typical automation.

[0120] In some embodiments, a system controller 930 (which may include one or more physical or logical controllers) controls some or all of the operations of the process chamber. The system controller 930 may include one or more memory devices and one or more processors. In some embodiments, the apparatus includes a switching system for controlling flow rate and duration when performing the disclosed embodiments. In some embodiments, the apparatus may have a switching time of up to about 500 ms or up to about 750 ms. The switching time may depend on the flow chemistry, formulation selection, reactor architecture, and other factors.

[0121] In some implementations, the controller 930 is part of a system, which can be part of the examples described above. Such a system can include semiconductor processing equipment that includes one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems can be integrated with electronics for controlling their operation before, during, and after processing of semiconductor wafers or substrates. The electronics can be referred to as a "controller" that can control various components or subcomponents of one or more systems. Depending on the processing parameters and / or system type, the controller 930 can be programmed to control any of the processes disclosed herein, including controlling the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transport to and from tools and other transport tools and / or load locks connected to or interfaced with a particular system.

[0122] In a broad sense, the controller 930 can be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits can include chips in the form of firmware that stores program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). The program instructions can be instructions delivered to the controller in the form of various separate settings (or program files) that define operating parameters for performing a particular process on or for a semiconductor wafer or system. In some embodiments, the operating parameters can be part of a recipe defined by a process engineer to complete one or more process steps during the manufacture of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or the die of the wafer.

[0123] In some implementations, the controller 930 can be part of or coupled to a computer that is integrated with, coupled to, or otherwise networked to the system, or a combination thereof. For example, the controller can be in the "cloud" or in all or part of a wafer fab host system, which can allow remote access to wafer processing. The computer can enable remote access to the system to monitor the current progress of manufacturing operations, review the history of past manufacturing operations, study trends or performance metrics from multiple manufacturing operations, change parameters of the current process, set processing steps to follow the current process, or start a new process. In some examples, a remote computer (e.g., a server) can provide process recipes to the system via a network (which can include a local network or the Internet). The remote computer can include a user interface that enables the input or programming of parameters and / or settings, which are then transmitted from the remote computer to the system. In some examples, the controller 930 receives instructions in the form of data that specify parameters for each processing step to be performed during one or more operations. It should be understood that the parameters can be specific to the type of process to be performed and the type of tool the controller is configured to interface with or control. Thus, as described above, the controller 930 can be distributed, for example, by including one or more discrete controllers networked together and working toward a common purpose (e.g., process and control as described herein). An example of a distributed controller for such a purpose is one or more integrated circuits on a chamber communicating with one or more integrated circuits located remotely (e.g., at a platform level or as part of a remote computer), which combine to control the process on the chamber.

[0124] Exemplary systems may include, but are not limited to, plasma etch chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etch chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, ALD chambers or modules, ALE chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing system that may be associated with or used in the manufacture and / or preparation of semiconductor wafers.

[0125] As described above, depending on one or more processing steps to be performed by the tool, the controller can communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, a host computer, another controller, or tools used in the material transport of wafer containers to and from tool locations and / or load ports in a semiconductor manufacturing facility.

[0126] Figure 10Depicted is a semiconductor processing cluster architecture with various modules that interface with a vacuum transfer module 1038 (VTM). The arrangement of transfer modules that "transfer" wafers between multiple storage facilities and processing modules can be referred to as a "cluster tool architecture" system. An airlock 1030 (also referred to as a load lock or transfer module) is shown in a VTM 1038 having four processing modules 1020a-1020d, which can be individually optimized to perform various manufacturing processes. For example, processing modules 1020a-1020d can be implemented to perform substrate etching, deposition, ion implantation, wafer cleaning, sputtering, and / or other semiconductor processes. In some embodiments, any one of the deposition of a vertical mask, the etching of a patterned etch mask, and the etching of a target layer is performed in the same module. In some embodiments, any one of the deposition of a vertical mask, the etching of a patterned etch mask, and the etching of a target layer is performed in different modules of the same tool. One or more substrate etch processing modules (any of 1020a-1020d) can be implemented as disclosed herein, i.e., for any of deposition of a vertical mask, etching of a patterned etch mask, and etching of a target layer, as well as other suitable functions according to the disclosed embodiments. The airlocks 1030 and processing modules 1020 can be referred to as "stations." Each station has a facet 1036 that interfaces the station with a VTM 1038. Within each facet, sensors 1-18 are used to detect the passage of wafers 1026 as they move between stations.

[0127] A robot 1022 transfers wafers 1026 between stations. In one embodiment, the robot 1022 has one arm, and in another embodiment, the robot 1022 has two arms, each with an end effector 1024 to pick up a wafer (e.g., wafer 1026) for transport. In an atmospheric transfer module (ATM) 1040, a front-end robot 1032 is used to transfer wafers 1026 from a cassette or front-opening unpacking pod (FOUP) 1034 in a load port module (LPM) 1042 to an airlock 1030. A module hub 1028 within the processing module 1020 is a suitable location for placing wafers 1026. An aligner 1044 in the ATM 1040 is used to align the wafers.

[0128] In an exemplary processing method, a wafer is placed in one of the FOUPs 1034 in the LPM 1042. A front-end robot 1032 transfers the wafer from the FOUP 1034 to the aligner 1044, which allows the wafer 1026 to be properly centered before etching or processing. After alignment, the wafer 1026 is moved by the front-end robot 1032 into the airlock 1030. Because the airlock module has the ability to match the environments between the ATM and VTM, the wafer 1026 can be moved between the two pressure environments without damage. From the airlock module 1030, the wafer 1026 is moved by the robot 1022 through the VTM 1038 and into one of the processing modules 1020a-1020d. To accomplish this wafer movement, the robot 1022 utilizes an end effector 1024 located on each of its arms. Once the wafer 1026 has been processed, it is moved from the processing modules 1020a-1020d to the airlock module 1030 by the robot 1022. From here, the wafer 1026 can be moved by the front end robot 1032 to one of the FOUPs 1034 or to the aligner 1044.

[0129] It should be noted that the computer controlling the movement of the wafers may be local to the cluster architecture, or may be located external to the cluster architecture in the manufacturing shop or at a remote location and connected to the cluster architecture via a network. Figure 9 The controller described can utilize Figure 10 tools in .

[0130] The embodiments disclosed herein describe the deposition of materials onto substrates such as wafers, substrates, or other workpieces. The workpieces can have a variety of shapes, sizes, and materials. In this application, the terms "semiconductor wafer," "wafer," "substrate," "wafer substrate," and "partially fabricated integrated circuit" are used interchangeably. Those skilled in the art will understand that the term "partially fabricated integrated circuit" can refer to a silicon wafer during any of the many stages of integrated circuit fabrication.

[0131] in conclusion

[0132] Although the above embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be implemented within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatus of the embodiments of the present invention. Therefore, the embodiments of the present invention are to be considered as illustrative rather than restrictive, and the embodiments are not to be limited to the details given herein.

Claims

1. A method for processing a semiconductor substrate, comprising: providing a semiconductor substrate having a patterned etch mask over a target layer, the patterned etch mask comprising spaced-apart positive features, each spaced-apart positive feature having a field and a sidewall; and depositing a vertical growth mask selectively over the field of the spaced-apart positive features relative to the target layer, wherein The depositing of a vertical growth mask includes: the vertical growth mask being substantially not deposited on the sidewalls of the positive features; and etching a target layer using the patterned etching mask and the vertical growth mask as masks, The depositing and etching are performed in one or more cycles, and the depositing of the vertical growth mask includes replenishing the vertical growth mask to achieve continuous etching of the target layer.

2. The method of claim 1 , wherein the vertical growth mask comprises at least one feature; and wherein a critical dimension of the at least one feature of the vertical growth mask is substantially the same as a critical dimension of a corresponding spaced-apart positive feature of the patterned etch mask. The method of claim 1 , wherein depositing the vertical growth mask and etching the target layer are performed simultaneously.

4. The method of claim 1, wherein a size of the spaces between the spaced-apart positive features of the vertical growth mask is substantially the same as a size of the spaces between the spaced-apart positive features of the patterned etch mask.

5. The method according to claim 1, wherein Depositing the vertical growth mask includes cycles of one or more pulses using (i) a first gas and (ii) a mixture of second and third gases.

6. The method according to claim 5, wherein: The first gas includes a tungsten-containing precursor, and the mixture of the second and third gases includes a mixture of argon and hydrogen.

7. The method according to claim 1, wherein The width of the vertical growth mask is within 150% of the width of the patterned etch mask. 8 . The method of claim 1 , further comprising etching the vertical growth mask and the target layer, and selectively depositing an additional vertical growth mask on the etched vertical growth mask.

9. A method for processing a semiconductor substrate, comprising: providing a semiconductor substrate having a patterned etch mask over a target layer, the patterned etch mask having spaced-apart positive features, each spaced-apart positive feature having a first critical dimension and field and sidewalls; and depositing a mask over the field of corresponding spaced positive features relative to the target layer, the mask having a second critical dimension, wherein the mask is deposited substantially without depositing on sidewalls of the spaced-apart positive features, and the deposition is performed using one or more alternating pulse cycles of (i) a first gas and (ii) a mixture of a second gas and a third gas, etching the target layer using the patterned etching mask and the deposited mask while replenishing the deposited mask to form an etched target layer, in, The deposition thickness of the mask is controlled so that the second critical dimension is maintained within 150% of the first critical dimension.

10. The method according to claim 9, wherein: The second critical dimension remains within 150% of the first critical dimension, but is not substantially deposited on the sidewalls of the spaced-apart positive features.

11. The method of claim 9, wherein the first gas comprises a tungsten-containing precursor and the mixture of the second and third gases comprises a mixture of argon and hydrogen.

12. A method for processing a semiconductor substrate, comprising: providing a semiconductor substrate having a patterned etch mask over a target layer, the patterned etch mask having spaced-apart positive features, each spaced-apart positive feature having a field and a sidewall; and depositing a vertically grown tungsten-containing mask selectively over the field of the spaced-apart positive features relative to a target layer, wherein the tungsten-containing mask is deposited substantially without depositing on sidewalls of the spaced-apart positive features; and etching the target layer using the patterned etch mask and the tungsten-containing mask as masks, The deposition and etching are performed in one or more cycles, and the deposition of the tungsten-containing mask includes replenishing the tungsten-containing mask to a thickness sufficient to continue etching the target layer. 13 . The method of claim 12 , further comprising patterning the target layer using at least a patterned etch mask and a vertically selectively grown tungsten-containing mask. The method of claim 13 , wherein the deposition of the vertical selectively grown tungsten-containing mask and the patterning of the target layer are performed simultaneously.

15. The method of claim 13, wherein the deposition of the vertical selectively grown tungsten-containing mask and the patterning of the target layer are alternately performed in a cycle.

16. A method for processing a semiconductor substrate, comprising: providing a semiconductor substrate comprising a carbon-containing target layer, an antireflective layer, and a patterned photoresist; patterning the anti-reflective layer to form a patterned anti-reflective mask; exposing the semiconductor substrate to a tungsten-containing precursor and igniting a plasma to selectively deposit a tungsten-containing mask to form a patterned tungsten-containing mask on fields of the patterned antireflective mask; and The carbon-containing target layer is patterned using the patterned anti-reflective mask and the patterned tungsten-containing mask.

17. The method of claim 16, wherein depositing the tungsten-containing mask comprises using one or more cycles of (i) pulses of the first gas and (ii) pulses of a mixture of the second and third gases.

18. The method of claim 17, wherein the first gas comprises a tungsten-containing precursor and the mixture of the second and third gases comprises a mixture of argon and hydrogen.

19. The method of claim 17, further comprising selecting a number of one or more cycles based on a pulse duration of the first gas, a pulse duration of the mixture of the second and third gases, a desired thickness of the tungsten-containing mask, or a combination thereof.

20. The method of claim 16, wherein the forming of the patterned tungsten-containing mask and the patterning of the carbon-containing target layer are performed simultaneously.

21. The method of claim 16, wherein forming the patterned tungsten-containing mask and patterning the carbon-containing target layer are performed in a cycle.

22. A method for processing a semiconductor substrate, comprising: providing a semiconductor substrate comprising a carbon-containing target layer and a patterned etch mask having a first critical dimension; exposing the semiconductor substrate to a plasma generated by one or more pulses of a mixture of argon and hydrogen gases and one or more pulses of a tungsten-containing precursor using a plasma power between 100 W and 500 W at a substrate temperature below 160° C. to form a tungsten material having a second critical dimension on the patterned etch mask; and patterning the carbon-containing target layer using the patterned etch mask and the tungsten material, The second critical dimension is within 150% of the first critical dimension.

23. The method of claim 22, wherein the one or more pulses of the argon and hydrogen mixture comprise a duration between 100 milliseconds and 10 seconds.

24. The method of claim 22, wherein the one or more pulses of the tungsten-containing precursor comprise a duration between 100 milliseconds and 10 seconds.

25. The method of claim 22, wherein the one or more pulses of the tungsten-containing precursor and the one or more pulses of the argon and hydrogen mixture comprise a plurality of alternating pulses of the tungsten-containing precursor and the argon and hydrogen mixture.

26. The method of claim 25, wherein the plurality of alternating pulses comprises a number of cycles selected based on a duration of each of the plurality of alternating pulses of the tungsten-containing precursor and the argon and hydrogen gas mixture, a desired thickness of the tungsten material, or a combination thereof.

27. The method of claim 26, wherein the number of cycles is between 3 cycles and 20 cycles.

28. The method of claim 22, wherein the forming of the tungsten material and the patterning of the carbon-containing target layer are performed simultaneously.

29. The method of claim 22, wherein the forming of the tungsten material and the patterning of the carbon-containing target layer are performed in a cyclic manner.

30. An apparatus for processing a semiconductor substrate, comprising: a reaction chamber comprising a susceptor for holding a substrate, wherein the substrate has a patterned etch mask having a first critical dimension; a plasma source coupled to the reaction chamber and configured to generate plasma; one or more first gas inlets coupled to the reaction chamber; a second gas inlet coupled to the reaction chamber; as well as A controller, which contains instructions for: introducing a mixture of argon and hydrogen and a tungsten-containing precursor; Generating the plasma using a plasma power between 100 W and 500 W; as well as Setting the temperature of the susceptor to below 160° C. and forming a tungsten material having a second critical dimension on the patterned etch mask; patterning a carbon-containing target layer using the patterned etch mask and the tungsten material, The second critical dimension is within 150% of the first critical dimension.

31. The apparatus of claim 30, wherein the tungsten-containing precursor is introduced in one or more pulses, and the mixture of argon and hydrogen is introduced in one or more pulses.

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