Chip edge detection method and device

Abstract

The present invention discloses a chip edge detection method and device, wherein the chip includes at least one storage area, each storage area includes multiple storage units, including: after writing preset data to each storage unit located at the edge of the chip and / or the edge of the storage area, reading the data of each storage unit at the edge of the chip and / or the edge of the storage area as read data; determining the chip edge detection result according to the read data and the preset data. The chip edge detection method provided by the embodiment of the present invention does not require the technical support of the edge integrity detection circuit of the chip original factory, and does not need to set up a corresponding detection circuit additionally, which can simplify the chip detection process, and can effectively detect and screen the chip before and after the chip leaves the factory, thereby improving the effective performance of the finished semiconductor device and ensuring the quality and reliability of electronic products; at the same time, it can realize the detection of cracks at the edges of multiple storage areas, further improving the reliability of the chip.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of integrated circuit testing, and in particular to a chip edge detection method and device. Background Art

[0002] The carrier of chip integrated circuit (IC) is divided from wafer. After cutting the wafer, it may cause defects such as chipping and cracking on the chip edge. Chip edge defects are one of the serious failure causes of semiconductor devices. The quality of semiconductor devices directly determines the size, weight, ease of use, life, performance and cost of electronic products. It is related to the effective connection from device to system and the quality and competitiveness of microelectronic products. Therefore, detecting the integrity of chip edges and screening chips in advance can ensure the quality and reliability of electronic products.

[0003] At present, the chipping detection circuit (CDC) is a common design for detecting cracks in high-end integrated circuit chips. Figure 1 It is a schematic diagram of the structure of the chip edge integrity detection circuit in the prior art. Figure 1 As shown in the figure, the general practice is to make a loop around the edge of the chip, send a signal through a pin (Pad1), and receive it at another pin (Pad2) after going around the chip. If the signal is received within the specified time, the chip is judged to be qualified (Pass), that is, there is no crack defect. If the signal does not come back within the specified time, the chip is judged to be unqualified (Fail), that is, there may be a crack defect.

[0004] However, the edge integrity detection circuit is a test mode (Test Mode) of the chip manufacturer, and is usually not open to the public. When testing the packaged chips, the foundry cannot effectively screen the chips, and the edge integrity detection circuit can only detect the periphery of the chip, and cannot detect cracks in the storage areas inside the chip. Moreover, for memory chips, edge detection of the storage area (cell area) inside the chip is more meaningful. Summary of the invention

[0005] The present invention provides a chip edge detection method and device to realize chip edge integrity detection and chip internal storage area edge integrity detection.

[0006] In a first aspect, an embodiment of the present invention provides a chip edge detection method, wherein the chip includes at least one storage area, each of the storage areas includes a plurality of storage units, including:

[0007] After writing preset data into each of the storage cells located at the edge of the chip and / or the edge of the storage area, reading data from each of the storage cells at the edge of the chip and / or the edge of the storage area as read data;

[0008] The detection result of the chip edge and / or the storage area edge is determined according to the read data and the preset data.

[0009] Optionally, the storage area further includes a plurality of word lines and a plurality of bit lines, the storage cells in the same row share the word lines, and the storage cells in the same column share the bit lines; wherein the word line electrically connected to the storage cells located at the edge of the chip and / or the edge of the storage area and arranged in sequence along the row direction is the first word line;

[0010] After writing preset data to each of the storage cells located at the edge of the chip and / or the edge of the storage area, reading data of each of the storage cells at the edge of the chip and / or the edge of the storage area as read data, comprises:

[0011] Providing an address selection signal to the first word line to write preset data into the storage cells at the edge of the chip and / or the edge of the storage area;

[0012] Data stored in each of the memory cells electrically connected to the first word line is read through each of the bit lines as read data.

[0013] Optionally, the bit line electrically connected to each storage unit located at the edge of the chip and / or the edge of the storage area and arranged in sequence along the column direction is the first bit line;

[0014] Reading data of each storage unit at the edge of the chip and / or the edge of the storage area as read data further includes:

[0015] Addressing signals are provided to each of the word lines in sequence, and data of a column of the storage cells electrically connected to the first bit lines are read one by one through the first bit lines as read data.

[0016] Optionally, determining the chip edge and / or storage area edge detection result according to the read data and the preset data includes:

[0017] Determining whether the read data are all the same as the preset data;

[0018] If not, it is determined that cracks exist at the edge of the chip and / or the edge of the storage area.

[0019] Optionally, before providing addressing signals to the word lines in sequence and reading data of a column of storage cells electrically connected to the first bit lines one by one through the first bit lines as read data, the method further includes:

[0020] Erasing the data written into each of the storage cells in the storage area, so that before reading the data of a column of the storage cells electrically connected to the first bit line one by one through the first bit line, the preset data of each of the storage cells are all erased data;

[0021] Determining the chip edge and / or storage area edge detection result according to the read data and the preset data includes:

[0022] determining whether the read data read through the first bit line are all the same as the erased data;

[0023] If not, it is determined that cracks exist at the edge of the chip and / or the edge of the storage area.

[0024] In a second aspect, an embodiment of the present invention further provides a chip edge detection device, wherein the chip includes at least one storage area, each of the storage areas includes a plurality of storage units, and is characterized in that it includes:

[0025] A read data acquisition module, configured to read data from each of the storage cells at the edge of the chip and / or the edge of the storage area as read data after writing preset data to each of the storage cells at the edge of the chip and / or the edge of the storage area;

[0026] A result determination module is used to determine the detection result of the chip edge and / or the storage area edge according to the read data and the preset data.

[0027] Optionally, the storage area further includes a plurality of word lines and a plurality of bit lines, the storage cells in the same row share the word lines, and the storage cells in the same column share the bit lines; wherein the word line electrically connected to the storage cells located at the edge of the chip and / or the edge of the storage area and arranged in sequence along the row direction is the first word line;

[0028] The reading data acquisition module comprises:

[0029] An address signal providing unit, used for providing an address signal to the first word line, so as to write preset data into the storage unit at the edge of the chip and / or the edge of the storage area;

[0030] The first data reading unit is used to read the data stored in each of the storage cells electrically connected to the first word line through each of the bit lines as read data.

[0031] Optionally, the bit line electrically connected to each storage unit located at the edge of the chip and / or the edge of the storage area and arranged in sequence along the column direction is the first bit line;

[0032] The reading data acquisition module also includes:

[0033] The second data reading unit is used to provide addressing signals to each of the word lines in sequence, and read data of a column of the storage cells electrically connected to the first bit lines one by one through the first bit lines as read data.

[0034] Optionally, the result determination module includes:

[0035] The first comparison and judgment unit is used to judge whether the read data are all the same as the preset data; if not, it is determined that cracks exist at the edge of the chip and / or the edge of the storage area.

[0036] Optionally, the chip edge detection device further includes:

[0037] a data erasing module, for erasing the data written into each of the storage cells in the storage area before providing addressing signals to each of the word lines in sequence and reading the data of a column of the storage cells electrically connected to the first bit lines one by one as read data through the first bit lines, so that before reading the data of a column of the storage cells electrically connected to the first bit lines one by one through the first bit lines, the preset data of each of the storage cells are all erased data;

[0038] The result determination module also includes:

[0039] The second comparison and judgment unit is used to judge whether the read data read through the first bit line are all the same as the erased data; if not, it is determined that cracks exist at the edge of the chip and / or the edge of the storage area.

[0040] The chip edge detection method provided by the embodiment of the present invention, after writing preset data to each storage unit located at the edge of the chip and / or the edge of the storage area, reads the data of each storage unit at the edge of the chip and / or the edge of the storage area as read data, and then detects the integrity of the chip edge and / or the edge of the storage area according to the read data and the preset data. It does not require the technical support of the edge integrity detection circuit of the chip manufacturer, and does not need to additionally set up a corresponding detection circuit. It can simplify the chip detection process, and can effectively detect and screen the chip before and after the chip leaves the factory, thereby improving the effective performance of the finished semiconductor device and ensuring the quality and reliability of electronic products. At the same time, when the chip includes multiple storage areas, it can detect the crack conditions at the edges of each storage area to detect the edge integrity of the storage area inside the chip, thereby further improving the reliability of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It is a schematic diagram of the structure of a chip edge integrity detection circuit in the prior art;

[0042] Figure 2 is a schematic diagram of the structure of a chip provided by an embodiment of the present invention;

[0043] Figure 3 is a flow chart of a chip edge detection method provided by an embodiment of the present invention;

[0044] Figure 4 is a flow chart of another chip edge detection method provided by an embodiment of the present invention;

[0045] Figure 5 is a flow chart of another chip edge detection method provided by an embodiment of the present invention;

[0046] Figure 6 is a schematic diagram of a chip edge detection device provided by an embodiment of the present invention;

[0047] Figure 7 It is a schematic diagram of a chip edge detection device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0048] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0049] An embodiment of the present invention provides a chip edge detection method, which can detect the integrity of the chip edge and / or the edge of the storage area. The chip edge detection method can be executed using the chip edge detection device provided by the embodiment of the present invention. The chip edge detection device is implemented by software and / or hardware, and the chip edge detection device can be integrated into a detection device.

[0050] For ease of understanding, the principles of reading, writing and erasing are explained by taking Nand Flash storage chip as an example. Nand Flash includes control pins such as address latch enable, chip select, command latch enable, power-on read enable, read enable, write enable, write protection, data input / output, etc. Specifically, when the command latch enable pin and chip select pin are low level, the address latch enable pin and read enable pin are high level, the write enable pin is on the rising edge, and other pins are invalid, the address input of the read mode is performed; when the command latch enable pin and read enable pin are high level, the address latch enable pin and chip select pin are low level, the write enable pin is on the rising edge, and other pins are invalid, the command input of the read mode is performed. When the command latch enable pin and chip select pin are low, the address latch enable pin, read enable pin and write protection pin are high, the write enable pin is on the rising edge, and other pins are invalid, the address input of the write mode is performed; when the command latch enable pin, read enable pin and write protection pin are high, the address latch enable pin and chip select pin are low, the write enable pin is on the rising edge, and other pins are invalid, the command input of the read mode is performed. When the write protection pin is high and other pins are invalid pins, it is the erase mode.

[0051] Figure 3 A flow chart of a chip edge detection method provided by an embodiment of the present invention is as follows: Figure 3 As shown, the chip edge detection method includes:

[0052] S110 , after writing preset data into each storage unit located at the edge of the chip and / or the edge of the storage area, reading data of each storage unit located at the edge of the chip and / or the edge of the storage area as read data.

[0053] Specifically, Figure 2 A schematic diagram of the structure of a chip provided by an embodiment of the present invention is shown in FIG. Figure 2As shown, the chip includes at least one storage area 110, for example, the chip may include four storage areas 110, and each storage area 110 includes a plurality of storage units 120. Whether there is a crack defect at the edge of the chip can be determined by detecting whether the data read from the storage unit 120 located at the edge of the chip in the storage area 110 is the same as the preset data written; and whether there is a crack defect at the edge of the storage area 110 can be determined by detecting whether the data read from the storage unit 120 located at the edge of the storage area in the storage area 110 is the same as the preset data written. When detecting whether there is a crack at the edge of the chip, the chip can be controlled to be in write mode, and the host computer can be used to write preset data to each storage unit 120 located at the edge of the chip in each storage area 110 through the I / O port of the chip, and then the chip can be controlled to be in read mode to read the contents of each storage unit 120 where the preset data is written as read data. Similarly, when detecting whether there is a crack at the edge of the storage area, preset data can be written to each storage unit 120 located at the edge of the storage area 110, and the data of each storage unit 120 where the preset data is written can be read as read data. Exemplarily, each storage unit 120 stores a binary data, and the data written to the chip is usually hexadecimal, so the data is written in groups of 8 storage units. For example, the preset data written can all be hexadecimal values ​​other than hexadecimal "FF", such as the commonly used "AA", "00" or "55". Taking the written data as hexadecimal "AA" as an example, its corresponding binary is "1010 1010", then the preset data in the 8 storage units 120 in a storage unit group are: 10101010 respectively; in addition, the read / write / erase mode of the chip can be set by inputting high and low level signals to the relevant control pins of the chip.

[0054] S120 , determining a chip edge and / or storage area edge detection result according to the read data and preset data.

[0055] Specifically, if the read data is consistent with the preset data, the integrity of the detected chip edge and / or storage area edge is good and there are no cracks. If the read data is inconsistent with the preset data, the detected chip edge and / or storage area edge has cracks, so the chip can be screened. Exemplarily, when the written preset data is all hexadecimal "AA", the corresponding binary data is "1010 1010". If the read data is all "AA", it is determined that the integrity of the detected chip edge and / or storage area edge is good and there are no cracks. If a write error (Program Fail) occurs during the writing process or the read data is not "AA", it is determined that the storage unit 120 at the chip edge and / or storage area edge is abnormally written, indicating that the detected chip edge and / or storage area edge may have cracks along the word line direction.

[0056] The chip edge detection method provided by the embodiment of the present invention, after writing preset data to each storage unit located at the edge of the chip and / or the edge of the storage area, reads the data of each storage unit at the edge of the chip and / or the edge of the storage area as read data, and then detects the integrity of the chip edge and / or the edge of the storage area according to the read data and the preset data. It does not require the technical support of the edge integrity detection circuit of the chip manufacturer, and does not need to additionally set up a corresponding detection circuit. It can simplify the chip detection process, and can effectively detect and screen the chip before and after the chip leaves the factory, thereby improving the effective performance of the finished semiconductor device and ensuring the quality and reliability of electronic products. At the same time, when the chip includes multiple storage areas, it can detect the crack conditions at the edges of each storage area to detect the edge integrity of the storage area inside the chip, thereby further improving the reliability of the chip.

[0057] In addition, by performing read and write tests on each selected storage unit, crack detection inside the chip can also be achieved, and all-round detection of the chip can be achieved. The technical principle is similar to the technical principle of detecting the edge of the chip and / or the edge of the storage area, and will not be repeated here. For ease of description, the following takes the detection of cracks on the edge of the chip as an example to exemplify the technical solution of the embodiment of the present invention.

[0058] Optional, continue to refer to Figure 2 The storage area 110 also includes multiple word lines 130 and multiple bit lines 140. The storage cells 120 located in the same row share the word line 130, and the storage cells 120 located in the same column share the bit line 140; wherein the word line 130 electrically connected to the storage cells 120 located at the edge of the chip and / or the edge of the storage area and arranged in sequence along the row direction is the first word line 131. Figure 4 is a flow chart of another chip edge detection method provided by an embodiment of the present invention. Figure 4 As shown, the chip edge detection method includes:

[0059] S210 , providing an address selection signal to a first word line to write preset data into storage cells at an edge of a chip and / or an edge of a storage area.

[0060] Specifically, the position of each storage unit 120 in the chip can be defined by the intersection of the word line 130 and the bit line 140. For example, when the first word line 131 is located at the edge of the chip, when detecting cracks at the edge of the chip, an address selection signal can be provided to the first word line 131 at the edge of the chip, so that all storage units 120 located on the first word line 131 are selected, so that the preset data can be written into each storage unit 120 electrically connected to the first word line 131. The host computer can input the address selection signal to the first word line 131 through the I / O port of the chip, and transmit it to each storage unit 120 electrically connected to the first word line 131 through the first word line 131. Exemplarily, the preset data can be other hexadecimal data except the hexadecimal "FF", for example, it can be the commonly used "AA", "00" or "55".

[0061] S220 , reading data stored in each storage unit electrically connected to the first word line through each bit line as read data.

[0062] Specifically, the control chip is in a "read" mode, and the data stored in each storage unit 120 electrically connected to the first word line 131 is read as read data through each bit line 140, and it is detected whether the data stored in each storage unit 120 located at the edge of the chip can be read normally. Exemplarily, if the data stored in the storage unit 120 can be read normally, the read data should be the same as the preset data; if the data stored in the storage unit 120 is read abnormally, the read data is different from the preset data.

[0063] S230, determining whether the read data are all the same as the preset data; if so, executing step S240; if not, executing step S250.

[0064] S240: Determine whether there are no cracks at the edge of the chip and / or the edge of the storage area.

[0065] S250: Determine whether cracks exist at the edge of the chip and / or the edge of the storage area.

[0066] Specifically, if the read data is consistent with the preset data, the integrity of the detected chip edge and / or storage area edge is good and there is no crack. If the read data is inconsistent with the preset data, the detected chip edge and / or storage area edge has a crack, so the chip can be screened. Exemplarily, if the written preset data is "AA" and the read data is "AA", it is determined that the detected chip edge and / or storage area edge has a good integrity and no crack. If there is a situation that the read data is inconsistent with the preset data, the storage unit 120 at the chip edge and / or storage area edge is abnormal in reading and writing, indicating that the detected chip edge and / or storage area edge may have a crack.

[0067] Exemplarily, in order to ensure the accuracy of the test results, multiple word lines 130 adjacent to the first word line 131 at the edge of the chip and / or the edge of the storage area may be additionally tested. For example, if the test result shows that the multiple word lines 130 closest to the edge of the chip and / or the edge of the storage area are in a disconnected state, in order to exclude other reasons rather than chip cracks, another or more word lines 130 located near the center of the storage area may be tested. If the test results are all disconnected, it is determined that there are cracks at the edge of the chip. It should be noted that the embodiment of the present invention is only described by taking the Nand Flash chip as an example, and the detection method provided by the embodiment of the present invention is also applicable to other chips with storage functions.

[0068] The embodiment of the present invention provides an addressing signal to the first word line to write a preset signal into a storage unit electrically connected to the first word line at the edge of the chip and / or the edge of the storage area, and reads data in each storage unit electrically connected to the first word line to detect whether the first word line is broken, and then detects the integrity of the chip edge and / or the edge of the storage area through the breakage of the first word line. There is no need to set up a dedicated detection circuit, which simplifies the detection process and can effectively detect and screen the chip before and after the chip leaves the factory, thereby improving the effective performance of the finished semiconductor device and ensuring the quality and reliability of electronic products.

[0069] Optional, continue to refer to Figure 2 The bit line electrically connected to each memory cell located at the edge of the chip and / or the edge of the storage area and arranged in sequence along the column direction is the first bit line 141, Figure 5 is a flow chart of another chip edge detection method provided by an embodiment of the present invention. Figure 5 As shown, the chip edge detection method includes:

[0070] S310 , providing addressing signals to each word line in sequence, so as to write preset data into the chip and / or storage area and storage cells electrically connected to each word line.

[0071] Exemplarily, when detecting cracks at the edge of the chip and / or the edge of the storage area with the first bit line 141 as the edge, several word lines 130 may be selected, and address selection signals may be provided to each word line 130 in turn, so that the storage unit 120 electrically connected to each word line 130 is selected, so that the preset data can be written into each storage unit 120 electrically connected to each word line 130. Among them, the host computer may input the address selection signal to each word line 130 through the I / O port of the chip, and transmit the preset data to each storage unit 120 electrically connected to each word line 130 through each word line 130. Exemplarily, the preset data may be other hexadecimal values ​​except the hexadecimal "FF", for example, it may be the commonly used "AA".

[0072] S320 , reading data of a column of memory cells electrically connected to the first bit line in a one-to-one correspondence through the first bit line as read data.

[0073] Specifically, the control chip is in a "read" mode, and the data stored in each storage unit 120 electrically connected to each word line 130 is read as read data through the first bit line 141, and it is detected whether the data stored in each storage unit 120 located at the edge of the chip can be read normally. Exemplarily, if the data stored in the storage unit 120 can be read normally, the read data should be the same as the preset data; if the data stored in the storage unit 120 is read abnormally, the read data is inconsistent with the preset data.

[0074] S330, determining whether the read data are all the same as the preset data; if so, executing step S340; if not, executing step S350.

[0075] S340: Determine whether there are no cracks at the edge of the chip and / or the edge of the storage area.

[0076] S350: Determine whether cracks exist at the edge of the chip and / or the edge of the storage area.

[0077] Specifically, if the read data is consistent with the preset data, the integrity of the detected chip edge and / or storage area edge is good and there is no crack. If the read data is inconsistent with the preset data, the detected chip edge and / or storage area edge has a crack, so the chip can be screened. Exemplarily, when writing data to the chip, the data will be written into all the storage cells 120 electrically connected to a word line 130. The data written is usually hexadecimal, so the data is written in a storage cell group of 8 storage cells 120. For example, if the preset data written to each storage cell 120 electrically connected to the word line 130 through the word line 130 is hexadecimal "AA", that is, the preset data stored in the storage cell group consisting of 8 storage cells 120 electrically connected to the word line 130 is "1010 1010". Therefore, when the read data is consistent with the preset data and is also "AA", it indicates that the integrity of the detected chip edge and / or storage area edge is good and there is no crack; if there is a situation where the binary data in the storage unit 120 corresponding to the first bit line 141 is always "0", for example, the read data is "2A", and its corresponding binary is "0010 1010", then the read data is inconsistent with the preset data, indicating that there is a crack at the detected chip edge and / or storage area edge. The embodiment of the present invention only uses the preset data of hexadecimal "AA" as an example. For the convenience of detection, it can also be other hexadecimal values ​​that meet the scheme.

[0078] Exemplarily, in order to ensure the accuracy of the test results, multiple bit lines 140 adjacent to the first bit line 140 at the edge of the chip and / or the edge of the storage area may be additionally tested. For example, if the test result shows that the first bit line 141 closest to the edge of the chip and / or the edge of the storage area is in a disconnected state, in order to exclude other reasons rather than chip cracks, another or more bit lines 140 located near the center of the storage area and adjacent to the first bit line 141 may be further tested. If the test results are all disconnected, it is determined that there is a crack at the edge of the chip. It should be noted that the embodiment of the present invention is only described by taking the Nand Flash chip as an example, and the detection method provided in the embodiment of the present invention is also applicable to other chips with storage functions.

[0079] The embodiment of the present invention provides an addressing signal to each word line to write a preset signal into a storage unit electrically connected to each word line at the edge of the chip and / or the edge of the storage area, and reads the data in each storage unit electrically connected to each word line to detect whether the first bit line is broken, and then detects the integrity of the chip edge and / or the edge of the storage area through the breakage of the first bit line. There is no need to set up a dedicated detection circuit, which simplifies the detection process and can effectively detect and screen the chip before and after the chip leaves the factory, thereby improving the effective performance of the finished semiconductor device and ensuring the quality and reliability of electronic products.

[0080] Optional, Figure 6 A flowchart of another chip edge detection method provided by an embodiment of the present invention is as follows: Figure 6 As shown, the chip edge detection method includes:

[0081] S410 , providing an address selection signal to a first word line to write preset data into storage cells at an edge of a chip and / or an edge of a storage area.

[0082] S420 , reading data stored in each storage unit electrically connected to the first word line through each bit line as read data.

[0083] S430, determining whether the read data are all the same as the preset data; if so, executing step S470; if not, executing step S440.

[0084] S440, erasing the data written into each storage unit in the storage area, so that before reading the data of a column of storage units electrically connected to the first bit line one by one through the first bit line, the preset data of each storage unit are all erased data.

[0085] Specific, combined Figure 2, if the word line 130 at the edge of the chip is detected without cracks, the cracks of the bit line 140 at the edge of the chip are detected, so that all edges around the chip can be detected. A specific implementation method is that after the cracks of the word line 120 at the edge of the chip are detected, the control pin of the control chip is controlled to perform an "erase" operation, so that the data in each storage unit 120 in the chip can be erased. Taking the aforementioned Nand Flash chip as an example, if the preset data written in S410 is hexadecimal "AA", its corresponding binary is "1010 1010", after the "erase" operation is performed, the data in the storage area 110 becomes "FF", and its corresponding binary is "1111 1111", so that before the data of a column of storage units 120 electrically connected to the first bit line 141 are read one by one through the first bit line 141, the preset data stored in each storage unit group composed of 8 storage units 120 is "1111 1111".

[0086] S450, providing addressing signals to each word line in sequence, and reading data of a column of storage cells electrically connected to the first bit line one by one through the first bit line as read data.

[0087] Specific, combined Figure 2 After erasing the data written into each storage unit in the storage area, the host computer provides addressing signals to each word line 130 in sequence through the I / O port of the chip to select the corresponding storage unit 120 to read the data therein. Taking the above-mentioned embodiment as an example, for example, the storage units 120 electrically connected to the first word line 131 at both ends of the chip and the storage units 120 electrically connected to the word line 130 located in the middle part can be selected for data reading operations, and then the data of each selected storage unit 120 electrically connected to the first bit line 141 in a column is read one by one through the first bit line 141 as read data.

[0088] S460, determining whether the read data read through the first bit line are all the same as the erased data; if so, executing step S470; if not, executing step S480.

[0089] S470: Determine whether there are no cracks at the edge of the chip and / or the edge of the storage area.

[0090] S480: Determine whether cracks exist at the edge of the chip and / or the edge of the storage area.

[0091] Specific, combined Figure 2, read the data in each selected storage unit 120 through the first bit line 141. If the read data of each storage unit 120 is the same as the erased data, it is determined that the first bit line 141 at the edge of the chip is not disconnected, which can further indicate that the integrity of the chip edge is good; if each storage unit 120 has read data that is different from the erased data, it is determined that the first bit line 141 at the edge of the chip is disconnected, and there is a crack at the edge of the chip. Exemplarily, if the first bit line 141 at the edge of the chip is disconnected, the data in the storage unit 120 corresponding to the first bit line 141 is always "0", and the read data is "7F", which is different from the erased data "FF", which proves that there is a crack at the edge of the chip; if the first bit line 141 at the edge of the chip is not disconnected, the data in the storage unit group composed of the storage unit 120 corresponding to the first bit line 141 is "1111 1111", and the read data "FF" is the same as the erased data "FF", which proves that there is no crack at the edge of the chip.

[0092] Exemplarily, data can also be read to determine whether there are cracks in the seven bit lines 140 sequentially adjacent to the first bit line 141. To ensure the accuracy of the test results, one or several word lines 130 adjacent to the first word line 131 and several word lines 140 adjacent to the first bit line 141 can be additionally tested to rule out the possibility that the chip read and write abnormalities are caused by other reasons rather than chip cracks. If the test results of several adjacent word lines 130 or bit lines 140 are all disconnected, it is determined that there is a crack at the edge of the chip.

[0093] The chip edge detection method provided by the embodiment of the present invention first performs a read and write test on each storage unit electrically connected to the first word line to detect the integrity of the chip edge with the first word line as the edge, then erases the data of each storage unit of the chip, reads the data of each storage unit electrically connected to the first bit line, and detects the integrity of the chip edge with the first bit line as the edge, thereby realizing the integrity detection of the edges around each storage area of ​​the chip. The chip edge detection method provided by the embodiment of the present invention does not require the technical support of the edge integrity detection circuit of the chip original factory, is easy to operate, simple and reliable, so that the chip foundry can effectively detect and screen the chip, improve the effective performance of the finished semiconductor device, and ensure the quality and reliability of electronic products.

[0094] Based on the same inventive concept, an embodiment of the present invention also provides a chip edge detection device, which can detect the integrity of the chip edge. The chip edge detection device can be used to execute the chip edge detection method provided by an embodiment of the present invention. The chip edge detection device can be implemented by software and / or hardware. Figure 7 is a schematic diagram of a chip edge detection device provided by an embodiment of the present invention, such as Figure 7As shown, the chip edge detection device includes a read data acquisition module 710 and a result determination module 720. The read data acquisition module 710 is used to read the data of each storage unit at the edge of the chip and / or the edge of the storage area as read data after writing preset data to each storage unit at the edge of the chip and / or the edge of the storage area; the result determination module 720 is used to determine the chip edge and / or storage area edge detection result according to the read data and the preset data.

[0095] Optional, reference Figure 7 , the read data acquisition module 710 includes an address signal providing unit 711, a first data reading unit 712 and a second data reading unit 713. The address signal providing unit 711 is used to provide an address signal to the first word line to write the preset data into the storage unit at the edge of the chip and / or the edge of the storage area; the first data reading unit 712 is used to read the data stored in each storage unit electrically connected to the first word line through each bit line as the read data; the second data reading unit 713 is used to provide an address signal to each word line in turn, and read the data of a column of storage cells electrically connected to the first bit line one by one through the first bit line as the read data.

[0096] Optional, continue to refer to Figure 7 The result determination module 720 includes a first comparison and judgment unit 721; the first comparison and judgment unit 721 is used to determine whether the read data are all the same as the preset data; if not, it is determined that there is a crack on the edge of the chip.

[0097] Optional, continue to refer to Figure 7 The chip edge detection device also includes: a data erasing module 730; the data erasing module 730 is used to erase the data written into each storage unit in the storage area before providing addressing signals to each word line in sequence and reading the data of a column of storage units electrically connected to the first bit line one by one as read data through the first bit line, so that before reading the data of a column of storage units electrically connected to the first bit line one by one through the first bit line, the preset data of each storage unit are all erased data; the result determination module 720 also includes a second comparison and judgment unit 722, which is used to judge whether the read data read through the first bit line are all the same as the erased data; if not, it is determined that there are cracks at the edge of the chip and / or the edge of the storage area.

[0098] The chip edge detection device provided in an embodiment of the present invention can execute the chip edge detection method provided in any embodiment of the present invention, and can realize the integrity detection of the chip edge without the technical support of the edge integrity detection circuit of the chip original factory, so that the chip foundry can effectively detect and screen the chip, thereby improving the effective performance of the finished semiconductor device and ensuring the quality and reliability of electronic products.

[0099] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A chip edge detection method, wherein the chip comprises at least one storage area, each of the storage areas comprises a plurality of storage units, characterized in that: include: After writing preset data into each of the storage cells located at the edge of the chip and / or the edge of the storage area, reading data from each of the storage cells at the edge of the chip and / or the edge of the storage area as read data; Determine the detection result of the chip edge and / or the storage area edge according to the read data and the preset data; The storage area further includes a plurality of word lines and a plurality of bit lines, the storage cells in the same row share the word lines, and the storage cells in the same column share the bit lines; the word line electrically connected to the storage cells located at the edge of the chip and / or the edge of the storage area and arranged in sequence along the row direction is the first word line; After writing preset data to each of the storage cells located at the edge of the chip and / or the edge of the storage area, reading the data of each of the storage cells at the edge of the chip and / or the edge of the storage area as read data, comprising: providing an addressing signal to the first word line to write the preset data to the storage cells at the edge of the chip and / or the edge of the storage area; reading the data stored in each of the storage cells electrically connected to the first word line as read data through each of the bit lines; The bit line electrically connected to each memory cell located at the edge of the chip and / or the edge of the storage area and arranged in sequence along the column direction is the first bit line; Reading the data of each of the storage cells at the edge of the chip and / or the edge of the storage area as read data, further comprising: providing an addressing signal to each of the word lines in sequence, and reading the data of a column of the storage cells electrically connected to the first bit lines one by one through the first bit lines as read data; Before providing addressing signals to each of the word lines in sequence and reading data of a column of the storage cells electrically connected to the first bit lines one by one as read data through the first bit lines, the method further includes: erasing the data written into each of the storage cells in the storage area, so that before reading data of a column of the storage cells electrically connected to the first bit lines one by one through the first bit lines, the preset data of each of the storage cells are all erased data; Determine the detection result of the chip edge and / or the storage area edge according to the read data and the preset data, including: judging whether the read data read through the first bit line are all the same as the erased data; if not, determine that cracks exist at the chip edge and / or the storage area edge.

2. The chip edge detection method according to claim 1, characterized in that: Determining the chip edge and / or storage area edge detection result according to the read data and the preset data includes: Determining whether the read data are all the same as the preset data; If not, it is determined that cracks exist at the edge of the chip and / or the edge of the storage area.

3. A chip edge detection device, wherein the chip comprises at least one storage area, each of the storage areas comprises a plurality of storage units, characterized in that: include: A read data acquisition module, configured to read data from each of the storage cells at the edge of the chip and / or the edge of the storage area as read data after writing preset data to each of the storage cells at the edge of the chip and / or the edge of the storage area; A result determination module, used to determine the detection result of the chip edge and / or the storage area edge according to the read data and the preset data; The storage area further includes a plurality of word lines and a plurality of bit lines, the storage cells in the same row share the word lines, and the storage cells in the same column share the bit lines; the word line electrically connected to the storage cells located at the edge of the chip and / or the edge of the storage area and arranged in sequence along the row direction is the first word line; The read data acquisition module includes: an address signal providing unit, used to provide an address signal to the first word line, so as to write preset data into the storage unit at the edge of the chip and / or the edge of the storage area; a first data reading unit, used to read the data stored in each of the storage units electrically connected to the first word line through each of the bit lines as read data; The bit line electrically connected to each memory cell located at the edge of the chip and / or the edge of the storage area and arranged in sequence along the column direction is the first bit line; The read data acquisition module further includes: a second data reading unit, which is used to sequentially provide addressing signals to each of the word lines, and read data of a column of the storage cells electrically connected to the first bit line in a one-to-one correspondence through the first bit line as read data; The chip edge detection device further includes: a data erasing module, which is used to erase the data written into each of the storage cells in the storage area before providing addressing signals to each of the word lines in sequence and reading the data of a column of the storage cells electrically connected to the first bit lines one by one as read data through the first bit lines, so that before reading the data of a column of the storage cells electrically connected to the first bit lines one by one through the first bit lines, the preset data of each of the storage cells are all erased data; The result determination module further includes: a second comparison judgment unit, configured to judge whether the read data read through the first bit line are all the same as the erased data; if not, determining whether cracks exist at the chip edge and / or storage area edge.

4. The chip edge detection device according to claim 3, characterized in that: The result determination module comprises: The first comparison and judgment unit is used to judge whether the read data are all the same as the preset data; if not, it is determined that cracks exist at the edge of the chip and / or the edge of the storage area.

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