A processing method and device

Abstract

The present invention provides a processing method and device, wherein the processing method includes detecting microcode instructions; when an erroneous microcode instruction is detected, the method further includes one of the following: discarding a message corresponding to the erroneous microcode instruction; or, debugging a thread corresponding to the erroneous microcode instruction, thereby solving the problem of message errors caused by occasional errors of microcode instructions in related technologies and improving the processing efficiency of erroneous messages.

Description

Technical Field

[0001] The present invention relates to the field of communications, and in particular to a processing method and device. Background Art

[0002] In the related technology, the field of message forwarding generally adopts a programmable message processing system called a network processor, which performs parallel data processing on the forwarded messages. On the one hand, it provides bandwidth throughput, and on the other hand, it can cope with increasingly diverse network protocols and has a high degree of flexibility.

[0003] With the increase in the amount of data processed by network equipment, the various differences in working environments, and the diversification of various network protocols that need to be processed, we often encounter errors in message processing. For example, the circuit scale of the message processing system is getting larger and larger, and the network processor's instructions may have temporary errors, such as electromagnetic interference, which will cause accidental errors in messages; or the instability of the circuit caused by the aging of the equipment will also cause accidental errors in messages. For such occasional errors, which are not fixed, especially those related to microcode instructions, it is difficult to capture such erroneous messages.

[0004] There is no solution to the problem of message errors caused by occasional errors in microcode instructions in related technologies. Summary of the invention

[0005] The embodiment of the present invention provides a processing method and device to at least solve the problem of message errors caused by occasional errors of microcode instructions in the related art.

[0006] According to an embodiment of the present invention, a processing method is provided, comprising:

[0007] Detecting microcode instructions;

[0008] In the case where an erroneous microcode instruction is detected, the method further includes one of the following: discarding a message corresponding to the erroneous microcode instruction; or performing debugging processing on a thread corresponding to the erroneous microcode instruction.

[0009] According to another embodiment of the present invention, there is provided a processing device, comprising:

[0010] A detection module, used for detecting microcode instructions;

[0011] The processing module is used to discard the message corresponding to the erroneous microcode instruction when an erroneous microcode instruction is detected; or to debug the thread corresponding to the erroneous microcode instruction when an erroneous microcode instruction is detected.

[0012] According to yet another embodiment of the present invention, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any one of the above method embodiments when run.

[0013] According to yet another embodiment of the present invention, there is provided an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0014] Through the embodiments of the present invention, since microcode instructions are detected, when an erroneous microcode instruction is detected, the method also includes one of the following: discarding the message corresponding to the erroneous microcode instruction; or, debugging the thread corresponding to the erroneous microcode instruction. Therefore, the problem of message errors caused by occasional errors of microcode instructions in the related technology can be solved, and the processing efficiency of error messages is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0016] Figure 1 is a flowchart of a processing method according to an embodiment of the present invention;

[0017] Figure 2 is a structural block diagram of a processing device according to an embodiment of the present invention;

[0018] Figure 3 is a flow chart of an error reporting and debugging method for occasional errors of microcode instructions according to an optional embodiment of the present invention;

[0019] Figure 4 is a structural block diagram of a microcode exception handling device according to an optional embodiment of the present invention;

[0020] Figure 5 is a flow chart of microcode instruction detection according to an optional embodiment of the present invention;

[0021] Figure 6 is a flow chart of a debugging process according to an alternative embodiment of the present invention. DETAILED DESCRIPTION

[0022] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.

[0023] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0024] Example 1

[0025] The method embodiment provided in the first embodiment of the present application can be executed in a computing device. Figure 1 is a flowchart of a processing method according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:

[0026] Step S101, detecting microcode instructions;

[0027] Step S103, when an erroneous microcode instruction is detected, the method further includes one of the following: discarding a message corresponding to the erroneous microcode instruction; or debugging a thread corresponding to the erroneous microcode instruction.

[0028] Through the above steps, since the microcode instructions are detected; in the case of detecting an erroneous microcode instruction, the method also includes one of the following: discarding the message corresponding to the erroneous microcode instruction; or, debugging the thread corresponding to the erroneous microcode instruction, thereby solving the problem of message errors caused by occasional errors of microcode instructions in related technologies and improving the processing efficiency of error messages.

[0029] Optionally, debugging the thread corresponding to the erroneous microcode instruction includes: storing debugging information, wherein the debugging information is used to characterize the running status of the thread; reading the debugging information, and debugging the thread according to the debugging information.

[0030] Optionally, the method further includes: before discarding the message corresponding to the erroneous microcode instruction, jumping to the address of the message discard instruction; or, before debugging the thread corresponding to the erroneous microcode instruction, jumping to the address of the debugging instruction.

[0031] Optionally, the method further includes: after jumping to the address of the message discard instruction, continuing to execute the correct microcode instruction; or, after jumping to the address of the debug instruction, continuing to execute the correct microcode instruction.

[0032] Optionally, the microcode instruction is detected, including at least one of the following: detecting the opcode and operand of the microcode instruction, and determining that the microcode instruction is an erroneous microcode instruction when the opcode does not belong to a preset specified type and the operand exceeds a preset operand threshold; or detecting the address of a memory accessed by the microcode instruction, and determining that the microcode instruction is an erroneous microcode instruction when the address does not belong to a preset address range; or detecting the number of microcode instructions corresponding to a specified message, and determining that the microcode instruction is an erroneous microcode instruction when the number exceeds a preset number threshold.

[0033] It should be noted that the microcode instruction can be determined as an erroneous microcode instruction when any one of the above situations is met, or when any two of the above situations are met, or when all of the above situations are met.

[0034] Optionally, after discarding the message corresponding to the erroneous microcode instruction, the method further includes: feeding back the reason for discarding the message to the message forwarding device.

[0035] Optionally, the method further includes: when an erroneous microcode instruction is detected, counting the type and / or number of the erroneous microcode instruction.

[0036] In this embodiment, a processing device is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0037] Figure 2 is a structural block diagram of a processing device according to an embodiment of the present invention. Figure 2 As shown, the device comprises:

[0038] A detection module 22, used for detecting microcode instructions;

[0039] The processing module 24 is used to discard the message corresponding to the erroneous microcode instruction when an erroneous microcode instruction is detected; or to debug the thread corresponding to the erroneous microcode instruction when an erroneous microcode instruction is detected.

[0040] Through the above-mentioned module, since the microcode instructions are detected, when an erroneous microcode instruction is detected, the method also includes one of the following: discarding the message corresponding to the erroneous microcode instruction; or, debugging the thread corresponding to the erroneous microcode instruction, thereby solving the problem of message errors caused by occasional errors of microcode instructions in related technologies and improving the processing efficiency of error messages.

[0041] Optionally, the processing module 24 is used to debug the thread corresponding to the erroneous microcode instruction when an erroneous microcode instruction is detected. The processing module 24 includes:

[0042] The storage module is used to store debugging information, wherein the debugging information is used to characterize the running status of the thread; the reading module is used to read the debugging information and debug the thread according to the debugging information.

[0043] Optionally, the device also includes: a first jump module, used to jump to the address of the message discard instruction before discarding the message corresponding to the erroneous microcode instruction; or, a second jump module, used to jump to the address of the debugging instruction before debugging the thread corresponding to the erroneous microcode instruction.

[0044] Optionally, the device further includes: a first execution module, used to continue executing the correct microcode instruction after jumping to the address of the message discard instruction; or a second execution module, used to continue executing the correct microcode instruction after jumping to the address of the debug instruction.

[0045] Optionally, the detection module 22 includes: a first detection module, used to detect the opcode and operand of the microcode instruction, and determine that the microcode instruction is an erroneous microcode instruction when the opcode does not belong to a preset specified type and the operand exceeds a preset operand threshold; or, a second detection module, used to detect the address of the memory accessed by the microcode instruction, and determine that the microcode instruction is an erroneous microcode instruction when the address does not belong to a preset address range; or, a third detection module, used to detect the number of microcode instructions corresponding to a specified message, and determine that the microcode instruction is an erroneous microcode instruction when the number exceeds a preset number threshold.

[0046] Optionally, the device further includes: a feedback module, configured to feed back a reason for discarding the message to the message forwarding device after discarding the message corresponding to the erroneous microcode instruction.

[0047] Optionally, the device further comprises: a statistical module, for counting the type and / or number of erroneous microcode instructions when an erroneous microcode instruction is detected.

[0048] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0049] Alternative Implementation

[0050] This embodiment can solve the problem of message errors caused by occasional errors in microcode instructions, fully utilize the programmable characteristics of the message forwarding system, and combine software and hardware. This embodiment provides a means of error reporting and debugging without affecting the forwarding of normal messages.

[0051] Figure 3 is a flow chart of an error reporting and debugging method for occasional errors of microcode instructions according to an optional embodiment of the present invention, such as Figure 3 As shown, including:

[0052] Step 1: microcode instruction error detection, for example, detecting occasional errors in microcode instructions.

[0053] Exemplarily, in this embodiment, the occasional errors of microcode instructions are subdivided into three types: the first is an illegal instruction error; the second is an illegal storage access error; and the third is a timeout error. An illegal instruction error means that the instruction read back from the instruction memory and then sent to the microengine for execution is outside the defined hardware instruction set and is not a legal instruction. This type of instruction is impossible to exist during the microcode compilation process and will only exist when the hardware is unstable or the instruction storage fails. Errors in illegal storage access are generally more hidden and difficult to detect in the compilation stage, but can be detected in the instruction execution stage. The detection of illegal storage access errors here is a check prior to execution, that is, it is detected before access to the storage and the storage access operation is controlled based on the check results. A timeout error occurs when the number of microcode instructions required to forward a message exceeds the threshold planned by the microcode designer. This timeout error generally occurs in microcodes with some jump and loop structures. If an occasional error occurs in the jump address, it will jump to some instruction segments that are not intended by the microcode designer, and there is a possibility of microcode execution timeout.

[0054] Step 2: Select the microcode instruction error reporting method.

[0055] After detecting an occasional error in a microcode instruction, this embodiment provides two error reporting methods: The first error reporting method is to directly discard the message, and provide the reason for discarding the message to the message forwarding device, and also perform abnormal statistical counting. This method is the most commonly used and will be used during normal work. The second error reporting method is to allow the corresponding error thread to enter the debugging state according to the user's register configuration.

[0056] Step 3: Microcode instruction error debugging.

[0057] After the thread with the error enters the debug mode, this embodiment provides a debugging method as described below: when the instruction fails, if it is configured to enter the debug state, it will jump into a debug instruction segment; through this debug instruction segment, the key information that needs to be debugged will be transmitted to a key-ram of a kernel; after executing the debug instruction segment, a trap1 instruction will be executed cyclically and an interrupt will be reported, waiting for further debugging by the user. The user can configure a register to read and process the debug data in the key-ram and transfer it to a debug-ram. The content of this debug-ram can be read out by the user for analysis.

[0058] Optionally, Figure 4 is a block diagram of a microcode exception handling device according to an optional embodiment of the present invention. Figure 4 As shown, the microcode exception processing device includes the following modules: an error detection module A, a microcode execution module B, an instruction address generation module C, a debugging processing module D and an error type statistics module E.

[0059] The error detection module A and the instruction address generation module C are relatively important parts of this embodiment, and can solve the problem of occasional instruction errors by combining software and hardware.

[0060] Error detection module A: This module is used to detect the three microcode instruction errors defined above. These detection processes can be implemented through hardware structures.

[0061] Microcode execution module B: This module is the module that executes microcode instructions and is the module that performs microcode execution in the programmable message forwarding system.

[0062] Instruction address generation module C: This module adds the instruction address jump function for abnormal situations on the basis of the instruction address generation module. Different exception handling is achieved through different jump addresses; the microcodes for the exception handling corresponding to different jump addresses can be implemented through software programs.

[0063] Debug processing module D: This module is used to implement debugging. The hardware functions that need to be implemented when the user enters the debug mode through register configuration when the microcode instruction fails. It includes the transfer of debugging information from the microengine to debug-ram; and provides a read interface to transfer the contents of debug-ram to the host computer; reporting interrupts to allow users to start debugging operations.

[0064] Error type statistics module E: This module is used to count the three types of instruction errors. The count value can be provided to the user to determine whether the microcode instruction exception is sporadic. For example, if some storage addresses of the instruction storage fail and cause illegal instructions to appear, then the count value will accumulate rapidly and has a linear relationship with the number of messages.

[0065] Optionally, the error detection module A detects the input instruction, and if there is no error, the instruction is input as is to the microcode execution module B. If an error is detected, the error situation is sent to the instruction address generation module C; the instruction address generation module C generates the corresponding microcode instruction jump address according to the type of error, takes the new microcode and returns it to the microcode execution module B; the microcode execution module B directly discards the message or enters the debugging mode by executing the relevant instructions.

[0066] If the debug mode is entered, the microcode execution module B will execute a debug instruction and store the relevant debug data in the key-ram; then the debug processing module D will upload an interrupt to notify the user to debug the faulty thread. The user can move the debug-related information from the key-ram to the debug-ram by configuring a register; the debug processing module D provides a read interface for the user to read the debug information in the debug-ram for debugging analysis. The debug processing module D can also generate a debug instruction address based on the user's configuration to fetch the corresponding debug instruction and send it to the microcode execution module B for execution.

[0067] Module E is used to count the types of microcode instruction errors and provide a reading interface for the user to analyze the cause of the error.

[0068] Compared with the related art, the method and device described in this embodiment propose a check and exception handling scheme for occasional errors of microcode instructions, which achieves the goal of improving the reliability of the message processing system and the flexibility of exception handling by spending a small amount of hardware resources and combining software and hardware under the hardware conditions of the existing programmable system.

[0069] The implementation of the technical solution is further described in detail below in conjunction with the accompanying drawings. The processing steps of this embodiment are as follows:

[0070] Step 1: Error detection. Optionally, Figure 5is a flow chart of microcode instruction detection according to an optional embodiment of the present invention, such as Figure 5 As shown, first check whether it is an illegal instruction. If so, encode the 3-bit error type err_flag into 3'b001; otherwise, continue to check for memory access errors. If there is an error, encode the 3-bit error type err_flag into 3'b010; otherwise, continue to check for instruction execution timeout. If there is an error, encode the 3-bit error type err_flag into 3'b100.

[0071] Step 2: Choose whether to discard the message directly or enter debug mode according to the register configuration. A 3-bit dsr register is set in the hardware; it can be read and written by the CPU. The following example explains in detail how this 3-bit dsr register works with err_flag.

[0072] If an illegal instruction error occurs, err_flag = 3'b001. If bit0 of dsr is configured to 0, it means that the message is discarded directly. If bit0 of dsr is configured to 1, it means that the debug mode needs to be entered.

[0073] If a memory access error occurs, err_flag = 3'b010. If bit1 of dsr is set to 0, the message is discarded directly. If bit1 of dsr is set to 1, it means that the debug mode needs to be entered.

[0074] If an instruction execution timeout error occurs, then err_flag = 3'b100; if bit2 of dsr is configured to 0, it means that the message is discarded directly; if bit2 of dsr is configured to 1, it means that the debug mode needs to be entered.

[0075] Step 3: If the debug mode is entered, the debug information will be stored in key-ram and the interrupt will be reported. The user can move the debug information from key-ram to debug-ram through the CPU read-write interface and read it out for analysis.

[0076] Figure 6 is a flowchart of the debugging process according to an optional embodiment of the present invention. Figure 6 The detailed description is as follows:

[0077] When entering the debugging mode, the first step is to store the debugging information into the key-ram. The debugging information here includes two categories: one is the message data; the other is the execution environment data of the microcode engine.

[0078] The second step is to report the interrupt to tell the host that an error has occurred.

[0079] The third step is for the host to move the key-ram information to debug-ram and read it out to analyze the specific cause of the error.

[0080] The fourth step is that the host sends a debugging instruction to debug the message being debugged.

[0081] Step 5 is to exit debug mode.

[0082] Optionally, the device of this embodiment includes five modules: an error checking module A; a microcode execution module B; an instruction address generation module C; a debugging processing module D; and an error type statistics module E. Some embodiments are proposed below for the implementation of some modules.

[0083] The implementation of the error checking module A is described below based on three different errors:

[0084] The first illegal instruction error is implemented as follows: the format of the instruction is simplified to "opcode + operand" for explanation, where the opcode is used to indicate what instruction it is; and the operand is the data processed by the instruction. The first type of illegal instruction error is that the opcode of the input instruction does not belong to any opcode in the instruction set defined by the hardware, which means that the instruction is changed to an illegal instruction; the second type is that the value range of the operand of a certain type of instruction does not conform to the definition of the instruction set.

[0085] The second memory access error is implemented as follows: in the hardware, there are certain memory addresses that cannot be directly accessed by microcode instructions. If the memory address accessed by analyzing the instruction exceeds the range set by the hardware, it will be determined that a memory access error has occurred.

[0086] The third timeout error is implemented as follows: Generally speaking, the microcode instructions for processing a message are limited. If a message runs many instructions but has not yet finished, it is considered that a timeout error has occurred. A timeout threshold is set in the hardware through a register; there is also a counter for counting the number of instructions executed by the message, which increases by 1 each time an instruction is executed; if the value of the counter exceeds the timeout threshold, a timeout error is reported.

[0087] The implementation of the microcode execution module B is to execute the microcode instructions, which is generally implemented in a multi-stage pipeline.

[0088] The implementation of instruction address generation module C is as follows:

[0089] The purpose of instruction address generation module C is to generate the instruction fetch address of the next instruction; there are three sources; the first source is the normal sequential increment or jump of instruction address. The second source is the address jump when an error occurs. It is divided into two categories; the first category is when entering debug mode, it jumps to the address of the debug instruction segment; the second category is the direct packet discard mode; it will jump to the corresponding discard instruction address (3 types of errors correspond to 3 different discard instruction addresses). The third source is the debug instruction jump address, which is used for debugging purposes.

[0090] An embodiment of the debugging module D is as follows:

[0091] This module needs to implement the following steps in hardware: 1. Report interrupts to the host. 2. Read debug data from kernel RAM and write it to debug-ram. 3. Provide a CPU interface to read debug-ram data for debugging analysis. 4. Generate debug instruction addresses based on host configuration.

[0092] An embodiment of the error type statistics module E is as follows:

[0093] Three counters are set in the hardware, corresponding to the count of illegal instruction errors, the count of storage access errors, and the count of timeout errors. These three counters can be read and cleared by the host statistics CPU read and write interface.

[0094] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0095] An embodiment of the present invention further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0096] Optionally, in this embodiment, the computer-readable storage medium may be configured to store a computer program for performing the following steps:

[0097] Step S1, detecting the microcode instruction;

[0098] Step S2, when an erroneous microcode instruction is detected, the method further includes one of the following: discarding the message corresponding to the erroneous microcode instruction; or, debugging the thread corresponding to the erroneous microcode instruction.

[0099] Through the above steps, since the microcode instructions are detected; in the case of detecting an erroneous microcode instruction, the method also includes one of the following: discarding the message corresponding to the erroneous microcode instruction; or, debugging the thread corresponding to the erroneous microcode instruction, thereby solving the problem of message errors caused by occasional errors of microcode instructions in related technologies and improving the processing efficiency of error messages.

[0100] Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments and optional implementation modes, and this embodiment will not be described in detail here.

[0101] Optionally, in this embodiment, the above-mentioned storage medium may include but is not limited to: a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and other media that can store computer programs.

[0102] An embodiment of the present invention further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0103] Optionally, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0104] Optionally, in this embodiment, the processor may be configured to perform the following steps through a computer program:

[0105] Step S1, detecting the microcode instruction;

[0106] Step S2, when an erroneous microcode instruction is detected, the method further includes one of the following: discarding the message corresponding to the erroneous microcode instruction; or, debugging the thread corresponding to the erroneous microcode instruction.

[0107] Through the above steps, since the microcode instructions are detected; in the case of detecting an erroneous microcode instruction, the method also includes one of the following: discarding the message corresponding to the erroneous microcode instruction; or, debugging the thread corresponding to the erroneous microcode instruction, thereby solving the problem of message errors caused by occasional errors of microcode instructions in related technologies and improving the processing efficiency of error messages.

[0108] Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments and optional implementation modes, and this embodiment will not be described in detail here.

[0109] Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, and optionally, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order than here, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.

[0110] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A processing method, characterized in that: include: Testing the microcode instruction before executing the microcode instruction; Among them, the error microcode instructions include three types: illegal instruction errors, illegal storage access errors and timeout errors; Detect whether it is an illegal instruction, if yes, encode the error type variable value of the microcode instruction as a first value; if no, continue to check for memory access errors, if there is an error, encode the error type variable value of the microcode instruction as a second value; if there is no error, continue to check for instruction execution timeout, if timeout, encode the error type variable value of the microcode instruction as a third value; Selecting to discard the message corresponding to the erroneous microcode instruction or to debug the thread corresponding to the erroneous microcode instruction according to the preset register configuration and the error type code value; If the debug mode is entered, the debug information is stored in the key-ram, and an interrupt is reported. The debug information is moved from the key-ram to the debug-ram through the CPU read-write interface and read out for analysis; Before discarding the message corresponding to the erroneous microcode instruction, jump to the address of the message discard instruction, and after jumping to the address of the message discard instruction, continue to execute the correct microcode instruction; or, Before debugging the thread corresponding to the erroneous microcode instruction, jump to the address of the debugging instruction, and after jumping to the address of the debugging instruction, continue to execute the correct microcode instruction.

2. The method according to claim 1, characterized in that Debugging the thread corresponding to the erroneous microcode instruction includes: Storing debugging information, wherein the debugging information is used to characterize the running status of the thread; The debugging information is read, and the thread is debugged according to the debugging information.

3. The method according to claim 1, characterized in that Detecting the microcode instruction includes at least one of the following: Detecting an operation code and an operand of the microcode instruction, and determining that the microcode instruction is an erroneous microcode instruction when the operation code does not belong to a preset specified type and the operand exceeds a preset operand threshold; or, detecting an address of a memory accessed by the microcode instruction, and determining that the microcode instruction is an erroneous microcode instruction when the address does not belong to a preset address range; or, The number of microcode instructions corresponding to the specified message is detected, and when the number exceeds a preset number threshold, the microcode instruction is determined to be an erroneous microcode instruction.

4. The method according to claim 1, characterized in that: After discarding the message corresponding to the erroneous microcode instruction, the method further includes: The reason for discarding the message is fed back to the message forwarding device.

5. The method according to claim 1, characterized in that The method further comprises: When an erroneous microcode instruction is detected, the type and / or number of the erroneous microcode instruction are counted.

6. A processing device, characterized in that: include: A detection module, used for detecting the microcode instruction before executing the microcode instruction; Among them, the error microcode instructions include three types: illegal instruction errors, illegal storage access errors and timeout errors; A processing module, used to detect whether it is an illegal instruction, if so, encode the error type variable value of the microcode instruction as a first value; if not, continue to check for memory access errors, if there is an error, encode the error type variable value of the microcode instruction as a second value; if there is no error, continue to check for instruction execution timeout, if timeout, encode the error type variable value of the microcode instruction as a third value; according to the preset register configuration and the error type code value, select to discard the message corresponding to the erroneous microcode instruction, or debug the thread corresponding to the erroneous microcode instruction; If the debug mode is entered, the device is also used to store the debug information in the key-ram, report the interrupt, and move the debug information from the key-ram to the debug-ram through the CPU read-write interface and read it out for analysis; Before discarding the message corresponding to the erroneous microcode instruction, the device is further used to jump to the address of the message discard instruction, and after jumping to the address of the message discard instruction, continue to execute the correct microcode instruction; or, Before debugging the thread corresponding to the erroneous microcode instruction, the device is further used to jump to the address of the debugging instruction, and after jumping to the address of the debugging instruction, continue to execute the correct microcode instruction.

7. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program is configured to execute the method according to any one of claims 1 to 5 when executed.

8. An electronic device comprising a memory and a processor, characterized in that: A computer program is stored in the memory, and the processor is configured to run the computer program to perform the method according to any one of claims 1 to 5.

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