Thin film transistor array substrate and electronic device including the array substrate

Abstract

A thin film transistor array substrate and an electronic device including the array substrate. A thin film transistor array substrate and an electronic device including the thin film transistor array substrate are provided. The thin film transistor array substrate includes: a first active layer, the first active layer is arranged on a substrate; a first gate insulating film, the first gate insulating film is arranged on the first active layer; a first gate, the first gate is arranged on the first gate insulating film to overlap with a portion of the first active layer; a first insulating film, the first insulating film is arranged on the first gate; a second active layer, the second active layer is arranged on the first insulating film to overlap with the first active layer and the first gate; a second gate insulating film, the second gate insulating film is arranged on the second active layer; and a second gate, the second gate is arranged on the second gate insulating film to overlap with a portion of the second active layer. The first gate and the second gate overlap each other, so the area occupied by the transistor can be reduced.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a thin film transistor (TFT) array substrate and an electronic device including the TFT array substrate. Background Art

[0002] With the development of information society, the demand for various electronic devices such as display devices and lighting fixtures has increased in various forms. Such electronic devices may include a panel in which data lines and gate lines are arranged, a data driver for driving the data lines, and a gate driver for driving the gate lines.

[0003] In a panel which is the core of an electronic device, a large number of transistors for various functions may be provided to drive the panel.

[0004] For this reason, the panel manufacturing process is complicated and difficult to manage. Therefore, the pursuit of process convenience may lead to a decrease in the device performance of the transistor.

[0005] In addition, the integration of transistors is increased to achieve excellent characteristics of electronic devices such as high resolution. However, due to problems in manufacturing process, design, etc., it is impossible to reduce the size of transistors indefinitely. Therefore, it is necessary to provide a transistor whose structure enables electronic devices to be highly integrated without reducing the characteristics of the transistor. Summary of the invention

[0006] Embodiments of the present disclosure are intended to provide a thin film transistor (TFT) array substrate and an electronic device including the TFT array substrate, wherein the TFT array substrate has the following structure: the area occupied by transistors in the horizontal direction is reduced by stacking at least two transistors on the substrate in a direction perpendicular to the substrate.

[0007] In addition, an embodiment of the present disclosure is directed to providing a TFT array substrate and an electronic device including the TFT array substrate, the TFT array substrate having a structure in which gates of at least two transistors are connected to nodes corresponding to each other so that leakage current can be reduced.

[0008] In addition, an embodiment of the present disclosure is intended to provide a TFT array substrate and an electronic device including the TFT array substrate, wherein the TFT array substrate has the following structure: contact holes formed for electrical connection between elements included in at least two transistors overlapping each other are appropriately arranged to prevent damage to the elements included in the transistors during the manufacturing process.

[0009] According to one aspect of the present disclosure, an electronic device is provided, which includes a panel and a driving circuit for driving the panel. The transistor arranged in the panel includes: a first active layer, the first active layer is arranged on a substrate; a first gate insulating film, the first gate insulating film is arranged on the first active layer to overlap with a portion of the first active layer; a first gate, the first gate is arranged on the first gate insulating film to overlap with a portion of the first active layer; a first insulating film, the first insulating film is arranged on the first gate; a second active layer, the second active layer is arranged on the first insulating film to overlap with the first active layer and the first gate; a second gate insulating film, the second gate insulating film is arranged on the second active layer; and a second gate, the second gate is arranged on the second gate insulating film to overlap with a portion of the second active layer. The first gate and the second gate overlap each other.

[0010] According to one aspect of the present disclosure, a TFT array substrate is provided, the TFT array substrate comprising: a substrate; a first active layer, the first active layer being disposed on the substrate; a first gate insulating film, the first gate insulating film being disposed on the first active layer; a first gate, the first gate being disposed on the first gate insulating film to overlap with a portion of the first active layer; a first insulating film, the first insulating film being disposed on the first gate; a second active layer, the second active layer being disposed on the first insulating film to overlap with the first active layer and the first gate; a second gate insulating film, the second gate insulating film being disposed on the second active layer; and a second gate, the second gate being disposed on the second gate insulating film to overlap with a portion of the second active layer. The first gate and the second gate overlap each other.

[0011] According to an embodiment of the present disclosure, a TFT array substrate and an electronic device including the TFT array substrate can be provided, wherein the TFT array substrate has the following structure: the area occupied by transistors in the horizontal direction is reduced by stacking at least two transistors on the substrate in a direction perpendicular to the substrate.

[0012] According to an embodiment of the present disclosure, a TFT array substrate having a structure in which gates of at least two transistors are connected to nodes corresponding to each other so that leakage current can be reduced and an electronic device including the same can be provided.

[0013] According to an embodiment of the present disclosure, a TFT array substrate and an electronic device including the TFT array substrate can be provided, wherein the TFT array substrate has the following structure: contact holes formed for electrical connection between elements included in at least two transistors overlapping each other are appropriately arranged to prevent damage to the elements included in the transistors during the manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0015] Figure 1 is a diagram schematically illustrating a configuration of an electronic device according to an embodiment of the present disclosure;

[0016] Figure 2 An implementation example of an electronic device according to an embodiment of the present disclosure is shown;

[0017] Figure 3 shows a structure of a sub-pixel when the panel according to an embodiment of the present disclosure is an organic light emitting diode (OLED) panel;

[0018] Figure 4 shows a structure of a sub-pixel when the panel according to an embodiment of the present disclosure is a liquid crystal display (LCD) panel;

[0019] Figure 5 is a diagram schematically illustrating a gate driving circuit provided in a panel according to an embodiment of the present disclosure;

[0020] Figure 6 is a cross-sectional view of a transistor according to an embodiment of the present disclosure;

[0021] Figure 7 The embodiment according to the present disclosure is shown Figure 6 The equivalent circuit of the transistor;

[0022] Figure 8 is a plan view illustrating a partial region of a display device including a transistor according to other embodiments of the present disclosure;

[0023] Fig. 9 According to the embodiment of the present disclosure, Figure 8 A cross-sectional view taken along line AB;

[0024] Fig.10 is a cross-sectional view of a transistor according to other embodiments of the present disclosure;

[0025] Fig.11 The embodiment according to the present disclosure is shown Figures 8 to 10 The equivalent circuit of the transistor shown;

[0026] Fig.12 is a plan view illustrating a partial region of a display device including a transistor according to still another embodiment of the present disclosure;

[0027] Fig.13 According to the embodiment of the present disclosure, Fig.12A cross-sectional view taken along line CD;

[0028] Fig.14 and Fig.15 The embodiment according to the present disclosure is shown in Fig.12 and Fig.13 The signal waveform of the transistor and the equivalent circuit of the transistor are shown;

[0029] Fig.16 is a plan view illustrating a partial region of a display device including a transistor according to still another embodiment of the present disclosure;

[0030] Fig.17 According to the embodiment of the present disclosure, Fig.16 A cross-sectional view taken along line EF of ; and

[0031] Fig.18 An equivalent circuit of a transistor according to still another embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0032] In the following description of examples or embodiments of the present disclosure, reference will be made to the accompanying drawings, in which specific examples or embodiments that can be implemented are shown by way of illustration, and in which the same reference numerals and numbers may be used to designate the same or similar components, even if they are shown in different drawings from each other. In addition, in the following description of examples or embodiments of the present disclosure, when it is determined that a detailed description of the well-known functions and components incorporated herein may make the subject matter in some embodiments of the present disclosure unclear, the description will be omitted. Terms such as "including", "having", "comprising", "consisting of", and "formed of" used herein are generally intended to allow the addition of other components unless these terms are used together with the term "only". As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0033] Terms such as "first", "second", "A", "B", "(A)" or "(B)" may be used herein to describe elements of the present disclosure. Each of these terms is not used to limit the nature, sequence, order or quantity of the elements, etc., but is only used to distinguish the corresponding element from other elements.

[0034] When it is mentioned that a first element is “connected or coupled to” a second element, “contacts or overlaps” the second element, etc., it should be interpreted that not only the first element can be “directly connected or coupled to” the second element or “directly contact or overlaps” the second element, but also a third element can be “interposed” between the first element and the second element, or the first element and the second element can be “connected or coupled” or “contacts or overlaps” each other via a fourth element. Here, the second element can be included in at least one of the two or more elements that are “connected or coupled”, “contacts or overlaps”, etc., to each other.

[0035] When time-related terms such as "after", "next", "then", "before", etc. are used to describe a process or operation of an element or configuration, or a flow or step in an operation, process, or manufacturing method, unless used with the terms "directly" or "immediately", these terms can be used to describe non-continuous or non-sequential processes or operations.

[0036] In addition, when any dimension, relative dimension, etc. is mentioned, even if no relevant description is specified, it should be considered that the numerical value of the element or feature, or the corresponding information (e.g., level, range, etc.) includes tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). In addition, the term "may" fully encompasses all meanings of the term "can".

[0037] Figure 1 is a diagram schematically illustrating a configuration of an electronic device according to an embodiment of the present disclosure.

[0038] The electronic device according to the embodiment of the present disclosure may include a display device, a lighting fixture, a light emitting device, etc. For ease of description, the display device will be mainly described below. However, the present disclosure can be applied to various other electronic devices such as lighting fixtures and light emitting devices in the same manner as long as the transistor is included therein.

[0039] An electronic device according to an embodiment of the present disclosure may include a panel PNL for displaying an image or outputting light, and a driving circuit for driving the panel PNL.

[0040] In the panel PNL, a plurality of data lines DL and a plurality of gate lines GL may be provided, and a plurality of sub-pixels SP defined by the plurality of data lines DL and the plurality of gate lines GL may be arranged in a matrix form.

[0041] In the panel PNL, a plurality of data lines DL and a plurality of gate lines GL may be arranged to cross. For example, a plurality of gate lines GL may be arranged in rows or columns, and a plurality of data lines DL may be arranged in columns or rows. For ease of description, it is assumed below that a plurality of gate lines GL are arranged in rows and a plurality of data lines DL are arranged in columns.

[0042] In the panel PNL, in addition to a plurality of data lines DL and a plurality of gate lines GL, other types of signal lines may be provided according to a sub-pixel structure, etc. Driving voltage lines, reference voltage lines, common voltage lines, etc. may also be provided.

[0043] The panel PNL may be one of various types of panels such as a liquid crystal display (LCD) panel and an organic light emitting diode (OLED) panel.

[0044] The type of the signal line provided in the panel PNL may vary depending on a sub-pixel structure, a panel type (eg, an LCD panel or an OLED panel), etc. In this specification, the signal line may include an electrode to which a signal is applied.

[0045] The panel PNL may include a display area A / A in which a video (image) is displayed and a non-display area (N / A) which is an outer area of ​​the display area A / A and in which no video (image) is displayed. The non-display area N / A may also be referred to as a "bezel area".

[0046] In the display area A / A, a plurality of sub-pixels SP for video display are arranged.

[0047] In the non-display area N / A, a pad portion electrically connected to the data driver DDR may be provided, and a plurality of data link lines for connecting the pad portion and the plurality of data lines DL may also be provided. The plurality of data link lines may be a portion of the plurality of data lines DL extending to the non-display area N / A, or may be an additional pattern electrically connected to the plurality of data lines DL.

[0048] In the non-display area N / A, lines related to gate driving may be provided to transmit a voltage (signal) required for gate driving to the gate driver GDR through a pad portion electrically connected to the data driver DDR. For example, the lines related to gate driving may include a clock line for transmitting a clock signal, a gate voltage line for transmitting gate voltages VGH and VGL, and a gate driving control signal line for transmitting various control signals required for generating a scan signal. Unlike the gate lines GL provided in the display area A / A, these lines related to gate driving are provided in the non-display area N / A.

[0049] The driving circuit may include a data driver DDR for driving a plurality of data lines DL, a gate driver GDR for driving a plurality of gate lines GL, a controller CTR for controlling the data driver DDR and the gate driver GDR, and the like.

[0050] The data driver DDR may drive the plurality of data lines DL by outputting data voltages to the plurality of data lines DL.

[0051] The gate driver GDR may drive the plurality of gate lines GL by outputting scan signals to the plurality of gate lines GL.

[0052] The controller CTR may control the operation of driving the data driver DDR and the gate driver GDR by providing various control signals DCS and GCS required for the operation of driving the data driver DDR and the gate driver GDR. In addition, the controller CTR may provide the image data DATA to the data driver DDR.

[0053] The controller CTR starts scanning according to the timing of each frame, converts input image data input from the outside of the electronic device into a data signal format used in the data driver DDR to output the converted image data DATA, and controls data driving at an appropriate time for scanning.

[0054] In order to control the data driver DDR and the gate driver GDR, the controller CTR receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input data enable (DE) signal, and a clock signal CLK from the outside (e.g., a host system), and generates various control signals and outputs them to the data driver DDR and the gate driver GDR.

[0055] For example, in order to control the gate driver GDR, the controller CTR outputs various gate control signals (GCS) including a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable (GOE) signal, and the like.

[0056] Furthermore, in order to control the data driver DDR, the controller CTR outputs various data control signals (DCS) including a source start pulse (SSP), a source sampling clock (SSC), a source output enable (SOE) signal, and the like.

[0057] The controller CTR may be a timing controller used in a general display technology or a control device that may perform other control functions in addition to the control function of the timing controller.

[0058] The controller CTR may be implemented as a separate component from the data driver DDR, or integrated with the data driver DDR as an integrated circuit.

[0059] The data driver DDR receives the image data DATA from the controller CTR and supplies data voltages to the plurality of data lines DL, thereby driving the plurality of data lines DL. The data driver DDR is also called a "source driver".

[0060] The data driver DDR may transmit and receive various signals to and from the controller CTR through various interfaces.

[0061] The gate driver GDR sequentially drives the plurality of gate lines GL by sequentially supplying scan signals to the plurality of gate lines GL. The gate driver GDR is also referred to as a "scan driver".

[0062] The gate driver GDR sequentially supplies scan signals having a turn-on voltage or a turn-off voltage to the plurality of gate lines GL under the control of the controller CTR.

[0063] When a specific gate line is activated by the gate driver GDR, the data driver DDR converts the image data DATA received from the controller CTR into an analog data voltage and supplies the analog data voltage to the plurality of data lines DL.

[0064] In some cases, the data driver DDR may be disposed only on one side (eg, upper or lower side) or on both sides (eg, upper and lower sides) of the panel PNL according to a driving method, panel design, etc.

[0065] In some cases, the gate driver GDR may be disposed only on one side (eg, left or right) or on both sides (eg, left and right) of the panel PNL according to a driving method, panel design, etc.

[0066] The data driver DDR may include one or more source driver integrated circuits SDIC.

[0067] Each source driver integrated circuit SDIC may include a shift register, a latch circuit, a digital-to-analog converter (DAC), an output buffer, etc. In some cases, the data driver DDR may further include one or more analog-to-digital converters (ADCs).

[0068] Each source driver integrated circuit SDIC is a source driver integrated circuit SDIC of a tape automated bonding (TAB) type or a chip on glass (COG) type, and can be connected to a bonding pad of the panel PNL or directly disposed on the panel PNL. In some cases, each source driver integrated circuit SDIC can be integrated with the panel PNL. In addition, each source driver integrated circuit SDIC can also be implemented as a chip on film (COF) type. In this case, each source driver integrated circuit SDIC can be mounted on a circuit film and connected to a data line DL in the panel PNL through the circuit film.

[0069] The gate driver GDR may include a plurality of gate driving circuits GDC, and each of the plurality of gate driving circuits GDC may correspond to one of the plurality of gate lines GL.

[0070] Each gate driving circuit GDC may include a shift register, a level shifter, and the like.

[0071] Each gate drive circuit GDC is a gate drive circuit of a TAB type or a COG type and can be connected to a bonding pad of the panel PNL. In addition, each gate drive circuit GDC can be implemented as a COF type. In this case, each gate drive circuit GDC can be mounted on a circuit film and electrically connected to a gate line GL in the panel PNL through the circuit film. In addition, each gate drive circuit GDC can be implemented as a panel internal gate (GIP) type and embedded in the panel PNL. That is, each gate drive circuit GDC can be directly formed in the panel PNL.

[0072] Figure 2 An implementation example of an electronic device according to an embodiment of the present disclosure is shown;

[0073] Reference Figure 2 In the electronic device according to the embodiment of the present disclosure, the data driver DDR can be implemented as a COF type among various types (TAB, COG, COF, etc.), and the gate driver GDR can be implemented as a GIP type among various types (TAB, COG, COF, GIP, etc.).

[0074] The data driver DDR may be implemented as one or more source driver integrated circuits SDIC. Figure 2 An example is shown in which the data driver DDR is implemented as a plurality of source driver integrated circuits SDIC.

[0075] When the data driver DDR is implemented as a COF type, each source driver integrated circuit SDIC for implementing the data driver DDR may be mounted on the source side circuit film SF.

[0076] One side of the source side circuit film SF may be electrically connected to a pad portion (a group of pads) present in the non-display area N / A.

[0077] On the source-side circuit film SF, wires may be disposed to electrically connect the source driver integrated circuit SDIC to the panel PNL.

[0078] For circuit connection between a plurality of source driver integrated circuits SDIC and other devices, the electronic device may include at least one source printed circuit board SPCB and a control printed circuit board CPCB for mounting control components and various electrical devices.

[0079] The other side of the source side circuit film SF on which the source driver integrated circuit SDIC is mounted may be connected to at least one source printed circuit board SPCB.

[0080] That is, one side of the source side circuit film SF on which the source driver integrated circuit SDIC is mounted may be electrically connected to the non-display area N / A of the panel PNL, and the other side thereof may be electrically connected to the source printed circuit board SPCB.

[0081] On the control printed circuit board CPCB, a controller CTR for controlling operations of a data driver DDR, a gate driver GDR, etc. may be disposed.

[0082] In addition, a power management integrated circuit (IC) PMIC or the like may be additionally disposed on the control printed circuit board CPCB to provide various voltages or currents to the panel PNL, the data driver DDR, the gate driver GDR, etc. or to control various voltages or currents to be provided thereto.

[0083] The source printed circuit board SPCB and the control printed circuit board CPCB may be connected by at least one connection member CBL in the circuit. As an example, the connection member CBL may be a flexible printed circuit (FPC) or a flexible flat cable (FFC), etc.

[0084] At least one source printed circuit board SPCB and the control printed circuit board CPCB may be integrated into one printed circuit board.

[0085] When the gate driver GDR is implemented as a GIP type, a plurality of gate driving circuits GDC included in the gate driver GDR may be directly formed on the non-display area N / A of the panel PNL.

[0086] Each of the plurality of gate driving circuits GDC may output a corresponding scan signal SCAN to a corresponding gate line GL disposed in the display area A / A of the panel PNL.

[0087] Various signals (clock signal, high-level gate voltage VGH, low-level gate voltage VGL, start signal VST, reset signal RST, etc.) required to generate a scan signal can be provided to a plurality of gate drive circuits GDC arranged on the panel PNL through lines related to gate drive arranged in the non-display area N / A.

[0088] The gate driving related lines disposed in the non-display area N / A may be electrically connected to the source side circuit film SF disposed closest to the plurality of gate driving circuits GDC.

[0089] Figure 3 The structure of the sub-pixel SP is shown when the panel PNL according to the embodiment of the present disclosure is an OLED panel.

[0090] Reference Figure 3 In the panel PNL as an OLED panel, each sub-pixel SP may include an organic light emitting diode OLED, a driving transistor DRT for driving the organic light emitting diode OLED, a switching transistor O-SWT electrically connected between a first node N1 of the driving transistor DRT and a corresponding data line DL, and a storage capacitor Cst electrically connected between the first node N1 and the second node N2 of the driving transistor DRT, etc.

[0091] The organic light emitting diode OLED may include an anode, an organic light emitting layer, a cathode, and the like.

[0092] according to Figure 3 In the circuit example of FIG. 1 , the anode electrode (also referred to as the “pixel electrode”) of the organic light emitting diode OLED may be electrically connected to the second node N2 of the driving transistor DRT. The base voltage EVSS may be applied to the cathode electrode (also referred to as the “common electrode”) of the organic light emitting diode OLED.

[0093] As an example, the base voltage EVSS may be a ground voltage or a voltage higher or lower than the ground voltage. In addition, the base voltage EVSS may vary depending on the driving state. For example, the base voltage EVSS for an image operation may be set to be different from the base voltage for a sensing operation.

[0094] The driving transistor DRT drives the organic light emitting diode OLED by supplying a driving current to the organic light emitting diode OLED.

[0095] The driving transistor DRT may include a first node N1, a second node N2, a third node N3, and the like.

[0096] The first node N1 of the driving transistor DRT may be a gate node and may be electrically connected to a source node or a drain node of the switching transistor O-SWT. The second node N2 of the driving transistor DRT may be a source node or a drain node and may be electrically connected to an anode (or cathode) of the organic light emitting diode OLED. The third node N3 of the driving transistor DRT may be a drain node or a source node. The driving voltage EVDD may be applied to the third node N3, and the third node N3 may be electrically connected to a driving voltage line DVL providing the driving voltage EVDD.

[0097] The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the driving transistor DRT and maintain a data voltage Vdata corresponding to an image signal voltage or a voltage corresponding to the data voltage Vdata for one frame time (or a determined time).

[0098] The drain node or source node of the switching transistor O-SWT can be electrically connected to the corresponding data line DL, the source node or drain node of the switching transistor O-SWT can be electrically connected to the first node N1 of the driving transistor DRT, and the gate node of the switching transistor O-SWT can be electrically connected to the corresponding selection line and receive the scan signal SCAN.

[0099] The switch transistor O-SWT may receive a scan signal SCAN through a corresponding gate line, so that the switch transistor O-SWT may be controlled to be turned on or off.

[0100] The switching transistor O-SWT may be turned on by the scan signal SCAN and transmit the data voltage Vdata provided through the corresponding data line DL to the first node N1 of the driving transistor DRT.

[0101] Furthermore, the storage capacitor Cst may be an external capacitor intentionally designed outside the driving transistor DRT, rather than a parasitic capacitor (eg, Cgs or Cgd) that is an internal capacitor existing between the first node N1 and the second node N2 of the driving transistor DRT.

[0102] Each of the driving transistor DRT and the switching transistor O-SWT may be an n-type transistor or a p-type transistor.

[0103] Figure 3 The sub-pixel structure shown is a two-transistor single capacitor (2T1C) structure and is only an example for description. In some cases, each sub-pixel structure may also include one or more transistors or one or more capacitors. Alternatively, each of the multiple sub-pixels may have the same structure, or some of the multiple sub-pixels may have another structure.

[0104] Figure 4 The structure of the sub-pixel SP is shown when the panel PNL according to the embodiment of the present disclosure is an LCD panel.

[0105] Reference Figure 4 , each sub-pixel SP in the panel PNL as an LCD panel may include a pixel electrode PXL, a switching transistor L-SWT, and the like.

[0106] The switching transistor L-SWT may be controlled by a scan signal SCAN and be electrically connected between the data line DL and the pixel electrode PXL.

[0107] The switching transistor L-SWT is turned on by the scan signal to transmit the data voltage Vdata provided through the data line DL to the pixel electrode PXL. The pixel electrode PXL applied with the data voltage Vdata can form an electric field together with the common electrode COM applied with the common voltage. That is, a capacitor (storage capacitor) can be formed between the pixel electrode PXL and the common electrode COM.

[0108] Figure 5 is a diagram schematically illustrating a gate driving circuit GDC provided in a panel PNL according to an embodiment of the present disclosure.

[0109] Reference Figure 5 Each gate driving circuit GDC may include a pull-up transistor Tup, a pull-down transistor Tdown, a control switch circuit CSC, and the like.

[0110] The control switch circuit CSC is a circuit that controls a voltage of a node Q corresponding to a gate node of the pull-up transistor Tup and a voltage of a node QB corresponding to a gate node of the pull-down transistor Tdown and may include a plurality of switches (transistors).

[0111] The pull-up transistor Tup provides a gating signal Vgate corresponding to a first level voltage (e.g., a high level voltage VGH) to the gating line GL through the gating signal output node Nout. The pull-down transistor Tdown provides a gating signal Vgate corresponding to a second level voltage (e.g., a low level voltage VGL) to the gating line GL through the gating signal output node Nout. The pull-up transistor Tup and the pull-down transistor Tdown may be turned on at different timings.

[0112] The pull-up transistor Tup is electrically connected between a clock signal applying node Nclk to which the clock signal CLK is applied and a gate signal output node Nout electrically connected to the gate line GL, and is turned on or off by the voltage of the node Q.

[0113] The gate node of the pull-up transistor Tup is electrically connected to the node Q. The drain node or source node of the pull-up transistor Tup is electrically connected to the clock signal applying node Nclk. The source node or drain node of the pull-up transistor Tup is electrically connected to the gate signal output node Nout through which the gate signal Vgate is output.

[0114] The pull-up transistor Tup is turned on by the voltage of the node Q, and outputs the gate signal Vgate having the high-level voltage VGH in the high-level period of the clock signal CLK to the gate signal output node Nout.

[0115] The gate signal Vgate of the high level voltage VGH output to the gate signal output node Nout is supplied to the corresponding gate line GL.

[0116] The pull-down transistor Tdown is electrically connected between the selection signal output node Nout and the base voltage node Nvss, and is turned on or off by the voltage of the node QB.

[0117] The gate node of the pull-down transistor Tdown is electrically connected to the node QB. The drain node or source node of the pull-down transistor Tdown is electrically connected to the base voltage node Nvss, and the base voltage VSS as a constant voltage is applied to the drain node or source node connected to the base voltage node Nvss. The source node or drain node of the pull-down transistor Tdown is electrically connected to the gating signal output node Nout from which the gating signal Vgate is output.

[0118] The pull-down transistor Tdown is turned on by the voltage of the node QB, and outputs the gate signal Vgate having the low level voltage VGL to the gate signal output node Nout. Therefore, the gate signal Vgate having the low level voltage VGL can be provided to the corresponding gate line GL through the gate signal output node Nout. As an example, the gate signal Vgate having the low level voltage VGL can be the base voltage VSS.

[0119] In addition, the control switch circuit CSC may include two or more transistors, etc., and there are main nodes such as a node Q, a node QB, a set node S (also referred to as a "start node"), and a reset node R. In some cases, there may be additional input nodes in the control switch circuit CSC to which various voltages such as a driving voltage VDD are applied.

[0120] In the control switch circuit CSC, the node Q is electrically connected to the gate node of the pull-up transistor Tup, and is repeatedly charged and discharged.

[0121] In the control switch circuit CSC, the node QB is electrically connected to the gate node of the pull-down transistor Tdown, and is repeatedly charged and discharged.

[0122] In the control switch circuit CSC, a set signal SET is applied to the set node S for instructing the corresponding gate driving circuit GDC to start gate driving.

[0123] The set signal SET applied to the set node S may be a start signal VST input from the outside of the gate driver GDR or a feedback signal (carry signal) of a gate signal Vgate output from a gate driving circuit GDC in a previous stage of the current gate driving circuit GDC.

[0124] The reset signal RST applied to the reset node R of the control switch circuit CSC may be a reset signal for simultaneously initializing the gate driving circuits GDC in all stages or a carry signal input from another stage (previous stage or next stage).

[0125] The control switch circuit CSC charges the node Q in response to the set signal SET, and discharges the node Q in response to the reset signal RST. The control switch circuit CSC may include an inverter circuit to charge or discharge the node Q and the node QB at different timings.

[0126] like Figure 3 As shown, in each of a plurality of sub-pixels SP in a display area A / A of a panel PNL as an OLED panel, a driving transistor DRT and a switching transistor O-SWT may be provided.

[0127] like Figure 4 As shown, a switching transistor L-SWT may be provided in each of a plurality of sub-pixels SP in a display area A / A of a panel PNL as an LCD panel.

[0128] As such, in each region of a plurality of sub-pixels SP in the display region of the panel PNL, which may be an OLED panel or an LCD panel, a transistor DRT and an O-SWT or a transistor L-SWT may be provided.

[0129] In addition, if Figure 2 As shown, when the gate driving circuit GDC is implemented as a GIP type, that is, when the gate driving circuit GDC is embedded in the panel PNL, including Figure 5 Various transistors (Tup, Tdown, and transistors in the control switch circuit CSC) in the gate driving circuit GDC shown may be disposed in the non-display area N / A which is an outer area of ​​the display area A / A of the panel PNL.

[0130] In addition, when the area occupied by the various transistors TR disposed in the non-display area N / A increases, the area of ​​the non-display area N / A may increase. This may cause a problem that the frame size of the display device increases. To this end, various transistor structures that reduce the area occupied by the transistor TR will be described below.

[0131] Figure 6 is a cross-sectional view of a transistor according to an embodiment of the present disclosure. Figure 7 The embodiment according to the present disclosure is shown Figure 6 The equivalent circuit of a transistor.

[0132] Reference Figure 6 , each transistor according to an embodiment of the present disclosure may include a first active layer 620 , a first gate 635 , a second active layer 650 , and a second gate 665 .

[0133] Specifically, according to an embodiment of the present disclosure, at least two transistors may be stacked on the substrate 600 .

[0134] For example, one transistor (a transistor disposed at a lower portion) may include a first active layer 620 and a first gate 635. The first active layer 620 may include at least two regions made conductive, and each region may function as one of a source and a drain.

[0135] Another transistor disposed on the above transistor (transistor disposed on the upper portion) may include a second active layer 650 and a second gate 665. The second active layer 650 may include at least two regions made conductive, and each region may function as one of a source and a drain.

[0136] At least one buffer layer 610 may be disposed on the substrate 600. In some cases, the buffer layer 610 may be omitted. Alternatively, the buffer layer 610 may have a structure in which a plurality of thin films are disposed. In this case, a plurality of inorganic layers may be stacked in the structure, but the present disclosure is not limited thereto.

[0137] The buffer layer 610 may be formed of an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON), but the present disclosure is not limited thereto.

[0138] When the buffer layer 610 includes a plurality of layers, at least two inorganic material layers among silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc. may be alternately disposed in the structure, but the present disclosure is not limited thereto.

[0139] In the following description, it is assumed that the buffer layer 610 has a single-layer structure.

[0140] The first active layer 620 may be disposed on the buffer layer 610 .

[0141] The first active layer 620 may be one of various types of semiconductor layers.

[0142] As an example, the first active layer 620 may be formed of an oxide semiconductor. The material of the first active layer 620 is a metal oxide semiconductor, which may be an oxide of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or a combination of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti) and oxides thereof.

[0143] For example, the first active layer 620 may include at least one of zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), and indium zinc tin oxide (IZTO).

[0144] Although the first active layer 620 is Figure 6 6. Although shown as a single layer in FIG. 6, the present disclosure is not limited thereto. For example, the first active layer 620 may include two or more layers.

[0145] The first gate insulating film 630 may be disposed on the first active layer 620. In addition, the first gate insulating film 630 may be disposed to overlap a portion of the first active layer 620.

[0146] The first gate insulating film 630 may be formed of an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON), but the present disclosure is not limited thereto.

[0147] The first gate 635 may be disposed on the first gate insulating film 630 .

[0148] The first gate electrode 635 may be formed of a metal such as aluminum (Al), silver (Ag), copper (Cu), molybdenum (Mo), chromium (Cr), tantalum (Ta), and titanium (Ti), or an alloy thereof.

[0149] In addition, although the first gate 635 is Figure 6 635 is shown as a single layer, but the present disclosure is not limited thereto. For example, the first gate 635 may have a multilayer film structure of two or more layers. Examples of multilayer films may be a double-layer film including a lower film such as titanium (Ti), tantalum (Ta), molybdenum (Mo) or ITO and an upper film such as copper (Cu), a three-layer film such as molybdenum-aluminum-molybdenum (Mo-Al-Mo), etc. However, the first gate 635 may be formed of various other metals or conductive materials in addition to the above-mentioned metals or conductive materials.

[0150] The first gate 635 may be disposed to overlap a portion of the first active layer 620 .

[0151] At least one end of the first gate 635 may be disposed to overlap at least one end of the first gate insulating film 630. In addition, the first gate 635 may be disposed to overlap a portion of the first gate insulating film 630.

[0152] That is, the first gate 635 and the first gate insulating film 630 may be disposed to expose a portion of the first active layer 620 .

[0153] A region of the first active layer 620 exposed by (not overlapping) the first gate 635 may have higher conductivity than a region of the first active layer 620 overlapping the first gate 635 .

[0154] For example, a region of the first active layer 620 that does not overlap the first gate electrode 635 may be made conductive.

[0155] Then, the first active layer 620 may include a first channel region 622 overlapping the first gate 635 , and a first region 621 and a second region 623 disposed at both sides of the first channel region 622 , with the first channel region 622 interposed therebetween.

[0156] The first channel region 622 may have lower conductivity than the first region 621 and the second region 623 .

[0157] One of the first region 621 and the second region 623 may function as a source or a drain of a transistor disposed at a lower portion.

[0158] For example, the first region 621 may be a source of a transistor disposed at a lower portion, and the second region 623 may be a drain of the transistor, but the present disclosure is not limited thereto. The first region 621 may be a drain of the transistor, and the second region 623 may be a source of the transistor.

[0159] The first insulating film 640 may be disposed on the first active layer 620, the first gate insulating film 630, and the first gate 635. The first insulating film 640 may be disposed to cover the first gate insulating film 630 and the first gate 635.

[0160] The first insulating film 640 may be formed of an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON), but the present disclosure is not limited thereto.

[0161] Although the first insulating film 640 Figure 6640 is shown as a single layer, but the present disclosure is not limited thereto. For example, the first insulating film 640 may have a multi-layer film structure.

[0162] The second active layer 650 may be disposed on the first insulating film 640 .

[0163] The second active layer 650 may be disposed to overlap the first active layer 620. In addition, the second active layer 650 may be disposed to overlap the first gate electrode 635.

[0164] The second active layer 650 may be formed of an oxide semiconductor. The material of the second active layer 650 is a metal oxide semiconductor, which may be an oxide of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or a combination of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti) and oxides thereof.

[0165] For example, the second active layer 650 may include at least one of zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), and indium zinc tin oxide (IZTO).

[0166] Although the second active layer 650 is Figure 6 6. Although shown as a single layer in FIG. 6, the present disclosure is not limited thereto. For example, the second active layer 650 may include two or more layers.

[0167] The second gate insulating film 660 may be disposed on the second active layer 650. In addition, the second gate insulating film 660 may be disposed to overlap a portion of the second active layer 650.

[0168] The second gate insulating film 660 may be formed of an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON), but the present disclosure is not limited thereto.

[0169] The second gate 665 may be disposed on the second gate insulating film 660 .

[0170] The second gate electrode 665 may be formed of a metal such as aluminum (Al), silver (Ag), copper (Cu), molybdenum (Mo), chromium (Cr), tantalum (Ta), and titanium (Ti), or an alloy thereof.

[0171] In addition, although the second gate 665 is Figure 6665 is shown as a single layer, but the present disclosure is not limited thereto. For example, the second gate 665 may have a multilayer film structure of two or more layers. Examples of multilayer films may be a double-layer film including a lower film such as titanium (Ti), tantalum (Ta), molybdenum (Mo) or ITO and an upper film such as copper (Cu), a three-layer film of molybdenum-aluminum-molybdenum (Mo-Al-Mo), etc. However, the second gate 665 may be formed of various other metals or conductive materials in addition to the above-mentioned metals or conductive materials.

[0172] The second gate 665 may be disposed to overlap a portion of the second active layer 650 .

[0173] At least one end of the second gate 665 may be disposed to overlap at least one end of the second gate insulating film 660. In addition, the second gate 665 may be disposed to overlap a portion of the second gate insulating film 660.

[0174] That is, the second gate 665 and the second gate insulating film 660 may be disposed to expose a portion of the second active layer 650 .

[0175] A region of the second active layer 650 exposed by (not overlapping) the second gate 665 may have higher electrical conductivity than a region of the second active layer 650 overlapping the second gate 665 .

[0176] For example, a region of the second active layer 650 that does not overlap the second gate electrode 665 may be made conductive.

[0177] Then, the second active layer 650 may include a second channel region 652 overlapping the second gate 665 , and a third region 651 and a fourth region 653 disposed at both sides of the second channel region 652 with the second channel region 652 interposed therebetween.

[0178] The second channel region 652 may have lower conductivity than the third region 651 and the fourth region 653 .

[0179] One of the third region 651 and the fourth region 653 may function as a source or a drain of a transistor disposed at an upper portion.

[0180] For example, the third region 651 may be a source of a transistor disposed at an upper portion, and the fourth region 653 may be a drain of the transistor, but the present disclosure is not limited thereto. The third region 651 may be a drain of the transistor, and the fourth region 653 may be a source of the transistor.

[0181] In addition, the third region 651 of the second active layer 650 may contact the first region 621 through the first hole H1 provided in the first insulating film 640. The fourth region 653 of the second active layer 650 may contact the second region 623 of the first active layer 620 through the second hole H2 provided in the first insulating film 640.

[0182] The second insulating film 670 may be disposed on the second active layer 650, the second gate insulating film 660, and the second gate 665. The second insulating film 670 may be disposed to cover the second gate insulating film 660 and the second gate 665.

[0183] The second insulating film 670 may be formed of an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON), but the present disclosure is not limited thereto.

[0184] Although the second insulating film 670 Figure 6 6. Although shown as a single layer in FIG. 6, the present disclosure is not limited thereto. For example, the second insulating film 670 may have a multi-layer film structure.

[0185] The first electrode 680 and the second electrode 690 may be disposed to be spaced apart from each other on the second insulating film 670 .

[0186] The first electrode 680 may contact the third region 651 of the second active layer 650 through the third hole H3 provided in the second insulating film 670. That is, the first electrode 680 may be electrically connected to the third region 651 of the second active layer 650 and may also be electrically connected to the first region 621 of the first active layer 620.

[0187] The second electrode 690 may contact the fourth region 653 of the second active layer 650 through the fourth hole H4 provided in the second insulating film 670. That is, the second electrode 690 may be electrically connected to the fourth region 653 of the second active layer 650 and may also be electrically connected to the second region 623 of the first active layer 620.

[0188] A signal may be applied to at least one of the first electrode 680 and the second electrode 690 .

[0189] when Figure 6 When the first gate 635 and the second gate 665 of the transistor are turned on, the first channel region 622 of the first active layer 620 and the second channel region 652 of the second active layer 650 may be activated.

[0190] Reference Figure 6 and Figure 7According to an embodiment of the present disclosure, the first gate 635 and the second gate 665 may be connected to the same gate node. In addition, the drain of the first transistor and the drain of the second transistor may be connected to the same node, and the source of the first transistor and the drain of the second transistor may also be connected to the same node.

[0191] like Figure 7 As shown, the first gate 635 and the second gate 665 are connected to the same node and can therefore be turned on simultaneously by one signal. To this end, the two channel regions can be activated by one selection signal. Therefore, the current path can be increased and the current capability of the transistor can be maximized.

[0192] The second transistor may perform an operation corresponding to a transistor having a double gate structure including the first gate 635 .

[0193] like Figure 6 As shown, the first active layer 620, the first gate 635, the second active layer 650 and the second gate 665 of the transistor are arranged to overlap each other, so that the area occupied by the transistor in the display device can be reduced and the electrical characteristics of the transistor can be improved.

[0194] Then, we will refer to Figures 8 to 11 Structures and circuit diagrams of transistors according to other embodiments of the present disclosure are described.

[0195] Figure 8 is a plan view illustrating a partial region of a display device including a transistor according to other embodiments of the present disclosure. Fig. 9 According to the embodiment of the present disclosure, Figure 8 A cross-sectional view taken along line AB. Fig.10 is a cross-sectional view of a transistor according to other embodiments of the present disclosure. Fig.11 The embodiment according to the present disclosure is shown Figures 8 to 10 The equivalent circuit of the transistor is shown.

[0196] In the following description, the same details (configuration, effect, etc.) as those of the above-described embodiment may be omitted.

[0197] Reference Figure 8 and Fig. 9 , transistors according to other embodiments may have a structure in which at least two transistors are stacked on the substrate 600 and each transistor is connected to one gate signal line.

[0198] For example, one transistor (a transistor disposed at a lower portion) may include a first active layer 820 and a first gate 835. The first active layer 820 may include at least two regions made conductive, and each region may function as one of a source and a drain.

[0199] In addition, another transistor disposed on the above transistor (transistor disposed on the upper portion) may include a second active layer 850 and a second gate 865. The second active layer 850 may include at least two regions made conductive, and each region may function as one of a source and a drain.

[0200] Specifically, the third electrode 890 (or the first conductive layer) may be disposed on the substrate 600. Figure 8 As shown, the third electrode 890 may have a line shape in a plan view, but the present disclosure is not limited thereto. For example, the third electrode 890 may have an island shape.

[0201] Despite Figure 8 and Fig. 9 Although not shown, a buffer layer may be disposed between the third electrode 890 and the substrate 600 .

[0202] In addition, the third electrode 890 may be formed of a metal such as aluminum (Al), silver (Ag), copper (Cu), molybdenum (Mo), chromium (Cr), tantalum (Ta), and titanium (Ti), an alloy thereof, or the like. Fig. 9 890 is shown as a single layer, but the present disclosure is not limited thereto. For example, the third electrode 890 may have a multi-layer film structure of two or more layers.

[0203] The first insulating film 910 may be disposed on the third electrode 890 .

[0204] The first insulating film 910 may be formed of an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON), but the present disclosure is not limited thereto. Fig. 9 910 is shown as a single layer, but the present disclosure is not limited thereto. For example, the first insulating film 910 may have a multi-layer film structure.

[0205] The first active layer 820 may be disposed on the first insulating film 910 .

[0206] like Figure 8 and Fig. 9 As shown, the third electrode 890 of the transistor disposed at the lower portion may be disposed to overlap a portion of the first active layer 820 .

[0207] The first gate insulating film 930 may be disposed on the first active layer 820 , and the first gate 835 may be disposed on the first gate insulating film 930 .

[0208] like Figure 8 As shown, the first gate 835 may have a linear shape, but the present disclosure is not limited thereto.

[0209] In addition, if Figure 8 and Fig. 9 As shown, the first gate 835 may be disposed to overlap a portion of the first active layer 820 .

[0210] The first active layer 820 may include a first channel region 922 overlapping the first gate 835 , and a first region 921 and a second region 923 disposed at both sides of the first channel region 922 , with the first channel region 922 interposed therebetween.

[0211] The first channel region 922 may have lower electrical conductivity than the first region 921 and the second region 923 .

[0212] One of the first region 921 and the second region 923 may function as a source or a drain of a transistor disposed at a lower portion.

[0213] For example, the first region 921 may be a source of a transistor disposed at a lower portion, and the second region 923 may be a drain of the transistor, but the present disclosure is not limited thereto. The first region 921 may be a drain of the transistor, and the second region 923 may be a source of the transistor.

[0214] The first region 921 of the first active layer 820 may contact the third electrode 890 through the fifth hole H5 provided in the first insulating film 910. That is, the first region 921 of the first active layer 820 may be electrically connected to the third electrode 890.

[0215] The second insulating film 940 may be disposed on the first active layer 820, the first gate insulating film 930, and the first gate 835. The second insulating film 940 may be disposed to cover the first gate insulating film 930 and the first gate 835.

[0216] The second active layer 850 may be disposed on the second insulating film 940 .

[0217] like Figure 8 and Fig. 9 As shown, a portion of the second active layer 850 may be disposed to overlap the third electrode 890 and the first gate electrode 835. In addition, the second active layer 850 may be disposed to overlap a portion or the entirety of the first active layer 820.

[0218] The second gate insulating film 960 may be disposed on the second active layer 850 , and the second gate 865 may be disposed on the second gate insulating film 960 .

[0219] In addition, if Figure 8 and Fig. 9 As shown, the second gate 865 may be disposed to overlap a portion of the second active layer 850 .

[0220] The second active layer 850 may include a second channel region 952 overlapping the second gate 865 , and a third region 951 and a fourth region 953 disposed at both sides of the second channel region 952 , with the second channel region 952 interposed therebetween.

[0221] The second channel region 952 may have lower conductivity than the third region 951 and the fourth region 953 .

[0222] One of the third region 951 and the fourth region 953 may function as a source or a drain of a transistor disposed at an upper portion.

[0223] For example, the third region 951 may be a source of a transistor disposed at an upper portion, and the fourth region 953 may be a drain of the transistor, but the present disclosure is not limited thereto. The third region 951 may be a drain of the transistor, and the fourth region 953 may be a source of the transistor.

[0224] The fourth region 953 of the second active layer 850 may contact the second region 923 of the first active layer 820 through the sixth hole H6 provided in the second insulating film 940. That is, the fourth region 953 of the second active layer 850 contacts the second region 923 of the first active layer 820, so that the second active layer 850 and the first active layer 820 may be electrically connected.

[0225] The third insulating film 970 may be disposed on the second active layer 850, the second gate insulating film 960, and the second gate 865. The third insulating film 970 may be disposed to cover the second gate insulating film 960 and the second gate 865.

[0226] The fourth electrode 880 may be disposed on the third insulating film 970. Figure 8 As shown, the fourth electrode 880 may have a line shape in a plan view, but the present disclosure is not limited thereto. For example, the fourth electrode 880 may have an island shape.

[0227] like Figure 8 and Fig. 9As shown, the fourth electrode 880 may be disposed to overlap the third electrode 890. In addition, the fourth electrode 880 may also overlap a portion of the first active layer 820 and a portion of the second active layer 850.

[0228] On the other hand, the fourth electrode 880 may overlap the second active layer 850 in a region corresponding to a region where the third electrode 890 overlaps the first active layer 820 .

[0229] In addition, the fourth electrode 880 may be formed of a metal such as aluminum (Al), silver (Ag), copper (Cu), molybdenum (Mo), chromium (Cr), tantalum (Ta), and titanium (Ti), an alloy thereof, or the like. Fig. 9 8 is shown as a single layer, but the present disclosure is not limited thereto. For example, the fourth electrode 880 may have a multi-layer film structure of two or more layers.

[0230] The fourth electrode 880 may contact the third region 951 of the second active layer 850 through the eighth hole H8 provided in the third insulating film 970. That is, the fourth electrode 880 may be electrically connected to the third region 951 of the second active layer 850.

[0231] In addition, the fifth electrode 895 may be disposed on the third insulating film 970 to be spaced apart from the fourth electrode 880 .

[0232] The fifth electrode 895 may contact the fourth region 953 of the second active layer 850 through a ninth hole H9 provided in the third insulating film 970 .

[0233] Although not shown in the drawings, the fifth electrode 895 may be electrically connected to another adjacent transistor provided in the display panel.

[0234] Reference Figure 8 and Fig. 9 The third electrode 890 and the fourth electrode 880 may be disposed to overlap each other. The third electrode 890 may be connected to the first active layer 820 through the fifth hole H5, and the fourth electrode 880 may be electrically connected to the second active layer 850 through the eighth hole H8.

[0235] The first insulating film 910 may have at least one fifth hole H5 , and the third insulating film 970 may also have at least one eighth hole H8 .

[0236] In this case, if Figure 8 and Fig. 9 As shown, the fifth hole H5 and the eighth hole H8 may not overlap each other.

[0237] Since the fifth hole H5 and the eighth hole H8 do not overlap each other, it is possible to prevent at least one of the active layer 820 and the active layer 850 from being damaged during the formation of the fifth hole H5 and the eighth hole H8.

[0238] In addition, the first active layer 820, the second active layer 850 and the fifth electrode 895 can be arranged to at least partially overlap each other, so that the fourth region 953 of the second active layer 850 can be electrically connected to the second region 923 of the first active layer 820 through the sixth hole H6, and the fifth electrode 895 can be connected to the fourth region 953 of the second active layer 850 through the ninth hole H9.

[0239] The second insulating film 940 may have at least one sixth hole H6 , and the third insulating film 970 may have at least one ninth hole H9 .

[0240] In this case, if Figure 8 and Fig. 9 As shown, the sixth hole H6 and the ninth hole H9 may not overlap each other.

[0241] Since the sixth hole H6 and the ninth hole H9 do not overlap each other, it is possible to prevent at least one of the active layer 820 and the active layer 850 from being damaged during the formation of the sixth hole H6 and the ninth hole H9.

[0242] However, the present disclosure is not limited thereto, and Fig.10 As shown, the fifth hole H5 and the eighth hole H8 may overlap with each other, and the sixth hole H6 and the ninth hole H9 may overlap with each other.

[0243] In addition, refer to Figure 8 and Fig.11 , transistors according to other embodiments of the present disclosure may be electrically connected to the same selection signal line 815 .

[0244] Specifically, each of the first gate 835 and the second gate 865 may be electrically connected to a single gate signal line 815. The first gate 835 may be connected to the gate signal line 815 through the first contact hole C1, and the second gate 865 may be connected to the gate signal line 815 through the second contact hole C2.

[0245] That is to say, Fig.11 As shown, the first gate 835 and the second gate 865 may be connected to the same gate node.

[0246] In addition, the first active layer 820 and the second active layer 850 are electrically connected through the sixth hole H6 so that the first channel region 922 and the second channel region 952 can be connected in series. In this case, the first active layer 820 including the first channel region 922 can be provided to ensure electrical stability of the second active layer 850.

[0247] For example, when the first gate 835 and the second gate 865 are turned off, even if a signal is applied to the third electrode 890 , the first active layer 820 may prevent the second channel region 952 of the second active layer 850 from being activated.

[0248] In the above structure, one transistor may include a first gate electrode 835 and a first active layer 820. In addition, one of the third electrode 890 and the second region 923 of the first active layer 820 made conductive is used as a source, and the other is used as a drain. In this way, one transistor (hereinafter referred to as a "first transistor") may be configured.

[0249] In addition, the third electrode 890 disposed on the substrate 600 may prevent light from being incident on the first active layer 820 , so that characteristics of the first active layer 820 may not be changed.

[0250] In addition, another transistor may include a second gate 865 and a second active layer 850, a fourth electrode 880 and one of the fourth regions 953 of the second active layer 850 made conductive is used as a source, and the other is used as a drain, so that another transistor (hereinafter referred to as "second transistor") can be configured.

[0251] In this way, the first transistor and the second transistor are arranged to overlap in the height direction of the substrate 600, so that the area occupied by the transistor in the horizontal direction can be reduced in the display panel.

[0252] Therefore, when the first transistor and the second transistor exist in the non-display region of the display panel, the area of ​​the non-display region can be reduced by stacking the first transistor and the second transistor in a vertical direction.

[0253] Subsequently, the following will refer to Fig.12 and Fig.13 A structure of a transistor according to still another embodiment of the present disclosure is described.

[0254] Fig.12 is a plan view illustrating a partial region of a display device including a transistor according to still another embodiment of the present disclosure. Fig.13 According to the embodiment of the present disclosure, Fig.12 A cross-sectional view taken along line CD.

[0255] In the following description, the same details (configuration, effect, etc.) as those of the above-described embodiment may be omitted.

[0256] Reference Fig.12 and Fig.13 , transistors according to still other embodiments may have a structure in which at least two transistors are stacked on a substrate 600 and each transistor is connected to a gate signal line 1215 (wherein the gate signal line is a line for providing a signal to a gate).

[0257] The sixth electrode 1290 may be disposed on the substrate 600. The sixth electrode 1290 may be disposed on the substrate 600. Figure 8 and Fig. 9 The sixth electrode 1290 is located at a position corresponding to the third electrode 890 shown in FIG. 8 , but is different from the third electrode 890 in that the sixth electrode 1290 is disposed to overlap with the first channel region 922 of the first active layer 820 .

[0258] Specifically, the sixth electrode 1290 may overlap the first region 921 and the first channel region 922. In some cases, such as Fig.13 As shown, the sixth electrode 1290 may overlap the first region 921 , the first channel region 922 , and the second region 923 of the first active layer 820 .

[0259] In addition, the sixth electrode 1290 may be disposed to overlap the first gate electrode 835 and the second gate electrode 865 .

[0260] Although the sixth electrode 1290 may be a line to which the clock signal CLK is applied, the present disclosure is not limited thereto.

[0261] The first active layer 820 may contact the sixth electrode 1290 through a tenth hole H10 provided in the first insulating film 910 .

[0262] The second active layer 850 disposed on the first gate 835 may contact the first active layer 820 through the eleventh hole H11 disposed in the second insulating film 940. Specifically, the fourth region 853 of the second active layer 850 may be electrically connected to the second region 923 of the first active layer 820 through the eleventh hole H11.

[0263] The third insulating film 970 may be disposed on the second gate electrode 865 disposed on the second active layer 850 , and the seventh electrode 1280 may be disposed on the third insulating film 970 .

[0264] The seventh electrode 1280 may contact the third region 851 of the second active layer 850 through the twelfth hole H12 provided in the third insulating film 970 .

[0265] exist Fig.12 and Fig.13 In the structure shown, one transistor may include a first gate 835 and a first active layer 820. Then, one of the first region 921 of the first active layer 820 and the second region 923 of the first active layer 820 is used as a source, and the other is used as a drain, so that one transistor (hereinafter referred to as a "first transistor") may be configured.

[0266] In addition, another transistor may include a second gate 865 and a second active layer 850. One of the third region 851 of the second active layer 850 and the fourth region 853 of the second active layer 850 serves as a source and the other serves as a drain, so that another transistor (hereinafter referred to as a "second transistor") may be configured.

[0267] In this way, the first transistor and the second transistor are arranged to overlap in the height direction of the substrate 600, so that the area occupied by the transistor in the horizontal direction can be reduced in the display panel.

[0268] Therefore, when the first transistor and the second transistor exist in the non-display region of the display panel, the area of ​​the non-display region can be reduced by stacking the first transistor and the second transistor in a vertical direction.

[0269] Subsequently, the following will refer to Fig.14 and Fig.15 Description applied to Fig.12 and Fig.13 The signal waveform of the transistor and the equivalent circuit of the transistor are shown.

[0270] Fig.14 and Fig.15 The embodiment according to the present disclosure is shown in Fig.12 and Fig.13 The signal waveform of the transistor and the equivalent circuit of the transistor are shown.

[0271] First, refer to Fig.14 When the clock signal CLK is applied to the sixth electrode 1290 to apply the clock signal CLK to Fig.13 When the transistor is turned on, there is a high level period due to the clock signal CLK, and when the high level period of the clock signal CLK corresponds to the high level period of the selection signal, Fig.13 and Fig.14 The first transistor and the second transistor shown may be turned on.

[0272] In this case, the second transistor may perform an operation corresponding to a transistor having a double gate structure including the first gate 835 .

[0273] Specifically, when the clock signal CLK is applied to Fig.13and Fig.14 When the sixth electrode 1290 shown and the first gate 835 and the second gate 865 connected to the same node are turned on, a signal applied to the sixth electrode 1290 can pass through the first active layer 820 and the second active layer 850 and be output through the seventh electrode 1280 .

[0274] like Fig.15 As shown, even when the clock signal CLK is applied to the sixth electrode 1290, the gating signal may not be applied. In this case, the first gate 835 and the second gate 865 are turned off. Therefore, the signal applied to the sixth electrode 1290 will not be transmitted to the first active layer 820 and the second active layer 850.

[0275] Furthermore, even when the first gate 835 is turned off, the clock signal CLK applied to the sixth electrode 1290 may be transmitted to the first active layer 820. However, in this case, the second gate 865 is also turned off, so the signal is not transmitted to the second active layer 850.

[0276] That is, since the first gate 835 and the second gate 865 are turned off at the same time, a signal applied to the sixth electrode 1290 is not transmitted to the seventh electrode 1280 as an output terminal, so that leakage current can be reduced.

[0277] In the display device according to the embodiment of the present disclosure, at least two transistors are disposed to overlap each other and are electrically connected, so that leakage current can be reduced.

[0278] The following will refer to Figures 16 to 18 An arrangement of a transistor according to still another embodiment of the present disclosure is described.

[0279] Fig.16 is a plan view illustrating a partial region of a display device including a transistor according to still another embodiment of the present disclosure. Fig.17 According to the embodiment of the present disclosure, Fig.16 A cross-sectional view taken along line EF. Fig.18 An equivalent circuit of a transistor according to still another embodiment of the present disclosure is shown.

[0280] In the following description, the same details (configuration, effect, etc.) as those of the above-described embodiment may be omitted.

[0281] Reference Fig.16 and Fig.17 , a transistor according to still another embodiment may have a structure in which at least two transistors are stacked on a substrate 600 and each transistor is connected to one gate signal line 815 (wherein the gate signal line is a line for supplying a signal to a gate).

[0282] For example, the first transistor and the second transistor may be provided on a substrate.

[0283] The first transistor may include a first active layer 1620 and a first gate 835. One of the first region 1721 and the second region 1723 of the first active layer 1620 made conductive may be a source of the first transistor, and the other may be a drain of the first transistor.

[0284] Under the first transistor, the eighth electrode 1690 and the ninth electrode 1695 are disposed to be spaced apart from each other. The eighth electrode 1690 and the ninth electrode 1695 may prevent light from being incident on the first active layer 1620 so that characteristics of the first active layer 1620 are not changed.

[0285] The first insulating film 910 may be disposed on the eighth electrode 1690 and the ninth electrode 1695 .

[0286] The first active layer 1620 including the first region 1721 , the first channel region 1722 , and the second region 1723 may be disposed on the first insulating film 910 .

[0287] The first region 1721 of the first active layer 1620 may contact the eighth electrode 1690 through the thirteenth hole H13 provided in the first insulating film 910 . The second region 1723 of the first active layer 1620 may contact the ninth electrode 1695 through the fourteenth hole H14 provided in the first insulating film 910 .

[0288] The first gate insulating film 930 may be disposed on the first active layer 1620 , and the first gate 835 may be disposed on the first gate insulating film 930 .

[0289] The second transistor may include a second active layer 1650 and a second gate 865. One of the third and fourth regions 1751 and 1753 of the second active layer 1650 made conductive may be a source of the second transistor, and the other may be a drain of the second transistor.

[0290] The second active layer 1650 of the second transistor may be disposed on the second insulating film 940 disposed on the first gate 835. The second active layer 1650 may include a third region 1751, a second channel region 1752, and a fourth region 1753.

[0291] The second gate insulating film 960 may be disposed on the second active layer 1650 , and the second gate 865 may be disposed on the second gate insulating film 960 .

[0292] The third insulating film 970 may be disposed on the second active layer 1650 , the second gate insulating film 960 , and the second gate 865 .

[0293] On the third insulating film 970 , the tenth electrode 1680 and the eleventh electrode 1685 may be arranged to be spaced apart from each other.

[0294] The tenth electrode 1680 may contact the third region 1751 of the second active layer 1650 through the fifteenth hole H15 provided in the third insulating film 970. The eleventh electrode 1685 may contact the fourth region 1753 of the second active layer 1650 through the sixteenth hole H16 provided in the third insulating film 970.

[0295] like Fig.16 and Fig.17 As shown, the eighth electrode 1690 of the first transistor and the tenth electrode 1680 of the second transistor may overlap each other.

[0296] In addition, the ninth electrode 1695 of the first transistor and the eleventh electrode 1685 of the second transistor may overlap each other.

[0297] The eighth electrode 1690 and the tenth electrode 1680 may be drains of the first transistor and the second transistor, respectively, and the ninth electrode 1695 and the eleventh electrode 1685 may be sources of the first transistor and the second transistor, respectively, but the present disclosure is not limited thereto.

[0298] The first active layer 1620 and the second active layer 1650 may be disposed to overlap the eighth electrode 1690 , the ninth electrode 1695 , the tenth electrode 1680 , and the eleventh electrode 1685 .

[0299] In addition, refer to Fig.16 and Fig.18 , a transistor according to still another embodiment of the present disclosure may be electrically connected to the same selection signal line 815 .

[0300] That is to say, Fig.18 As shown, the first gate 835 and the second gate 865 may be connected to the same gate node. In addition, the first active layer 1620 and the second active layer 1650 are spaced apart from each other by the second insulating film 940 interposed therebetween, so that the first channel region 1722 and the second channel region 1752 may be connected in parallel.

[0301] Therefore, the resistance of the first channel region 1722 and the resistance of the second channel region 1752 can be reduced.

[0302] As described above, the electrical characteristics of the plurality of transistors according to still another embodiment of the present disclosure can be adjusted by the connection structure of the channel regions of the respective transistors.

[0303] In addition, since the first gate 835 and the second gate 865 are connected to the same node, the second transistor may perform an operation corresponding to a transistor having a double gate structure including the first gate 835 disposed under the second active layer 1650 .

[0304] That is, since the first gate 835 and the second gate 865 are connected to the same selection signal line 815, the same signal is applied to the first gate 835 and the second gate 865, so when the second gate 865 is turned off, the first gate 835 is also turned off. In this way, the double gates overlapping each other are turned off, so that no leakage current can flow through the second active layer 1650.

[0305] In addition, the first transistor and the second transistor are disposed to overlap in the height direction of the substrate 600, so that the area occupied by the transistors in the horizontal direction can be reduced in the display panel.

[0306] According to an embodiment of the present disclosure, a thin film transistor (TFT) array substrate and an electronic device including the TFT array substrate can be provided, wherein the TFT array substrate has the following structure: the area occupied by the transistor in the horizontal direction is reduced by stacking at least two transistors on the substrate in a direction perpendicular to the substrate.

[0307] According to an embodiment of the present disclosure, it is possible to provide a TFT array substrate having a structure in which gates of at least two transistors are connected to nodes corresponding to each other so that leakage current can be reduced, and to provide an electronic device including the TFT array substrate.

[0308] According to an embodiment of the present disclosure, a TFT array substrate and an electronic device including the TFT array substrate can be provided, wherein the TFT array substrate has the following structure: contact holes formed for electrical connection between elements included in at least two transistors overlapping each other are appropriately arranged to prevent damage to the elements included in the transistors during the manufacturing process.

[0309] The above description has been given to enable any technician in the field to make and use the technical concept of the present disclosure, and the above description has been provided in the context of specific applications and their requirements. Various modifications, additions and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. The above description and accompanying drawings provide examples of the technical concept of the present disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concept of the present disclosure. Therefore, the scope of the present disclosure is not limited to the embodiments shown, but should be given the widest scope consistent with the claims. The scope of protection of the present disclosure should be interpreted based on the attached claims, and all technical concepts within their equivalent ranges should be interpreted as included within the scope of the present disclosure.

[0310] CROSS-REFERENCE TO RELATED APPLICATIONS

[0311] This application claims priority to Korean Patent Application No. 10-2019-0171760, filed on December 20, 2019, which is hereby incorporated by reference for all purposes as if fully set forth herein.

Claims

1. An electronic device, comprising: panel; a driving circuit configured to drive the panel; Wherein, the transistors arranged in the panel include: A first active layer, wherein the first active layer is disposed on a substrate; a first gate insulating film disposed on the first active layer to overlap a portion of the first active layer; a first gate disposed on the first gate insulating film to overlap a portion of the first active layer; a first insulating film, the first insulating film being disposed on the first gate; a second active layer disposed on the first insulating film to overlap the first active layer and the first gate; a second gate insulating film provided on the second active layer; and a second gate disposed on the second gate insulating film to overlap a portion of the second active layer, The first gate and the second gate overlap each other, and The first gate and the second gate are electrically connected to the same node.

2. The electronic device according to claim 1, wherein: The first active layer includes: a first channel region, the first channel region overlapping the first gate; and a first region and a second region, the first region and the second region being made conductive and spaced apart from each other, the first channel region being interposed between the first region and the second region, and The second active layer includes: a second channel region, the second channel region overlapping the second gate; and a third region and a fourth region, the third region and the fourth region are made conductive and spaced apart from each other, and the second channel region is interposed between the third region and the fourth region.

3. The electronic device according to claim 2, wherein: The first insulating film includes: a first hole exposing an upper surface of the first region of the first active layer; and a second hole, the second hole exposing an upper surface of the second region of the first active layer, The third region of the second active layer contacts the first region of the first active layer through the first hole, and The fourth region of the second active layer contacts the second region of the first active layer through the second hole.

4. The electronic device according to claim 3, further comprising: a second insulating film, the second insulating film being disposed on the second gate; as well as a first electrode and a second electrode, the first electrode and the second electrode being disposed on the second insulating film and spaced apart from each other, Wherein, the second insulating film comprises: a third hole exposing an upper surface of the third region of the second active layer; and a fourth hole, the fourth hole exposing an upper surface of the fourth region of the second active layer, The first electrode contacts the third region of the second active layer through the third hole, and The second electrode contacts the fourth region of the second active layer through the fourth hole.

5. The electronic device according to claim 2, further comprising: a third insulating film, the third insulating film being disposed below the first active layer; as well as A first conductive layer is provided below the third insulating film.

6. The electronic device according to claim 5, wherein: The third insulating film includes a fifth hole that exposes an upper surface of the first conductive layer, and The first region of the first active layer contacts the first conductive layer through the fifth hole.

7. The electronic device according to claim 6, wherein: The first insulating film includes a sixth hole that exposes an upper surface of the second region of the first active layer, and The fourth region of the second active layer contacts the first active layer through the sixth hole.

8. The electronic device according to claim 5, further comprising a third electrode located on a second insulating film provided on the second gate, and The third electrode contacts the third region of the second active layer through a seventh hole provided in the second insulating film.

9. The electronic device according to claim 8, further comprising a fourth electrode provided on the second insulating film so as to be spaced apart from the third electrode, in, The fourth electrode contacts the fourth region of the second active layer through an eighth hole provided in the second insulating film.

10. The electronic device according to claim 9, wherein: The fourth electrode is electrically connected to another adjacent transistor disposed on the substrate.

11. The electronic device according to claim 5, wherein: The first conductive layer does not overlap the first channel region of the first active layer and the second region of the first active layer.

12. The electronic device according to claim 5, wherein: The first conductive layer overlaps the first region, the first channel region, and the second region of the first active layer.

13. The electronic device according to claim 12, wherein: A clock signal is applied to the first conductive layer. 14 . The electronic device according to claim 5 , further comprising a second conductive layer disposed coplanar with the first conductive layer and spaced apart from the first conductive layer.

15. The electronic device according to claim 14, wherein: The second conductive layer overlaps the second region of the first active layer and does not overlap the first channel region of the first active layer and the first region of the first active layer.

16. The electronic device according to claim 14, wherein: The third insulating film includes a ninth hole that exposes an upper surface of the second conductive layer, and The second region of the first active layer contacts the second conductive layer through the ninth hole.

17. The electronic device according to claim 14, further comprising a fifth electrode and a sixth electrode, the fifth electrode and the sixth electrode being disposed to be spaced apart from each other on a second insulating film disposed on the second gate electrode, The fifth electrode contacts the third region of the second active layer through a tenth hole provided in the second insulating film, and The sixth electrode contacts the fourth region of the second active layer through an eleventh hole provided in the second insulating film.

18. A thin film transistor array substrate, comprising: substrate; a first active layer, wherein the first active layer is disposed on the substrate; a first gate insulating film, the first gate insulating film being disposed on the first active layer; a first gate disposed on the first gate insulating film to overlap a portion of the first active layer; a first insulating film, the first insulating film being disposed on the first gate; a second active layer disposed on the first insulating film to overlap the first active layer and the first gate; a second gate insulating film, the second gate insulating film being disposed on the second active layer; as well as a second gate disposed on the second gate insulating film to overlap a portion of the second active layer, wherein the first gate and the second gate overlap each other, and The first gate and the second gate are electrically connected to the same node.

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